registers.hh revision 14106:293e3f4b1321
1/* 2 * Copyright (c) 2010-2011, 2014, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_REGISTERS_HH__ 44#define __ARCH_ARM_REGISTERS_HH__ 45 46#include "arch/arm/ccregs.hh" 47#include "arch/arm/generated/max_inst_regs.hh" 48#include "arch/arm/intregs.hh" 49#include "arch/arm/miscregs.hh" 50#include "arch/arm/types.hh" 51#include "arch/generic/vec_pred_reg.hh" 52#include "arch/generic/vec_reg.hh" 53 54namespace ArmISA { 55 56 57// For a predicated instruction, we need all the 58// destination registers to also be sources 59const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 60 ArmISAInst::MaxInstSrcRegs; 61using ArmISAInst::MaxInstDestRegs; 62using ArmISAInst::MaxMiscDestRegs; 63 64// Number of VecElem per Vector Register, computed based on the vector length 65constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords; 66 67using VecElem = uint32_t; 68using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 69using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 70using VecRegContainer = VecReg::Container; 71 72using VecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg, 73 VecPredRegHasPackedRepr, false>; 74using ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg, 75 VecPredRegHasPackedRepr, true>; 76using VecPredRegContainer = VecPredReg::Container; 77 78// Constants Related to the number of registers 79const int NumIntArchRegs = NUM_ARCH_INTREGS; 80// The number of single precision floating point registers 81const int NumFloatV7ArchRegs = 64; 82const int NumFloatV8ArchRegs = 128; 83const int NumFloatSpecialRegs = 32; 84const int NumVecV7ArchRegs = 64; 85const int NumVecV8ArchRegs = 32; 86const int NumVecSpecialRegs = 8; 87 88const int NumVecIntrlvRegs = 4; 89const int NumIntRegs = NUM_INTREGS; 90const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; 91const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs; 92const int VECREG_UREG0 = 32; 93const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0 94const int PREDREG_FFR = 16; 95const int PREDREG_UREG0 = 17; 96const int NumCCRegs = NUM_CCREGS; 97const int NumMiscRegs = NUM_MISCREGS; 98const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs; 99const int INTRLVREG1 = INTRLVREG0 + 1; 100const int INTRLVREG2 = INTRLVREG0 + 2; 101const int INTRLVREG3 = INTRLVREG0 + 3; 102 103#define ISA_HAS_CC_REGS 104 105const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + 106 NumVecPredRegs + NumMiscRegs; 107 108// semantically meaningful register indices 109const int ReturnValueReg = 0; 110const int ReturnValueReg1 = 1; 111const int ReturnValueReg2 = 2; 112const int NumArgumentRegs = 4; 113const int NumArgumentRegs64 = 8; 114const int ArgumentReg0 = 0; 115const int ArgumentReg1 = 1; 116const int ArgumentReg2 = 2; 117const int ArgumentReg3 = 3; 118const int FramePointerReg = 11; 119const int StackPointerReg = INTREG_SP; 120const int ReturnAddressReg = INTREG_LR; 121const int PCReg = INTREG_PC; 122 123const int ZeroReg = INTREG_ZERO; 124 125const int SyscallNumReg = ReturnValueReg; 126const int SyscallPseudoReturnReg = ReturnValueReg; 127const int SyscallSuccessReg = ReturnValueReg; 128 129} // namespace ArmISA 130 131#endif 132