registers.hh revision 13610 
1/*
2 * Copyright (c) 2010-2011, 2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_REGISTERS_HH__
44#define __ARCH_ARM_REGISTERS_HH__
45
46#include "arch/arm/ccregs.hh"
47#include "arch/arm/generated/max_inst_regs.hh"
48#include "arch/arm/intregs.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "arch/generic/vec_pred_reg.hh"
52#include "arch/generic/vec_reg.hh"
53
54namespace ArmISA {
55
56
57// For a predicated instruction, we need all the
58// destination registers to also be sources
59const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
60    ArmISAInst::MaxInstSrcRegs;
61using ArmISAInst::MaxInstDestRegs;
62using ArmISAInst::MaxMiscDestRegs;
63
64// Number of VecElem per Vector Register, computed based on the vector length
65constexpr unsigned NumVecElemPerVecReg = 4;
66using VecElem = uint32_t;
67using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
68using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
69using VecRegContainer = VecReg::Container;
70
71constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
72
73// Dummy typedefs
74using VecPredReg = ::DummyVecPredReg;
75using ConstVecPredReg = ::DummyConstVecPredReg;
76using VecPredRegContainer = ::DummyVecPredRegContainer;
77constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
78constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
79
80// condition code register; must be at least 32 bits for FpCondCodes
81typedef uint64_t CCReg;
82
83// Constants Related to the number of registers
84const int NumIntArchRegs = NUM_ARCH_INTREGS;
85// The number of single precision floating point registers
86const int NumFloatV7ArchRegs  = 64;
87const int NumFloatV8ArchRegs  = 128;
88const int NumFloatSpecialRegs = 32;
89const int NumVecV7ArchRegs  = 64;
90const int NumVecV8ArchRegs  = 32;
91const int NumVecSpecialRegs = 8;
92
93const int NumIntRegs = NUM_INTREGS;
94const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
95const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs;
96const int NumVecPredRegs = 1;
97const int NumCCRegs = NUM_CCREGS;
98const int NumMiscRegs = NUM_MISCREGS;
99
100#define ISA_HAS_CC_REGS
101
102const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
103    NumVecPredRegs + NumMiscRegs;
104
105// semantically meaningful register indices
106const int ReturnValueReg = 0;
107const int ReturnValueReg1 = 1;
108const int ReturnValueReg2 = 2;
109const int NumArgumentRegs = 4;
110const int NumArgumentRegs64 = 8;
111const int ArgumentReg0 = 0;
112const int ArgumentReg1 = 1;
113const int ArgumentReg2 = 2;
114const int ArgumentReg3 = 3;
115const int FramePointerReg = 11;
116const int StackPointerReg = INTREG_SP;
117const int ReturnAddressReg = INTREG_LR;
118const int PCReg = INTREG_PC;
119
120const int ZeroReg = INTREG_ZERO;
121
122const int SyscallNumReg = ReturnValueReg;
123const int SyscallPseudoReturnReg = ReturnValueReg;
124const int SyscallSuccessReg = ReturnValueReg;
125
126} // namespace ArmISA
127
128#endif
129