registers.hh revision 7592
16019SN/A/*
26019SN/A * Copyright (c) 2007-2008 The Florida State University
36019SN/A * All rights reserved.
46019SN/A *
56019SN/A * Redistribution and use in source and binary forms, with or without
66019SN/A * modification, are permitted provided that the following conditions are
76019SN/A * met: redistributions of source code must retain the above copyright
86019SN/A * notice, this list of conditions and the following disclaimer;
96019SN/A * redistributions in binary form must reproduce the above copyright
106019SN/A * notice, this list of conditions and the following disclaimer in the
116019SN/A * documentation and/or other materials provided with the distribution;
126019SN/A * neither the name of the copyright holders nor the names of its
136019SN/A * contributors may be used to endorse or promote products derived from
146019SN/A * this software without specific prior written permission.
156019SN/A *
166019SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176019SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186019SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196019SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206019SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216019SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
226019SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
236019SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
246019SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256019SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266019SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276019SN/A *
286019SN/A * Authors: Stephen Hines
296019SN/A */
306019SN/A
316329Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_REGISTERS_HH__
326329Sgblack@eecs.umich.edu#define __ARCH_ARM_REGISTERS_HH__
336019SN/A
346329Sgblack@eecs.umich.edu#include "arch/arm/max_inst_regs.hh"
356717Sgblack@eecs.umich.edu#include "arch/arm/intregs.hh"
366329Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh"
376328SN/A
386329Sgblack@eecs.umich.edunamespace ArmISA {
396328SN/A
406329Sgblack@eecs.umich.eduusing ArmISAInst::MaxInstSrcRegs;
416329Sgblack@eecs.umich.eduusing ArmISAInst::MaxInstDestRegs;
426328SN/A
437310Sgblack@eecs.umich.edutypedef uint16_t  RegIndex;
446328SN/A
456329Sgblack@eecs.umich.edutypedef uint64_t IntReg;
466328SN/A
476329Sgblack@eecs.umich.edu// floating point register file entry type
486329Sgblack@eecs.umich.edutypedef uint32_t FloatRegBits;
496329Sgblack@eecs.umich.edutypedef float FloatReg;
506328SN/A
516329Sgblack@eecs.umich.edu// cop-0/cop-1 system control register
526329Sgblack@eecs.umich.edutypedef uint64_t MiscReg;
536328SN/A
546329Sgblack@eecs.umich.edu// Constants Related to the number of registers
556717Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_ARCH_INTREGS;
567177Sgblack@eecs.umich.edu// The number of single precision floating point registers
577177Sgblack@eecs.umich.educonst int NumFloatArchRegs = 64;
587592SAli.Saidi@ARM.comconst int NumFloatSpecialRegs = 8;
596328SN/A
606717Sgblack@eecs.umich.educonst int NumIntRegs = NUM_INTREGS;
616329Sgblack@eecs.umich.educonst int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
626328SN/A
636329Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS;
646328SN/A
656328SN/A
666329Sgblack@eecs.umich.edu// semantically meaningful register indices
676329Sgblack@eecs.umich.educonst int ReturnValueReg = 0;
686329Sgblack@eecs.umich.educonst int ReturnValueReg1 = 1;
696329Sgblack@eecs.umich.educonst int ReturnValueReg2 = 2;
706329Sgblack@eecs.umich.educonst int ArgumentReg0 = 0;
716329Sgblack@eecs.umich.educonst int ArgumentReg1 = 1;
726329Sgblack@eecs.umich.educonst int ArgumentReg2 = 2;
736329Sgblack@eecs.umich.educonst int ArgumentReg3 = 3;
746329Sgblack@eecs.umich.educonst int FramePointerReg = 11;
756717Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_SP;
766717Sgblack@eecs.umich.educonst int ReturnAddressReg = INTREG_LR;
776717Sgblack@eecs.umich.educonst int PCReg = INTREG_PC;
786328SN/A
796717Sgblack@eecs.umich.educonst int ZeroReg = INTREG_ZERO;
806328SN/A
816329Sgblack@eecs.umich.educonst int SyscallNumReg = ReturnValueReg;
826329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = ReturnValueReg;
836329Sgblack@eecs.umich.educonst int SyscallSuccessReg = ReturnValueReg;
846328SN/A
856329Sgblack@eecs.umich.edu// These help enumerate all the registers for dependence tracking.
867498Sgblack@eecs.umich.educonst int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1);
876329Sgblack@eecs.umich.educonst int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
886329Sgblack@eecs.umich.edu
896329Sgblack@eecs.umich.edutypedef union {
906329Sgblack@eecs.umich.edu    IntReg   intreg;
916329Sgblack@eecs.umich.edu    FloatReg fpreg;
926329Sgblack@eecs.umich.edu    MiscReg  ctrlreg;
936329Sgblack@eecs.umich.edu} AnyReg;
946329Sgblack@eecs.umich.edu
956329Sgblack@eecs.umich.eduenum FPControlRegNums {
966329Sgblack@eecs.umich.edu   FIR = NumFloatArchRegs,
976329Sgblack@eecs.umich.edu   FCCR,
986329Sgblack@eecs.umich.edu   FEXR,
996329Sgblack@eecs.umich.edu   FENR,
1006329Sgblack@eecs.umich.edu   FCSR
1016329Sgblack@eecs.umich.edu};
1026329Sgblack@eecs.umich.edu
1036329Sgblack@eecs.umich.eduenum FCSRBits {
1046329Sgblack@eecs.umich.edu    Inexact = 1,
1056329Sgblack@eecs.umich.edu    Underflow,
1066329Sgblack@eecs.umich.edu    Overflow,
1076329Sgblack@eecs.umich.edu    DivideByZero,
1086329Sgblack@eecs.umich.edu    Invalid,
1096329Sgblack@eecs.umich.edu    Unimplemented
1106329Sgblack@eecs.umich.edu};
1116329Sgblack@eecs.umich.edu
1126329Sgblack@eecs.umich.eduenum FCSRFields {
1136329Sgblack@eecs.umich.edu    Flag_Field = 1,
1146329Sgblack@eecs.umich.edu    Enable_Field = 6,
1156329Sgblack@eecs.umich.edu    Cause_Field = 11
1166329Sgblack@eecs.umich.edu};
1176329Sgblack@eecs.umich.edu
1186328SN/A} // namespace ArmISA
1196019SN/A
1206019SN/A#endif
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