process.cc revision 7678
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 * Ali Saidi 42 */ 43 44#include "arch/arm/isa_traits.hh" 45#include "arch/arm/process.hh" 46#include "arch/arm/types.hh" 47#include "base/loader/elf_object.hh" 48#include "base/loader/object_file.hh" 49#include "base/misc.hh" 50#include "cpu/thread_context.hh" 51#include "mem/page_table.hh" 52#include "mem/translating_port.hh" 53#include "sim/byteswap.hh" 54#include "sim/process_impl.hh" 55#include "sim/system.hh" 56 57using namespace std; 58using namespace ArmISA; 59 60ArmLiveProcess::ArmLiveProcess(LiveProcessParams *params, ObjectFile *objFile, 61 ObjectFile::Arch _arch) 62 : LiveProcess(params, objFile), arch(_arch) 63{ 64 stack_base = 0xbf000000L; 65 66 // Set pointer for next thread stack. Reserve 8M for main stack. 67 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 68 69 // Set up break point (Top of Heap) 70 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 71 brk_point = roundUp(brk_point, VMPageSize); 72 73 // Set up region for mmaps. For now, start at bottom of kuseg space. 74 mmap_start = mmap_end = 0x40000000L; 75} 76 77void 78ArmLiveProcess::startup() 79{ 80 LiveProcess::startup(); 81 argsInit(MachineBytes, VMPageSize); 82 for (int i = 0; i < contextIds.size(); i++) { 83 ThreadContext * tc = system->getThreadContext(contextIds[i]); 84 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); 85 // Enable the floating point coprocessors. 86 cpacr.cp10 = 0x3; 87 cpacr.cp11 = 0x3; 88 tc->setMiscReg(MISCREG_CPACR, cpacr); 89 // Generically enable floating point support. 90 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 91 fpexc.en = 1; 92 tc->setMiscReg(MISCREG_FPEXC, fpexc); 93 } 94} 95 96void 97ArmLiveProcess::copyStringArray32(std::vector<std::string> &strings, 98 Addr array_ptr, Addr data_ptr, 99 TranslatingPort* memPort) 100{ 101 Addr data_ptr_swap; 102 for (int i = 0; i < strings.size(); ++i) { 103 data_ptr_swap = htog(data_ptr); 104 memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr_swap, 105 sizeof(uint32_t)); 106 memPort->writeString(data_ptr, strings[i].c_str()); 107 array_ptr += sizeof(uint32_t); 108 data_ptr += strings[i].size() + 1; 109 } 110 // add NULL terminator 111 data_ptr = 0; 112 113 memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr, sizeof(uint32_t)); 114} 115 116void 117ArmLiveProcess::argsInit(int intSize, int pageSize) 118{ 119 typedef AuxVector<uint32_t> auxv_t; 120 std::vector<auxv_t> auxv; 121 122 string filename; 123 if (argv.size() < 1) 124 filename = ""; 125 else 126 filename = argv[0]; 127 128 //We want 16 byte alignment 129 uint64_t align = 16; 130 131 // load object file into target memory 132 objFile->loadSections(initVirtMem); 133 134 enum ArmCpuFeature { 135 Arm_Swp = 1 << 0, 136 Arm_Half = 1 << 1, 137 Arm_Thumb = 1 << 2, 138 Arm_26Bit = 1 << 3, 139 Arm_FastMult = 1 << 4, 140 Arm_Fpa = 1 << 5, 141 Arm_Vfp = 1 << 6, 142 Arm_Edsp = 1 << 7, 143 Arm_Java = 1 << 8, 144 Arm_Iwmmxt = 1 << 9, 145 Arm_Crunch = 1 << 10, 146 Arm_ThumbEE = 1 << 11, 147 Arm_Neon = 1 << 12, 148 Arm_Vfpv3 = 1 << 13, 149 Arm_Vfpv3d16 = 1 << 14 150 }; 151 152 //Setup the auxilliary vectors. These will already have endian conversion. 153 //Auxilliary vectors are loaded only for elf formatted executables. 154 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 155 if (elfObject) { 156 uint32_t features = 157 Arm_Swp | 158 Arm_Half | 159 Arm_Thumb | 160// Arm_26Bit | 161 Arm_FastMult | 162// Arm_Fpa | 163 Arm_Vfp | 164 Arm_Edsp | 165// Arm_Java | 166// Arm_Iwmmxt | 167// Arm_Crunch | 168 Arm_ThumbEE | 169 Arm_Neon | 170 Arm_Vfpv3 | 171 Arm_Vfpv3d16 | 172 0; 173 174 //Bits which describe the system hardware capabilities 175 //XXX Figure out what these should be 176 auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 177 //The system page size 178 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::VMPageSize)); 179 //Frequency at which times() increments 180 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64)); 181 // For statically linked executables, this is the virtual address of the 182 // program header tables if they appear in the executable image 183 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 184 // This is the size of a program header entry from the elf file. 185 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 186 // This is the number of program headers from the original elf file. 187 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 188 //This is the address of the elf "interpreter", It should be set 189 //to 0 for regular executables. It should be something else 190 //(not sure what) for dynamic libraries. 191 auxv.push_back(auxv_t(M5_AT_BASE, 0)); 192 193 //XXX Figure out what this should be. 194 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 195 //The entry point to the program 196 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 197 //Different user and group IDs 198 auxv.push_back(auxv_t(M5_AT_UID, uid())); 199 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 200 auxv.push_back(auxv_t(M5_AT_GID, gid())); 201 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 202 //Whether to enable "secure mode" in the executable 203 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 204 205 // Pointer to 16 bytes of random data 206 auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 207 208 //The filename of the program 209 auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 210 //The string "v71" -- ARM v7 architecture 211 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 212 } 213 214 //Figure out how big the initial stack nedes to be 215 216 // A sentry NULL void pointer at the top of the stack. 217 int sentry_size = intSize; 218 219 string platform = "v71"; 220 int platform_size = platform.size() + 1; 221 222 // Bytes for AT_RANDOM above, we'll just keep them 0 223 int aux_random_size = 16; // as per the specification 224 225 // The aux vectors are put on the stack in two groups. The first group are 226 // the vectors that are generated as the elf is loaded. The second group 227 // are the ones that were computed ahead of time and include the platform 228 // string. 229 int aux_data_size = filename.size() + 1; 230 231 int env_data_size = 0; 232 for (int i = 0; i < envp.size(); ++i) { 233 env_data_size += envp[i].size() + 1; 234 } 235 int arg_data_size = 0; 236 for (int i = 0; i < argv.size(); ++i) { 237 arg_data_size += argv[i].size() + 1; 238 } 239 240 int info_block_size = 241 sentry_size + env_data_size + arg_data_size + 242 aux_data_size + platform_size + aux_random_size; 243 244 //Each auxilliary vector is two 4 byte words 245 int aux_array_size = intSize * 2 * (auxv.size() + 1); 246 247 int envp_array_size = intSize * (envp.size() + 1); 248 int argv_array_size = intSize * (argv.size() + 1); 249 250 int argc_size = intSize; 251 252 //Figure out the size of the contents of the actual initial frame 253 int frame_size = 254 info_block_size + 255 aux_array_size + 256 envp_array_size + 257 argv_array_size + 258 argc_size; 259 260 //There needs to be padding after the auxiliary vector data so that the 261 //very bottom of the stack is aligned properly. 262 int partial_size = frame_size; 263 int aligned_partial_size = roundUp(partial_size, align); 264 int aux_padding = aligned_partial_size - partial_size; 265 266 int space_needed = frame_size + aux_padding; 267 268 stack_min = stack_base - space_needed; 269 stack_min = roundDown(stack_min, align); 270 stack_size = stack_base - stack_min; 271 272 // map memory 273 pTable->allocate(roundDown(stack_min, pageSize), 274 roundUp(stack_size, pageSize)); 275 276 // map out initial stack contents 277 uint32_t sentry_base = stack_base - sentry_size; 278 uint32_t aux_data_base = sentry_base - aux_data_size; 279 uint32_t env_data_base = aux_data_base - env_data_size; 280 uint32_t arg_data_base = env_data_base - arg_data_size; 281 uint32_t platform_base = arg_data_base - platform_size; 282 uint32_t aux_random_base = platform_base - aux_random_size; 283 uint32_t auxv_array_base = aux_random_base - aux_array_size - aux_padding; 284 uint32_t envp_array_base = auxv_array_base - envp_array_size; 285 uint32_t argv_array_base = envp_array_base - argv_array_size; 286 uint32_t argc_base = argv_array_base - argc_size; 287 288 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 289 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 290 DPRINTF(Stack, "0x%x - env data\n", env_data_base); 291 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 292 DPRINTF(Stack, "0x%x - random data\n", aux_random_base); 293 DPRINTF(Stack, "0x%x - platform base\n", platform_base); 294 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 295 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 296 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 297 DPRINTF(Stack, "0x%x - argc \n", argc_base); 298 DPRINTF(Stack, "0x%x - stack min\n", stack_min); 299 300 // write contents to stack 301 302 // figure out argc 303 uint32_t argc = argv.size(); 304 uint32_t guestArgc = ArmISA::htog(argc); 305 306 //Write out the sentry void * 307 uint32_t sentry_NULL = 0; 308 initVirtMem->writeBlob(sentry_base, 309 (uint8_t*)&sentry_NULL, sentry_size); 310 311 //Fix up the aux vectors which point to other data 312 for (int i = auxv.size() - 1; i >= 0; i--) { 313 if (auxv[i].a_type == M5_AT_PLATFORM) { 314 auxv[i].a_val = platform_base; 315 initVirtMem->writeString(platform_base, platform.c_str()); 316 } else if (auxv[i].a_type == M5_AT_EXECFN) { 317 auxv[i].a_val = aux_data_base; 318 initVirtMem->writeString(aux_data_base, filename.c_str()); 319 } else if (auxv[i].a_type == M5_AT_RANDOM) { 320 auxv[i].a_val = aux_random_base; 321 // Just leave the value 0, we don't want randomness 322 } 323 } 324 325 //Copy the aux stuff 326 for(int x = 0; x < auxv.size(); x++) 327 { 328 initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, 329 (uint8_t*)&(auxv[x].a_type), intSize); 330 initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 331 (uint8_t*)&(auxv[x].a_val), intSize); 332 } 333 //Write out the terminating zeroed auxilliary vector 334 const uint64_t zero = 0; 335 initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(), 336 (uint8_t*)&zero, 2 * intSize); 337 338 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 339 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 340 341 initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 342 343 ThreadContext *tc = system->getThreadContext(contextIds[0]); 344 //Set the stack pointer register 345 tc->setIntReg(StackPointerReg, stack_min); 346 //A pointer to a function to run when the program exits. We'll set this 347 //to zero explicitly to make sure this isn't used. 348 tc->setIntReg(ArgumentReg0, 0); 349 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively 350 if (argv.size() > 0) { 351 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size - 352 argv[argv.size() - 1].size() - 1); 353 } else { 354 tc->setIntReg(ArgumentReg1, 0); 355 } 356 if (envp.size() > 0) { 357 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size - 358 envp[envp.size() - 1].size() - 1); 359 } else { 360 tc->setIntReg(ArgumentReg2, 0); 361 } 362 363 Addr prog_entry = objFile->entryPoint(); 364 if (arch == ObjectFile::Thumb) 365 prog_entry = (prog_entry & ~mask(1)) | (ULL(1) << PcTBitShift); 366 tc->setPC(prog_entry); 367 tc->setNextPC(prog_entry + sizeof(MachInst)); 368 369 //Align the "stack_min" to a page boundary. 370 stack_min = roundDown(stack_min, pageSize); 371} 372 373ArmISA::IntReg 374ArmLiveProcess::getSyscallArg(ThreadContext *tc, int &i) 375{ 376 assert(i < 6); 377 return tc->readIntReg(ArgumentReg0 + i++); 378} 379 380uint64_t 381ArmLiveProcess::getSyscallArg(ThreadContext *tc, int &i, int width) 382{ 383 assert(width == 32 || width == 64); 384 if (width == 32) 385 return getSyscallArg(tc, i); 386 387 // 64 bit arguments are passed starting in an even register 388 if (i % 2 != 0) 389 i++; 390 391 // Registers r0-r6 can be used 392 assert(i < 5); 393 uint64_t val; 394 val = tc->readIntReg(ArgumentReg0 + i++); 395 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32); 396 return val; 397} 398 399 400void 401ArmLiveProcess::setSyscallArg(ThreadContext *tc, 402 int i, ArmISA::IntReg val) 403{ 404 assert(i < 4); 405 tc->setIntReg(ArgumentReg0 + i, val); 406} 407 408void 409ArmLiveProcess::setSyscallReturn(ThreadContext *tc, 410 SyscallReturn return_value) 411{ 412 tc->setIntReg(ReturnValueReg, return_value.value()); 413} 414