pagetable.hh revision 7436 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_PAGETABLE_H__
44#define __ARCH_ARM_PAGETABLE_H__
45
46#include "arch/arm/isa_traits.hh"
47#include "arch/arm/utility.hh"
48#include "arch/arm/vtophys.hh"
49#include "config/full_system.hh"
50
51namespace ArmISA {
52
53struct VAddr
54{
55    VAddr(Addr a) { panic("not implemented yet."); }
56};
57
58
59// ITB/DTB page table entry
60struct PTE
61{
62    void serialize(std::ostream &os)
63    {
64        panic("Need to implement PTE serialization\n");
65    }
66
67    void unserialize(Checkpoint *cp, const std::string &section)
68    {
69        panic("Need to implement PTE serialization\n");
70    }
71
72};
73
74struct TlbRange
75{
76    Addr va;
77    Addr size;
78    int contextId;
79    bool global;
80
81    inline bool
82    operator<(const TlbRange &r2) const
83    {
84        if (!(global || r2.global)) {
85            if (contextId < r2.contextId)
86                return true;
87            else if (contextId > r2.contextId)
88                return false;
89        }
90
91        if (va < r2.va)
92            return true;
93        return false;
94    }
95
96    inline bool
97    operator==(const TlbRange &r2) const
98    {
99        return va == r2.va &&
100               size == r2.size &&
101               contextId == r2.contextId &&
102               global == r2.global;
103    }
104};
105
106
107// ITB/DTB table entry
108struct TlbEntry
109{
110  public:
111    enum MemoryType {
112        StronglyOrdered,
113        Device,
114        Normal
115    };
116    enum DomainType {
117        DomainNoAccess = 0,
118        DomainClient,
119        DomainReserved,
120        DomainManager
121    };
122
123    // Matching variables
124    Addr pfn;
125    Addr size;              // Size of this entry, == Type of TLB Rec
126    Addr vpn;               // Virtual Page Number
127    uint32_t asid;          // Address Space Identifier
128    uint8_t N;              // Number of bits in pagesize
129    bool global;
130    bool valid;
131
132    // Type of memory
133    bool nonCacheable;     // Can we wrap this in mtype?
134    bool sNp;      // Section descriptor
135
136    // Memory Attributes
137    MemoryType mtype;
138    uint8_t innerAttrs;
139    uint8_t outerAttrs;
140    bool shareable;
141    uint32_t attributes;    // Memory attributes formatted for PAR
142
143
144    // Access permissions
145    bool xn;                // Execute Never
146    uint8_t ap:3;           // Access permissions bits
147    uint8_t domain:4;       // Access Domain
148
149    TlbRange range;         // For fast TLB searching
150
151    //Construct an entry that maps to physical address addr for SE mode
152    TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
153    {
154        pfn = _paddr >> PageShift;
155        size = PageBytes - 1;
156        asid = _asn;
157        global = false;
158        valid = true;
159
160        vpn = _vaddr >> PageShift;
161
162        nonCacheable = sNp = false;
163
164        xn = 0;
165        ap = 0; // ???
166        domain = DomainClient; //???
167    }
168
169    TlbEntry()
170    {}
171
172    void
173    updateVaddr(Addr new_vaddr)
174    {
175        vpn = new_vaddr >> PageShift;
176    }
177
178    Addr
179    pageStart()
180    {
181        return pfn << PageShift;
182    }
183
184    bool
185    match(Addr va, uint8_t cid)
186    {
187        Addr v = vpn << N;
188        if (valid && va >= v && va <= v + size && (global || cid == asid))
189            return true;
190        return false;
191    }
192
193    Addr
194    pAddr(Addr va)
195    {
196        return (pfn << N) | (va & size);
197    }
198
199    void serialize(std::ostream &os) { panic("Need to Implement\n"); }
200    void unserialize(Checkpoint *cp, const std::string &section)
201                   { panic("Need to Implement\n");}
202};
203
204
205
206};
207#endif // __ARCH_ARM_PAGETABLE_H__
208
209