nativetrace.cc revision 6724:70129fdded75
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/arm/isa_traits.hh" 32#include "arch/arm/miscregs.hh" 33#include "arch/arm/nativetrace.hh" 34#include "cpu/thread_context.hh" 35#include "params/ArmNativeTrace.hh" 36 37namespace Trace { 38 39#if TRACING_ON 40static const char *regNames[] = { 41 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 42 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", 43 "cpsr" 44}; 45#endif 46 47void 48Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent) 49{ 50 oldState = state[current]; 51 current = (current + 1) % 2; 52 newState = state[current]; 53 54 memcpy(newState, oldState, sizeof(state[0])); 55 56 uint32_t diffVector; 57 parent->read(&diffVector, sizeof(diffVector)); 58 diffVector = ArmISA::gtoh(diffVector); 59 60 int changes = 0; 61 for (int i = 0; i < STATE_NUMVALS; i++) { 62 if (diffVector & 0x1) { 63 changed[i] = true; 64 changes++; 65 } else { 66 changed[i] = false; 67 } 68 diffVector >>= 1; 69 } 70 71 uint32_t values[changes]; 72 parent->read(values, sizeof(values)); 73 int pos = 0; 74 for (int i = 0; i < STATE_NUMVALS; i++) { 75 if (changed[i]) { 76 newState[i] = ArmISA::gtoh(values[pos++]); 77 changed[i] = (newState[i] != oldState[i]); 78 } 79 } 80} 81 82void 83Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) 84{ 85 oldState = state[current]; 86 current = (current + 1) % 2; 87 newState = state[current]; 88 89 // Regular int regs 90 for (int i = 0; i < 15; i++) { 91 newState[i] = tc->readIntReg(i); 92 changed[i] = (oldState[i] != newState[i]); 93 } 94 95 //R15, aliased with the PC 96 newState[STATE_PC] = tc->readNextPC(); 97 changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]); 98 99 //CPSR 100 newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) | 101 tc->readIntReg(INTREG_CONDCODES); 102 changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); 103} 104 105void 106Trace::ArmNativeTrace::check(NativeTraceRecord *record) 107{ 108 ThreadContext *tc = record->getThread(); 109 // This area is read only on the target. It can't stop there to tell us 110 // what's going on, so we should skip over anything there also. 111 if (tc->readNextPC() > 0xffff0000) 112 return; 113 nState.update(this); 114 mState.update(tc); 115 116 bool errorFound = false; 117 // Regular int regs 118 for (int i = 0; i < STATE_NUMVALS; i++) { 119 if (nState.changed[i] || mState.changed[i]) { 120 const char *vergence = " "; 121 bool oldMatch = (mState.oldState[i] == nState.oldState[i]); 122 bool newMatch = (mState.newState[i] == nState.newState[i]); 123 if (oldMatch && newMatch) { 124 // The more things change, the more they stay the same. 125 continue; 126 } else if (oldMatch && !newMatch) { 127 vergence = "<>"; 128 } else if (!oldMatch && newMatch) { 129 vergence = "><"; 130 } 131 errorFound = true; 132 if (!nState.changed[i]) { 133 DPRINTF(ExecRegDelta, "%s [%5s] "\ 134 "Native: %#010x "\ 135 "M5: %#010x => %#010x\n", 136 vergence, regNames[i], 137 nState.newState[i], 138 mState.oldState[i], mState.newState[i]); 139 } else if (!mState.changed[i]) { 140 DPRINTF(ExecRegDelta, "%s [%5s] "\ 141 "Native: %#010x => %#010x "\ 142 "M5: %#010x \n", 143 vergence, regNames[i], 144 nState.oldState[i], nState.newState[i], 145 mState.newState[i]); 146 } else { 147 DPRINTF(ExecRegDelta, "%s [%5s] "\ 148 "Native: %#010x => %#010x "\ 149 "M5: %#010x => %#010x\n", 150 vergence, regNames[i], 151 nState.oldState[i], nState.newState[i], 152 mState.oldState[i], mState.newState[i]); 153 } 154 } 155 } 156 if (errorFound) { 157 StaticInstPtr inst = record->getStaticInst(); 158 assert(inst); 159 bool ran = true; 160 if (inst->isMicroop()) { 161 ran = false; 162 inst = record->getMacroStaticInst(); 163 } 164 assert(inst); 165 record->traceInst(inst, ran); 166 167 bool pcError = (mState.newState[STATE_PC] != 168 nState.newState[STATE_PC]); 169 if (stopOnPCError && pcError) 170 panic("Native trace detected an error in control flow!"); 171 } 172} 173 174} /* namespace Trace */ 175 176//////////////////////////////////////////////////////////////////////// 177// 178// ExeTracer Simulation Object 179// 180Trace::ArmNativeTrace * 181ArmNativeTraceParams::create() 182{ 183 return new Trace::ArmNativeTrace(this); 184}; 185