nativetrace.cc revision 6410:362e27c08d96 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/arm/isa_traits.hh"
32#include "arch/arm/miscregs.hh"
33#include "arch/arm/nativetrace.hh"
34#include "cpu/thread_context.hh"
35#include "params/ArmNativeTrace.hh"
36
37namespace Trace {
38
39#if TRACING_ON
40static const char *regNames[] = {
41    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
42    "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
43    "cpsr"
44};
45#endif
46
47void
48Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
49{
50    oldState = state[current];
51    current = (current + 1) % 2;
52    newState = state[current];
53
54    parent->read(newState, sizeof(newState[0]) * STATE_NUMVALS);
55    for (int i = 0; i < STATE_NUMVALS; i++) {
56        newState[i] = ArmISA::gtoh(newState[i]);
57        changed[i] = (oldState[i] != newState[i]);
58    }
59}
60
61void
62Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
63{
64    oldState = state[current];
65    current = (current + 1) % 2;
66    newState = state[current];
67
68    // Regular int regs
69    for (int i = 0; i < 15; i++) {
70        newState[i] = tc->readIntReg(i);
71        changed[i] = (oldState[i] != newState[i]);
72    }
73
74    //R15, aliased with the PC
75    newState[STATE_PC] = tc->readNextPC();
76    changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
77
78    //CPSR
79    newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR);
80    changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
81}
82
83void
84Trace::ArmNativeTrace::check(NativeTraceRecord *record)
85{
86    nState.update(this);
87    mState.update(record->getThread());
88
89    bool errorFound = false;
90    // Regular int regs
91    for (int i = 0; i < STATE_NUMVALS; i++) {
92        if (nState.changed[i] || mState.changed[i]) {
93            const char *vergence = "  ";
94            bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
95            bool newMatch = (mState.newState[i] == nState.newState[i]);
96            if (oldMatch && newMatch) {
97                // The more things change, the more they stay the same.
98                continue;
99            } else if (oldMatch && !newMatch) {
100                vergence = "<>";
101            } else if (!oldMatch && newMatch) {
102                vergence = "><";
103            }
104            errorFound = true;
105            if (!nState.changed[i]) {
106                DPRINTF(ExecRegDelta, "%s [%5s] "\
107                                      "Native:         %#010x         "\
108                                      "M5:     %#010x => %#010x\n",
109                                      vergence, regNames[i],
110                                      nState.newState[i],
111                                      mState.oldState[i], mState.newState[i]);
112            } else if (!mState.changed[i]) {
113                DPRINTF(ExecRegDelta, "%s [%5s] "\
114                                      "Native: %#010x => %#010x "\
115                                      "M5:             %#010x        \n",
116                                      vergence, regNames[i],
117                                      nState.oldState[i], nState.newState[i],
118                                      mState.newState[i]);
119            } else {
120                DPRINTF(ExecRegDelta, "%s [%5s] "\
121                                      "Native: %#010x => %#010x "\
122                                      "M5:     %#010x => %#010x\n",
123                                      vergence, regNames[i],
124                                      nState.oldState[i], nState.newState[i],
125                                      mState.oldState[i], mState.newState[i]);
126            }
127        }
128    }
129    if (errorFound) {
130        StaticInstPtr inst = record->getStaticInst();
131        assert(inst);
132        bool ran = true;
133        if (inst->isMicroop()) {
134            ran = false;
135            inst = record->getMacroStaticInst();
136        }
137        assert(inst);
138        record->traceInst(inst, ran);
139    }
140}
141
142} /* namespace Trace */
143
144////////////////////////////////////////////////////////////////////////
145//
146//  ExeTracer Simulation Object
147//
148Trace::ArmNativeTrace *
149ArmNativeTraceParams::create()
150{
151    return new Trace::ArmNativeTrace(this);
152};
153