nativetrace.cc revision 6409
14776SN/A/* 26365SN/A * Copyright (c) 2006 The Regents of The University of Michigan 34776SN/A * All rights reserved. 44776SN/A * 54776SN/A * Redistribution and use in source and binary forms, with or without 64776SN/A * modification, are permitted provided that the following conditions are 74776SN/A * met: redistributions of source code must retain the above copyright 84776SN/A * notice, this list of conditions and the following disclaimer; 94776SN/A * redistributions in binary form must reproduce the above copyright 104776SN/A * notice, this list of conditions and the following disclaimer in the 114776SN/A * documentation and/or other materials provided with the distribution; 124776SN/A * neither the name of the copyright holders nor the names of its 134776SN/A * contributors may be used to endorse or promote products derived from 144776SN/A * this software without specific prior written permission. 154776SN/A * 164776SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174776SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184776SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194776SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204776SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214776SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224776SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234776SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244776SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254776SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264776SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274776SN/A * 286365SN/A * Authors: Gabe Black 294776SN/A */ 304776SN/A 316397Sgblack@eecs.umich.edu#include "arch/arm/isa_traits.hh" 326397Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 336397Sgblack@eecs.umich.edu#include "arch/arm/nativetrace.hh" 344776SN/A#include "cpu/thread_context.hh" 356397Sgblack@eecs.umich.edu#include "params/ArmNativeTrace.hh" 364776SN/A 374776SN/Anamespace Trace { 384776SN/A 396398Sgblack@eecs.umich.edu#if TRACING_ON 406397Sgblack@eecs.umich.edustatic const char *regNames[] = { 416397Sgblack@eecs.umich.edu "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 426397Sgblack@eecs.umich.edu "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", 436397Sgblack@eecs.umich.edu "cpsr" 446365SN/A}; 456398Sgblack@eecs.umich.edu#endif 466398Sgblack@eecs.umich.edu 476398Sgblack@eecs.umich.eduvoid 486398Sgblack@eecs.umich.eduTrace::ArmNativeTrace::ThreadState::update(NativeTrace *parent) 496398Sgblack@eecs.umich.edu{ 506398Sgblack@eecs.umich.edu oldState = state[current]; 516398Sgblack@eecs.umich.edu current = (current + 1) % 2; 526398Sgblack@eecs.umich.edu newState = state[current]; 536398Sgblack@eecs.umich.edu 546398Sgblack@eecs.umich.edu parent->read(newState, sizeof(newState[0]) * STATE_NUMVALS); 556398Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 566398Sgblack@eecs.umich.edu newState[i] = ArmISA::gtoh(newState[i]); 576398Sgblack@eecs.umich.edu changed[i] = (oldState[i] != newState[i]); 586398Sgblack@eecs.umich.edu } 596398Sgblack@eecs.umich.edu} 606398Sgblack@eecs.umich.edu 616398Sgblack@eecs.umich.eduvoid 626398Sgblack@eecs.umich.eduTrace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) 636398Sgblack@eecs.umich.edu{ 646398Sgblack@eecs.umich.edu oldState = state[current]; 656398Sgblack@eecs.umich.edu current = (current + 1) % 2; 666398Sgblack@eecs.umich.edu newState = state[current]; 676398Sgblack@eecs.umich.edu 686398Sgblack@eecs.umich.edu // Regular int regs 696398Sgblack@eecs.umich.edu for (int i = 0; i < 15; i++) { 706398Sgblack@eecs.umich.edu newState[i] = tc->readIntReg(i); 716398Sgblack@eecs.umich.edu changed[i] = (oldState[i] != newState[i]); 726398Sgblack@eecs.umich.edu } 736398Sgblack@eecs.umich.edu 746398Sgblack@eecs.umich.edu //R15, aliased with the PC 756398Sgblack@eecs.umich.edu newState[STATE_PC] = tc->readNextPC(); 766398Sgblack@eecs.umich.edu changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]); 776398Sgblack@eecs.umich.edu 786398Sgblack@eecs.umich.edu //CPSR 796398Sgblack@eecs.umich.edu newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR); 806398Sgblack@eecs.umich.edu changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); 816398Sgblack@eecs.umich.edu} 826365SN/A 836365SN/Avoid 846397Sgblack@eecs.umich.eduTrace::ArmNativeTrace::check(NativeTraceRecord *record) 854776SN/A{ 866398Sgblack@eecs.umich.edu nState.update(this); 876398Sgblack@eecs.umich.edu mState.update(record->getThread()); 885523SN/A 896409Sgblack@eecs.umich.edu bool errorFound = false; 906397Sgblack@eecs.umich.edu // Regular int regs 916398Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 926398Sgblack@eecs.umich.edu if (nState.changed[i] || mState.changed[i]) { 936398Sgblack@eecs.umich.edu const char *vergence = " "; 946398Sgblack@eecs.umich.edu if (mState.oldState[i] == nState.oldState[i] && 956398Sgblack@eecs.umich.edu mState.newState[i] != nState.newState[i]) { 966398Sgblack@eecs.umich.edu vergence = "<>"; 976398Sgblack@eecs.umich.edu } else if (mState.oldState[i] != nState.oldState[i] && 986398Sgblack@eecs.umich.edu mState.newState[i] == nState.newState[i]) { 996398Sgblack@eecs.umich.edu vergence = "><"; 1006398Sgblack@eecs.umich.edu } 1016398Sgblack@eecs.umich.edu if (!nState.changed[i]) { 1026398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1036398Sgblack@eecs.umich.edu "Native: %#010x "\ 1046398Sgblack@eecs.umich.edu "M5: %#010x => %#010x\n", 1056398Sgblack@eecs.umich.edu vergence, regNames[i], 1066398Sgblack@eecs.umich.edu nState.newState[i], 1076398Sgblack@eecs.umich.edu mState.oldState[i], mState.newState[i]); 1086409Sgblack@eecs.umich.edu errorFound = true; 1096398Sgblack@eecs.umich.edu } else if (!mState.changed[i]) { 1106398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1116398Sgblack@eecs.umich.edu "Native: %#010x => %#010x "\ 1126398Sgblack@eecs.umich.edu "M5: %#010x \n", 1136398Sgblack@eecs.umich.edu vergence, regNames[i], 1146398Sgblack@eecs.umich.edu nState.oldState[i], nState.newState[i], 1156398Sgblack@eecs.umich.edu mState.newState[i]); 1166409Sgblack@eecs.umich.edu errorFound = true; 1176398Sgblack@eecs.umich.edu } else if (mState.oldState[i] != nState.oldState[i] || 1186398Sgblack@eecs.umich.edu mState.newState[i] != nState.newState[i]) { 1196398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1206398Sgblack@eecs.umich.edu "Native: %#010x => %#010x "\ 1216398Sgblack@eecs.umich.edu "M5: %#010x => %#010x\n", 1226398Sgblack@eecs.umich.edu vergence, regNames[i], 1236398Sgblack@eecs.umich.edu nState.oldState[i], nState.newState[i], 1246398Sgblack@eecs.umich.edu mState.oldState[i], mState.newState[i]); 1256409Sgblack@eecs.umich.edu errorFound = true; 1266398Sgblack@eecs.umich.edu } 1276398Sgblack@eecs.umich.edu } 1284776SN/A } 1296409Sgblack@eecs.umich.edu if (errorFound) { 1306409Sgblack@eecs.umich.edu StaticInstPtr inst = record->getStaticInst(); 1316409Sgblack@eecs.umich.edu assert(inst); 1326409Sgblack@eecs.umich.edu bool ran = true; 1336409Sgblack@eecs.umich.edu if (inst->isMicroop()) { 1346409Sgblack@eecs.umich.edu ran = false; 1356409Sgblack@eecs.umich.edu inst = record->getMacroStaticInst(); 1366409Sgblack@eecs.umich.edu } 1376409Sgblack@eecs.umich.edu assert(inst); 1386409Sgblack@eecs.umich.edu record->traceInst(inst, ran); 1396409Sgblack@eecs.umich.edu } 1404776SN/A} 1414776SN/A 1426365SN/A} /* namespace Trace */ 1434776SN/A 1444776SN/A//////////////////////////////////////////////////////////////////////// 1454776SN/A// 1464776SN/A// ExeTracer Simulation Object 1474776SN/A// 1486397Sgblack@eecs.umich.eduTrace::ArmNativeTrace * 1496397Sgblack@eecs.umich.eduArmNativeTraceParams::create() 1504776SN/A{ 1516397Sgblack@eecs.umich.edu return new Trace::ArmNativeTrace(this); 1524776SN/A}; 153