nativetrace.cc revision 6365
12329SN/A/* 22329SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32329SN/A * All rights reserved. 42329SN/A * 52329SN/A * Redistribution and use in source and binary forms, with or without 62329SN/A * modification, are permitted provided that the following conditions are 72329SN/A * met: redistributions of source code must retain the above copyright 82329SN/A * notice, this list of conditions and the following disclaimer; 92329SN/A * redistributions in binary form must reproduce the above copyright 102329SN/A * notice, this list of conditions and the following disclaimer in the 112329SN/A * documentation and/or other materials provided with the distribution; 122329SN/A * neither the name of the copyright holders nor the names of its 132329SN/A * contributors may be used to endorse or promote products derived from 142329SN/A * this software without specific prior written permission. 152329SN/A * 162329SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172329SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182329SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192329SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202329SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212329SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222329SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232329SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242329SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252329SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262329SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Gabe Black 292329SN/A */ 302292SN/A 312292SN/A#include "arch/sparc/isa_traits.hh" 322292SN/A#include "arch/sparc/registers.hh" 332292SN/A#include "arch/sparc/nativetrace.hh" 342680Sktlim@umich.edu#include "cpu/thread_context.hh" 352292SN/A#include "params/SparcNativeTrace.hh" 362292SN/A 372292SN/Anamespace Trace { 382292SN/A 392292SN/Astatic char *intRegNames[SparcISA::NumIntArchRegs] = { 402292SN/A //Global registers 412292SN/A "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 422292SN/A //Output registers 432292SN/A "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", 442292SN/A //Local registers 452329SN/A "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 462292SN/A //Input registers 472292SN/A "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", 482292SN/A}; 492329SN/A 502329SN/Avoid 512329SN/ATrace::SparcNativeTrace::check(NativeTraceRecord *record) 522680Sktlim@umich.edu{ 532680Sktlim@umich.edu ThreadContext *tc = record->getThread(); 542329SN/A 552329SN/A uint64_t regVal, realRegVal; 562292SN/A 572292SN/A // Integer registers 582680Sktlim@umich.edu 592733Sktlim@umich.edu // I doubt a real SPARC will describe more integer registers than this. 602292SN/A assert(SparcISA::NumIntArchRegs == 32); 612292SN/A char **regName = intRegNames; 622348SN/A for (int i = 0; i < SparcISA::NumIntArchRegs; i++) { 632733Sktlim@umich.edu regVal = tc->readIntReg(i); 642292SN/A read(&realRegVal, sizeof(realRegVal)); 652348SN/A realRegVal = SparcISA::gtoh(realRegVal); 662348SN/A checkReg(*(regName++), regVal, realRegVal); 672348SN/A } 682292SN/A 692292SN/A // PC 702348SN/A read(&realRegVal, sizeof(realRegVal)); 712348SN/A realRegVal = SparcISA::gtoh(realRegVal); 722348SN/A regVal = tc->readNextPC(); 732292SN/A checkReg("pc", regVal, realRegVal); 742292SN/A 752292SN/A // NPC 762733Sktlim@umich.edu read(&realRegVal, sizeof(realRegVal)); 772683Sktlim@umich.edu realRegVal = SparcISA::gtoh(realRegVal); 782292SN/A regVal = tc->readNextNPC(); 792292SN/A checkReg("npc", regVal, realRegVal); 802292SN/A 812733Sktlim@umich.edu // CCR 822678Sktlim@umich.edu read(&realRegVal, sizeof(realRegVal)); 832791Sktlim@umich.edu realRegVal = SparcISA::gtoh(realRegVal); 842292SN/A regVal = tc->readIntReg(SparcISA::NumIntArchRegs + 2); 852292SN/A checkReg("ccr", regVal, realRegVal); 862292SN/A} 872292SN/A 882680Sktlim@umich.edu} /* namespace Trace */ 892680Sktlim@umich.edu 902292SN/A//////////////////////////////////////////////////////////////////////// 912680Sktlim@umich.edu// 922680Sktlim@umich.edu// ExeTracer Simulation Object 932292SN/A// 942292SN/ATrace::SparcNativeTrace * 952348SN/ASparcNativeTraceParams::create() 962680Sktlim@umich.edu{ 972292SN/A return new Trace::SparcNativeTrace(this); 982292SN/A}; 992292SN/A