miscregs.hh revision 9431:8bb372a49e1b
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 45#include "base/bitunion.hh" 46#include "base/compiler.hh" 47 48namespace ArmISA 49{ 50 enum ConditionCode { 51 COND_EQ = 0, 52 COND_NE, // 1 53 COND_CS, // 2 54 COND_CC, // 3 55 COND_MI, // 4 56 COND_PL, // 5 57 COND_VS, // 6 58 COND_VC, // 7 59 COND_HI, // 8 60 COND_LS, // 9 61 COND_GE, // 10 62 COND_LT, // 11 63 COND_GT, // 12 64 COND_LE, // 13 65 COND_AL, // 14 66 COND_UC // 15 67 }; 68 69 enum MiscRegIndex { 70 MISCREG_CPSR = 0, 71 MISCREG_CPSR_Q, 72 MISCREG_SPSR, 73 MISCREG_SPSR_FIQ, 74 MISCREG_SPSR_IRQ, 75 MISCREG_SPSR_SVC, 76 MISCREG_SPSR_MON, 77 MISCREG_SPSR_UND, 78 MISCREG_SPSR_ABT, 79 MISCREG_FPSR, 80 MISCREG_FPSID, 81 MISCREG_FPSCR, 82 MISCREG_FPSCR_QC, // Cumulative saturation flag 83 MISCREG_FPSCR_EXC, // Cumulative FP exception flags 84 MISCREG_FPEXC, 85 MISCREG_MVFR0, 86 MISCREG_MVFR1, 87 MISCREG_SCTLR_RST, 88 MISCREG_SEV_MAILBOX, 89 90 // CP14 registers 91 MISCREG_CP14_START, 92 MISCREG_DBGDIDR = MISCREG_CP14_START, 93 MISCREG_DBGDSCR_INT, 94 MISCREG_DBGDTRRX_INT, 95 MISCREG_DBGTRTX_INT, 96 MISCREG_DBGWFAR, 97 MISCREG_DBGVCR, 98 MISCREG_DBGECR, 99 MISCREG_DBGDSCCR, 100 MISCREG_DBGSMCR, 101 MISCREG_DBGDTRRX_EXT, 102 MISCREG_DBGDSCR_EXT, 103 MISCREG_DBGDTRTX_EXT, 104 MISCREG_DBGDRCR, 105 MISCREG_DBGBVR, 106 MISCREG_DBGBCR, 107 MISCREG_DBGBVR_M, 108 MISCREG_DBGBCR_M, 109 MISCREG_DBGDRAR, 110 MISCREG_DBGBXVR_M, 111 MISCREG_DBGOSLAR, 112 MISCREG_DBGOSSRR, 113 MISCREG_DBGOSDLR, 114 MISCREG_DBGPRCR, 115 MISCREG_DBGPRSR, 116 MISCREG_DBGDSAR, 117 MISCREG_DBGITCTRL, 118 MISCREG_DBGCLAIMSET, 119 MISCREG_DBGCLAIMCLR, 120 MISCREG_DBGAUTHSTATUS, 121 MISCREG_DBGDEVID2, 122 MISCREG_DBGDEVID1, 123 MISCREG_DBGDEVID, 124 125 // CP15 registers 126 MISCREG_CP15_START, 127 MISCREG_SCTLR = MISCREG_CP15_START, 128 MISCREG_DCCISW, 129 MISCREG_DCCIMVAC, 130 MISCREG_DCCMVAC, 131 MISCREG_CONTEXTIDR, 132 MISCREG_TPIDRURW, 133 MISCREG_TPIDRURO, 134 MISCREG_TPIDRPRW, 135 MISCREG_CP15ISB, 136 MISCREG_CP15DSB, 137 MISCREG_CP15DMB, 138 MISCREG_CPACR, 139 MISCREG_CLIDR, 140 MISCREG_CCSIDR, 141 MISCREG_CSSELR, 142 MISCREG_ICIALLUIS, 143 MISCREG_ICIALLU, 144 MISCREG_ICIMVAU, 145 MISCREG_BPIMVA, 146 MISCREG_BPIALLIS, 147 MISCREG_BPIALL, 148 MISCREG_MIDR, 149 MISCREG_TTBR0, 150 MISCREG_TTBR1, 151 MISCREG_TLBTR, 152 MISCREG_DACR, 153 MISCREG_TLBIALLIS, 154 MISCREG_TLBIMVAIS, 155 MISCREG_TLBIASIDIS, 156 MISCREG_TLBIMVAAIS, 157 MISCREG_ITLBIALL, 158 MISCREG_ITLBIMVA, 159 MISCREG_ITLBIASID, 160 MISCREG_DTLBIALL, 161 MISCREG_DTLBIMVA, 162 MISCREG_DTLBIASID, 163 MISCREG_TLBIALL, 164 MISCREG_TLBIMVA, 165 MISCREG_TLBIASID, 166 MISCREG_TLBIMVAA, 167 MISCREG_DFSR, 168 MISCREG_IFSR, 169 MISCREG_DFAR, 170 MISCREG_IFAR, 171 MISCREG_MPIDR, 172 MISCREG_PRRR, 173 MISCREG_NMRR, 174 MISCREG_TTBCR, 175 MISCREG_ID_PFR0, 176 MISCREG_CTR, 177 MISCREG_SCR, 178 MISCREG_SDER, 179 MISCREG_PAR, 180 MISCREG_V2PCWPR, 181 MISCREG_V2PCWPW, 182 MISCREG_V2PCWUR, 183 MISCREG_V2PCWUW, 184 MISCREG_V2POWPR, 185 MISCREG_V2POWPW, 186 MISCREG_V2POWUR, 187 MISCREG_V2POWUW, 188 MISCREG_ID_MMFR0, 189 MISCREG_ID_MMFR2, 190 MISCREG_ID_MMFR3, 191 MISCREG_ACTLR, 192 MISCREG_PMCR, 193 MISCREG_PMCCNTR, 194 MISCREG_PMCNTENSET, 195 MISCREG_PMCNTENCLR, 196 MISCREG_PMOVSR, 197 MISCREG_PMSWINC, 198 MISCREG_PMSELR, 199 MISCREG_PMCEID0, 200 MISCREG_PMCEID1, 201 MISCREG_PMC_OTHER, 202 MISCREG_PMXEVCNTR, 203 MISCREG_PMUSERENR, 204 MISCREG_PMINTENSET, 205 MISCREG_PMINTENCLR, 206 MISCREG_ID_ISAR0, 207 MISCREG_ID_ISAR1, 208 MISCREG_ID_ISAR2, 209 MISCREG_ID_ISAR3, 210 MISCREG_ID_ISAR4, 211 MISCREG_ID_ISAR5, 212 MISCREG_LOCKFLAG, 213 MISCREG_LOCKADDR, 214 MISCREG_ID_PFR1, 215 MISCREG_L2CTLR, 216 MISCREG_CP15_UNIMP_START, 217 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 218 MISCREG_ID_DFR0, 219 MISCREG_ID_AFR0, 220 MISCREG_ID_MMFR1, 221 MISCREG_AIDR, 222 MISCREG_ADFSR, 223 MISCREG_AIFSR, 224 MISCREG_DCIMVAC, 225 MISCREG_DCISW, 226 MISCREG_MCCSW, 227 MISCREG_DCCMVAU, 228 MISCREG_NSACR, 229 MISCREG_VBAR, 230 MISCREG_MVBAR, 231 MISCREG_ISR, 232 MISCREG_FCEIDR, 233 MISCREG_L2LATENCY, 234 MISCREG_CRN15, 235 236 237 MISCREG_CP15_END, 238 239 // Dummy indices 240 MISCREG_NOP = MISCREG_CP15_END, 241 MISCREG_RAZ, 242 243 NUM_MISCREGS 244 }; 245 246 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 247 unsigned crm, unsigned opc2); 248 249 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 250 unsigned crm, unsigned opc2); 251 252 253 const char * const miscRegName[] = { 254 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 255 "spsr_mon", "spsr_und", "spsr_abt", 256 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 257 "mvfr0", "mvfr1", 258 "sctlr_rst", "sev_mailbox", 259 "DBGDIDR", 260 "DBGDSCR_INT", 261 "DBGDTRRX_INT", 262 "DBGTRTX_INT", 263 "DBGWFAR", 264 "DBGVCR", 265 "DBGECR", 266 "DBGDSCCR", 267 "DBGSMCR", 268 "DBGDTRRX_EXT", 269 "DBGDSCR_EXT", 270 "DBGDTRTX_EXT", 271 "DBGDRCR", 272 "DBGBVR", 273 "DBGBCR", 274 "DBGBVR_M", 275 "DBGBCR_M", 276 "DBGDRAR", 277 "DBGBXVR_M", 278 "DBGOSLAR", 279 "DBGOSSRR", 280 "DBGOSDLR", 281 "DBGPRCR", 282 "DBGPRSR", 283 "DBGDSAR", 284 "DBGITCTRL", 285 "DBGCLAIMSET", 286 "DBGCLAIMCLR", 287 "DBGAUTHSTATUS", 288 "DBGDEVID2", 289 "DBGDEVID1", 290 "DBGDEVID", 291 "sctlr", "dccisw", "dccimvac", "dccmvac", 292 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 293 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 294 "clidr", "ccsidr", "csselr", 295 "icialluis", "iciallu", "icimvau", 296 "bpimva", "bpiallis", "bpiall", 297 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 298 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 299 "itlbiall", "itlbimva", "itlbiasid", 300 "dtlbiall", "dtlbimva", "dtlbiasid", 301 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 302 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 303 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 304 "scr", "sder", "par", 305 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 306 "v2powpr", "v2powpw", "v2powur", "v2powuw", 307 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr", 308 "pmcntenset", "pmcntenclr", "pmovsr", 309 "pmswinc", "pmselr", "pmceid0", 310 "pmceid1", "pmc_other", "pmxevcntr", 311 "pmuserenr", "pmintenset", "pmintenclr", 312 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 313 "lockflag", "lockaddr", "id_pfr1", 314 "l2ctlr", 315 // Unimplemented below 316 "tcmtr", 317 "id_dfr0", "id_afr0", 318 "id_mmfr1", 319 "aidr", "adfsr", "aifsr", 320 "dcimvac", "dcisw", "mccsw", 321 "dccmvau", 322 "nsacr", 323 "vbar", "mvbar", "isr", "fceidr", "l2latency", 324 "crn15", 325 "nop", "raz" 326 }; 327 328 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 329 "The miscRegName array and NUM_MISCREGS are inconsistent."); 330 331 BitUnion32(CPSR) 332 Bitfield<31,30> nz; 333 Bitfield<29> c; 334 Bitfield<28> v; 335 Bitfield<27> q; 336 Bitfield<26,25> it1; 337 Bitfield<24> j; 338 Bitfield<19, 16> ge; 339 Bitfield<15,10> it2; 340 Bitfield<9> e; 341 Bitfield<8> a; 342 Bitfield<7> i; 343 Bitfield<6> f; 344 Bitfield<5> t; 345 Bitfield<4, 0> mode; 346 EndBitUnion(CPSR) 347 348 // This mask selects bits of the CPSR that actually go in the CondCodes 349 // integer register to allow renaming. 350 static const uint32_t CondCodesMask = 0xF00F0000; 351 static const uint32_t CpsrMaskQ = 0x08000000; 352 353 BitUnion32(SCTLR) 354 Bitfield<31> ie; // Instruction endianness 355 Bitfield<30> te; // Thumb Exception Enable 356 Bitfield<29> afe; // Access flag enable 357 Bitfield<28> tre; // TEX Remap bit 358 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 359 Bitfield<25> ee; // Exception Endianness bit 360 Bitfield<24> ve; // Interrupt vectors enable 361 Bitfield<23> xp; // Extended page table enable bit 362 Bitfield<22> u; // Alignment (now unused) 363 Bitfield<21> fi; // Fast interrupts configuration enable 364 Bitfield<19> dz; // Divide by Zero fault enable bit 365 Bitfield<18> rao2;// Read as one 366 Bitfield<17> br; // Background region bit 367 Bitfield<16> rao3;// Read as one 368 Bitfield<14> rr; // Round robin cache replacement 369 Bitfield<13> v; // Base address for exception vectors 370 Bitfield<12> i; // instruction cache enable 371 Bitfield<11> z; // branch prediction enable bit 372 Bitfield<10> sw; // Enable swp/swpb 373 Bitfield<9,8> rs; // deprecated protection bits 374 Bitfield<6,3> rao4;// Read as one 375 Bitfield<7> b; // Endianness support (unused) 376 Bitfield<2> c; // Cache enable bit 377 Bitfield<1> a; // Alignment fault checking 378 Bitfield<0> m; // MMU enable bit 379 EndBitUnion(SCTLR) 380 381 BitUnion32(CPACR) 382 Bitfield<1, 0> cp0; 383 Bitfield<3, 2> cp1; 384 Bitfield<5, 4> cp2; 385 Bitfield<7, 6> cp3; 386 Bitfield<9, 8> cp4; 387 Bitfield<11, 10> cp5; 388 Bitfield<13, 12> cp6; 389 Bitfield<15, 14> cp7; 390 Bitfield<17, 16> cp8; 391 Bitfield<19, 18> cp9; 392 Bitfield<21, 20> cp10; 393 Bitfield<23, 22> cp11; 394 Bitfield<25, 24> cp12; 395 Bitfield<27, 26> cp13; 396 Bitfield<29, 28> rsvd; 397 Bitfield<30> d32dis; 398 Bitfield<31> asedis; 399 EndBitUnion(CPACR) 400 401 BitUnion32(FSR) 402 Bitfield<3, 0> fsLow; 403 Bitfield<7, 4> domain; 404 Bitfield<10> fsHigh; 405 Bitfield<11> wnr; 406 Bitfield<12> ext; 407 EndBitUnion(FSR) 408 409 BitUnion32(FPSCR) 410 Bitfield<0> ioc; 411 Bitfield<1> dzc; 412 Bitfield<2> ofc; 413 Bitfield<3> ufc; 414 Bitfield<4> ixc; 415 Bitfield<7> idc; 416 Bitfield<8> ioe; 417 Bitfield<9> dze; 418 Bitfield<10> ofe; 419 Bitfield<11> ufe; 420 Bitfield<12> ixe; 421 Bitfield<15> ide; 422 Bitfield<18, 16> len; 423 Bitfield<21, 20> stride; 424 Bitfield<23, 22> rMode; 425 Bitfield<24> fz; 426 Bitfield<25> dn; 427 Bitfield<26> ahp; 428 Bitfield<27> qc; 429 Bitfield<28> v; 430 Bitfield<29> c; 431 Bitfield<30> z; 432 Bitfield<31> n; 433 EndBitUnion(FPSCR) 434 435 // This mask selects bits of the FPSCR that actually go in the FpCondCodes 436 // integer register to allow renaming. 437 static const uint32_t FpCondCodesMask = 0xF0000000; 438 // This mask selects the cumulative FP exception flags of the FPSCR. 439 static const uint32_t FpscrExcMask = 0x0000009F; 440 // This mask selects the cumulative saturation flag of the FPSCR. 441 static const uint32_t FpscrQcMask = 0x08000000; 442 443 BitUnion32(FPEXC) 444 Bitfield<31> ex; 445 Bitfield<30> en; 446 Bitfield<29, 0> subArchDefined; 447 EndBitUnion(FPEXC) 448 449 BitUnion32(MVFR0) 450 Bitfield<3, 0> advSimdRegisters; 451 Bitfield<7, 4> singlePrecision; 452 Bitfield<11, 8> doublePrecision; 453 Bitfield<15, 12> vfpExceptionTrapping; 454 Bitfield<19, 16> divide; 455 Bitfield<23, 20> squareRoot; 456 Bitfield<27, 24> shortVectors; 457 Bitfield<31, 28> roundingModes; 458 EndBitUnion(MVFR0) 459 460 BitUnion32(MVFR1) 461 Bitfield<3, 0> flushToZero; 462 Bitfield<7, 4> defaultNaN; 463 Bitfield<11, 8> advSimdLoadStore; 464 Bitfield<15, 12> advSimdInteger; 465 Bitfield<19, 16> advSimdSinglePrecision; 466 Bitfield<23, 20> advSimdHalfPrecision; 467 Bitfield<27, 24> vfpHalfPrecision; 468 Bitfield<31, 28> raz; 469 EndBitUnion(MVFR1) 470 471 BitUnion32(PRRR) 472 Bitfield<1,0> tr0; 473 Bitfield<3,2> tr1; 474 Bitfield<5,4> tr2; 475 Bitfield<7,6> tr3; 476 Bitfield<9,8> tr4; 477 Bitfield<11,10> tr5; 478 Bitfield<13,12> tr6; 479 Bitfield<15,14> tr7; 480 Bitfield<16> ds0; 481 Bitfield<17> ds1; 482 Bitfield<18> ns0; 483 Bitfield<19> ns1; 484 Bitfield<24> nos0; 485 Bitfield<25> nos1; 486 Bitfield<26> nos2; 487 Bitfield<27> nos3; 488 Bitfield<28> nos4; 489 Bitfield<29> nos5; 490 Bitfield<30> nos6; 491 Bitfield<31> nos7; 492 EndBitUnion(PRRR) 493 494 BitUnion32(NMRR) 495 Bitfield<1,0> ir0; 496 Bitfield<3,2> ir1; 497 Bitfield<5,4> ir2; 498 Bitfield<7,6> ir3; 499 Bitfield<9,8> ir4; 500 Bitfield<11,10> ir5; 501 Bitfield<13,12> ir6; 502 Bitfield<15,14> ir7; 503 Bitfield<17,16> or0; 504 Bitfield<19,18> or1; 505 Bitfield<21,20> or2; 506 Bitfield<23,22> or3; 507 Bitfield<25,24> or4; 508 Bitfield<27,26> or5; 509 Bitfield<29,28> or6; 510 Bitfield<31,30> or7; 511 EndBitUnion(NMRR) 512 513 BitUnion32(CONTEXTIDR) 514 Bitfield<7,0> asid; 515 Bitfield<31,8> procid; 516 EndBitUnion(CONTEXTIDR) 517 518 BitUnion32(L2CTLR) 519 Bitfield<2,0> sataRAMLatency; 520 Bitfield<4,3> reserved_4_3; 521 Bitfield<5> dataRAMSetup; 522 Bitfield<8,6> tagRAMLatency; 523 Bitfield<9> tagRAMSetup; 524 Bitfield<11,10> dataRAMSlice; 525 Bitfield<12> tagRAMSlice; 526 Bitfield<20,13> reserved_20_13; 527 Bitfield<21> eccandParityEnable; 528 Bitfield<22> reserved_22; 529 Bitfield<23> interptCtrlPresent; 530 Bitfield<25,24> numCPUs; 531 Bitfield<30,26> reserved_30_26; 532 Bitfield<31> l2rstDISABLE_monitor; 533 EndBitUnion(L2CTLR) 534 535 BitUnion32(CTR) 536 Bitfield<3,0> iCacheLineSize; 537 Bitfield<13,4> raz_13_4; 538 Bitfield<15,14> l1IndexPolicy; 539 Bitfield<19,16> dCacheLineSize; 540 Bitfield<23,20> erg; 541 Bitfield<27,24> cwg; 542 Bitfield<28> raz_28; 543 Bitfield<31,29> format; 544 EndBitUnion(CTR) 545} 546 547#endif // __ARCH_ARM_MISCREGS_HH__ 548