miscregs.hh revision 8205:7ecbffb674aa
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 45#include "base/bitunion.hh" 46 47namespace ArmISA 48{ 49 enum ConditionCode { 50 COND_EQ = 0, 51 COND_NE, // 1 52 COND_CS, // 2 53 COND_CC, // 3 54 COND_MI, // 4 55 COND_PL, // 5 56 COND_VS, // 6 57 COND_VC, // 7 58 COND_HI, // 8 59 COND_LS, // 9 60 COND_GE, // 10 61 COND_LT, // 11 62 COND_GT, // 12 63 COND_LE, // 13 64 COND_AL, // 14 65 COND_UC // 15 66 }; 67 68 enum MiscRegIndex { 69 MISCREG_CPSR = 0, 70 MISCREG_SPSR, 71 MISCREG_SPSR_FIQ, 72 MISCREG_SPSR_IRQ, 73 MISCREG_SPSR_SVC, 74 MISCREG_SPSR_MON, 75 MISCREG_SPSR_UND, 76 MISCREG_SPSR_ABT, 77 MISCREG_FPSR, 78 MISCREG_FPSID, 79 MISCREG_FPSCR, 80 MISCREG_FPSCR_QC, // Cumulative saturation flag 81 MISCREG_FPSCR_EXC, // Cumulative FP exception flags 82 MISCREG_FPEXC, 83 MISCREG_MVFR0, 84 MISCREG_MVFR1, 85 MISCREG_SCTLR_RST, 86 MISCREG_SEV_MAILBOX, 87 88 // CP15 registers 89 MISCREG_CP15_START, 90 MISCREG_SCTLR = MISCREG_CP15_START, 91 MISCREG_DCCISW, 92 MISCREG_DCCIMVAC, 93 MISCREG_DCCMVAC, 94 MISCREG_CONTEXTIDR, 95 MISCREG_TPIDRURW, 96 MISCREG_TPIDRURO, 97 MISCREG_TPIDRPRW, 98 MISCREG_CP15ISB, 99 MISCREG_CP15DSB, 100 MISCREG_CP15DMB, 101 MISCREG_CPACR, 102 MISCREG_CLIDR, 103 MISCREG_CCSIDR, 104 MISCREG_CSSELR, 105 MISCREG_ICIALLUIS, 106 MISCREG_ICIALLU, 107 MISCREG_ICIMVAU, 108 MISCREG_BPIMVA, 109 MISCREG_BPIALLIS, 110 MISCREG_BPIALL, 111 MISCREG_MIDR, 112 MISCREG_TTBR0, 113 MISCREG_TTBR1, 114 MISCREG_TLBTR, 115 MISCREG_DACR, 116 MISCREG_TLBIALLIS, 117 MISCREG_TLBIMVAIS, 118 MISCREG_TLBIASIDIS, 119 MISCREG_TLBIMVAAIS, 120 MISCREG_ITLBIALL, 121 MISCREG_ITLBIMVA, 122 MISCREG_ITLBIASID, 123 MISCREG_DTLBIALL, 124 MISCREG_DTLBIMVA, 125 MISCREG_DTLBIASID, 126 MISCREG_TLBIALL, 127 MISCREG_TLBIMVA, 128 MISCREG_TLBIASID, 129 MISCREG_TLBIMVAA, 130 MISCREG_DFSR, 131 MISCREG_IFSR, 132 MISCREG_DFAR, 133 MISCREG_IFAR, 134 MISCREG_MPIDR, 135 MISCREG_PRRR, 136 MISCREG_NMRR, 137 MISCREG_TTBCR, 138 MISCREG_ID_PFR0, 139 MISCREG_CTR, 140 MISCREG_SCR, 141 MISCREG_SDER, 142 MISCREG_PAR, 143 MISCREG_V2PCWPR, 144 MISCREG_V2PCWPW, 145 MISCREG_V2PCWUR, 146 MISCREG_V2PCWUW, 147 MISCREG_V2POWPR, 148 MISCREG_V2POWPW, 149 MISCREG_V2POWUR, 150 MISCREG_V2POWUW, 151 MISCREG_ID_MMFR0, 152 MISCREG_ACTLR, 153 MISCREG_PMCR, 154 MISCREG_PMCCNTR, 155 MISCREG_PMCNTENSET, 156 MISCREG_PMCNTENCLR, 157 MISCREG_PMOVSR, 158 MISCREG_PMSWINC, 159 MISCREG_PMSELR, 160 MISCREG_PMCEID0, 161 MISCREG_PMCEID1, 162 MISCREG_PMC_OTHER, 163 MISCREG_PMXEVCNTR, 164 MISCREG_PMUSERENR, 165 MISCREG_PMINTENSET, 166 MISCREG_PMINTENCLR, 167 MISCREG_ID_ISAR0, 168 MISCREG_ID_ISAR1, 169 MISCREG_ID_ISAR2, 170 MISCREG_ID_ISAR3, 171 MISCREG_ID_ISAR4, 172 MISCREG_ID_ISAR5, 173 MISCREG_CP15_UNIMP_START, 174 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 175 MISCREG_ID_PFR1, 176 MISCREG_ID_DFR0, 177 MISCREG_ID_AFR0, 178 MISCREG_ID_MMFR1, 179 MISCREG_ID_MMFR2, 180 MISCREG_ID_MMFR3, 181 MISCREG_AIDR, 182 MISCREG_ADFSR, 183 MISCREG_AIFSR, 184 MISCREG_DCIMVAC, 185 MISCREG_DCISW, 186 MISCREG_MCCSW, 187 MISCREG_DCCMVAU, 188 MISCREG_NSACR, 189 MISCREG_VBAR, 190 MISCREG_MVBAR, 191 MISCREG_ISR, 192 MISCREG_FCEIDR, 193 MISCREG_L2LATENCY, 194 195 196 MISCREG_CP15_END, 197 198 // Dummy indices 199 MISCREG_NOP = MISCREG_CP15_END, 200 MISCREG_RAZ, 201 202 NUM_MISCREGS 203 }; 204 205 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 206 unsigned crm, unsigned opc2); 207 208 const char * const miscRegName[NUM_MISCREGS] = { 209 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 210 "spsr_mon", "spsr_und", "spsr_abt", 211 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 212 "mvfr0", "mvfr1", 213 "sctlr_rst", "sev_mailbox", 214 "sctlr", "dccisw", "dccimvac", "dccmvac", 215 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 216 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 217 "clidr", "ccsidr", "csselr", 218 "icialluis", "iciallu", "icimvau", 219 "bpimva", "bpiallis", "bpiall", 220 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 221 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 222 "itlbiall", "itlbimva", "itlbiasid", 223 "dtlbiall", "dtlbimva", "dtlbiasid", 224 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 225 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 226 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 227 "scr", "sder", "par", 228 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 229 "v2powpr", "v2powpw", "v2powur", "v2powuw", 230 "id_mmfr0", "actlr", "pmcr", "pmccntr", 231 "pmcntenset", "pmcntenclr", "pmovsr", 232 "pmswinc", "pmselr", "pmceid0", 233 "pmceid1", "pmc_other", "pmxevcntr", 234 "pmuserenr", "pmintenset", "pmintenclr", 235 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 236 // Unimplemented below 237 "tcmtr", 238 "id_pfr1", "id_dfr0", "id_afr0", 239 "id_mmfr1", "id_mmfr2", "id_mmfr3", 240 "aidr", "adfsr", "aifsr", 241 "dcimvac", "dcisw", "mccsw", 242 "dccmvau", 243 "nsacr", 244 "vbar", "mvbar", "isr", "fceidr", "l2latency", 245 "nop", "raz" 246 }; 247 248 BitUnion32(CPSR) 249 Bitfield<31> n; 250 Bitfield<30> z; 251 Bitfield<29> c; 252 Bitfield<28> v; 253 Bitfield<27> q; 254 Bitfield<26,25> it1; 255 Bitfield<24> j; 256 Bitfield<19, 16> ge; 257 Bitfield<15,10> it2; 258 Bitfield<9> e; 259 Bitfield<8> a; 260 Bitfield<7> i; 261 Bitfield<6> f; 262 Bitfield<5> t; 263 Bitfield<4, 0> mode; 264 EndBitUnion(CPSR) 265 266 // This mask selects bits of the CPSR that actually go in the CondCodes 267 // integer register to allow renaming. 268 static const uint32_t CondCodesMask = 0xF80F0000; 269 270 BitUnion32(SCTLR) 271 Bitfield<31> ie; // Instruction endianness 272 Bitfield<30> te; // Thumb Exception Enable 273 Bitfield<29> afe; // Access flag enable 274 Bitfield<28> tre; // TEX Remap bit 275 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 276 Bitfield<25> ee; // Exception Endianness bit 277 Bitfield<24> ve; // Interrupt vectors enable 278 Bitfield<23> xp; // Extended page table enable bit 279 Bitfield<22> u; // Alignment (now unused) 280 Bitfield<21> fi; // Fast interrupts configuration enable 281 Bitfield<19> dz; // Divide by Zero fault enable bit 282 Bitfield<18> rao2;// Read as one 283 Bitfield<17> br; // Background region bit 284 Bitfield<16> rao3;// Read as one 285 Bitfield<14> rr; // Round robin cache replacement 286 Bitfield<13> v; // Base address for exception vectors 287 Bitfield<12> i; // instruction cache enable 288 Bitfield<11> z; // branch prediction enable bit 289 Bitfield<10> sw; // Enable swp/swpb 290 Bitfield<9,8> rs; // deprecated protection bits 291 Bitfield<6,3> rao4;// Read as one 292 Bitfield<7> b; // Endianness support (unused) 293 Bitfield<2> c; // Cache enable bit 294 Bitfield<1> a; // Alignment fault checking 295 Bitfield<0> m; // MMU enable bit 296 EndBitUnion(SCTLR) 297 298 BitUnion32(CPACR) 299 Bitfield<1, 0> cp0; 300 Bitfield<3, 2> cp1; 301 Bitfield<5, 4> cp2; 302 Bitfield<7, 6> cp3; 303 Bitfield<9, 8> cp4; 304 Bitfield<11, 10> cp5; 305 Bitfield<13, 12> cp6; 306 Bitfield<15, 14> cp7; 307 Bitfield<17, 16> cp8; 308 Bitfield<19, 18> cp9; 309 Bitfield<21, 20> cp10; 310 Bitfield<23, 22> cp11; 311 Bitfield<25, 24> cp12; 312 Bitfield<27, 26> cp13; 313 Bitfield<30> d32dis; 314 Bitfield<31> asedis; 315 EndBitUnion(CPACR) 316 317 BitUnion32(FSR) 318 Bitfield<3, 0> fsLow; 319 Bitfield<7, 4> domain; 320 Bitfield<10> fsHigh; 321 Bitfield<11> wnr; 322 Bitfield<12> ext; 323 EndBitUnion(FSR) 324 325 BitUnion32(FPSCR) 326 Bitfield<0> ioc; 327 Bitfield<1> dzc; 328 Bitfield<2> ofc; 329 Bitfield<3> ufc; 330 Bitfield<4> ixc; 331 Bitfield<7> idc; 332 Bitfield<8> ioe; 333 Bitfield<9> dze; 334 Bitfield<10> ofe; 335 Bitfield<11> ufe; 336 Bitfield<12> ixe; 337 Bitfield<15> ide; 338 Bitfield<18, 16> len; 339 Bitfield<21, 20> stride; 340 Bitfield<23, 22> rMode; 341 Bitfield<24> fz; 342 Bitfield<25> dn; 343 Bitfield<26> ahp; 344 Bitfield<27> qc; 345 Bitfield<28> v; 346 Bitfield<29> c; 347 Bitfield<30> z; 348 Bitfield<31> n; 349 EndBitUnion(FPSCR) 350 351 // This mask selects bits of the FPSCR that actually go in the FpCondCodes 352 // integer register to allow renaming. 353 static const uint32_t FpCondCodesMask = 0xF0000000; 354 // This mask selects the cumulative FP exception flags of the FPSCR. 355 static const uint32_t FpscrExcMask = 0x0000009F; 356 // This mask selects the cumulative saturation flag of the FPSCR. 357 static const uint32_t FpscrQcMask = 0x08000000; 358 359 BitUnion32(FPEXC) 360 Bitfield<31> ex; 361 Bitfield<30> en; 362 Bitfield<29, 0> subArchDefined; 363 EndBitUnion(FPEXC) 364 365 BitUnion32(MVFR0) 366 Bitfield<3, 0> advSimdRegisters; 367 Bitfield<7, 4> singlePrecision; 368 Bitfield<11, 8> doublePrecision; 369 Bitfield<15, 12> vfpExceptionTrapping; 370 Bitfield<19, 16> divide; 371 Bitfield<23, 20> squareRoot; 372 Bitfield<27, 24> shortVectors; 373 Bitfield<31, 28> roundingModes; 374 EndBitUnion(MVFR0) 375 376 BitUnion32(MVFR1) 377 Bitfield<3, 0> flushToZero; 378 Bitfield<7, 4> defaultNaN; 379 Bitfield<11, 8> advSimdLoadStore; 380 Bitfield<15, 12> advSimdInteger; 381 Bitfield<19, 16> advSimdSinglePrecision; 382 Bitfield<23, 20> advSimdHalfPrecision; 383 Bitfield<27, 24> vfpHalfPrecision; 384 Bitfield<31, 28> raz; 385 EndBitUnion(MVFR1) 386 387 BitUnion32(PRRR) 388 Bitfield<1,0> tr0; 389 Bitfield<3,2> tr1; 390 Bitfield<5,4> tr2; 391 Bitfield<7,6> tr3; 392 Bitfield<9,8> tr4; 393 Bitfield<11,10> tr5; 394 Bitfield<13,12> tr6; 395 Bitfield<15,14> tr7; 396 Bitfield<16> ds0; 397 Bitfield<17> ds1; 398 Bitfield<18> ns0; 399 Bitfield<19> ns1; 400 Bitfield<24> nos0; 401 Bitfield<25> nos1; 402 Bitfield<26> nos2; 403 Bitfield<27> nos3; 404 Bitfield<28> nos4; 405 Bitfield<29> nos5; 406 Bitfield<30> nos6; 407 Bitfield<31> nos7; 408 EndBitUnion(PRRR) 409 410 BitUnion32(NMRR) 411 Bitfield<1,0> ir0; 412 Bitfield<3,2> ir1; 413 Bitfield<5,4> ir2; 414 Bitfield<7,6> ir3; 415 Bitfield<9,8> ir4; 416 Bitfield<11,10> ir5; 417 Bitfield<13,12> ir6; 418 Bitfield<15,14> ir7; 419 Bitfield<17,16> or0; 420 Bitfield<19,18> or1; 421 Bitfield<21,20> or2; 422 Bitfield<23,22> or3; 423 Bitfield<25,24> or4; 424 Bitfield<27,26> or5; 425 Bitfield<29,28> or6; 426 Bitfield<31,30> or7; 427 EndBitUnion(NMRR) 428 429}; 430 431#endif // __ARCH_ARM_MISCREGS_HH__ 432