miscregs.hh revision 8058:a259ab86cabf
19243SN/A/* 212706Swendy.elsasser@arm.com * Copyright (c) 2010 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2009 The Regents of The University of Michigan 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Gabe Black 419243SN/A */ 429967SN/A#ifndef __ARCH_ARM_MISCREGS_HH__ 4310618SOmar.Naji@arm.com#define __ARCH_ARM_MISCREGS_HH__ 4411678Swendy.elsasser@arm.com 4512266Sradhika.jagtap@arm.com#include "base/bitunion.hh" 469243SN/A 479243SN/Anamespace ArmISA 4811793Sbrandon.potter@amd.com{ 4911793Sbrandon.potter@amd.com enum ConditionCode { 5010146Sandreas.hansson@arm.com COND_EQ = 0, 519356SN/A COND_NE, // 1 5210146Sandreas.hansson@arm.com COND_CS, // 2 5310247Sandreas.hansson@arm.com COND_CC, // 3 5410208Sandreas.hansson@arm.com COND_MI, // 4 559352SN/A COND_PL, // 5 569814SN/A COND_VS, // 6 579243SN/A COND_VC, // 7 589243SN/A COND_HI, // 8 5910432SOmar.Naji@arm.com COND_LS, // 9 609243SN/A COND_GE, // 10 6110146Sandreas.hansson@arm.com COND_LT, // 11 629243SN/A COND_GT, // 12 6310619Sandreas.hansson@arm.com COND_LE, // 13 649243SN/A COND_AL, // 14 6510211Sandreas.hansson@arm.com COND_UC // 15 6611678Swendy.elsasser@arm.com }; 6712084Sspwilson2@wisc.edu 6812084Sspwilson2@wisc.edu enum MiscRegIndex { 6910489SOmar.Naji@arm.com MISCREG_CPSR = 0, 709831SN/A MISCREG_ITSTATE, 719831SN/A MISCREG_SPSR, 729831SN/A MISCREG_SPSR_FIQ, 739831SN/A MISCREG_SPSR_IRQ, 749831SN/A MISCREG_SPSR_SVC, 7510140SN/A MISCREG_SPSR_MON, 7610646Sandreas.hansson@arm.com MISCREG_SPSR_UND, 779243SN/A MISCREG_SPSR_ABT, 7810394Swendy.elsasser@arm.com MISCREG_FPSR, 7910394Swendy.elsasser@arm.com MISCREG_FPSID, 809566SN/A MISCREG_FPSCR, 819243SN/A MISCREG_FPSCR_QC, // Cumulative saturation flag 829243SN/A MISCREG_FPSCR_EXC, // Cumulative FP exception flags 8310140SN/A MISCREG_FPEXC, 8410140SN/A MISCREG_MVFR0, 8510147Sandreas.hansson@arm.com MISCREG_MVFR1, 8610147Sandreas.hansson@arm.com MISCREG_SCTLR_RST, 8712706Swendy.elsasser@arm.com MISCREG_SEV_MAILBOX, 8812706Swendy.elsasser@arm.com 8910394Swendy.elsasser@arm.com // CP15 registers 9010394Swendy.elsasser@arm.com MISCREG_CP15_START, 9111673SOmar.Naji@arm.com MISCREG_SCTLR = MISCREG_CP15_START, 9212706Swendy.elsasser@arm.com MISCREG_DCCISW, 9312706Swendy.elsasser@arm.com MISCREG_DCCIMVAC, 949243SN/A MISCREG_DCCMVAC, 959243SN/A MISCREG_CONTEXTIDR, 9610141SN/A MISCREG_TPIDRURW, 979726SN/A MISCREG_TPIDRURO, 989726SN/A MISCREG_TPIDRPRW, 9912706Swendy.elsasser@arm.com MISCREG_CP15ISB, 10012266Sradhika.jagtap@arm.com MISCREG_CP15DSB, 10112266Sradhika.jagtap@arm.com MISCREG_CP15DMB, 1029243SN/A MISCREG_CPACR, 10310620Sandreas.hansson@arm.com MISCREG_CLIDR, 10410620Sandreas.hansson@arm.com MISCREG_CCSIDR, 10510620Sandreas.hansson@arm.com MISCREG_CSSELR, 10610620Sandreas.hansson@arm.com MISCREG_ICIALLUIS, 10710620Sandreas.hansson@arm.com MISCREG_ICIALLU, 10810889Sandreas.hansson@arm.com MISCREG_ICIMVAU, 10910889Sandreas.hansson@arm.com MISCREG_BPIMVA, 11010889Sandreas.hansson@arm.com MISCREG_BPIALLIS, 11110618SOmar.Naji@arm.com MISCREG_BPIALL, 11212081Sspwilson2@wisc.edu MISCREG_MIDR, 11310618SOmar.Naji@arm.com MISCREG_TTBR0, 11410246Sandreas.hansson@arm.com MISCREG_TTBR1, 11510246Sandreas.hansson@arm.com MISCREG_TLBTR, 11610140SN/A MISCREG_DACR, 11710140SN/A MISCREG_TLBIALLIS, 11810140SN/A MISCREG_TLBIMVAIS, 11910140SN/A MISCREG_TLBIASIDIS, 12010140SN/A MISCREG_TLBIMVAAIS, 1219243SN/A MISCREG_ITLBIALL, 1229243SN/A MISCREG_ITLBIMVA, 1239567SN/A MISCREG_ITLBIASID, 1249243SN/A MISCREG_DTLBIALL, 12510489SOmar.Naji@arm.com MISCREG_DTLBIMVA, 12610489SOmar.Naji@arm.com MISCREG_DTLBIASID, 12710489SOmar.Naji@arm.com MISCREG_TLBIALL, 12810489SOmar.Naji@arm.com MISCREG_TLBIMVA, 12910489SOmar.Naji@arm.com MISCREG_TLBIASID, 13010489SOmar.Naji@arm.com MISCREG_TLBIMVAA, 13110489SOmar.Naji@arm.com MISCREG_DFSR, 13210489SOmar.Naji@arm.com MISCREG_IFSR, 13310489SOmar.Naji@arm.com MISCREG_DFAR, 13410489SOmar.Naji@arm.com MISCREG_IFAR, 1359243SN/A MISCREG_MPIDR, 1369243SN/A MISCREG_PRRR, 1379831SN/A MISCREG_NMRR, 1389831SN/A MISCREG_TTBCR, 1399831SN/A MISCREG_ID_PFR0, 1409831SN/A MISCREG_CTR, 1419831SN/A MISCREG_SCR, 1429243SN/A MISCREG_SDER, 14310207Sandreas.hansson@arm.com MISCREG_PAR, 14410207Sandreas.hansson@arm.com MISCREG_V2PCWPR, 14510207Sandreas.hansson@arm.com MISCREG_V2PCWPW, 14610207Sandreas.hansson@arm.com MISCREG_V2PCWUR, 14710207Sandreas.hansson@arm.com MISCREG_V2PCWUW, 14810394Swendy.elsasser@arm.com MISCREG_V2POWPR, 14910394Swendy.elsasser@arm.com MISCREG_V2POWPW, 15010394Swendy.elsasser@arm.com MISCREG_V2POWUR, 15110394Swendy.elsasser@arm.com MISCREG_V2POWUW, 15210394Swendy.elsasser@arm.com MISCREG_ID_MMFR0, 15310394Swendy.elsasser@arm.com MISCREG_ACTLR, 15410394Swendy.elsasser@arm.com MISCREG_PMCR, 15510394Swendy.elsasser@arm.com MISCREG_PMCCNTR, 15610394Swendy.elsasser@arm.com MISCREG_PMCNTENSET, 15710394Swendy.elsasser@arm.com MISCREG_PMCNTENCLR, 15810394Swendy.elsasser@arm.com MISCREG_PMOVSR, 15910394Swendy.elsasser@arm.com MISCREG_PMSWINC, 16010394Swendy.elsasser@arm.com MISCREG_PMSELR, 16110394Swendy.elsasser@arm.com MISCREG_PMCEID0, 16210394Swendy.elsasser@arm.com MISCREG_PMCEID1, 16310394Swendy.elsasser@arm.com MISCREG_PMC_OTHER, 16410394Swendy.elsasser@arm.com MISCREG_PMXEVCNTR, 16510394Swendy.elsasser@arm.com MISCREG_PMUSERENR, 16610394Swendy.elsasser@arm.com MISCREG_PMINTENSET, 16710394Swendy.elsasser@arm.com MISCREG_PMINTENCLR, 16810394Swendy.elsasser@arm.com MISCREG_CP15_UNIMP_START, 16912706Swendy.elsasser@arm.com MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 17012706Swendy.elsasser@arm.com MISCREG_ID_PFR1, 17112706Swendy.elsasser@arm.com MISCREG_ID_DFR0, 17212706Swendy.elsasser@arm.com MISCREG_ID_AFR0, 17312706Swendy.elsasser@arm.com MISCREG_ID_MMFR1, 17412706Swendy.elsasser@arm.com MISCREG_ID_MMFR2, 17510394Swendy.elsasser@arm.com MISCREG_ID_MMFR3, 17610561SOmar.Naji@arm.com MISCREG_ID_ISAR0, 17710561SOmar.Naji@arm.com MISCREG_ID_ISAR1, 17810394Swendy.elsasser@arm.com MISCREG_ID_ISAR2, 17910394Swendy.elsasser@arm.com MISCREG_ID_ISAR3, 18010394Swendy.elsasser@arm.com MISCREG_ID_ISAR4, 18110394Swendy.elsasser@arm.com MISCREG_ID_ISAR5, 18210394Swendy.elsasser@arm.com MISCREG_AIDR, 18310394Swendy.elsasser@arm.com MISCREG_ADFSR, 1849243SN/A MISCREG_AIFSR, 1859243SN/A MISCREG_DCIMVAC, 1869243SN/A MISCREG_DCISW, 18710146Sandreas.hansson@arm.com MISCREG_MCCSW, 18810140SN/A MISCREG_DCCMVAU, 18910466Sandreas.hansson@arm.com MISCREG_NSACR, 19010466Sandreas.hansson@arm.com MISCREG_VBAR, 19110466Sandreas.hansson@arm.com MISCREG_MVBAR, 19210146Sandreas.hansson@arm.com MISCREG_ISR, 19310140SN/A MISCREG_FCEIDR, 19410140SN/A MISCREG_L2LATENCY, 19510140SN/A 19610646Sandreas.hansson@arm.com 19710646Sandreas.hansson@arm.com MISCREG_CP15_END, 19810646Sandreas.hansson@arm.com 19910646Sandreas.hansson@arm.com // Dummy indices 20010646Sandreas.hansson@arm.com MISCREG_NOP = MISCREG_CP15_END, 20110646Sandreas.hansson@arm.com MISCREG_RAZ, 20210646Sandreas.hansson@arm.com 20310646Sandreas.hansson@arm.com NUM_MISCREGS 20410646Sandreas.hansson@arm.com }; 20510646Sandreas.hansson@arm.com 20610646Sandreas.hansson@arm.com MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 20710646Sandreas.hansson@arm.com unsigned crm, unsigned opc2); 20810646Sandreas.hansson@arm.com 20910646Sandreas.hansson@arm.com const char * const miscRegName[NUM_MISCREGS] = { 21010646Sandreas.hansson@arm.com "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 21110646Sandreas.hansson@arm.com "spsr_mon", "spsr_und", "spsr_abt", 21210646Sandreas.hansson@arm.com "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 21310646Sandreas.hansson@arm.com "mvfr0", "mvfr1", 21410646Sandreas.hansson@arm.com "sctlr_rst", "sev_mailbox", 21510646Sandreas.hansson@arm.com "sctlr", "dccisw", "dccimvac", "dccmvac", 21610646Sandreas.hansson@arm.com "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 21710646Sandreas.hansson@arm.com "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 21810646Sandreas.hansson@arm.com "clidr", "ccsidr", "csselr", 21910646Sandreas.hansson@arm.com "icialluis", "iciallu", "icimvau", 22010646Sandreas.hansson@arm.com "bpimva", "bpiallis", "bpiall", 22110646Sandreas.hansson@arm.com "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 22210646Sandreas.hansson@arm.com "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 22310646Sandreas.hansson@arm.com "itlbiall", "itlbimva", "itlbiasid", 22410646Sandreas.hansson@arm.com "dtlbiall", "dtlbimva", "dtlbiasid", 22510646Sandreas.hansson@arm.com "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 22610646Sandreas.hansson@arm.com "dfsr", "ifsr", "dfar", "ifar", "mpidr", 22710646Sandreas.hansson@arm.com "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 22810646Sandreas.hansson@arm.com "scr", "sder", "par", 22910646Sandreas.hansson@arm.com "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 23010646Sandreas.hansson@arm.com "v2powpr", "v2powpw", "v2powur", "v2powuw", 23110646Sandreas.hansson@arm.com "id_mmfr0","actlr", "pmcr", "pmcntr", 23210646Sandreas.hansson@arm.com "pmcntenset", "pmcntenclr", "pmovsr", 23310646Sandreas.hansson@arm.com "pmswinc", "pmselr", "pmceid0", 23410646Sandreas.hansson@arm.com "pmceid1", "pmc_other", "pmxevcntr", 23510646Sandreas.hansson@arm.com "pmuserenr", "pmintenset", "pmintenclr", 23610140SN/A // Unimplemented below 23710140SN/A "tcmtr", 23810140SN/A "id_pfr1", "id_dfr0", "id_afr0", 23910146Sandreas.hansson@arm.com "id_mmfr1", "id_mmfr2", "id_mmfr3", 2409243SN/A "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 24110619Sandreas.hansson@arm.com "aidr", 24210619Sandreas.hansson@arm.com "adfsr", "aifsr", 24310618SOmar.Naji@arm.com "dcimvac", "dcisw", "mccsw", 24410619Sandreas.hansson@arm.com "dccmvau", 24510619Sandreas.hansson@arm.com "nsacr", 24610619Sandreas.hansson@arm.com "vbar", "mvbar", "isr", "fceidr", 24710619Sandreas.hansson@arm.com "nop", "raz" 24810619Sandreas.hansson@arm.com }; 24910619Sandreas.hansson@arm.com 25010619Sandreas.hansson@arm.com BitUnion32(CPSR) 25110619Sandreas.hansson@arm.com Bitfield<31> n; 25210619Sandreas.hansson@arm.com Bitfield<30> z; 25310619Sandreas.hansson@arm.com Bitfield<29> c; 25410619Sandreas.hansson@arm.com Bitfield<28> v; 25510619Sandreas.hansson@arm.com Bitfield<27> q; 25610619Sandreas.hansson@arm.com Bitfield<26,25> it1; 25710619Sandreas.hansson@arm.com Bitfield<24> j; 25812706Swendy.elsasser@arm.com Bitfield<19, 16> ge; 25910618SOmar.Naji@arm.com Bitfield<15,10> it2; 2609243SN/A Bitfield<9> e; 2619243SN/A Bitfield<8> a; 2629243SN/A Bitfield<7> i; 26310146Sandreas.hansson@arm.com Bitfield<6> f; 2649243SN/A Bitfield<5> t; 2659243SN/A Bitfield<4, 0> mode; 2669243SN/A EndBitUnion(CPSR) 26711334Sandreas.hansson@arm.com 26811334Sandreas.hansson@arm.com BitUnion8(ITSTATE) 26911334Sandreas.hansson@arm.com /* Note that the split (cond, mask) below is not as in ARM ARM. 2709243SN/A * But it is more convenient for simulation. The condition 2719243SN/A * is always the concatenation of the top 3 bits and the next bit, 2729243SN/A * which applies when one of the bottom 4 bits is set. 2739243SN/A * Refer to predecoder.cc for the use case. 27411334Sandreas.hansson@arm.com */ 2759243SN/A Bitfield<7, 4> cond; 2769243SN/A Bitfield<3, 0> mask; 2779243SN/A // Bitfields for moving to/from CPSR 2789243SN/A Bitfield<7, 2> top6; 2799243SN/A Bitfield<1, 0> bottom2; 2809243SN/A EndBitUnion(ITSTATE) 2819243SN/A 2829243SN/A // This mask selects bits of the CPSR that actually go in the CondCodes 28310146Sandreas.hansson@arm.com // integer register to allow renaming. 2849243SN/A static const uint32_t CondCodesMask = 0xF80F0000; 2859831SN/A 2869831SN/A BitUnion32(SCTLR) 2879831SN/A Bitfield<31> ie; // Instruction endianness 2889243SN/A Bitfield<30> te; // Thumb Exception Enable 2899831SN/A Bitfield<29> afe; // Access flag enable 2909831SN/A Bitfield<28> tre; // TEX Remap bit 2919243SN/A Bitfield<27> nmfi;// Non-maskable fast interrupts enable 2929243SN/A Bitfield<25> ee; // Exception Endianness bit 2939243SN/A Bitfield<24> ve; // Interrupt vectors enable 29410146Sandreas.hansson@arm.com Bitfield<23> xp; // Extended page table enable bit 2959243SN/A Bitfield<22> u; // Alignment (now unused) 2969831SN/A Bitfield<21> fi; // Fast interrupts configuration enable 2979831SN/A Bitfield<19> dz; // Divide by Zero fault enable bit 2989831SN/A Bitfield<18> rao2;// Read as one 2999243SN/A Bitfield<17> br; // Background region bit 3009243SN/A Bitfield<16> rao3;// Read as one 30110146Sandreas.hansson@arm.com Bitfield<14> rr; // Round robin cache replacement 30210146Sandreas.hansson@arm.com Bitfield<13> v; // Base address for exception vectors 30310143SN/A Bitfield<12> i; // instruction cache enable 3049243SN/A Bitfield<11> z; // branch prediction enable bit 3059669SN/A Bitfield<10> sw; // Enable swp/swpb 30610136SN/A Bitfield<9,8> rs; // deprecated protection bits 30710136SN/A Bitfield<6,3> rao4;// Read as one 3089243SN/A Bitfield<7> b; // Endianness support (unused) 3099967SN/A Bitfield<2> c; // Cache enable bit 31010245Sandreas.hansson@arm.com Bitfield<1> a; // Alignment fault checking 31110245Sandreas.hansson@arm.com Bitfield<0> m; // MMU enable bit 31210245Sandreas.hansson@arm.com EndBitUnion(SCTLR) 3139243SN/A 31410286Sandreas.hansson@arm.com BitUnion32(CPACR) 31510286Sandreas.hansson@arm.com Bitfield<1, 0> cp0; 3169831SN/A Bitfield<3, 2> cp1; 3179243SN/A Bitfield<5, 4> cp2; 3189491SN/A Bitfield<7, 6> cp3; 3199831SN/A Bitfield<9, 8> cp4; 32010136SN/A Bitfield<11, 10> cp5; 3219491SN/A Bitfield<13, 12> cp6; 3229491SN/A Bitfield<15, 14> cp7; 3239831SN/A Bitfield<17, 16> cp8; 3249243SN/A Bitfield<19, 18> cp9; 3259669SN/A Bitfield<21, 20> cp10; 3269566SN/A Bitfield<23, 22> cp11; 3279566SN/A Bitfield<25, 24> cp12; 3289669SN/A Bitfield<27, 26> cp13; 3299669SN/A Bitfield<30> d32dis; 3309669SN/A Bitfield<31> asedis; 3319669SN/A EndBitUnion(CPACR) 3329669SN/A 3339669SN/A BitUnion32(FSR) 3349669SN/A Bitfield<3, 0> fsLow; 3359669SN/A Bitfield<7, 4> domain; 3369669SN/A Bitfield<10> fsHigh; 3379669SN/A Bitfield<11> wnr; 33811189Sandreas.hansson@arm.com Bitfield<12> ext; 3399669SN/A EndBitUnion(FSR) 34010136SN/A 34110286Sandreas.hansson@arm.com BitUnion32(FPSCR) 34210286Sandreas.hansson@arm.com Bitfield<0> ioc; 34310286Sandreas.hansson@arm.com Bitfield<1> dzc; 3449669SN/A Bitfield<2> ofc; 3459669SN/A Bitfield<3> ufc; 3469669SN/A Bitfield<4> ixc; 34710286Sandreas.hansson@arm.com Bitfield<7> idc; 34810286Sandreas.hansson@arm.com Bitfield<8> ioe; 3499669SN/A Bitfield<9> dze; 3509669SN/A Bitfield<10> ofe; 3519491SN/A Bitfield<11> ufe; 3529243SN/A Bitfield<12> ixe; 3539243SN/A Bitfield<15> ide; 3549243SN/A Bitfield<18, 16> len; 3559491SN/A Bitfield<21, 20> stride; 3569491SN/A Bitfield<23, 22> rMode; 3579243SN/A Bitfield<24> fz; 3589243SN/A Bitfield<25> dn; 3599243SN/A Bitfield<26> ahp; 36011189Sandreas.hansson@arm.com Bitfield<27> qc; 3619243SN/A Bitfield<28> v; 36210136SN/A Bitfield<29> c; 3639491SN/A Bitfield<30> z; 3649491SN/A Bitfield<31> n; 3659491SN/A EndBitUnion(FPSCR) 36610286Sandreas.hansson@arm.com 36710286Sandreas.hansson@arm.com // This mask selects bits of the FPSCR that actually go in the FpCondCodes 36810286Sandreas.hansson@arm.com // integer register to allow renaming. 3699566SN/A static const uint32_t FpCondCodesMask = 0xF0000000; 3709566SN/A // This mask selects the cumulative FP exception flags of the FPSCR. 3719566SN/A static const uint32_t FpscrExcMask = 0x0000009F; 3729566SN/A // This mask selects the cumulative saturation flag of the FPSCR. 3739566SN/A static const uint32_t FpscrQcMask = 0x08000000; 3749491SN/A 3759491SN/A BitUnion32(FPEXC) 3769243SN/A Bitfield<31> ex; 3779243SN/A Bitfield<30> en; 3789243SN/A Bitfield<29, 0> subArchDefined; 3799491SN/A EndBitUnion(FPEXC) 3809243SN/A 3819243SN/A BitUnion32(MVFR0) 3829243SN/A Bitfield<3, 0> advSimdRegisters; 38310286Sandreas.hansson@arm.com Bitfield<7, 4> singlePrecision; 38410286Sandreas.hansson@arm.com Bitfield<11, 8> doublePrecision; 3859243SN/A Bitfield<15, 12> vfpExceptionTrapping; 38611189Sandreas.hansson@arm.com Bitfield<19, 16> divide; 3879243SN/A Bitfield<23, 20> squareRoot; 3889243SN/A Bitfield<27, 24> shortVectors; 3899243SN/A Bitfield<31, 28> roundingModes; 3909243SN/A EndBitUnion(MVFR0) 3919243SN/A 3929243SN/A BitUnion32(MVFR1) 3939243SN/A Bitfield<3, 0> flushToZero; 39410245Sandreas.hansson@arm.com Bitfield<7, 4> defaultNaN; 3959243SN/A Bitfield<11, 8> advSimdLoadStore; 3969243SN/A Bitfield<15, 12> advSimdInteger; 3979831SN/A Bitfield<19, 16> advSimdSinglePrecision; 3989243SN/A Bitfield<23, 20> advSimdHalfPrecision; 3999243SN/A Bitfield<27, 24> vfpHalfPrecision; 4009567SN/A Bitfield<31, 28> raz; 4019567SN/A EndBitUnion(MVFR1) 4029967SN/A 4039967SN/A BitUnion32(PRRR) 40410618SOmar.Naji@arm.com Bitfield<1,0> tr0; 4059243SN/A Bitfield<3,2> tr1; 4069243SN/A Bitfield<5,4> tr2; 4079243SN/A Bitfield<7,6> tr3; 40810146Sandreas.hansson@arm.com Bitfield<9,8> tr4; 4099243SN/A Bitfield<11,10> tr5; 4109243SN/A Bitfield<13,12> tr6; 4119243SN/A Bitfield<15,14> tr7; 4129243SN/A Bitfield<16> ds0; 4139243SN/A Bitfield<17> ds1; 4149831SN/A Bitfield<18> ns0; 4159831SN/A Bitfield<19> ns1; 4169831SN/A Bitfield<24> nos0; 4179831SN/A Bitfield<25> nos1; 4189831SN/A Bitfield<26> nos2; 4199831SN/A Bitfield<27> nos3; 4209831SN/A Bitfield<28> nos4; 4219831SN/A Bitfield<29> nos5; 4229243SN/A Bitfield<30> nos6; 4239831SN/A Bitfield<31> nos7; 4249831SN/A EndBitUnion(PRRR) 4259831SN/A 4269831SN/A BitUnion32(NMRR) 4279831SN/A Bitfield<1,0> ir0; 4289831SN/A Bitfield<3,2> ir1; 4299831SN/A Bitfield<5,4> ir2; 4309243SN/A Bitfield<7,6> ir3; 4319831SN/A Bitfield<9,8> ir4; 4329831SN/A Bitfield<11,10> ir5; 4339831SN/A Bitfield<13,12> ir6; 43410889Sandreas.hansson@arm.com Bitfield<15,14> ir7; 43510889Sandreas.hansson@arm.com Bitfield<17,16> or0; 43610889Sandreas.hansson@arm.com Bitfield<19,18> or1; 43710889Sandreas.hansson@arm.com Bitfield<21,20> or2; 43810889Sandreas.hansson@arm.com Bitfield<23,22> or3; 43910889Sandreas.hansson@arm.com Bitfield<25,24> or4; 44010889Sandreas.hansson@arm.com Bitfield<27,26> or5; 44110889Sandreas.hansson@arm.com Bitfield<29,28> or6; 44210889Sandreas.hansson@arm.com Bitfield<31,30> or7; 44310889Sandreas.hansson@arm.com EndBitUnion(NMRR) 44410889Sandreas.hansson@arm.com 44510889Sandreas.hansson@arm.com}; 44610889Sandreas.hansson@arm.com 44710889Sandreas.hansson@arm.com#endif // __ARCH_ARM_MISCREGS_HH__ 44810889Sandreas.hansson@arm.com