miscregs.hh revision 7408:ee6949c5bb5b
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 45#include "base/bitunion.hh" 46 47namespace ArmISA 48{ 49 enum ConditionCode { 50 COND_EQ = 0, 51 COND_NE, // 1 52 COND_CS, // 2 53 COND_CC, // 3 54 COND_MI, // 4 55 COND_PL, // 5 56 COND_VS, // 6 57 COND_VC, // 7 58 COND_HI, // 8 59 COND_LS, // 9 60 COND_GE, // 10 61 COND_LT, // 11 62 COND_GT, // 12 63 COND_LE, // 13 64 COND_AL, // 14 65 COND_UC // 15 66 }; 67 68 enum MiscRegIndex { 69 MISCREG_CPSR = 0, 70 MISCREG_ITSTATE, 71 MISCREG_SPSR, 72 MISCREG_SPSR_FIQ, 73 MISCREG_SPSR_IRQ, 74 MISCREG_SPSR_SVC, 75 MISCREG_SPSR_MON, 76 MISCREG_SPSR_UND, 77 MISCREG_SPSR_ABT, 78 MISCREG_FPSR, 79 MISCREG_FPSID, 80 MISCREG_FPSCR, 81 MISCREG_FPEXC, 82 MISCREG_MVFR0, 83 MISCREG_MVFR1, 84 MISCREG_SCTLR_RST, 85 MISCREG_SEV_MAILBOX, 86 87 // CP15 registers 88 MISCREG_CP15_START, 89 MISCREG_SCTLR = MISCREG_CP15_START, 90 MISCREG_DCCISW, 91 MISCREG_DCCIMVAC, 92 MISCREG_DCCMVAC, 93 MISCREG_CONTEXTIDR, 94 MISCREG_TPIDRURW, 95 MISCREG_TPIDRURO, 96 MISCREG_TPIDRPRW, 97 MISCREG_CP15ISB, 98 MISCREG_CP15DSB, 99 MISCREG_CP15DMB, 100 MISCREG_CPACR, 101 MISCREG_CLIDR, 102 MISCREG_CCSIDR, 103 MISCREG_CSSELR, 104 MISCREG_ICIALLUIS, 105 MISCREG_ICIALLU, 106 MISCREG_ICIMVAU, 107 MISCREG_BPIMVA, 108 MISCREG_BPIALLIS, 109 MISCREG_BPIALL, 110 MISCREG_MIDR, 111 MISCREG_TTBR0, 112 MISCREG_TTBR1, 113 MISCREG_TLBTR, 114 MISCREG_DACR, 115 MISCREG_TLBIALLIS, 116 MISCREG_TLBIMVAIS, 117 MISCREG_TLBIASIDIS, 118 MISCREG_TLBIMVAAIS, 119 MISCREG_ITLBIALL, 120 MISCREG_ITLBIMVA, 121 MISCREG_ITLBIASID, 122 MISCREG_DTLBIALL, 123 MISCREG_DTLBIMVA, 124 MISCREG_DTLBIASID, 125 MISCREG_TLBIALL, 126 MISCREG_TLBIMVA, 127 MISCREG_TLBIASID, 128 MISCREG_TLBIMVAA, 129 MISCREG_DFSR, 130 MISCREG_IFSR, 131 MISCREG_DFAR, 132 MISCREG_IFAR, 133 MISCREG_MPIDR, 134 MISCREG_PRRR, 135 MISCREG_NMRR, 136 MISCREG_TTBCR, 137 MISCREG_ID_PFR0, 138 MISCREG_CTR, 139 MISCREG_SCR, 140 MISCREG_SDER, 141 MISCREG_CP15_UNIMP_START, 142 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 143 MISCREG_ID_PFR1, 144 MISCREG_ID_DFR0, 145 MISCREG_ID_AFR0, 146 MISCREG_ID_MMFR0, 147 MISCREG_ID_MMFR1, 148 MISCREG_ID_MMFR2, 149 MISCREG_ID_MMFR3, 150 MISCREG_ID_ISAR0, 151 MISCREG_ID_ISAR1, 152 MISCREG_ID_ISAR2, 153 MISCREG_ID_ISAR3, 154 MISCREG_ID_ISAR4, 155 MISCREG_ID_ISAR5, 156 MISCREG_PAR, 157 MISCREG_AIDR, 158 MISCREG_ACTLR, 159 MISCREG_ADFSR, 160 MISCREG_AIFSR, 161 MISCREG_DCIMVAC, 162 MISCREG_DCISW, 163 MISCREG_MCCSW, 164 MISCREG_DCCMVAU, 165 MISCREG_NSACR, 166 MISCREG_V2PCWPR, 167 MISCREG_V2PCWPW, 168 MISCREG_V2PCWUR, 169 MISCREG_V2PCWUW, 170 MISCREG_V2POWPR, 171 MISCREG_V2POWPW, 172 MISCREG_V2POWUR, 173 MISCREG_V2POWUW, 174 MISCREG_VBAR, 175 MISCREG_MVBAR, 176 MISCREG_ISR, 177 MISCREG_FCEIDR, 178 179 180 MISCREG_CP15_END, 181 182 // Dummy indices 183 MISCREG_NOP = MISCREG_CP15_END, 184 MISCREG_RAZ, 185 186 NUM_MISCREGS 187 }; 188 189 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 190 unsigned crm, unsigned opc2); 191 192 const char * const miscRegName[NUM_MISCREGS] = { 193 "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 194 "spsr_mon", "spsr_und", "spsr_abt", 195 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1", 196 "sctlr_rst", "sev_mailbox", 197 "sctlr", "dccisw", "dccimvac", "dccmvac", 198 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 199 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 200 "clidr", "ccsidr", "csselr", 201 "icialluis", "iciallu", "icimvau", 202 "bpimva", "bpiallis", "bpiall", 203 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 204 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 205 "itlbiall", "itlbimva", "itlbiasid", 206 "dtlbiall", "dtlbimva", "dtlbiasid", 207 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 208 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 209 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr" 210 "scr", "sder" 211 // Unimplemented below 212 "tcmtr", 213 "id_pfr1", "id_dfr0", "id_afr0", 214 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", 215 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 216 "par", "aidr", "actlr", 217 "adfsr", "aifsr", 218 "dcimvac", "dcisw", "mccsw", 219 "dccmvau", 220 "nsacr", 221 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 222 "v2powpr", "v2powpw", "v2powur", "v2powuw", 223 "vbar", "mvbar", "isr", "fceidr", 224 "nop", "raz" 225 }; 226 227 BitUnion32(CPSR) 228 Bitfield<31> n; 229 Bitfield<30> z; 230 Bitfield<29> c; 231 Bitfield<28> v; 232 Bitfield<27> q; 233 Bitfield<26,25> it1; 234 Bitfield<24> j; 235 Bitfield<19, 16> ge; 236 Bitfield<15,10> it2; 237 Bitfield<9> e; 238 Bitfield<8> a; 239 Bitfield<7> i; 240 Bitfield<6> f; 241 Bitfield<5> t; 242 Bitfield<4, 0> mode; 243 EndBitUnion(CPSR) 244 245 BitUnion8(ITSTATE) 246 Bitfield<7, 4> cond; 247 Bitfield<3, 0> mask; 248 // Bitfields for moving to/from CPSR 249 Bitfield<7, 2> top6; 250 Bitfield<1, 0> bottom2; 251 EndBitUnion(ITSTATE) 252 253 // This mask selects bits of the CPSR that actually go in the CondCodes 254 // integer register to allow renaming. 255 static const uint32_t CondCodesMask = 0xF80F0000; 256 257 BitUnion32(SCTLR) 258 Bitfield<31> ie; // Instruction endianness 259 Bitfield<30> te; // Thumb Exception Enable 260 Bitfield<29> afe; // Access flag enable 261 Bitfield<28> tre; // TEX Remap bit 262 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 263 Bitfield<25> ee; // Exception Endianness bit 264 Bitfield<24> ve; // Interrupt vectors enable 265 Bitfield<23> xp; // Extended page table enable bit 266 Bitfield<22> u; // Alignment (now unused) 267 Bitfield<21> fi; // Fast interrupts configuration enable 268 Bitfield<19> dz; // Divide by Zero fault enable bit 269 Bitfield<18> rao2;// Read as one 270 Bitfield<17> br; // Background region bit 271 Bitfield<16> rao3;// Read as one 272 Bitfield<14> rr; // Round robin cache replacement 273 Bitfield<13> v; // Base address for exception vectors 274 Bitfield<12> i; // instruction cache enable 275 Bitfield<11> z; // branch prediction enable bit 276 Bitfield<10> sw; // Enable swp/swpb 277 Bitfield<9,8> rs; // deprecated protection bits 278 Bitfield<6,3> rao4;// Read as one 279 Bitfield<7> b; // Endianness support (unused) 280 Bitfield<2> c; // Cache enable bit 281 Bitfield<1> a; // Alignment fault checking 282 Bitfield<0> m; // MMU enable bit 283 EndBitUnion(SCTLR) 284 285 BitUnion32(CPACR) 286 Bitfield<1, 0> cp0; 287 Bitfield<3, 2> cp1; 288 Bitfield<5, 4> cp2; 289 Bitfield<7, 6> cp3; 290 Bitfield<9, 8> cp4; 291 Bitfield<11, 10> cp5; 292 Bitfield<13, 12> cp6; 293 Bitfield<15, 14> cp7; 294 Bitfield<17, 16> cp8; 295 Bitfield<19, 18> cp9; 296 Bitfield<21, 20> cp10; 297 Bitfield<23, 22> cp11; 298 Bitfield<25, 24> cp12; 299 Bitfield<27, 26> cp13; 300 Bitfield<30> d32dis; 301 Bitfield<31> asedis; 302 EndBitUnion(CPACR) 303 304 BitUnion32(FSR) 305 Bitfield<3, 0> fsLow; 306 Bitfield<7, 4> domain; 307 Bitfield<10> fsHigh; 308 Bitfield<11> wnr; 309 Bitfield<12> ext; 310 EndBitUnion(FSR) 311 312 BitUnion32(FPSCR) 313 Bitfield<0> ioc; 314 Bitfield<1> dzc; 315 Bitfield<2> ofc; 316 Bitfield<3> ufc; 317 Bitfield<4> ixc; 318 Bitfield<7> idc; 319 Bitfield<8> ioe; 320 Bitfield<9> dze; 321 Bitfield<10> ofe; 322 Bitfield<11> ufe; 323 Bitfield<12> ixe; 324 Bitfield<15> ide; 325 Bitfield<18, 16> len; 326 Bitfield<21, 20> stride; 327 Bitfield<23, 22> rMode; 328 Bitfield<24> fz; 329 Bitfield<25> dn; 330 Bitfield<26> ahp; 331 Bitfield<27> qc; 332 Bitfield<28> v; 333 Bitfield<29> c; 334 Bitfield<30> z; 335 Bitfield<31> n; 336 EndBitUnion(FPSCR) 337 338 BitUnion32(MVFR0) 339 Bitfield<3, 0> advSimdRegisters; 340 Bitfield<7, 4> singlePrecision; 341 Bitfield<11, 8> doublePrecision; 342 Bitfield<15, 12> vfpExceptionTrapping; 343 Bitfield<19, 16> divide; 344 Bitfield<23, 20> squareRoot; 345 Bitfield<27, 24> shortVectors; 346 Bitfield<31, 28> roundingModes; 347 EndBitUnion(MVFR0) 348 349 BitUnion32(MVFR1) 350 Bitfield<3, 0> flushToZero; 351 Bitfield<7, 4> defaultNaN; 352 Bitfield<11, 8> advSimdLoadStore; 353 Bitfield<15, 12> advSimdInteger; 354 Bitfield<19, 16> advSimdSinglePrecision; 355 Bitfield<23, 20> advSimdHalfPrecision; 356 Bitfield<27, 24> vfpHalfPrecision; 357 Bitfield<31, 28> raz; 358 EndBitUnion(MVFR1) 359 360 BitUnion32(PRRR) 361 Bitfield<1,0> tr0; 362 Bitfield<3,2> tr1; 363 Bitfield<5,4> tr2; 364 Bitfield<7,6> tr3; 365 Bitfield<9,8> tr4; 366 Bitfield<11,10> tr5; 367 Bitfield<13,12> tr6; 368 Bitfield<15,14> tr7; 369 Bitfield<16> ds0; 370 Bitfield<17> ds1; 371 Bitfield<18> ns0; 372 Bitfield<19> ns1; 373 Bitfield<24> nos0; 374 Bitfield<25> nos1; 375 Bitfield<26> nos2; 376 Bitfield<27> nos3; 377 Bitfield<28> nos4; 378 Bitfield<29> nos5; 379 Bitfield<30> nos6; 380 Bitfield<31> nos7; 381 EndBitUnion(PRRR) 382 383 BitUnion32(NMRR) 384 Bitfield<1,0> ir0; 385 Bitfield<3,2> ir1; 386 Bitfield<5,4> ir2; 387 Bitfield<7,6> ir3; 388 Bitfield<9,8> ir4; 389 Bitfield<11,10> ir5; 390 Bitfield<13,12> ir6; 391 Bitfield<15,14> ir7; 392 Bitfield<17,16> or0; 393 Bitfield<19,18> or1; 394 Bitfield<21,20> or2; 395 Bitfield<23,22> or3; 396 Bitfield<25,24> or4; 397 Bitfield<27,26> or5; 398 Bitfield<29,28> or6; 399 Bitfield<31,30> or7; 400 EndBitUnion(NMRR) 401 402}; 403 404#endif // __ARCH_ARM_MISCREGS_HH__ 405