miscregs.hh revision 7406
11689SN/A/*
21689SN/A * Copyright (c) 2010 ARM Limited
39919Ssteve.reinhardt@amd.com * All rights reserved
41689SN/A *
51689SN/A * The license below extends only to copyright in the software and shall
61689SN/A * not be construed as granting a license to any other intellectual
71689SN/A * property including but not limited to intellectual property relating
81689SN/A * to a hardware implementation of the functionality of the software
91689SN/A * licensed hereunder.  You may use the software subject to the license
101689SN/A * terms below provided that you ensure that this notice is replicated
111689SN/A * unmodified and in its entirety in all distributions of the software,
121689SN/A * modified or unmodified, in source code or in binary form.
131689SN/A *
141689SN/A * Copyright (c) 2009 The Regents of The University of Michigan
151689SN/A * All rights reserved.
161689SN/A *
171689SN/A * Redistribution and use in source and binary forms, with or without
181689SN/A * modification, are permitted provided that the following conditions are
191689SN/A * met: redistributions of source code must retain the above copyright
201689SN/A * notice, this list of conditions and the following disclaimer;
211689SN/A * redistributions in binary form must reproduce the above copyright
221689SN/A * notice, this list of conditions and the following disclaimer in the
231689SN/A * documentation and/or other materials provided with the distribution;
241689SN/A * neither the name of the copyright holders nor the names of its
251689SN/A * contributors may be used to endorse or promote products derived from
261689SN/A * this software without specific prior written permission.
271689SN/A *
282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
341060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
351060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
361060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
371060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382669Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
391684SN/A *
401717SN/A * Authors: Gabe Black
419919Ssteve.reinhardt@amd.com */
428232Snate@binkert.org#ifndef __ARCH_ARM_MISCREGS_HH__
431060SN/A#define __ARCH_ARM_MISCREGS_HH__
441060SN/A
459919Ssteve.reinhardt@amd.com#include "base/bitunion.hh"
469919Ssteve.reinhardt@amd.com
479919Ssteve.reinhardt@amd.comnamespace ArmISA
489919Ssteve.reinhardt@amd.com{
499919Ssteve.reinhardt@amd.com    enum ConditionCode {
509919Ssteve.reinhardt@amd.com        COND_EQ  =   0,
519919Ssteve.reinhardt@amd.com        COND_NE, //  1
529919Ssteve.reinhardt@amd.com        COND_CS, //  2
539919Ssteve.reinhardt@amd.com        COND_CC, //  3
549919Ssteve.reinhardt@amd.com        COND_MI, //  4
559919Ssteve.reinhardt@amd.com        COND_PL, //  5
569919Ssteve.reinhardt@amd.com        COND_VS, //  6
579919Ssteve.reinhardt@amd.com        COND_VC, //  7
589919Ssteve.reinhardt@amd.com        COND_HI, //  8
599919Ssteve.reinhardt@amd.com        COND_LS, //  9
609919Ssteve.reinhardt@amd.com        COND_GE, // 10
619919Ssteve.reinhardt@amd.com        COND_LT, // 11
629919Ssteve.reinhardt@amd.com        COND_GT, // 12
639919Ssteve.reinhardt@amd.com        COND_LE, // 13
649919Ssteve.reinhardt@amd.com        COND_AL, // 14
659919Ssteve.reinhardt@amd.com        COND_UC  // 15
669919Ssteve.reinhardt@amd.com    };
679919Ssteve.reinhardt@amd.com
689919Ssteve.reinhardt@amd.com    enum MiscRegIndex {
699919Ssteve.reinhardt@amd.com        MISCREG_CPSR = 0,
709919Ssteve.reinhardt@amd.com        MISCREG_SPSR,
719919Ssteve.reinhardt@amd.com        MISCREG_SPSR_FIQ,
729919Ssteve.reinhardt@amd.com        MISCREG_SPSR_IRQ,
739919Ssteve.reinhardt@amd.com        MISCREG_SPSR_SVC,
749919Ssteve.reinhardt@amd.com        MISCREG_SPSR_MON,
759919Ssteve.reinhardt@amd.com        MISCREG_SPSR_UND,
769919Ssteve.reinhardt@amd.com        MISCREG_SPSR_ABT,
779919Ssteve.reinhardt@amd.com        MISCREG_FPSR,
789919Ssteve.reinhardt@amd.com        MISCREG_FPSID,
799919Ssteve.reinhardt@amd.com        MISCREG_FPSCR,
809919Ssteve.reinhardt@amd.com        MISCREG_FPEXC,
819919Ssteve.reinhardt@amd.com        MISCREG_MVFR0,
829919Ssteve.reinhardt@amd.com        MISCREG_MVFR1,
831060SN/A        MISCREG_SCTLR_RST,
841060SN/A        MISCREG_SEV_MAILBOX,
851060SN/A
861060SN/A        // CP15 registers
871060SN/A        MISCREG_CP15_START,
881060SN/A        MISCREG_SCTLR = MISCREG_CP15_START,
891060SN/A        MISCREG_DCCISW,
902292SN/A        MISCREG_DCCIMVAC,
912292SN/A        MISCREG_DCCMVAC,
922292SN/A        MISCREG_CONTEXTIDR,
931060SN/A        MISCREG_TPIDRURW,
941060SN/A        MISCREG_TPIDRURO,
959919Ssteve.reinhardt@amd.com        MISCREG_TPIDRPRW,
961060SN/A        MISCREG_CP15ISB,
971060SN/A        MISCREG_CP15DSB,
989919Ssteve.reinhardt@amd.com        MISCREG_CP15DMB,
999919Ssteve.reinhardt@amd.com        MISCREG_CPACR,
1009919Ssteve.reinhardt@amd.com        MISCREG_CLIDR,
1019919Ssteve.reinhardt@amd.com        MISCREG_CCSIDR,
1029919Ssteve.reinhardt@amd.com        MISCREG_CSSELR,
1031060SN/A        MISCREG_ICIALLUIS,
1049919Ssteve.reinhardt@amd.com        MISCREG_ICIALLU,
1051060SN/A        MISCREG_ICIMVAU,
1061060SN/A        MISCREG_BPIMVA,
1079919Ssteve.reinhardt@amd.com        MISCREG_BPIALLIS,
1081060SN/A        MISCREG_BPIALL,
1099919Ssteve.reinhardt@amd.com        MISCREG_MIDR,
1109919Ssteve.reinhardt@amd.com        MISCREG_TTBR0,
1119919Ssteve.reinhardt@amd.com        MISCREG_TTBR1,
1129919Ssteve.reinhardt@amd.com        MISCREG_TLBTR,
1139919Ssteve.reinhardt@amd.com        MISCREG_DACR,
1141060SN/A        MISCREG_TLBIALLIS,
1159919Ssteve.reinhardt@amd.com        MISCREG_TLBIMVAIS,
1169919Ssteve.reinhardt@amd.com        MISCREG_TLBIASIDIS,
1179919Ssteve.reinhardt@amd.com        MISCREG_TLBIMVAAIS,
1189919Ssteve.reinhardt@amd.com        MISCREG_ITLBIALL,
1199919Ssteve.reinhardt@amd.com        MISCREG_ITLBIMVA,
1209919Ssteve.reinhardt@amd.com        MISCREG_ITLBIASID,
1211060SN/A        MISCREG_DTLBIALL,
1221060SN/A        MISCREG_DTLBIMVA,
1232292SN/A        MISCREG_DTLBIASID,
1242292SN/A        MISCREG_TLBIALL,
1259919Ssteve.reinhardt@amd.com        MISCREG_TLBIMVA,
1269919Ssteve.reinhardt@amd.com        MISCREG_TLBIASID,
1272292SN/A        MISCREG_TLBIMVAA,
1289919Ssteve.reinhardt@amd.com        MISCREG_DFSR,
1299919Ssteve.reinhardt@amd.com        MISCREG_IFSR,
1302292SN/A        MISCREG_DFAR,
1319919Ssteve.reinhardt@amd.com        MISCREG_IFAR,
1321060SN/A        MISCREG_MPIDR,
1332292SN/A        MISCREG_PRRR,
1349919Ssteve.reinhardt@amd.com        MISCREG_NMRR,
1352292SN/A        MISCREG_TTBCR,
1362292SN/A        MISCREG_ID_PFR0,
1379919Ssteve.reinhardt@amd.com        MISCREG_CTR,
1381060SN/A        MISCREG_SCR,
1392292SN/A        MISCREG_SDER,
1409919Ssteve.reinhardt@amd.com        MISCREG_CP15_UNIMP_START,
1411060SN/A        MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
1422292SN/A        MISCREG_ID_PFR1,
1439919Ssteve.reinhardt@amd.com        MISCREG_ID_DFR0,
1441060SN/A        MISCREG_ID_AFR0,
1452292SN/A        MISCREG_ID_MMFR0,
1469919Ssteve.reinhardt@amd.com        MISCREG_ID_MMFR1,
1471060SN/A        MISCREG_ID_MMFR2,
1482292SN/A        MISCREG_ID_MMFR3,
1499919Ssteve.reinhardt@amd.com        MISCREG_ID_ISAR0,
1501060SN/A        MISCREG_ID_ISAR1,
1512292SN/A        MISCREG_ID_ISAR2,
1529919Ssteve.reinhardt@amd.com        MISCREG_ID_ISAR3,
1531060SN/A        MISCREG_ID_ISAR4,
1542292SN/A        MISCREG_ID_ISAR5,
1559919Ssteve.reinhardt@amd.com        MISCREG_PAR,
1561060SN/A        MISCREG_AIDR,
1572292SN/A        MISCREG_ACTLR,
1589919Ssteve.reinhardt@amd.com        MISCREG_ADFSR,
1591060SN/A        MISCREG_AIFSR,
1602292SN/A        MISCREG_DCIMVAC,
1619919Ssteve.reinhardt@amd.com        MISCREG_DCISW,
1621060SN/A        MISCREG_MCCSW,
1631060SN/A        MISCREG_DCCMVAU,
1641060SN/A        MISCREG_NSACR,
1659919Ssteve.reinhardt@amd.com        MISCREG_V2PCWPR,
1661060SN/A        MISCREG_V2PCWPW,
1672292SN/A        MISCREG_V2PCWUR,
1681060SN/A        MISCREG_V2PCWUW,
1691060SN/A        MISCREG_V2POWPR,
1709919Ssteve.reinhardt@amd.com        MISCREG_V2POWPW,
1719919Ssteve.reinhardt@amd.com        MISCREG_V2POWUR,
1729919Ssteve.reinhardt@amd.com        MISCREG_V2POWUW,
1739919Ssteve.reinhardt@amd.com        MISCREG_VBAR,
1749919Ssteve.reinhardt@amd.com        MISCREG_MVBAR,
1751060SN/A        MISCREG_ISR,
1765362Sksewell@umich.edu        MISCREG_FCEIDR,
1775364Sksewell@umich.edu
1785364Sksewell@umich.edu
1795364Sksewell@umich.edu        MISCREG_CP15_END,
1805364Sksewell@umich.edu
1815364Sksewell@umich.edu        // Dummy indices
1825364Sksewell@umich.edu        MISCREG_NOP = MISCREG_CP15_END,
1835364Sksewell@umich.edu        MISCREG_RAZ,
1845364Sksewell@umich.edu
1855364Sksewell@umich.edu        NUM_MISCREGS
1865364Sksewell@umich.edu    };
1875364Sksewell@umich.edu
1881060SN/A    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
1891060SN/A                               unsigned crm, unsigned opc2);
1901060SN/A
1912292SN/A    const char * const miscRegName[NUM_MISCREGS] = {
192        "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
193        "spsr_mon", "spsr_und", "spsr_abt",
194        "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
195        "sctlr_rst", "sev_mailbox",
196        "sctlr", "dccisw", "dccimvac", "dccmvac",
197        "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
198        "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
199        "clidr", "ccsidr", "csselr",
200        "icialluis", "iciallu", "icimvau",
201        "bpimva", "bpiallis", "bpiall",
202        "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
203        "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
204        "itlbiall", "itlbimva", "itlbiasid",
205        "dtlbiall", "dtlbimva", "dtlbiasid",
206        "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
207        "dfsr", "ifsr", "dfar", "ifar", "mpidr",
208        "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr"
209        "scr", "sder"
210        // Unimplemented below
211        "tcmtr",
212        "id_pfr1", "id_dfr0", "id_afr0",
213        "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
214        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
215        "par", "aidr", "actlr",
216        "adfsr", "aifsr",
217        "dcimvac", "dcisw", "mccsw",
218        "dccmvau",
219        "nsacr",
220        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
221        "v2powpr", "v2powpw", "v2powur", "v2powuw",
222        "vbar", "mvbar", "isr", "fceidr",
223        "nop", "raz"
224    };
225
226    BitUnion32(CPSR)
227        Bitfield<31> n;
228        Bitfield<30> z;
229        Bitfield<29> c;
230        Bitfield<28> v;
231        Bitfield<27> q;
232        Bitfield<26,25> it1;
233        Bitfield<24> j;
234        Bitfield<19, 16> ge;
235        Bitfield<15,10> it2;
236        Bitfield<9> e;
237        Bitfield<8> a;
238        Bitfield<7> i;
239        Bitfield<6> f;
240        Bitfield<5> t;
241        Bitfield<4, 0> mode;
242    EndBitUnion(CPSR)
243
244    // This mask selects bits of the CPSR that actually go in the CondCodes
245    // integer register to allow renaming.
246    static const uint32_t CondCodesMask = 0xF80F0000;
247
248    BitUnion32(SCTLR)
249        Bitfield<31> ie;  // Instruction endianness
250        Bitfield<30> te;  // Thumb Exception Enable
251        Bitfield<29> afe; // Access flag enable
252        Bitfield<28> tre; // TEX Remap bit
253        Bitfield<27> nmfi;// Non-maskable fast interrupts enable
254        Bitfield<25> ee;  // Exception Endianness bit
255        Bitfield<24> ve;  // Interrupt vectors enable
256        Bitfield<23> xp; //  Extended page table enable bit
257        Bitfield<22> u;   // Alignment (now unused)
258        Bitfield<21> fi;  // Fast interrupts configuration enable
259        Bitfield<19> dz;  // Divide by Zero fault enable bit
260        Bitfield<18> rao2;// Read as one
261        Bitfield<17> br;  // Background region bit
262        Bitfield<16> rao3;// Read as one
263        Bitfield<14> rr;  // Round robin cache replacement
264        Bitfield<13> v;   // Base address for exception vectors
265        Bitfield<12> i;   // instruction cache enable
266        Bitfield<11> z;   // branch prediction enable bit
267        Bitfield<10> sw;  // Enable swp/swpb
268        Bitfield<9,8> rs;   // deprecated protection bits
269        Bitfield<6,3> rao4;// Read as one
270        Bitfield<7>  b;   // Endianness support (unused)
271        Bitfield<2>  c;   // Cache enable bit
272        Bitfield<1>  a;   // Alignment fault checking
273        Bitfield<0>  m;   // MMU enable bit
274    EndBitUnion(SCTLR)
275
276    BitUnion32(CPACR)
277        Bitfield<1, 0> cp0;
278        Bitfield<3, 2> cp1;
279        Bitfield<5, 4> cp2;
280        Bitfield<7, 6> cp3;
281        Bitfield<9, 8> cp4;
282        Bitfield<11, 10> cp5;
283        Bitfield<13, 12> cp6;
284        Bitfield<15, 14> cp7;
285        Bitfield<17, 16> cp8;
286        Bitfield<19, 18> cp9;
287        Bitfield<21, 20> cp10;
288        Bitfield<23, 22> cp11;
289        Bitfield<25, 24> cp12;
290        Bitfield<27, 26> cp13;
291        Bitfield<30> d32dis;
292        Bitfield<31> asedis;
293    EndBitUnion(CPACR)
294
295    BitUnion32(FSR)
296        Bitfield<3, 0> fsLow;
297        Bitfield<7, 4> domain;
298        Bitfield<10> fsHigh;
299        Bitfield<11> wnr;
300        Bitfield<12> ext;
301    EndBitUnion(FSR)
302
303    BitUnion32(FPSCR)
304        Bitfield<0> ioc;
305        Bitfield<1> dzc;
306        Bitfield<2> ofc;
307        Bitfield<3> ufc;
308        Bitfield<4> ixc;
309        Bitfield<7> idc;
310        Bitfield<8> ioe;
311        Bitfield<9> dze;
312        Bitfield<10> ofe;
313        Bitfield<11> ufe;
314        Bitfield<12> ixe;
315        Bitfield<15> ide;
316        Bitfield<18, 16> len;
317        Bitfield<21, 20> stride;
318        Bitfield<23, 22> rMode;
319        Bitfield<24> fz;
320        Bitfield<25> dn;
321        Bitfield<26> ahp;
322        Bitfield<27> qc;
323        Bitfield<28> v;
324        Bitfield<29> c;
325        Bitfield<30> z;
326        Bitfield<31> n;
327    EndBitUnion(FPSCR)
328
329    BitUnion32(MVFR0)
330        Bitfield<3, 0> advSimdRegisters;
331        Bitfield<7, 4> singlePrecision;
332        Bitfield<11, 8> doublePrecision;
333        Bitfield<15, 12> vfpExceptionTrapping;
334        Bitfield<19, 16> divide;
335        Bitfield<23, 20> squareRoot;
336        Bitfield<27, 24> shortVectors;
337        Bitfield<31, 28> roundingModes;
338    EndBitUnion(MVFR0)
339
340    BitUnion32(MVFR1)
341        Bitfield<3, 0> flushToZero;
342        Bitfield<7, 4> defaultNaN;
343        Bitfield<11, 8> advSimdLoadStore;
344        Bitfield<15, 12> advSimdInteger;
345        Bitfield<19, 16> advSimdSinglePrecision;
346        Bitfield<23, 20> advSimdHalfPrecision;
347        Bitfield<27, 24> vfpHalfPrecision;
348        Bitfield<31, 28> raz;
349    EndBitUnion(MVFR1)
350
351    BitUnion32(PRRR)
352       Bitfield<1,0> tr0;
353       Bitfield<3,2> tr1;
354       Bitfield<5,4> tr2;
355       Bitfield<7,6> tr3;
356       Bitfield<9,8> tr4;
357       Bitfield<11,10> tr5;
358       Bitfield<13,12> tr6;
359       Bitfield<15,14> tr7;
360       Bitfield<16> ds0;
361       Bitfield<17> ds1;
362       Bitfield<18> ns0;
363       Bitfield<19> ns1;
364       Bitfield<24> nos0;
365       Bitfield<25> nos1;
366       Bitfield<26> nos2;
367       Bitfield<27> nos3;
368       Bitfield<28> nos4;
369       Bitfield<29> nos5;
370       Bitfield<30> nos6;
371       Bitfield<31> nos7;
372   EndBitUnion(PRRR)
373
374   BitUnion32(NMRR)
375       Bitfield<1,0> ir0;
376       Bitfield<3,2> ir1;
377       Bitfield<5,4> ir2;
378       Bitfield<7,6> ir3;
379       Bitfield<9,8> ir4;
380       Bitfield<11,10> ir5;
381       Bitfield<13,12> ir6;
382       Bitfield<15,14> ir7;
383       Bitfield<17,16> or0;
384       Bitfield<19,18> or1;
385       Bitfield<21,20> or2;
386       Bitfield<23,22> or3;
387       Bitfield<25,24> or4;
388       Bitfield<27,26> or5;
389       Bitfield<29,28> or6;
390       Bitfield<31,30> or7;
391   EndBitUnion(NMRR)
392
393};
394
395#endif // __ARCH_ARM_MISCREGS_HH__
396