miscregs.hh revision 7404:bfc74724914e
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 45#include "base/bitunion.hh" 46 47namespace ArmISA 48{ 49 enum ConditionCode { 50 COND_EQ = 0, 51 COND_NE, // 1 52 COND_CS, // 2 53 COND_CC, // 3 54 COND_MI, // 4 55 COND_PL, // 5 56 COND_VS, // 6 57 COND_VC, // 7 58 COND_HI, // 8 59 COND_LS, // 9 60 COND_GE, // 10 61 COND_LT, // 11 62 COND_GT, // 12 63 COND_LE, // 13 64 COND_AL, // 14 65 COND_UC // 15 66 }; 67 68 enum MiscRegIndex { 69 MISCREG_CPSR = 0, 70 MISCREG_SPSR, 71 MISCREG_SPSR_FIQ, 72 MISCREG_SPSR_IRQ, 73 MISCREG_SPSR_SVC, 74 MISCREG_SPSR_MON, 75 MISCREG_SPSR_UND, 76 MISCREG_SPSR_ABT, 77 MISCREG_FPSR, 78 MISCREG_FPSID, 79 MISCREG_FPSCR, 80 MISCREG_FPEXC, 81 MISCREG_MVFR0, 82 MISCREG_MVFR1, 83 MISCREG_SCTLR_RST, 84 MISCREG_SEV_MAILBOX, 85 86 // CP15 registers 87 MISCREG_CP15_START, 88 MISCREG_SCTLR = MISCREG_CP15_START, 89 MISCREG_DCCISW, 90 MISCREG_DCCIMVAC, 91 MISCREG_DCCMVAC, 92 MISCREG_CONTEXTIDR, 93 MISCREG_TPIDRURW, 94 MISCREG_TPIDRURO, 95 MISCREG_TPIDRPRW, 96 MISCREG_CP15ISB, 97 MISCREG_CP15DSB, 98 MISCREG_CP15DMB, 99 MISCREG_CPACR, 100 MISCREG_CLIDR, 101 MISCREG_CCSIDR, 102 MISCREG_CSSELR, 103 MISCREG_ICIALLUIS, 104 MISCREG_ICIALLU, 105 MISCREG_ICIMVAU, 106 MISCREG_BPIMVA, 107 MISCREG_BPIALLIS, 108 MISCREG_BPIALL, 109 MISCREG_MIDR, 110 MISCREG_TTBR0, 111 MISCREG_TTBR1, 112 MISCREG_TLBTR, 113 MISCREG_DACR, 114 MISCREG_TLBIALLIS, 115 MISCREG_TLBIMVAIS, 116 MISCREG_TLBIASIDIS, 117 MISCREG_TLBIMVAAIS, 118 MISCREG_ITLBIALL, 119 MISCREG_ITLBIMVA, 120 MISCREG_ITLBIASID, 121 MISCREG_DTLBIALL, 122 MISCREG_DTLBIMVA, 123 MISCREG_DTLBIASID, 124 MISCREG_TLBIALL, 125 MISCREG_TLBIMVA, 126 MISCREG_TLBIASID, 127 MISCREG_TLBIMVAA, 128 MISCREG_DFSR, 129 MISCREG_IFSR, 130 MISCREG_DFAR, 131 MISCREG_IFAR, 132 MISCREG_MPIDR, 133 MISCREG_PRRR, 134 MISCREG_NMRR, 135 MISCREG_TTBCR, 136 MISCREG_ID_PFR0, 137 MISCREG_CP15_UNIMP_START, 138 MISCREG_CTR = MISCREG_CP15_UNIMP_START, 139 MISCREG_TCMTR, 140 MISCREG_ID_PFR1, 141 MISCREG_ID_DFR0, 142 MISCREG_ID_AFR0, 143 MISCREG_ID_MMFR0, 144 MISCREG_ID_MMFR1, 145 MISCREG_ID_MMFR2, 146 MISCREG_ID_MMFR3, 147 MISCREG_ID_ISAR0, 148 MISCREG_ID_ISAR1, 149 MISCREG_ID_ISAR2, 150 MISCREG_ID_ISAR3, 151 MISCREG_ID_ISAR4, 152 MISCREG_ID_ISAR5, 153 MISCREG_PAR, 154 MISCREG_AIDR, 155 MISCREG_ACTLR, 156 MISCREG_ADFSR, 157 MISCREG_AIFSR, 158 MISCREG_DCIMVAC, 159 MISCREG_DCISW, 160 MISCREG_MCCSW, 161 MISCREG_DCCMVAU, 162 MISCREG_SCR, 163 MISCREG_SDER, 164 MISCREG_NSACR, 165 MISCREG_V2PCWPR, 166 MISCREG_V2PCWPW, 167 MISCREG_V2PCWUR, 168 MISCREG_V2PCWUW, 169 MISCREG_V2POWPR, 170 MISCREG_V2POWPW, 171 MISCREG_V2POWUR, 172 MISCREG_V2POWUW, 173 MISCREG_VBAR, 174 MISCREG_MVBAR, 175 MISCREG_ISR, 176 MISCREG_FCEIDR, 177 178 179 MISCREG_CP15_END, 180 181 // Dummy indices 182 MISCREG_NOP = MISCREG_CP15_END, 183 MISCREG_RAZ, 184 185 NUM_MISCREGS 186 }; 187 188 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 189 unsigned crm, unsigned opc2); 190 191 const char * const miscRegName[NUM_MISCREGS] = { 192 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 193 "spsr_mon", "spsr_und", "spsr_abt", 194 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1", 195 "sctlr_rst", "sev_mailbox", 196 "sctlr", "dccisw", "dccimvac", "dccmvac", 197 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 198 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 199 "clidr", "ccsidr", "csselr", 200 "icialluis", "iciallu", "icimvau", 201 "bpimva", "bpiallis", "bpiall", 202 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 203 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 204 "itlbiall", "itlbimva", "itlbiasid", 205 "dtlbiall", "dtlbimva", "dtlbiasid", 206 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 207 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 208 "prrr", "nmrr", "ttbcr", "id_pfr0", 209 // Unimplemented below 210 "ctr", "tcmtr", 211 "id_pfr1", "id_dfr0", "id_afr0", 212 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", 213 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 214 "par", "aidr", "actlr", 215 "adfsr", "aifsr", 216 "dcimvac", "dcisw", "mccsw", 217 "dccmvau", 218 "scr", "sder", "nsacr", 219 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 220 "v2powpr", "v2powpw", "v2powur", "v2powuw", 221 "vbar", "mvbar", "isr", "fceidr", 222 "nop", "raz" 223 }; 224 225 BitUnion32(CPSR) 226 Bitfield<31> n; 227 Bitfield<30> z; 228 Bitfield<29> c; 229 Bitfield<28> v; 230 Bitfield<27> q; 231 Bitfield<26,25> it1; 232 Bitfield<24> j; 233 Bitfield<19, 16> ge; 234 Bitfield<15,10> it2; 235 Bitfield<9> e; 236 Bitfield<8> a; 237 Bitfield<7> i; 238 Bitfield<6> f; 239 Bitfield<5> t; 240 Bitfield<4, 0> mode; 241 EndBitUnion(CPSR) 242 243 // This mask selects bits of the CPSR that actually go in the CondCodes 244 // integer register to allow renaming. 245 static const uint32_t CondCodesMask = 0xF80F0000; 246 247 BitUnion32(SCTLR) 248 Bitfield<31> ie; // Instruction endianness 249 Bitfield<30> te; // Thumb Exception Enable 250 Bitfield<29> afe; // Access flag enable 251 Bitfield<28> tre; // TEX Remap bit 252 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 253 Bitfield<25> ee; // Exception Endianness bit 254 Bitfield<24> ve; // Interrupt vectors enable 255 Bitfield<23> rao1;// Read as one 256 Bitfield<22> u; // Alignment (now unused) 257 Bitfield<21> fi; // Fast interrupts configuration enable 258 Bitfield<19> dz; // Divide by Zero fault enable bit 259 Bitfield<18> rao2;// Read as one 260 Bitfield<17> br; // Background region bit 261 Bitfield<16> rao3;// Read as one 262 Bitfield<14> rr; // Round robin cache replacement 263 Bitfield<13> v; // Base address for exception vectors 264 Bitfield<12> i; // instruction cache enable 265 Bitfield<11> z; // branch prediction enable bit 266 Bitfield<10> sw; // Enable swp/swpb 267 Bitfield<6,3> rao4;// Read as one 268 Bitfield<7> b; // Endianness support (unused) 269 Bitfield<2> c; // Cache enable bit 270 Bitfield<1> a; // Alignment fault checking 271 Bitfield<0> m; // MMU enable bit 272 EndBitUnion(SCTLR) 273 274 BitUnion32(CPACR) 275 Bitfield<1, 0> cp0; 276 Bitfield<3, 2> cp1; 277 Bitfield<5, 4> cp2; 278 Bitfield<7, 6> cp3; 279 Bitfield<9, 8> cp4; 280 Bitfield<11, 10> cp5; 281 Bitfield<13, 12> cp6; 282 Bitfield<15, 14> cp7; 283 Bitfield<17, 16> cp8; 284 Bitfield<19, 18> cp9; 285 Bitfield<21, 20> cp10; 286 Bitfield<23, 22> cp11; 287 Bitfield<25, 24> cp12; 288 Bitfield<27, 26> cp13; 289 Bitfield<30> d32dis; 290 Bitfield<31> asedis; 291 EndBitUnion(CPACR) 292 293 BitUnion32(FSR) 294 Bitfield<3, 0> fsLow; 295 Bitfield<7, 4> domain; 296 Bitfield<10> fsHigh; 297 Bitfield<11> wnr; 298 Bitfield<12> ext; 299 EndBitUnion(FSR) 300 301 BitUnion32(FPSCR) 302 Bitfield<0> ioc; 303 Bitfield<1> dzc; 304 Bitfield<2> ofc; 305 Bitfield<3> ufc; 306 Bitfield<4> ixc; 307 Bitfield<7> idc; 308 Bitfield<8> ioe; 309 Bitfield<9> dze; 310 Bitfield<10> ofe; 311 Bitfield<11> ufe; 312 Bitfield<12> ixe; 313 Bitfield<15> ide; 314 Bitfield<18, 16> len; 315 Bitfield<21, 20> stride; 316 Bitfield<23, 22> rMode; 317 Bitfield<24> fz; 318 Bitfield<25> dn; 319 Bitfield<26> ahp; 320 Bitfield<27> qc; 321 Bitfield<28> v; 322 Bitfield<29> c; 323 Bitfield<30> z; 324 Bitfield<31> n; 325 EndBitUnion(FPSCR) 326 327 BitUnion32(MVFR0) 328 Bitfield<3, 0> advSimdRegisters; 329 Bitfield<7, 4> singlePrecision; 330 Bitfield<11, 8> doublePrecision; 331 Bitfield<15, 12> vfpExceptionTrapping; 332 Bitfield<19, 16> divide; 333 Bitfield<23, 20> squareRoot; 334 Bitfield<27, 24> shortVectors; 335 Bitfield<31, 28> roundingModes; 336 EndBitUnion(MVFR0) 337 338 BitUnion32(MVFR1) 339 Bitfield<3, 0> flushToZero; 340 Bitfield<7, 4> defaultNaN; 341 Bitfield<11, 8> advSimdLoadStore; 342 Bitfield<15, 12> advSimdInteger; 343 Bitfield<19, 16> advSimdSinglePrecision; 344 Bitfield<23, 20> advSimdHalfPrecision; 345 Bitfield<27, 24> vfpHalfPrecision; 346 Bitfield<31, 28> raz; 347 EndBitUnion(MVFR1) 348 349 BitUnion32(PRRR) 350 Bitfield<1,0> tr0; 351 Bitfield<3,2> tr1; 352 Bitfield<5,4> tr2; 353 Bitfield<7,6> tr3; 354 Bitfield<9,8> tr4; 355 Bitfield<11,10> tr5; 356 Bitfield<13,12> tr6; 357 Bitfield<15,14> tr7; 358 Bitfield<16> ds0; 359 Bitfield<17> ds1; 360 Bitfield<18> ns0; 361 Bitfield<19> ns1; 362 Bitfield<24> nos0; 363 Bitfield<25> nos1; 364 Bitfield<26> nos2; 365 Bitfield<27> nos3; 366 Bitfield<28> nos4; 367 Bitfield<29> nos5; 368 Bitfield<30> nos6; 369 Bitfield<31> nos7; 370 EndBitUnion(PRRR) 371 372 BitUnion32(NMRR) 373 Bitfield<1,0> ir0; 374 Bitfield<3,2> ir1; 375 Bitfield<5,4> ir2; 376 Bitfield<7,6> ir3; 377 Bitfield<9,8> ir4; 378 Bitfield<11,10> ir5; 379 Bitfield<13,12> ir6; 380 Bitfield<15,14> ir7; 381 Bitfield<17,16> or0; 382 Bitfield<19,18> or1; 383 Bitfield<21,20> or2; 384 Bitfield<23,22> or3; 385 Bitfield<25,24> or4; 386 Bitfield<27,26> or5; 387 Bitfield<29,28> or6; 388 Bitfield<31,30> or7; 389 EndBitUnion(NMRR) 390 391}; 392 393#endif // __ARCH_ARM_MISCREGS_HH__ 394