miscregs.hh revision 7349:8b4564729c81 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49    enum ConditionCode {
50        COND_EQ  =   0,
51        COND_NE, //  1
52        COND_CS, //  2
53        COND_CC, //  3
54        COND_MI, //  4
55        COND_PL, //  5
56        COND_VS, //  6
57        COND_VC, //  7
58        COND_HI, //  8
59        COND_LS, //  9
60        COND_GE, // 10
61        COND_LT, // 11
62        COND_GT, // 12
63        COND_LE, // 13
64        COND_AL, // 14
65        COND_UC  // 15
66    };
67
68    enum MiscRegIndex {
69        MISCREG_CPSR = 0,
70        MISCREG_SPSR,
71        MISCREG_SPSR_FIQ,
72        MISCREG_SPSR_IRQ,
73        MISCREG_SPSR_SVC,
74        MISCREG_SPSR_MON,
75        MISCREG_SPSR_UND,
76        MISCREG_SPSR_ABT,
77        MISCREG_FPSR,
78        MISCREG_FPSID,
79        MISCREG_FPSCR,
80        MISCREG_FPEXC,
81        MISCREG_MVFR0,
82        MISCREG_MVFR1,
83
84        // CP15 registers
85        MISCREG_CP15_START,
86        MISCREG_SCTLR = MISCREG_CP15_START,
87        MISCREG_DCCISW,
88        MISCREG_DCCIMVAC,
89        MISCREG_DCCMVAC,
90        MISCREG_CONTEXTIDR,
91        MISCREG_TPIDRURW,
92        MISCREG_TPIDRURO,
93        MISCREG_TPIDRPRW,
94        MISCREG_CP15ISB,
95        MISCREG_CP15DSB,
96        MISCREG_CP15DMB,
97        MISCREG_CPACR,
98        MISCREG_CLIDR,
99        MISCREG_CCSIDR,
100        MISCREG_CSSELR,
101        MISCREG_ICIALLUIS,
102        MISCREG_ICIALLU,
103        MISCREG_ICIMVAU,
104        MISCREG_BPIMVA,
105        MISCREG_BPIALLIS,
106        MISCREG_BPIALL,
107        MISCREG_MPUIR,
108        MISCREG_MIDR,
109        MISCREG_RGNR,
110        MISCREG_DRBAR,
111        MISCREG_DRACR,
112        MISCREG_DRSR,
113        MISCREG_CP15_UNIMP_START,
114        MISCREG_CTR = MISCREG_CP15_UNIMP_START,
115        MISCREG_TCMTR,
116        MISCREG_MPIDR,
117        MISCREG_ID_PFR0,
118        MISCREG_ID_PFR1,
119        MISCREG_ID_DFR0,
120        MISCREG_ID_AFR0,
121        MISCREG_ID_MMFR0,
122        MISCREG_ID_MMFR1,
123        MISCREG_ID_MMFR2,
124        MISCREG_ID_MMFR3,
125        MISCREG_ID_ISAR0,
126        MISCREG_ID_ISAR1,
127        MISCREG_ID_ISAR2,
128        MISCREG_ID_ISAR3,
129        MISCREG_ID_ISAR4,
130        MISCREG_ID_ISAR5,
131        MISCREG_AIDR,
132        MISCREG_ACTLR,
133        MISCREG_DFSR,
134        MISCREG_IFSR,
135        MISCREG_ADFSR,
136        MISCREG_AIFSR,
137        MISCREG_DFAR,
138        MISCREG_IFAR,
139        MISCREG_IRBAR,
140        MISCREG_IRSR,
141        MISCREG_IRACR,
142        MISCREG_DCIMVAC,
143        MISCREG_DCISW,
144        MISCREG_MCCSW,
145        MISCREG_DCCMVAU,
146
147        MISCREG_CP15_END,
148
149        // Dummy indices
150        MISCREG_NOP = MISCREG_CP15_END,
151        MISCREG_RAZ,
152
153        NUM_MISCREGS
154    };
155
156    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
157                               unsigned crm, unsigned opc2);
158
159    const char * const miscRegName[NUM_MISCREGS] = {
160        "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
161        "spsr_mon", "spsr_und", "spsr_abt",
162        "fpsr", "fpsid", "fpscr", "fpexc",
163        "sctlr", "dccisw", "dccimvac", "dccmvac",
164        "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
165        "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
166        "clidr", "ccsidr", "csselr",
167        "icialluis", "iciallu", "icimvau",
168        "bpimva", "bpiallis", "bpiall",
169        "mpuir", "midr", "rgnr", "drbar", "dracr", "drsr",
170        "ctr", "tcmtr", "mpidr",
171        "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
172        "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
173        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
174        "aidr", "actlr",
175        "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
176        "irbar", "irsr", "iracr",
177        "dcimvac", "dcisw", "mccsw",
178        "dccmvau",
179        "nop", "raz"
180    };
181
182    BitUnion32(CPSR)
183        Bitfield<31> n;
184        Bitfield<30> z;
185        Bitfield<29> c;
186        Bitfield<28> v;
187        Bitfield<27> q;
188        Bitfield<26,25> it1;
189        Bitfield<24> j;
190        Bitfield<19, 16> ge;
191        Bitfield<15,10> it2;
192        Bitfield<9> e;
193        Bitfield<8> a;
194        Bitfield<7> i;
195        Bitfield<6> f;
196        Bitfield<5> t;
197        Bitfield<4, 0> mode;
198    EndBitUnion(CPSR)
199
200    // This mask selects bits of the CPSR that actually go in the CondCodes
201    // integer register to allow renaming.
202    static const uint32_t CondCodesMask = 0xF80F0000;
203
204    BitUnion32(SCTLR)
205        Bitfield<30> te;  // Thumb Exception Enable
206        Bitfield<29> afe; // Access flag enable
207        Bitfield<28> tre; // TEX Remap bit
208        Bitfield<27> nmfi;// Non-maskable fast interrupts enable
209        Bitfield<25> ee;  // Exception Endianness bit
210        Bitfield<24> ve;  // Interrupt vectors enable
211        Bitfield<23> rao1;// Read as one
212        Bitfield<22> u;   // Alignment (now unused)
213        Bitfield<21> fi;  // Fast interrupts configuration enable
214        Bitfield<18> rao2;// Read as one
215        Bitfield<17> ha;  // Hardware access flag enable
216        Bitfield<16> rao3;// Read as one
217        Bitfield<14> rr;  // Round robin cache replacement
218        Bitfield<13> v;   // Base address for exception vectors
219        Bitfield<12> i;   // instruction cache enable
220        Bitfield<11> z;   // branch prediction enable bit
221        Bitfield<10> sw;  // Enable swp/swpb
222        Bitfield<6,3> rao4;// Read as one
223        Bitfield<7>  b;   // Endianness support (unused)
224        Bitfield<2>  c;   // Cache enable bit
225        Bitfield<1>  a;   // Alignment fault checking
226        Bitfield<0>  m;   // MMU enable bit
227    EndBitUnion(SCTLR)
228
229    BitUnion32(CPACR)
230        Bitfield<1, 0> cp0;
231        Bitfield<3, 2> cp1;
232        Bitfield<5, 4> cp2;
233        Bitfield<7, 6> cp3;
234        Bitfield<9, 8> cp4;
235        Bitfield<11, 10> cp5;
236        Bitfield<13, 12> cp6;
237        Bitfield<15, 14> cp7;
238        Bitfield<17, 16> cp8;
239        Bitfield<19, 18> cp9;
240        Bitfield<21, 20> cp10;
241        Bitfield<23, 22> cp11;
242        Bitfield<25, 24> cp12;
243        Bitfield<27, 26> cp13;
244        Bitfield<30> d32dis;
245        Bitfield<31> asedis;
246    EndBitUnion(CPACR)
247};
248
249#endif // __ARCH_ARM_MISCREGS_HH__
250