miscregs.hh revision 7298
13021SN/A/* 23021SN/A * Copyright (c) 2010 ARM Limited 39285Sandreas.hansson@arm.com * All rights reserved 49285Sandreas.hansson@arm.com * 59285Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68540SN/A * not be construed as granting a license to any other intellectual 710220Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 810220Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 910220Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1010220Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1110220Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129150SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 139150SAli.Saidi@ARM.com * 1410036SAli.Saidi@ARM.com * Copyright (c) 2009 The Regents of The University of Michigan 1510036SAli.Saidi@ARM.com * All rights reserved. 169055Ssaidi@eecs.umich.edu * 179055Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 189055Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 199055Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 209055Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 219055Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 229055Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 239055Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 249285Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 259285Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 269285Sandreas.hansson@arm.com * this software without specific prior written permission. 279285Sandreas.hansson@arm.com * 289285Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299285Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309285Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319285Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329729Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339729Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349729Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359729Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369729Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379838Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389838Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399838Sandreas.hansson@arm.com * 409838Sandreas.hansson@arm.com * Authors: Gabe Black 419729Sandreas.hansson@arm.com */ 429729Sandreas.hansson@arm.com#ifndef __ARCH_ARM_MISCREGS_HH__ 439729Sandreas.hansson@arm.com#define __ARCH_ARM_MISCREGS_HH__ 449729Sandreas.hansson@arm.com 459729Sandreas.hansson@arm.com#include "base/bitunion.hh" 469729Sandreas.hansson@arm.com 4710036SAli.Saidi@ARM.comnamespace ArmISA 488540SN/A{ 498540SN/A enum ConditionCode { 508540SN/A COND_EQ = 0, 518540SN/A COND_NE, // 1 528540SN/A COND_CS, // 2 538540SN/A COND_CC, // 3 548540SN/A COND_MI, // 4 558540SN/A COND_PL, // 5 568540SN/A COND_VS, // 6 578540SN/A COND_VC, // 7 588540SN/A COND_HI, // 8 598540SN/A COND_LS, // 9 608540SN/A COND_GE, // 10 618540SN/A COND_LT, // 11 628540SN/A COND_GT, // 12 638540SN/A COND_LE, // 13 648540SN/A COND_AL, // 14 658540SN/A COND_UC // 15 668540SN/A }; 679285Sandreas.hansson@arm.com 688540SN/A enum MiscRegIndex { 698540SN/A MISCREG_CPSR = 0, 709150SAli.Saidi@ARM.com MISCREG_SPSR, 719150SAli.Saidi@ARM.com MISCREG_SPSR_FIQ, 729150SAli.Saidi@ARM.com MISCREG_SPSR_IRQ, 738540SN/A MISCREG_SPSR_SVC, 748540SN/A MISCREG_SPSR_MON, 759150SAli.Saidi@ARM.com MISCREG_SPSR_UND, 769150SAli.Saidi@ARM.com MISCREG_SPSR_ABT, 778540SN/A MISCREG_FPSR, 789150SAli.Saidi@ARM.com MISCREG_FPSID, 799150SAli.Saidi@ARM.com MISCREG_FPSCR, 808540SN/A MISCREG_FPEXC, 818540SN/A 829150SAli.Saidi@ARM.com // CP15 registers 839150SAli.Saidi@ARM.com MISCREG_CP15_START, 848540SN/A MISCREG_SCTLR = MISCREG_CP15_START, 858540SN/A MISCREG_DCCISW, 869285Sandreas.hansson@arm.com MISCREG_DCCIMVAC, 878540SN/A MISCREG_DCCMVAC, 888540SN/A MISCREG_CONTEXTIDR, 8910063Snilay@cs.wisc.edu MISCREG_TPIDRURW, 9010220Sandreas.hansson@arm.com MISCREG_TPIDRURO, 9110220Sandreas.hansson@arm.com MISCREG_TPIDRPRW, 9210220Sandreas.hansson@arm.com MISCREG_CP15ISB, 9310220Sandreas.hansson@arm.com MISCREG_CP15DSB, 9410220Sandreas.hansson@arm.com MISCREG_CP15DMB, 9510220Sandreas.hansson@arm.com MISCREG_CPACR, 9610220Sandreas.hansson@arm.com MISCREG_CLIDR, 9710220Sandreas.hansson@arm.com MISCREG_CCSIDR, 9810220Sandreas.hansson@arm.com MISCREG_CSSELR, 9910220Sandreas.hansson@arm.com MISCREG_ICIALLUIS, 10010220Sandreas.hansson@arm.com MISCREG_ICIALLU, 10110220Sandreas.hansson@arm.com MISCREG_ICIMVAU, 10210220Sandreas.hansson@arm.com MISCREG_BPIMVA, 10310220Sandreas.hansson@arm.com MISCREG_BPIALLIS, 10410220Sandreas.hansson@arm.com MISCREG_BPIALL, 10510220Sandreas.hansson@arm.com MISCREG_MPUIR, 10610220Sandreas.hansson@arm.com MISCREG_MIDR, 10710220Sandreas.hansson@arm.com MISCREG_CP15_UNIMP_START, 10810220Sandreas.hansson@arm.com MISCREG_CTR = MISCREG_CP15_UNIMP_START, 10910220Sandreas.hansson@arm.com MISCREG_TCMTR, 11010220Sandreas.hansson@arm.com MISCREG_MPIDR, 11110220Sandreas.hansson@arm.com MISCREG_ID_PFR0, 11210220Sandreas.hansson@arm.com MISCREG_ID_PFR1, 11310220Sandreas.hansson@arm.com MISCREG_ID_DFR0, 11410220Sandreas.hansson@arm.com MISCREG_ID_AFR0, 11510220Sandreas.hansson@arm.com MISCREG_ID_MMFR0, 11610220Sandreas.hansson@arm.com MISCREG_ID_MMFR1, 11710220Sandreas.hansson@arm.com MISCREG_ID_MMFR2, 11810220Sandreas.hansson@arm.com MISCREG_ID_MMFR3, 11910220Sandreas.hansson@arm.com MISCREG_ID_ISAR0, 12010220Sandreas.hansson@arm.com MISCREG_ID_ISAR1, 12110220Sandreas.hansson@arm.com MISCREG_ID_ISAR2, 12210220Sandreas.hansson@arm.com MISCREG_ID_ISAR3, 12310220Sandreas.hansson@arm.com MISCREG_ID_ISAR4, 12410220Sandreas.hansson@arm.com MISCREG_ID_ISAR5, 1259838Sandreas.hansson@arm.com MISCREG_AIDR, 1269838Sandreas.hansson@arm.com MISCREG_ACTLR, 1279838Sandreas.hansson@arm.com MISCREG_DFSR, 1289838Sandreas.hansson@arm.com MISCREG_IFSR, 1299838Sandreas.hansson@arm.com MISCREG_ADFSR, 1309838Sandreas.hansson@arm.com MISCREG_AIFSR, 1319838Sandreas.hansson@arm.com MISCREG_DFAR, 1329838Sandreas.hansson@arm.com MISCREG_IFAR, 1339838Sandreas.hansson@arm.com MISCREG_DRBAR, 13410036SAli.Saidi@ARM.com MISCREG_IRBAR, 13510036SAli.Saidi@ARM.com MISCREG_DRSR, 13610036SAli.Saidi@ARM.com MISCREG_IRSR, 13710036SAli.Saidi@ARM.com MISCREG_DRACR, 13810036SAli.Saidi@ARM.com MISCREG_IRACR, 13910036SAli.Saidi@ARM.com MISCREG_RGNR, 1409150SAli.Saidi@ARM.com MISCREG_DCIMVAC, 1419150SAli.Saidi@ARM.com MISCREG_DCISW, 1429150SAli.Saidi@ARM.com MISCREG_MCCSW, 1439150SAli.Saidi@ARM.com MISCREG_DCCMVAU, 1449150SAli.Saidi@ARM.com 1459150SAli.Saidi@ARM.com MISCREG_CP15_END, 1468835SAli.Saidi@ARM.com 1478835SAli.Saidi@ARM.com // Dummy indices 1488835SAli.Saidi@ARM.com MISCREG_NOP = MISCREG_CP15_END, 1498835SAli.Saidi@ARM.com MISCREG_RAZ, 1508835SAli.Saidi@ARM.com 1518835SAli.Saidi@ARM.com NUM_MISCREGS 1529285Sandreas.hansson@arm.com }; 1539285Sandreas.hansson@arm.com 1549285Sandreas.hansson@arm.com MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 1559285Sandreas.hansson@arm.com unsigned crm, unsigned opc2); 1569285Sandreas.hansson@arm.com 1579285Sandreas.hansson@arm.com const char * const miscRegName[NUM_MISCREGS] = { 1589150SAli.Saidi@ARM.com "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 1599150SAli.Saidi@ARM.com "spsr_mon", "spsr_und", "spsr_abt", 1609150SAli.Saidi@ARM.com "fpsr", "fpsid", "fpscr", "fpexc", 1619150SAli.Saidi@ARM.com "sctlr", "dccisw", "dccimvac", "dccmvac", 1629150SAli.Saidi@ARM.com "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 1639150SAli.Saidi@ARM.com "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 1649150SAli.Saidi@ARM.com "clidr", "ccsidr", "csselr", 1659150SAli.Saidi@ARM.com "icialluis", "iciallu", "icimvau", 1669150SAli.Saidi@ARM.com "bpimva", "bpiallis", "bpiall", 1679150SAli.Saidi@ARM.com "mpuir", "midr", "ctr", "tcmtr", "mpidr", 1689150SAli.Saidi@ARM.com "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", 1699150SAli.Saidi@ARM.com "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", 1709285Sandreas.hansson@arm.com "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 1719285Sandreas.hansson@arm.com "aidr", "actlr", 1729285Sandreas.hansson@arm.com "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", 1739285Sandreas.hansson@arm.com "drbar", "irbar", "drsr", "irsr", "dracr", "iracr", 1749285Sandreas.hansson@arm.com "rgnr", 1759285Sandreas.hansson@arm.com "dcimvac", "dcisw", "mccsw", 1768540SN/A "dccmvau", 1778540SN/A "nop", "raz" 1788540SN/A }; 1798540SN/A 1808983Snate@binkert.org BitUnion32(CPSR) 1818983Snate@binkert.org Bitfield<31> n; 1828540SN/A Bitfield<30> z; 1838540SN/A Bitfield<29> c; 1848835SAli.Saidi@ARM.com Bitfield<28> v; 1858835SAli.Saidi@ARM.com Bitfield<27> q; 1868835SAli.Saidi@ARM.com Bitfield<26,25> it1; 1878835SAli.Saidi@ARM.com Bitfield<24> j; 1888835SAli.Saidi@ARM.com Bitfield<19, 16> ge; 1898835SAli.Saidi@ARM.com Bitfield<15,10> it2; 1908835SAli.Saidi@ARM.com Bitfield<9> e; 1918835SAli.Saidi@ARM.com Bitfield<8> a; 1928835SAli.Saidi@ARM.com Bitfield<7> i; 1938835SAli.Saidi@ARM.com Bitfield<6> f; 1948835SAli.Saidi@ARM.com Bitfield<5> t; 1958835SAli.Saidi@ARM.com Bitfield<4, 0> mode; 1969150SAli.Saidi@ARM.com EndBitUnion(CPSR) 1979150SAli.Saidi@ARM.com 1989150SAli.Saidi@ARM.com // This mask selects bits of the CPSR that actually go in the CondCodes 1999150SAli.Saidi@ARM.com // integer register to allow renaming. 2009150SAli.Saidi@ARM.com static const uint32_t CondCodesMask = 0xF80F0000; 2019150SAli.Saidi@ARM.com 2028835SAli.Saidi@ARM.com // These otherwise unused bits of the PC are used to select a mode 2039055Ssaidi@eecs.umich.edu // like the J and T bits of the CPSR. 2048835SAli.Saidi@ARM.com static const Addr PcJBitShift = 33; 2059055Ssaidi@eecs.umich.edu static const Addr PcTBitShift = 34; 2068835SAli.Saidi@ARM.com static const Addr PcModeMask = (ULL(1) << PcJBitShift) | 2079055Ssaidi@eecs.umich.edu (ULL(1) << PcTBitShift); 2088540SN/A 2099838Sandreas.hansson@arm.com BitUnion32(SCTLR) 2109838Sandreas.hansson@arm.com Bitfield<30> te; // Thumb Exception Enable 2119838Sandreas.hansson@arm.com Bitfield<29> afe; // Access flag enable 2129838Sandreas.hansson@arm.com Bitfield<28> tre; // TEX Remap bit 2139838Sandreas.hansson@arm.com Bitfield<27> nmfi;// Non-maskable fast interrupts enable 2149838Sandreas.hansson@arm.com Bitfield<25> ee; // Exception Endianness bit 2159838Sandreas.hansson@arm.com Bitfield<24> ve; // Interrupt vectors enable 2169838Sandreas.hansson@arm.com Bitfield<23> rao1;// Read as one 2179797Sandreas.hansson@arm.com Bitfield<22> u; // Alignment (now unused) 2189797Sandreas.hansson@arm.com Bitfield<21> fi; // Fast interrupts configuration enable 2199838Sandreas.hansson@arm.com Bitfield<18> rao2;// Read as one 22010036SAli.Saidi@ARM.com Bitfield<17> ha; // Hardware access flag enable 22110036SAli.Saidi@ARM.com Bitfield<16> rao3;// Read as one 22210036SAli.Saidi@ARM.com Bitfield<14> rr; // Round robin cache replacement 22310036SAli.Saidi@ARM.com Bitfield<13> v; // Base address for exception vectors 22410036SAli.Saidi@ARM.com Bitfield<12> i; // instruction cache enable 22510036SAli.Saidi@ARM.com Bitfield<11> z; // branch prediction enable bit 2268835SAli.Saidi@ARM.com Bitfield<10> sw; // Enable swp/swpb 2278835SAli.Saidi@ARM.com Bitfield<6,3> rao4;// Read as one 2288835SAli.Saidi@ARM.com Bitfield<7> b; // Endianness support (unused) 2298835SAli.Saidi@ARM.com Bitfield<2> c; // Cache enable bit 2308835SAli.Saidi@ARM.com Bitfield<1> a; // Alignment fault checking 2318835SAli.Saidi@ARM.com Bitfield<0> m; // MMU enable bit 2328835SAli.Saidi@ARM.com EndBitUnion(SCTLR) 2338835SAli.Saidi@ARM.com}; 2348835SAli.Saidi@ARM.com 2358835SAli.Saidi@ARM.com#endif // __ARCH_ARM_MISCREGS_HH__ 2368835SAli.Saidi@ARM.com