miscregs.hh revision 7286
17949SAli.Saidi@ARM.com/* 27949SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37949SAli.Saidi@ARM.com * All rights reserved 47949SAli.Saidi@ARM.com * 57949SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67949SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77949SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87949SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97949SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107949SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117949SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127949SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137949SAli.Saidi@ARM.com * 147949SAli.Saidi@ARM.com * Copyright (c) 2009 The Regents of The University of Michigan 157949SAli.Saidi@ARM.com * All rights reserved. 167949SAli.Saidi@ARM.com * 177949SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 187949SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 197949SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 207949SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 217949SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 227949SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 237949SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 247949SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 257949SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 267949SAli.Saidi@ARM.com * this software without specific prior written permission. 277949SAli.Saidi@ARM.com * 287949SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297949SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307949SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317949SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327949SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337949SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347949SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357949SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367949SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377949SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387949SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397949SAli.Saidi@ARM.com * 407949SAli.Saidi@ARM.com * Authors: Gabe Black 417949SAli.Saidi@ARM.com */ 427949SAli.Saidi@ARM.com#ifndef __ARCH_ARM_MISCREGS_HH__ 437949SAli.Saidi@ARM.com#define __ARCH_ARM_MISCREGS_HH__ 447949SAli.Saidi@ARM.com 457949SAli.Saidi@ARM.com#include "base/bitunion.hh" 468635Schris.emmons@arm.com 477949SAli.Saidi@ARM.comnamespace ArmISA 488635Schris.emmons@arm.com{ 498635Schris.emmons@arm.com enum ConditionCode { 507949SAli.Saidi@ARM.com COND_EQ = 0, 517949SAli.Saidi@ARM.com COND_NE, // 1 527949SAli.Saidi@ARM.com COND_CS, // 2 538229Snate@binkert.org COND_CC, // 3 548229Snate@binkert.org COND_MI, // 4 558229Snate@binkert.org COND_PL, // 5 568229Snate@binkert.org COND_VS, // 6 577949SAli.Saidi@ARM.com COND_VC, // 7 588635Schris.emmons@arm.com COND_HI, // 8 597949SAli.Saidi@ARM.com COND_LS, // 9 608635Schris.emmons@arm.com COND_GE, // 10 617949SAli.Saidi@ARM.com COND_LT, // 11 627949SAli.Saidi@ARM.com COND_GT, // 12 638232Snate@binkert.org COND_LE, // 13 647949SAli.Saidi@ARM.com COND_AL, // 14 658635Schris.emmons@arm.com COND_UC // 15 667949SAli.Saidi@ARM.com }; 677949SAli.Saidi@ARM.com 687949SAli.Saidi@ARM.com enum MiscRegIndex { 699330Schander.sudanthi@arm.com MISCREG_CPSR = 0, 709330Schander.sudanthi@arm.com MISCREG_SPSR, 719330Schander.sudanthi@arm.com MISCREG_SPSR_FIQ, 729330Schander.sudanthi@arm.com MISCREG_SPSR_IRQ, 737949SAli.Saidi@ARM.com MISCREG_SPSR_SVC, 747949SAli.Saidi@ARM.com MISCREG_SPSR_MON, 757949SAli.Saidi@ARM.com MISCREG_SPSR_UND, 767949SAli.Saidi@ARM.com MISCREG_SPSR_ABT, 777949SAli.Saidi@ARM.com MISCREG_FPSR, 787949SAli.Saidi@ARM.com MISCREG_FPSID, 797949SAli.Saidi@ARM.com MISCREG_FPSCR, 807949SAli.Saidi@ARM.com MISCREG_FPEXC, 817949SAli.Saidi@ARM.com 827949SAli.Saidi@ARM.com // CP15 registers 837949SAli.Saidi@ARM.com MISCREG_CP15_START, 847949SAli.Saidi@ARM.com MISCREG_SCTLR = MISCREG_CP15_START, 857949SAli.Saidi@ARM.com MISCREG_DCCISW, 867949SAli.Saidi@ARM.com MISCREG_DCCIMVAC, 877949SAli.Saidi@ARM.com MISCREG_DCCMVAC, 887949SAli.Saidi@ARM.com MISCREG_CONTEXTIDR, 897949SAli.Saidi@ARM.com MISCREG_TPIDRURW, 907949SAli.Saidi@ARM.com MISCREG_TPIDRURO, 917949SAli.Saidi@ARM.com MISCREG_TPIDRPRW, 927949SAli.Saidi@ARM.com MISCREG_CP15ISB, 937949SAli.Saidi@ARM.com MISCREG_CP15DSB, 947949SAli.Saidi@ARM.com MISCREG_CP15DMB, 957949SAli.Saidi@ARM.com MISCREG_CPACR, 967949SAli.Saidi@ARM.com MISCREG_CLIDR, 977949SAli.Saidi@ARM.com MISCREG_ICIALLUIS, 987949SAli.Saidi@ARM.com MISCREG_ICIALLU, 997949SAli.Saidi@ARM.com MISCREG_ICIMVAU, 1007949SAli.Saidi@ARM.com MISCREG_BPIMVA, 1017949SAli.Saidi@ARM.com MISCREG_CP15_UNIMP_START, 1027949SAli.Saidi@ARM.com MISCREG_CTR = MISCREG_CP15_UNIMP_START, 1037949SAli.Saidi@ARM.com MISCREG_TCMTR, 1047949SAli.Saidi@ARM.com MISCREG_MPUIR, 1057949SAli.Saidi@ARM.com MISCREG_MPIDR, 1067949SAli.Saidi@ARM.com MISCREG_MIDR, 1077949SAli.Saidi@ARM.com MISCREG_ID_PFR0, 1089330Schander.sudanthi@arm.com MISCREG_ID_PFR1, 10910360Sandreas.hansson@arm.com MISCREG_ID_DFR0, 11010360Sandreas.hansson@arm.com MISCREG_ID_AFR0, 1117949SAli.Saidi@ARM.com MISCREG_ID_MMFR0, 1127949SAli.Saidi@ARM.com MISCREG_ID_MMFR1, 1137949SAli.Saidi@ARM.com MISCREG_ID_MMFR2, 1147949SAli.Saidi@ARM.com MISCREG_ID_MMFR3, 1157949SAli.Saidi@ARM.com MISCREG_ID_ISAR0, 1167949SAli.Saidi@ARM.com MISCREG_ID_ISAR1, 1177949SAli.Saidi@ARM.com MISCREG_ID_ISAR2, 1187949SAli.Saidi@ARM.com MISCREG_ID_ISAR3, 1197949SAli.Saidi@ARM.com MISCREG_ID_ISAR4, 1207949SAli.Saidi@ARM.com MISCREG_ID_ISAR5, 1217949SAli.Saidi@ARM.com MISCREG_CCSIDR, 1227949SAli.Saidi@ARM.com MISCREG_AIDR, 1237949SAli.Saidi@ARM.com MISCREG_CSSELR, 1247949SAli.Saidi@ARM.com MISCREG_ACTLR, 1257949SAli.Saidi@ARM.com MISCREG_DFSR, 1267949SAli.Saidi@ARM.com MISCREG_IFSR, 1277949SAli.Saidi@ARM.com MISCREG_ADFSR, 1287949SAli.Saidi@ARM.com MISCREG_AIFSR, 1297949SAli.Saidi@ARM.com MISCREG_DFAR, 1307949SAli.Saidi@ARM.com MISCREG_IFAR, 1317949SAli.Saidi@ARM.com MISCREG_DRBAR, 1327949SAli.Saidi@ARM.com MISCREG_IRBAR, 1337949SAli.Saidi@ARM.com MISCREG_DRSR, 1347949SAli.Saidi@ARM.com MISCREG_IRSR, 1357949SAli.Saidi@ARM.com MISCREG_DRACR, 1367949SAli.Saidi@ARM.com MISCREG_IRACR, 1377949SAli.Saidi@ARM.com MISCREG_RGNR, 1387949SAli.Saidi@ARM.com MISCREG_BPIALLIS, 1397949SAli.Saidi@ARM.com MISCREG_BPIALL, 1407949SAli.Saidi@ARM.com MISCREG_DCIMVAC, 1417949SAli.Saidi@ARM.com MISCREG_DCISW, 1427949SAli.Saidi@ARM.com MISCREG_MCCSW, 1437949SAli.Saidi@ARM.com MISCREG_DCCMVAU, 1447949SAli.Saidi@ARM.com 1457949SAli.Saidi@ARM.com MISCREG_CP15_END, 1467949SAli.Saidi@ARM.com 1477949SAli.Saidi@ARM.com // Dummy indices 1487949SAli.Saidi@ARM.com MISCREG_NOP = MISCREG_CP15_END, 1497949SAli.Saidi@ARM.com MISCREG_RAZ, 1507949SAli.Saidi@ARM.com 1517949SAli.Saidi@ARM.com NUM_MISCREGS 1527949SAli.Saidi@ARM.com }; 1537949SAli.Saidi@ARM.com 1547949SAli.Saidi@ARM.com MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 1557949SAli.Saidi@ARM.com unsigned crm, unsigned opc2); 1567949SAli.Saidi@ARM.com 1577949SAli.Saidi@ARM.com const char * const miscRegName[NUM_MISCREGS] = { 1587949SAli.Saidi@ARM.com "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 1597949SAli.Saidi@ARM.com "spsr_mon", "spsr_und", "spsr_abt", 1607949SAli.Saidi@ARM.com "fpsr", "fpsid", "fpscr", "fpexc", 1617949SAli.Saidi@ARM.com "sctlr", "dccisw", "dccimvac", "dccmvac", 1627949SAli.Saidi@ARM.com "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 1637949SAli.Saidi@ARM.com "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr", 1647949SAli.Saidi@ARM.com "icialluis", "iciallu", "icimvau", "bpimva", 1657949SAli.Saidi@ARM.com "ctr", "tcmtr", "mpuir", "mpidr", "midr", 1667949SAli.Saidi@ARM.com "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", 1677949SAli.Saidi@ARM.com "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", 1687949SAli.Saidi@ARM.com "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 1697949SAli.Saidi@ARM.com "ccsidr", "aidr", "csselr", "actlr", 1707949SAli.Saidi@ARM.com "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", 1717949SAli.Saidi@ARM.com "drbar", "irbar", "drsr", "irsr", "dracr", "iracr", 1727949SAli.Saidi@ARM.com "rgnr", "bpiallis", 1737949SAli.Saidi@ARM.com "bpiall", "dcimvac", "dcisw", "mccsw", 1747949SAli.Saidi@ARM.com "dccmvau", 1757949SAli.Saidi@ARM.com "nop", "raz" 1767949SAli.Saidi@ARM.com }; 1777949SAli.Saidi@ARM.com 17810156Sandreas@sandberg.pp.se BitUnion32(CPSR) 17910156Sandreas@sandberg.pp.se Bitfield<31> n; 18010156Sandreas@sandberg.pp.se Bitfield<30> z; 18110156Sandreas@sandberg.pp.se Bitfield<29> c; 18210156Sandreas@sandberg.pp.se Bitfield<28> v; 1837949SAli.Saidi@ARM.com Bitfield<27> q; 1847949SAli.Saidi@ARM.com Bitfield<26,25> it1; 1857949SAli.Saidi@ARM.com Bitfield<24> j; 1867949SAli.Saidi@ARM.com Bitfield<19, 16> ge; 18710422Sandreas.hansson@arm.com Bitfield<15,10> it2; 18810422Sandreas.hansson@arm.com Bitfield<9> e; 1897949SAli.Saidi@ARM.com Bitfield<8> a; 1907949SAli.Saidi@ARM.com Bitfield<7> i; 1917949SAli.Saidi@ARM.com Bitfield<6> f; 1927949SAli.Saidi@ARM.com Bitfield<5> t; 1937949SAli.Saidi@ARM.com Bitfield<4, 0> mode; 1947949SAli.Saidi@ARM.com EndBitUnion(CPSR) 1957949SAli.Saidi@ARM.com 1967949SAli.Saidi@ARM.com // This mask selects bits of the CPSR that actually go in the CondCodes 1977949SAli.Saidi@ARM.com // integer register to allow renaming. 1987949SAli.Saidi@ARM.com static const uint32_t CondCodesMask = 0xF80F0000; 1997949SAli.Saidi@ARM.com 2007949SAli.Saidi@ARM.com // These otherwise unused bits of the PC are used to select a mode 2017949SAli.Saidi@ARM.com // like the J and T bits of the CPSR. 2027949SAli.Saidi@ARM.com static const Addr PcJBitShift = 33; 2037949SAli.Saidi@ARM.com static const Addr PcTBitShift = 34; 2047949SAli.Saidi@ARM.com static const Addr PcModeMask = (ULL(1) << PcJBitShift) | 2057949SAli.Saidi@ARM.com (ULL(1) << PcTBitShift); 2067949SAli.Saidi@ARM.com 2077949SAli.Saidi@ARM.com BitUnion32(SCTLR) 2087949SAli.Saidi@ARM.com Bitfield<30> te; // Thumb Exception Enable 2097949SAli.Saidi@ARM.com Bitfield<29> afe; // Access flag enable 2107949SAli.Saidi@ARM.com Bitfield<28> tre; // TEX Remap bit 2117949SAli.Saidi@ARM.com Bitfield<27> nmfi;// Non-maskable fast interrupts enable 2127949SAli.Saidi@ARM.com Bitfield<25> ee; // Exception Endianness bit 2137949SAli.Saidi@ARM.com Bitfield<24> ve; // Interrupt vectors enable 2147949SAli.Saidi@ARM.com Bitfield<23> rao1;// Read as one 2157949SAli.Saidi@ARM.com Bitfield<22> u; // Alignment (now unused) 2167949SAli.Saidi@ARM.com Bitfield<21> fi; // Fast interrupts configuration enable 2177949SAli.Saidi@ARM.com Bitfield<18> rao2;// Read as one 2187949SAli.Saidi@ARM.com Bitfield<17> ha; // Hardware access flag enable 2197949SAli.Saidi@ARM.com Bitfield<16> rao3;// Read as one 2207949SAli.Saidi@ARM.com Bitfield<14> rr; // Round robin cache replacement 2217949SAli.Saidi@ARM.com Bitfield<13> v; // Base address for exception vectors 2227949SAli.Saidi@ARM.com Bitfield<12> i; // instruction cache enable 2237949SAli.Saidi@ARM.com Bitfield<11> z; // branch prediction enable bit 2247949SAli.Saidi@ARM.com Bitfield<10> sw; // Enable swp/swpb 2257949SAli.Saidi@ARM.com Bitfield<6,3> rao4;// Read as one 2267949SAli.Saidi@ARM.com Bitfield<7> b; // Endianness support (unused) 2277949SAli.Saidi@ARM.com Bitfield<2> c; // Cache enable bit 2287949SAli.Saidi@ARM.com Bitfield<1> a; // Alignment fault checking 2297949SAli.Saidi@ARM.com Bitfield<0> m; // MMU enable bit 2307949SAli.Saidi@ARM.com EndBitUnion(SCTLR) 2317949SAli.Saidi@ARM.com}; 2327949SAli.Saidi@ARM.com 2337949SAli.Saidi@ARM.com#endif // __ARCH_ARM_MISCREGS_HH__ 2347949SAli.Saidi@ARM.com