miscregs.hh revision 14128 
16242Sgblack@eecs.umich.edu/*
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396242Sgblack@eecs.umich.edu *
406242Sgblack@eecs.umich.edu * Authors: Gabe Black
416242Sgblack@eecs.umich.edu *          Giacomo Gabrielli
426242Sgblack@eecs.umich.edu */
436242Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MISCREGS_HH__
446242Sgblack@eecs.umich.edu#define __ARCH_ARM_MISCREGS_HH__
456242Sgblack@eecs.umich.edu
466242Sgblack@eecs.umich.edu#include <bitset>
476242Sgblack@eecs.umich.edu#include <tuple>
486242Sgblack@eecs.umich.edu
496242Sgblack@eecs.umich.edu#include "arch/arm/miscregs_types.hh"
506242Sgblack@eecs.umich.edu#include "base/compiler.hh"
516242Sgblack@eecs.umich.edu
526242Sgblack@eecs.umich.educlass ThreadContext;
536242Sgblack@eecs.umich.edu
546242Sgblack@eecs.umich.edu
556242Sgblack@eecs.umich.edunamespace ArmISA
566242Sgblack@eecs.umich.edu{
576242Sgblack@eecs.umich.edu    enum MiscRegIndex {
586242Sgblack@eecs.umich.edu        MISCREG_CPSR = 0,
596242Sgblack@eecs.umich.edu        MISCREG_SPSR,
606242Sgblack@eecs.umich.edu        MISCREG_SPSR_FIQ,
616242Sgblack@eecs.umich.edu        MISCREG_SPSR_IRQ,
626242Sgblack@eecs.umich.edu        MISCREG_SPSR_SVC,
636242Sgblack@eecs.umich.edu        MISCREG_SPSR_MON,
646242Sgblack@eecs.umich.edu        MISCREG_SPSR_ABT,
657111Sgblack@eecs.umich.edu        MISCREG_SPSR_HYP,
666242Sgblack@eecs.umich.edu        MISCREG_SPSR_UND,
676242Sgblack@eecs.umich.edu        MISCREG_ELR_HYP,
686242Sgblack@eecs.umich.edu        MISCREG_FPSID,
696242Sgblack@eecs.umich.edu        MISCREG_FPSCR,
706735Sgblack@eecs.umich.edu        MISCREG_MVFR1,
716242Sgblack@eecs.umich.edu        MISCREG_MVFR0,
726242Sgblack@eecs.umich.edu        MISCREG_FPEXC,
736242Sgblack@eecs.umich.edu
746723Sgblack@eecs.umich.edu        // Helper registers
756242Sgblack@eecs.umich.edu        MISCREG_CPSR_MODE,
766242Sgblack@eecs.umich.edu        MISCREG_CPSR_Q,
776261Sgblack@eecs.umich.edu        MISCREG_FPSCR_EXC,
786403Sgblack@eecs.umich.edu        MISCREG_FPSCR_QC,
796403Sgblack@eecs.umich.edu        MISCREG_LOCKADDR,
807783SGiacomo.Gabrielli@arm.com        MISCREG_LOCKFLAG,
817783SGiacomo.Gabrielli@arm.com        MISCREG_PRRR_MAIR0,
826403Sgblack@eecs.umich.edu        MISCREG_PRRR_MAIR0_NS,
837325Sgblack@eecs.umich.edu        MISCREG_PRRR_MAIR0_S,
847325Sgblack@eecs.umich.edu        MISCREG_NMRR_MAIR1,
857400SAli.Saidi@ARM.com        MISCREG_NMRR_MAIR1_NS,
867350SAli.Saidi@ARM.com        MISCREG_NMRR_MAIR1_S,
877259Sgblack@eecs.umich.edu        MISCREG_PMXEVTYPER_PMCCFILTR,
887259Sgblack@eecs.umich.edu        MISCREG_SCTLR_RST,
897259Sgblack@eecs.umich.edu        MISCREG_SEV_MAILBOX,
907259Sgblack@eecs.umich.edu
917264Sgblack@eecs.umich.edu        // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
927267Sgblack@eecs.umich.edu        MISCREG_DBGDIDR,
937285Sgblack@eecs.umich.edu        MISCREG_DBGDSCRint,
947265Sgblack@eecs.umich.edu        MISCREG_DBGDCCINT,
957266Sgblack@eecs.umich.edu        MISCREG_DBGDTRTXint,
967266Sgblack@eecs.umich.edu        MISCREG_DBGDTRRXint,
977266Sgblack@eecs.umich.edu        MISCREG_DBGWFAR,
987268Sgblack@eecs.umich.edu        MISCREG_DBGVCR,
997272Sgblack@eecs.umich.edu        MISCREG_DBGDTRRXext,
1007272Sgblack@eecs.umich.edu        MISCREG_DBGDSCRext,
1017271Sgblack@eecs.umich.edu        MISCREG_DBGDTRTXext,
1027273Sgblack@eecs.umich.edu        MISCREG_DBGOSECCR,
1037287Sgblack@eecs.umich.edu        MISCREG_DBGBVR0,
1047287Sgblack@eecs.umich.edu        MISCREG_DBGBVR1,
1057274Sgblack@eecs.umich.edu        MISCREG_DBGBVR2,
1067275Sgblack@eecs.umich.edu        MISCREG_DBGBVR3,
1077276Sgblack@eecs.umich.edu        MISCREG_DBGBVR4,
1087286Sgblack@eecs.umich.edu        MISCREG_DBGBVR5,
1097297Sgblack@eecs.umich.edu        MISCREG_DBGBCR0,
1107297Sgblack@eecs.umich.edu        MISCREG_DBGBCR1,
1117298Sgblack@eecs.umich.edu        MISCREG_DBGBCR2,
1127352Sgblack@eecs.umich.edu        MISCREG_DBGBCR3,
1137352Sgblack@eecs.umich.edu        MISCREG_DBGBCR4,
1147354Sgblack@eecs.umich.edu        MISCREG_DBGBCR5,
1157353Sgblack@eecs.umich.edu        MISCREG_DBGWVR0,
1167355Sgblack@eecs.umich.edu        MISCREG_DBGWVR1,
1177355Sgblack@eecs.umich.edu        MISCREG_DBGWVR2,
1187355Sgblack@eecs.umich.edu        MISCREG_DBGWVR3,
1197355Sgblack@eecs.umich.edu        MISCREG_DBGWCR0,
1207355Sgblack@eecs.umich.edu        MISCREG_DBGWCR1,
1217355Sgblack@eecs.umich.edu        MISCREG_DBGWCR2,
1227355Sgblack@eecs.umich.edu        MISCREG_DBGWCR3,
1237355Sgblack@eecs.umich.edu        MISCREG_DBGDRAR,
1247355Sgblack@eecs.umich.edu        MISCREG_DBGBXVR4,
1257355Sgblack@eecs.umich.edu        MISCREG_DBGBXVR5,
1267355Sgblack@eecs.umich.edu        MISCREG_DBGOSLAR,
1277355Sgblack@eecs.umich.edu        MISCREG_DBGOSLSR,
1287355Sgblack@eecs.umich.edu        MISCREG_DBGOSDLR,
1297355Sgblack@eecs.umich.edu        MISCREG_DBGPRCR,
1307362Sgblack@eecs.umich.edu        MISCREG_DBGDSAR,
1317362Sgblack@eecs.umich.edu        MISCREG_DBGCLAIMSET,
1327362Sgblack@eecs.umich.edu        MISCREG_DBGCLAIMCLR,
1337362Sgblack@eecs.umich.edu        MISCREG_DBGAUTHSTATUS,
1347390Sgblack@eecs.umich.edu        MISCREG_DBGDEVID2,
1357404SAli.Saidi@ARM.com        MISCREG_DBGDEVID1,
1367404SAli.Saidi@ARM.com        MISCREG_DBGDEVID0,
1377404SAli.Saidi@ARM.com        MISCREG_TEECR,  // not in ARM DDI 0487A.b+
1387404SAli.Saidi@ARM.com        MISCREG_JIDR,
1397406SAli.Saidi@ARM.com        MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
1407406SAli.Saidi@ARM.com        MISCREG_JOSCR,
1417406SAli.Saidi@ARM.com        MISCREG_JMCR,
1427436Sdam.sunwoo@arm.com
1437436Sdam.sunwoo@arm.com        // AArch32 CP15 registers (system control)
1447436Sdam.sunwoo@arm.com        MISCREG_MIDR,
1457436Sdam.sunwoo@arm.com        MISCREG_CTR,
1467436Sdam.sunwoo@arm.com        MISCREG_TCMTR,
1477436Sdam.sunwoo@arm.com        MISCREG_TLBTR,
1487436Sdam.sunwoo@arm.com        MISCREG_MPIDR,
1497436Sdam.sunwoo@arm.com        MISCREG_REVIDR,
1507436Sdam.sunwoo@arm.com        MISCREG_ID_PFR0,
1517583SAli.Saidi@arm.com        MISCREG_ID_PFR1,
1528284SAli.Saidi@ARM.com        MISCREG_ID_DFR0,
1537583SAli.Saidi@arm.com        MISCREG_ID_AFR0,
1547583SAli.Saidi@arm.com        MISCREG_ID_MMFR0,
1557583SAli.Saidi@arm.com        MISCREG_ID_MMFR1,
1567583SAli.Saidi@arm.com        MISCREG_ID_MMFR2,
1577583SAli.Saidi@arm.com        MISCREG_ID_MMFR3,
1587583SAli.Saidi@arm.com        MISCREG_ID_ISAR0,
1597583SAli.Saidi@arm.com        MISCREG_ID_ISAR1,
1607583SAli.Saidi@arm.com        MISCREG_ID_ISAR2,
1617583SAli.Saidi@arm.com        MISCREG_ID_ISAR3,
1627583SAli.Saidi@arm.com        MISCREG_ID_ISAR4,
1637583SAli.Saidi@arm.com        MISCREG_ID_ISAR5,
1647583SAli.Saidi@arm.com        MISCREG_CCSIDR,
1657583SAli.Saidi@arm.com        MISCREG_CLIDR,
1667583SAli.Saidi@arm.com        MISCREG_AIDR,
1677583SAli.Saidi@arm.com        MISCREG_CSSELR,
1688147SAli.Saidi@ARM.com        MISCREG_CSSELR_NS,
1698147SAli.Saidi@ARM.com        MISCREG_CSSELR_S,
1708147SAli.Saidi@ARM.com        MISCREG_VPIDR,
1718147SAli.Saidi@ARM.com        MISCREG_VMPIDR,
1728147SAli.Saidi@ARM.com        MISCREG_SCTLR,
1738147SAli.Saidi@ARM.com        MISCREG_SCTLR_NS,
1748208SAli.Saidi@ARM.com        MISCREG_SCTLR_S,
1758209SAli.Saidi@ARM.com        MISCREG_ACTLR,
1768209SAli.Saidi@ARM.com        MISCREG_ACTLR_NS,
1778299Schander.sudanthi@arm.com        MISCREG_ACTLR_S,
1787259Sgblack@eecs.umich.edu        MISCREG_CPACR,
1797406SAli.Saidi@ARM.com        MISCREG_SCR,
1807259Sgblack@eecs.umich.edu        MISCREG_SDER,
1817259Sgblack@eecs.umich.edu        MISCREG_NSACR,
1827259Sgblack@eecs.umich.edu        MISCREG_HSCTLR,
1837259Sgblack@eecs.umich.edu        MISCREG_HACTLR,
1847259Sgblack@eecs.umich.edu        MISCREG_HCR,
1857259Sgblack@eecs.umich.edu        MISCREG_HDCR,
1867259Sgblack@eecs.umich.edu        MISCREG_HCPTR,
1877259Sgblack@eecs.umich.edu        MISCREG_HSTR,
1887259Sgblack@eecs.umich.edu        MISCREG_HACR,
1897259Sgblack@eecs.umich.edu        MISCREG_TTBR0,
1907259Sgblack@eecs.umich.edu        MISCREG_TTBR0_NS,
1917351Sgblack@eecs.umich.edu        MISCREG_TTBR0_S,
1927351Sgblack@eecs.umich.edu        MISCREG_TTBR1,
1937351Sgblack@eecs.umich.edu        MISCREG_TTBR1_NS,
1947351Sgblack@eecs.umich.edu        MISCREG_TTBR1_S,
1957351Sgblack@eecs.umich.edu        MISCREG_TTBCR,
1968058SAli.Saidi@ARM.com        MISCREG_TTBCR_NS,
1977351Sgblack@eecs.umich.edu        MISCREG_TTBCR_S,
1987259Sgblack@eecs.umich.edu        MISCREG_HTCR,
1997259Sgblack@eecs.umich.edu        MISCREG_VTCR,
2007259Sgblack@eecs.umich.edu        MISCREG_DACR,
2017259Sgblack@eecs.umich.edu        MISCREG_DACR_NS,
2027259Sgblack@eecs.umich.edu        MISCREG_DACR_S,
2037259Sgblack@eecs.umich.edu        MISCREG_DFSR,
2047259Sgblack@eecs.umich.edu        MISCREG_DFSR_NS,
2056735Sgblack@eecs.umich.edu        MISCREG_DFSR_S,
2066261Sgblack@eecs.umich.edu        MISCREG_IFSR,
2076261Sgblack@eecs.umich.edu        MISCREG_IFSR_NS,
2087259Sgblack@eecs.umich.edu        MISCREG_IFSR_S,
2097259Sgblack@eecs.umich.edu        MISCREG_ADFSR,
2107259Sgblack@eecs.umich.edu        MISCREG_ADFSR_NS,
2116261Sgblack@eecs.umich.edu        MISCREG_ADFSR_S,
2128205SAli.Saidi@ARM.com        MISCREG_AIFSR,
2137259Sgblack@eecs.umich.edu        MISCREG_AIFSR_NS,
2147783SGiacomo.Gabrielli@arm.com        MISCREG_AIFSR_S,
2157783SGiacomo.Gabrielli@arm.com        MISCREG_HADFSR,
2167400SAli.Saidi@ARM.com        MISCREG_HAIFSR,
2177285Sgblack@eecs.umich.edu        MISCREG_HSR,
2187267Sgblack@eecs.umich.edu        MISCREG_DFAR,
2197287Sgblack@eecs.umich.edu        MISCREG_DFAR_NS,
2207287Sgblack@eecs.umich.edu        MISCREG_DFAR_S,
2217297Sgblack@eecs.umich.edu        MISCREG_IFAR,
2227297Sgblack@eecs.umich.edu        MISCREG_IFAR_NS,
2237355Sgblack@eecs.umich.edu        MISCREG_IFAR_S,
2247355Sgblack@eecs.umich.edu        MISCREG_HDFAR,
2257355Sgblack@eecs.umich.edu        MISCREG_HIFAR,
2267355Sgblack@eecs.umich.edu        MISCREG_HPFAR,
2277355Sgblack@eecs.umich.edu        MISCREG_ICIALLUIS,
2287390Sgblack@eecs.umich.edu        MISCREG_BPIALLIS,
2297436Sdam.sunwoo@arm.com        MISCREG_PAR,
2307436Sdam.sunwoo@arm.com        MISCREG_PAR_NS,
2317436Sdam.sunwoo@arm.com        MISCREG_PAR_S,
2327436Sdam.sunwoo@arm.com        MISCREG_ICIALLU,
2338284SAli.Saidi@ARM.com        MISCREG_ICIMVAU,
2347583SAli.Saidi@arm.com        MISCREG_CP15ISB,
2357583SAli.Saidi@arm.com        MISCREG_BPIALL,
2367583SAli.Saidi@arm.com        MISCREG_BPIMVA,
2377583SAli.Saidi@arm.com        MISCREG_DCIMVAC,
2388147SAli.Saidi@ARM.com        MISCREG_DCISW,
2398299Schander.sudanthi@arm.com        MISCREG_ATS1CPR,
2407583SAli.Saidi@arm.com        MISCREG_ATS1CPW,
2417406SAli.Saidi@ARM.com        MISCREG_ATS1CUR,
2428299Schander.sudanthi@arm.com        MISCREG_ATS1CUW,
2438284SAli.Saidi@ARM.com        MISCREG_ATS12NSOPR,
2448147SAli.Saidi@ARM.com        MISCREG_ATS12NSOPW,
2457297Sgblack@eecs.umich.edu        MISCREG_ATS12NSOUR,
2467272Sgblack@eecs.umich.edu        MISCREG_ATS12NSOUW,
2477406SAli.Saidi@ARM.com        MISCREG_DCCMVAC,
2488179Sgblack@eecs.umich.edu        MISCREG_DCCSW,
2497259Sgblack@eecs.umich.edu        MISCREG_CP15DSB,
2506242Sgblack@eecs.umich.edu        MISCREG_CP15DMB,
2516242Sgblack@eecs.umich.edu        MISCREG_DCCMVAU,
2526242Sgblack@eecs.umich.edu        MISCREG_DCCIMVAC,
2536242Sgblack@eecs.umich.edu        MISCREG_DCCISW,
2546242Sgblack@eecs.umich.edu        MISCREG_ATS1HR,
2556242Sgblack@eecs.umich.edu        MISCREG_ATS1HW,
2566242Sgblack@eecs.umich.edu        MISCREG_TLBIALLIS,
2576242Sgblack@eecs.umich.edu        MISCREG_TLBIMVAIS,
2586735Sgblack@eecs.umich.edu        MISCREG_TLBIASIDIS,
2596242Sgblack@eecs.umich.edu        MISCREG_TLBIMVAAIS,
2606242Sgblack@eecs.umich.edu        MISCREG_TLBIMVALIS,
2616735Sgblack@eecs.umich.edu        MISCREG_TLBIMVAALIS,
2626242Sgblack@eecs.umich.edu        MISCREG_ITLBIALL,
2636242Sgblack@eecs.umich.edu        MISCREG_ITLBIMVA,
2646242Sgblack@eecs.umich.edu        MISCREG_ITLBIASID,
2656242Sgblack@eecs.umich.edu        MISCREG_DTLBIALL,
2666242Sgblack@eecs.umich.edu        MISCREG_DTLBIMVA,
2676242Sgblack@eecs.umich.edu        MISCREG_DTLBIASID,
2686242Sgblack@eecs.umich.edu        MISCREG_TLBIALL,
2696735Sgblack@eecs.umich.edu        MISCREG_TLBIMVA,
2706750Sgblack@eecs.umich.edu        MISCREG_TLBIASID,
2716750Sgblack@eecs.umich.edu        MISCREG_TLBIMVAA,
2726750Sgblack@eecs.umich.edu        MISCREG_TLBIMVAL,
2736750Sgblack@eecs.umich.edu        MISCREG_TLBIMVAAL,
2746735Sgblack@eecs.umich.edu        MISCREG_TLBIIPAS2IS,
2757360Sgblack@eecs.umich.edu        MISCREG_TLBIIPAS2LIS,
2766735Sgblack@eecs.umich.edu        MISCREG_TLBIALLHIS,
2776735Sgblack@eecs.umich.edu        MISCREG_TLBIMVAHIS,
2786735Sgblack@eecs.umich.edu        MISCREG_TLBIALLNSNHIS,
2796735Sgblack@eecs.umich.edu        MISCREG_TLBIMVALHIS,
2806735Sgblack@eecs.umich.edu        MISCREG_TLBIIPAS2,
2816735Sgblack@eecs.umich.edu        MISCREG_TLBIIPAS2L,
2827406SAli.Saidi@ARM.com        MISCREG_TLBIALLH,
2836735Sgblack@eecs.umich.edu        MISCREG_TLBIMVAH,
2846735Sgblack@eecs.umich.edu        MISCREG_TLBIALLNSNH,
2857360Sgblack@eecs.umich.edu        MISCREG_TLBIMVALH,
2866735Sgblack@eecs.umich.edu        MISCREG_PMCR,
2877360Sgblack@eecs.umich.edu        MISCREG_PMCNTENSET,
2886735Sgblack@eecs.umich.edu        MISCREG_PMCNTENCLR,
2896735Sgblack@eecs.umich.edu        MISCREG_PMOVSR,
2906735Sgblack@eecs.umich.edu        MISCREG_PMSWINC,
2916735Sgblack@eecs.umich.edu        MISCREG_PMSELR,
2926735Sgblack@eecs.umich.edu        MISCREG_PMCEID0,
2936735Sgblack@eecs.umich.edu        MISCREG_PMCEID1,
2947406SAli.Saidi@ARM.com        MISCREG_PMCCNTR,
2956735Sgblack@eecs.umich.edu        MISCREG_PMXEVTYPER,
2966735Sgblack@eecs.umich.edu        MISCREG_PMCCFILTR,
2976735Sgblack@eecs.umich.edu        MISCREG_PMXEVCNTR,
2986735Sgblack@eecs.umich.edu        MISCREG_PMUSERENR,
2996735Sgblack@eecs.umich.edu        MISCREG_PMINTENSET,
3006735Sgblack@eecs.umich.edu        MISCREG_PMINTENCLR,
3017320Sgblack@eecs.umich.edu        MISCREG_PMOVSSET,
3027320Sgblack@eecs.umich.edu        MISCREG_L2CTLR,
3037320Sgblack@eecs.umich.edu        MISCREG_L2ECTLR,
3047320Sgblack@eecs.umich.edu        MISCREG_PRRR,
3057320Sgblack@eecs.umich.edu        MISCREG_PRRR_NS,
3067320Sgblack@eecs.umich.edu        MISCREG_PRRR_S,
3077320Sgblack@eecs.umich.edu        MISCREG_MAIR0,
3087320Sgblack@eecs.umich.edu        MISCREG_MAIR0_NS,
3097320Sgblack@eecs.umich.edu        MISCREG_MAIR0_S,
3107320Sgblack@eecs.umich.edu        MISCREG_NMRR,
3117320Sgblack@eecs.umich.edu        MISCREG_NMRR_NS,
3127320Sgblack@eecs.umich.edu        MISCREG_NMRR_S,
3137320Sgblack@eecs.umich.edu        MISCREG_MAIR1,
3147320Sgblack@eecs.umich.edu        MISCREG_MAIR1_NS,
3157320Sgblack@eecs.umich.edu        MISCREG_MAIR1_S,
3167320Sgblack@eecs.umich.edu        MISCREG_AMAIR0,
3178206SWilliam.Wang@arm.com        MISCREG_AMAIR0_NS,
3187320Sgblack@eecs.umich.edu        MISCREG_AMAIR0_S,
3197320Sgblack@eecs.umich.edu        MISCREG_AMAIR1,
3207320Sgblack@eecs.umich.edu        MISCREG_AMAIR1_NS,
3217362Sgblack@eecs.umich.edu        MISCREG_AMAIR1_S,
3227362Sgblack@eecs.umich.edu        MISCREG_HMAIR0,
3237362Sgblack@eecs.umich.edu        MISCREG_HMAIR1,
3247362Sgblack@eecs.umich.edu        MISCREG_HAMAIR0,
3257362Sgblack@eecs.umich.edu        MISCREG_HAMAIR1,
3267362Sgblack@eecs.umich.edu        MISCREG_VBAR,
3277362Sgblack@eecs.umich.edu        MISCREG_VBAR_NS,
3287362Sgblack@eecs.umich.edu        MISCREG_VBAR_S,
3297376Sgblack@eecs.umich.edu        MISCREG_MVBAR,
3307376Sgblack@eecs.umich.edu        MISCREG_RMR,
3317376Sgblack@eecs.umich.edu        MISCREG_ISR,
3327376Sgblack@eecs.umich.edu        MISCREG_HVBAR,
3337376Sgblack@eecs.umich.edu        MISCREG_FCSEIDR,
3347376Sgblack@eecs.umich.edu        MISCREG_CONTEXTIDR,
3357376Sgblack@eecs.umich.edu        MISCREG_CONTEXTIDR_NS,
3367376Sgblack@eecs.umich.edu        MISCREG_CONTEXTIDR_S,
3377376Sgblack@eecs.umich.edu        MISCREG_TPIDRURW,
3387376Sgblack@eecs.umich.edu        MISCREG_TPIDRURW_NS,
3397376Sgblack@eecs.umich.edu        MISCREG_TPIDRURW_S,
3407376Sgblack@eecs.umich.edu        MISCREG_TPIDRURO,
3417376Sgblack@eecs.umich.edu        MISCREG_TPIDRURO_NS,
3427376Sgblack@eecs.umich.edu        MISCREG_TPIDRURO_S,
3437376Sgblack@eecs.umich.edu        MISCREG_TPIDRPRW,
3447376Sgblack@eecs.umich.edu        MISCREG_TPIDRPRW_NS,
3457376Sgblack@eecs.umich.edu        MISCREG_TPIDRPRW_S,
3467376Sgblack@eecs.umich.edu        MISCREG_HTPIDR,
3477376Sgblack@eecs.umich.edu        MISCREG_CNTFRQ,
3487376Sgblack@eecs.umich.edu        MISCREG_CNTKCTL,
3497376Sgblack@eecs.umich.edu        MISCREG_CNTP_TVAL,
3507376Sgblack@eecs.umich.edu        MISCREG_CNTP_TVAL_NS,
3517376Sgblack@eecs.umich.edu        MISCREG_CNTP_TVAL_S,
3527376Sgblack@eecs.umich.edu        MISCREG_CNTP_CTL,
3537376Sgblack@eecs.umich.edu        MISCREG_CNTP_CTL_NS,
3547376Sgblack@eecs.umich.edu        MISCREG_CNTP_CTL_S,
3557383Sgblack@eecs.umich.edu        MISCREG_CNTV_TVAL,
3567643Sgblack@eecs.umich.edu        MISCREG_CNTV_CTL,
3577643Sgblack@eecs.umich.edu        MISCREG_CNTHCTL,
3587783SGiacomo.Gabrielli@arm.com        MISCREG_CNTHP_TVAL,
3597783SGiacomo.Gabrielli@arm.com        MISCREG_CNTHP_CTL,
3607783SGiacomo.Gabrielli@arm.com        MISCREG_IL1DATA0,
3617783SGiacomo.Gabrielli@arm.com        MISCREG_IL1DATA1,
3627783SGiacomo.Gabrielli@arm.com        MISCREG_IL1DATA2,
3637643Sgblack@eecs.umich.edu        MISCREG_IL1DATA3,
3647640Sgblack@eecs.umich.edu        MISCREG_DL1DATA0,
3657640Sgblack@eecs.umich.edu        MISCREG_DL1DATA1,
3667640Sgblack@eecs.umich.edu        MISCREG_DL1DATA2,
3677640Sgblack@eecs.umich.edu        MISCREG_DL1DATA3,
3687640Sgblack@eecs.umich.edu        MISCREG_DL1DATA4,
3697640Sgblack@eecs.umich.edu        MISCREG_RAMINDEX,
3707383Sgblack@eecs.umich.edu        MISCREG_L2ACTLR,
3717383Sgblack@eecs.umich.edu        MISCREG_CBAR,
3727383Sgblack@eecs.umich.edu        MISCREG_HTTBR,
3737383Sgblack@eecs.umich.edu        MISCREG_VTTBR,
3747383Sgblack@eecs.umich.edu        MISCREG_CNTPCT,
3757383Sgblack@eecs.umich.edu        MISCREG_CNTVCT,
3767383Sgblack@eecs.umich.edu        MISCREG_CNTP_CVAL,
3777383Sgblack@eecs.umich.edu        MISCREG_CNTP_CVAL_NS,
3787383Sgblack@eecs.umich.edu        MISCREG_CNTP_CVAL_S,
3797383Sgblack@eecs.umich.edu        MISCREG_CNTV_CVAL,
3807383Sgblack@eecs.umich.edu        MISCREG_CNTVOFF,
3817383Sgblack@eecs.umich.edu        MISCREG_CNTHP_CVAL,
3827383Sgblack@eecs.umich.edu        MISCREG_CPUMERRSR,
3837383Sgblack@eecs.umich.edu        MISCREG_L2MERRSR,
3847383Sgblack@eecs.umich.edu
3857383Sgblack@eecs.umich.edu        // AArch64 registers (Op0=2)
3867383Sgblack@eecs.umich.edu        MISCREG_MDCCINT_EL1,
3877383Sgblack@eecs.umich.edu        MISCREG_OSDTRRX_EL1,
3887383Sgblack@eecs.umich.edu        MISCREG_MDSCR_EL1,
3897383Sgblack@eecs.umich.edu        MISCREG_OSDTRTX_EL1,
3907383Sgblack@eecs.umich.edu        MISCREG_OSECCR_EL1,
3917404SAli.Saidi@ARM.com        MISCREG_DBGBVR0_EL1,
3927404SAli.Saidi@ARM.com        MISCREG_DBGBVR1_EL1,
3937404SAli.Saidi@ARM.com        MISCREG_DBGBVR2_EL1,
3947404SAli.Saidi@ARM.com        MISCREG_DBGBVR3_EL1,
3957404SAli.Saidi@ARM.com        MISCREG_DBGBVR4_EL1,
3967404SAli.Saidi@ARM.com        MISCREG_DBGBVR5_EL1,
3977404SAli.Saidi@ARM.com        MISCREG_DBGBCR0_EL1,
3987404SAli.Saidi@ARM.com        MISCREG_DBGBCR1_EL1,
3997404SAli.Saidi@ARM.com        MISCREG_DBGBCR2_EL1,
4007404SAli.Saidi@ARM.com        MISCREG_DBGBCR3_EL1,
4017404SAli.Saidi@ARM.com        MISCREG_DBGBCR4_EL1,
4027404SAli.Saidi@ARM.com        MISCREG_DBGBCR5_EL1,
4037404SAli.Saidi@ARM.com        MISCREG_DBGWVR0_EL1,
4047404SAli.Saidi@ARM.com        MISCREG_DBGWVR1_EL1,
4057404SAli.Saidi@ARM.com        MISCREG_DBGWVR2_EL1,
4067404SAli.Saidi@ARM.com        MISCREG_DBGWVR3_EL1,
4077404SAli.Saidi@ARM.com        MISCREG_DBGWCR0_EL1,
4087404SAli.Saidi@ARM.com        MISCREG_DBGWCR1_EL1,
4097404SAli.Saidi@ARM.com        MISCREG_DBGWCR2_EL1,
4107404SAli.Saidi@ARM.com        MISCREG_DBGWCR3_EL1,
4117404SAli.Saidi@ARM.com        MISCREG_MDCCSR_EL0,
4127404SAli.Saidi@ARM.com        MISCREG_MDDTR_EL0,
4137404SAli.Saidi@ARM.com        MISCREG_MDDTRTX_EL0,
4147404SAli.Saidi@ARM.com        MISCREG_MDDTRRX_EL0,
4157404SAli.Saidi@ARM.com        MISCREG_DBGVCR32_EL2,
4167404SAli.Saidi@ARM.com        MISCREG_MDRAR_EL1,
4177404SAli.Saidi@ARM.com        MISCREG_OSLAR_EL1,
4187404SAli.Saidi@ARM.com        MISCREG_OSLSR_EL1,
4197404SAli.Saidi@ARM.com        MISCREG_OSDLR_EL1,
4207404SAli.Saidi@ARM.com        MISCREG_DBGPRCR_EL1,
4217404SAli.Saidi@ARM.com        MISCREG_DBGCLAIMSET_EL1,
4227404SAli.Saidi@ARM.com        MISCREG_DBGCLAIMCLR_EL1,
4237404SAli.Saidi@ARM.com        MISCREG_DBGAUTHSTATUS_EL1,
4247404SAli.Saidi@ARM.com        MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
4257404SAli.Saidi@ARM.com        MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
4267404SAli.Saidi@ARM.com
4277404SAli.Saidi@ARM.com        // AArch64 registers (Op0=1,3)
4287404SAli.Saidi@ARM.com        MISCREG_MIDR_EL1,
4297404SAli.Saidi@ARM.com        MISCREG_MPIDR_EL1,
4307404SAli.Saidi@ARM.com        MISCREG_REVIDR_EL1,
4317404SAli.Saidi@ARM.com        MISCREG_ID_PFR0_EL1,
4327404SAli.Saidi@ARM.com        MISCREG_ID_PFR1_EL1,
4337404SAli.Saidi@ARM.com        MISCREG_ID_DFR0_EL1,
4346242Sgblack@eecs.umich.edu        MISCREG_ID_AFR0_EL1,
4356242Sgblack@eecs.umich.edu        MISCREG_ID_MMFR0_EL1,
4366242Sgblack@eecs.umich.edu        MISCREG_ID_MMFR1_EL1,
437        MISCREG_ID_MMFR2_EL1,
438        MISCREG_ID_MMFR3_EL1,
439        MISCREG_ID_ISAR0_EL1,
440        MISCREG_ID_ISAR1_EL1,
441        MISCREG_ID_ISAR2_EL1,
442        MISCREG_ID_ISAR3_EL1,
443        MISCREG_ID_ISAR4_EL1,
444        MISCREG_ID_ISAR5_EL1,
445        MISCREG_MVFR0_EL1,
446        MISCREG_MVFR1_EL1,
447        MISCREG_MVFR2_EL1,
448        MISCREG_ID_AA64PFR0_EL1,
449        MISCREG_ID_AA64PFR1_EL1,
450        MISCREG_ID_AA64DFR0_EL1,
451        MISCREG_ID_AA64DFR1_EL1,
452        MISCREG_ID_AA64AFR0_EL1,
453        MISCREG_ID_AA64AFR1_EL1,
454        MISCREG_ID_AA64ISAR0_EL1,
455        MISCREG_ID_AA64ISAR1_EL1,
456        MISCREG_ID_AA64MMFR0_EL1,
457        MISCREG_ID_AA64MMFR1_EL1,
458        MISCREG_CCSIDR_EL1,
459        MISCREG_CLIDR_EL1,
460        MISCREG_AIDR_EL1,
461        MISCREG_CSSELR_EL1,
462        MISCREG_CTR_EL0,
463        MISCREG_DCZID_EL0,
464        MISCREG_VPIDR_EL2,
465        MISCREG_VMPIDR_EL2,
466        MISCREG_SCTLR_EL1,
467        MISCREG_ACTLR_EL1,
468        MISCREG_CPACR_EL1,
469        MISCREG_SCTLR_EL2,
470        MISCREG_ACTLR_EL2,
471        MISCREG_HCR_EL2,
472        MISCREG_MDCR_EL2,
473        MISCREG_CPTR_EL2,
474        MISCREG_HSTR_EL2,
475        MISCREG_HACR_EL2,
476        MISCREG_SCTLR_EL3,
477        MISCREG_ACTLR_EL3,
478        MISCREG_SCR_EL3,
479        MISCREG_SDER32_EL3,
480        MISCREG_CPTR_EL3,
481        MISCREG_MDCR_EL3,
482        MISCREG_TTBR0_EL1,
483        MISCREG_TTBR1_EL1,
484        MISCREG_TCR_EL1,
485        MISCREG_TTBR0_EL2,
486        MISCREG_TCR_EL2,
487        MISCREG_VTTBR_EL2,
488        MISCREG_VTCR_EL2,
489        MISCREG_TTBR0_EL3,
490        MISCREG_TCR_EL3,
491        MISCREG_DACR32_EL2,
492        MISCREG_SPSR_EL1,
493        MISCREG_ELR_EL1,
494        MISCREG_SP_EL0,
495        MISCREG_SPSEL,
496        MISCREG_CURRENTEL,
497        MISCREG_NZCV,
498        MISCREG_DAIF,
499        MISCREG_FPCR,
500        MISCREG_FPSR,
501        MISCREG_DSPSR_EL0,
502        MISCREG_DLR_EL0,
503        MISCREG_SPSR_EL2,
504        MISCREG_ELR_EL2,
505        MISCREG_SP_EL1,
506        MISCREG_SPSR_IRQ_AA64,
507        MISCREG_SPSR_ABT_AA64,
508        MISCREG_SPSR_UND_AA64,
509        MISCREG_SPSR_FIQ_AA64,
510        MISCREG_SPSR_EL3,
511        MISCREG_ELR_EL3,
512        MISCREG_SP_EL2,
513        MISCREG_AFSR0_EL1,
514        MISCREG_AFSR1_EL1,
515        MISCREG_ESR_EL1,
516        MISCREG_IFSR32_EL2,
517        MISCREG_AFSR0_EL2,
518        MISCREG_AFSR1_EL2,
519        MISCREG_ESR_EL2,
520        MISCREG_FPEXC32_EL2,
521        MISCREG_AFSR0_EL3,
522        MISCREG_AFSR1_EL3,
523        MISCREG_ESR_EL3,
524        MISCREG_FAR_EL1,
525        MISCREG_FAR_EL2,
526        MISCREG_HPFAR_EL2,
527        MISCREG_FAR_EL3,
528        MISCREG_IC_IALLUIS,
529        MISCREG_PAR_EL1,
530        MISCREG_IC_IALLU,
531        MISCREG_DC_IVAC_Xt,
532        MISCREG_DC_ISW_Xt,
533        MISCREG_AT_S1E1R_Xt,
534        MISCREG_AT_S1E1W_Xt,
535        MISCREG_AT_S1E0R_Xt,
536        MISCREG_AT_S1E0W_Xt,
537        MISCREG_DC_CSW_Xt,
538        MISCREG_DC_CISW_Xt,
539        MISCREG_DC_ZVA_Xt,
540        MISCREG_IC_IVAU_Xt,
541        MISCREG_DC_CVAC_Xt,
542        MISCREG_DC_CVAU_Xt,
543        MISCREG_DC_CIVAC_Xt,
544        MISCREG_AT_S1E2R_Xt,
545        MISCREG_AT_S1E2W_Xt,
546        MISCREG_AT_S12E1R_Xt,
547        MISCREG_AT_S12E1W_Xt,
548        MISCREG_AT_S12E0R_Xt,
549        MISCREG_AT_S12E0W_Xt,
550        MISCREG_AT_S1E3R_Xt,
551        MISCREG_AT_S1E3W_Xt,
552        MISCREG_TLBI_VMALLE1IS,
553        MISCREG_TLBI_VAE1IS_Xt,
554        MISCREG_TLBI_ASIDE1IS_Xt,
555        MISCREG_TLBI_VAAE1IS_Xt,
556        MISCREG_TLBI_VALE1IS_Xt,
557        MISCREG_TLBI_VAALE1IS_Xt,
558        MISCREG_TLBI_VMALLE1,
559        MISCREG_TLBI_VAE1_Xt,
560        MISCREG_TLBI_ASIDE1_Xt,
561        MISCREG_TLBI_VAAE1_Xt,
562        MISCREG_TLBI_VALE1_Xt,
563        MISCREG_TLBI_VAALE1_Xt,
564        MISCREG_TLBI_IPAS2E1IS_Xt,
565        MISCREG_TLBI_IPAS2LE1IS_Xt,
566        MISCREG_TLBI_ALLE2IS,
567        MISCREG_TLBI_VAE2IS_Xt,
568        MISCREG_TLBI_ALLE1IS,
569        MISCREG_TLBI_VALE2IS_Xt,
570        MISCREG_TLBI_VMALLS12E1IS,
571        MISCREG_TLBI_IPAS2E1_Xt,
572        MISCREG_TLBI_IPAS2LE1_Xt,
573        MISCREG_TLBI_ALLE2,
574        MISCREG_TLBI_VAE2_Xt,
575        MISCREG_TLBI_ALLE1,
576        MISCREG_TLBI_VALE2_Xt,
577        MISCREG_TLBI_VMALLS12E1,
578        MISCREG_TLBI_ALLE3IS,
579        MISCREG_TLBI_VAE3IS_Xt,
580        MISCREG_TLBI_VALE3IS_Xt,
581        MISCREG_TLBI_ALLE3,
582        MISCREG_TLBI_VAE3_Xt,
583        MISCREG_TLBI_VALE3_Xt,
584        MISCREG_PMINTENSET_EL1,
585        MISCREG_PMINTENCLR_EL1,
586        MISCREG_PMCR_EL0,
587        MISCREG_PMCNTENSET_EL0,
588        MISCREG_PMCNTENCLR_EL0,
589        MISCREG_PMOVSCLR_EL0,
590        MISCREG_PMSWINC_EL0,
591        MISCREG_PMSELR_EL0,
592        MISCREG_PMCEID0_EL0,
593        MISCREG_PMCEID1_EL0,
594        MISCREG_PMCCNTR_EL0,
595        MISCREG_PMXEVTYPER_EL0,
596        MISCREG_PMCCFILTR_EL0,
597        MISCREG_PMXEVCNTR_EL0,
598        MISCREG_PMUSERENR_EL0,
599        MISCREG_PMOVSSET_EL0,
600        MISCREG_MAIR_EL1,
601        MISCREG_AMAIR_EL1,
602        MISCREG_MAIR_EL2,
603        MISCREG_AMAIR_EL2,
604        MISCREG_MAIR_EL3,
605        MISCREG_AMAIR_EL3,
606        MISCREG_L2CTLR_EL1,
607        MISCREG_L2ECTLR_EL1,
608        MISCREG_VBAR_EL1,
609        MISCREG_RVBAR_EL1,
610        MISCREG_ISR_EL1,
611        MISCREG_VBAR_EL2,
612        MISCREG_RVBAR_EL2,
613        MISCREG_VBAR_EL3,
614        MISCREG_RVBAR_EL3,
615        MISCREG_RMR_EL3,
616        MISCREG_CONTEXTIDR_EL1,
617        MISCREG_TPIDR_EL1,
618        MISCREG_TPIDR_EL0,
619        MISCREG_TPIDRRO_EL0,
620        MISCREG_TPIDR_EL2,
621        MISCREG_TPIDR_EL3,
622        MISCREG_CNTKCTL_EL1,
623        MISCREG_CNTFRQ_EL0,
624        MISCREG_CNTPCT_EL0,
625        MISCREG_CNTVCT_EL0,
626        MISCREG_CNTP_TVAL_EL0,
627        MISCREG_CNTP_CTL_EL0,
628        MISCREG_CNTP_CVAL_EL0,
629        MISCREG_CNTV_TVAL_EL0,
630        MISCREG_CNTV_CTL_EL0,
631        MISCREG_CNTV_CVAL_EL0,
632        MISCREG_PMEVCNTR0_EL0,
633        MISCREG_PMEVCNTR1_EL0,
634        MISCREG_PMEVCNTR2_EL0,
635        MISCREG_PMEVCNTR3_EL0,
636        MISCREG_PMEVCNTR4_EL0,
637        MISCREG_PMEVCNTR5_EL0,
638        MISCREG_PMEVTYPER0_EL0,
639        MISCREG_PMEVTYPER1_EL0,
640        MISCREG_PMEVTYPER2_EL0,
641        MISCREG_PMEVTYPER3_EL0,
642        MISCREG_PMEVTYPER4_EL0,
643        MISCREG_PMEVTYPER5_EL0,
644        MISCREG_CNTVOFF_EL2,
645        MISCREG_CNTHCTL_EL2,
646        MISCREG_CNTHP_TVAL_EL2,
647        MISCREG_CNTHP_CTL_EL2,
648        MISCREG_CNTHP_CVAL_EL2,
649        MISCREG_CNTPS_TVAL_EL1,
650        MISCREG_CNTPS_CTL_EL1,
651        MISCREG_CNTPS_CVAL_EL1,
652        MISCREG_IL1DATA0_EL1,
653        MISCREG_IL1DATA1_EL1,
654        MISCREG_IL1DATA2_EL1,
655        MISCREG_IL1DATA3_EL1,
656        MISCREG_DL1DATA0_EL1,
657        MISCREG_DL1DATA1_EL1,
658        MISCREG_DL1DATA2_EL1,
659        MISCREG_DL1DATA3_EL1,
660        MISCREG_DL1DATA4_EL1,
661        MISCREG_L2ACTLR_EL1,
662        MISCREG_CPUACTLR_EL1,
663        MISCREG_CPUECTLR_EL1,
664        MISCREG_CPUMERRSR_EL1,
665        MISCREG_L2MERRSR_EL1,
666        MISCREG_CBAR_EL1,
667        MISCREG_CONTEXTIDR_EL2,
668
669        // Introduced in ARMv8.1
670        MISCREG_TTBR1_EL2,
671        MISCREG_CNTHV_CTL_EL2,
672        MISCREG_CNTHV_CVAL_EL2,
673        MISCREG_CNTHV_TVAL_EL2,
674
675        MISCREG_ID_AA64MMFR2_EL1,
676
677        // GICv3, CPU interface
678        MISCREG_ICC_PMR_EL1,
679        MISCREG_ICC_IAR0_EL1,
680        MISCREG_ICC_EOIR0_EL1,
681        MISCREG_ICC_HPPIR0_EL1,
682        MISCREG_ICC_BPR0_EL1,
683        MISCREG_ICC_AP0R0_EL1,
684        MISCREG_ICC_AP0R1_EL1,
685        MISCREG_ICC_AP0R2_EL1,
686        MISCREG_ICC_AP0R3_EL1,
687        MISCREG_ICC_AP1R0_EL1,
688        MISCREG_ICC_AP1R0_EL1_NS,
689        MISCREG_ICC_AP1R0_EL1_S,
690        MISCREG_ICC_AP1R1_EL1,
691        MISCREG_ICC_AP1R1_EL1_NS,
692        MISCREG_ICC_AP1R1_EL1_S,
693        MISCREG_ICC_AP1R2_EL1,
694        MISCREG_ICC_AP1R2_EL1_NS,
695        MISCREG_ICC_AP1R2_EL1_S,
696        MISCREG_ICC_AP1R3_EL1,
697        MISCREG_ICC_AP1R3_EL1_NS,
698        MISCREG_ICC_AP1R3_EL1_S,
699        MISCREG_ICC_DIR_EL1,
700        MISCREG_ICC_RPR_EL1,
701        MISCREG_ICC_SGI1R_EL1,
702        MISCREG_ICC_ASGI1R_EL1,
703        MISCREG_ICC_SGI0R_EL1,
704        MISCREG_ICC_IAR1_EL1,
705        MISCREG_ICC_EOIR1_EL1,
706        MISCREG_ICC_HPPIR1_EL1,
707        MISCREG_ICC_BPR1_EL1,
708        MISCREG_ICC_BPR1_EL1_NS,
709        MISCREG_ICC_BPR1_EL1_S,
710        MISCREG_ICC_CTLR_EL1,
711        MISCREG_ICC_CTLR_EL1_NS,
712        MISCREG_ICC_CTLR_EL1_S,
713        MISCREG_ICC_SRE_EL1,
714        MISCREG_ICC_SRE_EL1_NS,
715        MISCREG_ICC_SRE_EL1_S,
716        MISCREG_ICC_IGRPEN0_EL1,
717        MISCREG_ICC_IGRPEN1_EL1,
718        MISCREG_ICC_IGRPEN1_EL1_NS,
719        MISCREG_ICC_IGRPEN1_EL1_S,
720        MISCREG_ICC_SRE_EL2,
721        MISCREG_ICC_CTLR_EL3,
722        MISCREG_ICC_SRE_EL3,
723        MISCREG_ICC_IGRPEN1_EL3,
724
725        // GICv3, CPU interface, virtualization
726        MISCREG_ICH_AP0R0_EL2,
727        MISCREG_ICH_AP0R1_EL2,
728        MISCREG_ICH_AP0R2_EL2,
729        MISCREG_ICH_AP0R3_EL2,
730        MISCREG_ICH_AP1R0_EL2,
731        MISCREG_ICH_AP1R1_EL2,
732        MISCREG_ICH_AP1R2_EL2,
733        MISCREG_ICH_AP1R3_EL2,
734        MISCREG_ICH_HCR_EL2,
735        MISCREG_ICH_VTR_EL2,
736        MISCREG_ICH_MISR_EL2,
737        MISCREG_ICH_EISR_EL2,
738        MISCREG_ICH_ELRSR_EL2,
739        MISCREG_ICH_VMCR_EL2,
740        MISCREG_ICH_LR0_EL2,
741        MISCREG_ICH_LR1_EL2,
742        MISCREG_ICH_LR2_EL2,
743        MISCREG_ICH_LR3_EL2,
744        MISCREG_ICH_LR4_EL2,
745        MISCREG_ICH_LR5_EL2,
746        MISCREG_ICH_LR6_EL2,
747        MISCREG_ICH_LR7_EL2,
748        MISCREG_ICH_LR8_EL2,
749        MISCREG_ICH_LR9_EL2,
750        MISCREG_ICH_LR10_EL2,
751        MISCREG_ICH_LR11_EL2,
752        MISCREG_ICH_LR12_EL2,
753        MISCREG_ICH_LR13_EL2,
754        MISCREG_ICH_LR14_EL2,
755        MISCREG_ICH_LR15_EL2,
756
757        MISCREG_ICV_PMR_EL1,
758        MISCREG_ICV_IAR0_EL1,
759        MISCREG_ICV_EOIR0_EL1,
760        MISCREG_ICV_HPPIR0_EL1,
761        MISCREG_ICV_BPR0_EL1,
762        MISCREG_ICV_AP0R0_EL1,
763        MISCREG_ICV_AP0R1_EL1,
764        MISCREG_ICV_AP0R2_EL1,
765        MISCREG_ICV_AP0R3_EL1,
766        MISCREG_ICV_AP1R0_EL1,
767        MISCREG_ICV_AP1R0_EL1_NS,
768        MISCREG_ICV_AP1R0_EL1_S,
769        MISCREG_ICV_AP1R1_EL1,
770        MISCREG_ICV_AP1R1_EL1_NS,
771        MISCREG_ICV_AP1R1_EL1_S,
772        MISCREG_ICV_AP1R2_EL1,
773        MISCREG_ICV_AP1R2_EL1_NS,
774        MISCREG_ICV_AP1R2_EL1_S,
775        MISCREG_ICV_AP1R3_EL1,
776        MISCREG_ICV_AP1R3_EL1_NS,
777        MISCREG_ICV_AP1R3_EL1_S,
778        MISCREG_ICV_DIR_EL1,
779        MISCREG_ICV_RPR_EL1,
780        MISCREG_ICV_SGI1R_EL1,
781        MISCREG_ICV_ASGI1R_EL1,
782        MISCREG_ICV_SGI0R_EL1,
783        MISCREG_ICV_IAR1_EL1,
784        MISCREG_ICV_EOIR1_EL1,
785        MISCREG_ICV_HPPIR1_EL1,
786        MISCREG_ICV_BPR1_EL1,
787        MISCREG_ICV_BPR1_EL1_NS,
788        MISCREG_ICV_BPR1_EL1_S,
789        MISCREG_ICV_CTLR_EL1,
790        MISCREG_ICV_CTLR_EL1_NS,
791        MISCREG_ICV_CTLR_EL1_S,
792        MISCREG_ICV_SRE_EL1,
793        MISCREG_ICV_SRE_EL1_NS,
794        MISCREG_ICV_SRE_EL1_S,
795        MISCREG_ICV_IGRPEN0_EL1,
796        MISCREG_ICV_IGRPEN1_EL1,
797        MISCREG_ICV_IGRPEN1_EL1_NS,
798        MISCREG_ICV_IGRPEN1_EL1_S,
799
800        MISCREG_ICC_AP0R0,
801        MISCREG_ICC_AP0R1,
802        MISCREG_ICC_AP0R2,
803        MISCREG_ICC_AP0R3,
804        MISCREG_ICC_AP1R0,
805        MISCREG_ICC_AP1R0_NS,
806        MISCREG_ICC_AP1R0_S,
807        MISCREG_ICC_AP1R1,
808        MISCREG_ICC_AP1R1_NS,
809        MISCREG_ICC_AP1R1_S,
810        MISCREG_ICC_AP1R2,
811        MISCREG_ICC_AP1R2_NS,
812        MISCREG_ICC_AP1R2_S,
813        MISCREG_ICC_AP1R3,
814        MISCREG_ICC_AP1R3_NS,
815        MISCREG_ICC_AP1R3_S,
816        MISCREG_ICC_ASGI1R,
817        MISCREG_ICC_BPR0,
818        MISCREG_ICC_BPR1,
819        MISCREG_ICC_BPR1_NS,
820        MISCREG_ICC_BPR1_S,
821        MISCREG_ICC_CTLR,
822        MISCREG_ICC_CTLR_NS,
823        MISCREG_ICC_CTLR_S,
824        MISCREG_ICC_DIR,
825        MISCREG_ICC_EOIR0,
826        MISCREG_ICC_EOIR1,
827        MISCREG_ICC_HPPIR0,
828        MISCREG_ICC_HPPIR1,
829        MISCREG_ICC_HSRE,
830        MISCREG_ICC_IAR0,
831        MISCREG_ICC_IAR1,
832        MISCREG_ICC_IGRPEN0,
833        MISCREG_ICC_IGRPEN1,
834        MISCREG_ICC_IGRPEN1_NS,
835        MISCREG_ICC_IGRPEN1_S,
836        MISCREG_ICC_MCTLR,
837        MISCREG_ICC_MGRPEN1,
838        MISCREG_ICC_MSRE,
839        MISCREG_ICC_PMR,
840        MISCREG_ICC_RPR,
841        MISCREG_ICC_SGI0R,
842        MISCREG_ICC_SGI1R,
843        MISCREG_ICC_SRE,
844        MISCREG_ICC_SRE_NS,
845        MISCREG_ICC_SRE_S,
846
847        MISCREG_ICH_AP0R0,
848        MISCREG_ICH_AP0R1,
849        MISCREG_ICH_AP0R2,
850        MISCREG_ICH_AP0R3,
851        MISCREG_ICH_AP1R0,
852        MISCREG_ICH_AP1R1,
853        MISCREG_ICH_AP1R2,
854        MISCREG_ICH_AP1R3,
855        MISCREG_ICH_HCR,
856        MISCREG_ICH_VTR,
857        MISCREG_ICH_MISR,
858        MISCREG_ICH_EISR,
859        MISCREG_ICH_ELRSR,
860        MISCREG_ICH_VMCR,
861        MISCREG_ICH_LR0,
862        MISCREG_ICH_LR1,
863        MISCREG_ICH_LR2,
864        MISCREG_ICH_LR3,
865        MISCREG_ICH_LR4,
866        MISCREG_ICH_LR5,
867        MISCREG_ICH_LR6,
868        MISCREG_ICH_LR7,
869        MISCREG_ICH_LR8,
870        MISCREG_ICH_LR9,
871        MISCREG_ICH_LR10,
872        MISCREG_ICH_LR11,
873        MISCREG_ICH_LR12,
874        MISCREG_ICH_LR13,
875        MISCREG_ICH_LR14,
876        MISCREG_ICH_LR15,
877        MISCREG_ICH_LRC0,
878        MISCREG_ICH_LRC1,
879        MISCREG_ICH_LRC2,
880        MISCREG_ICH_LRC3,
881        MISCREG_ICH_LRC4,
882        MISCREG_ICH_LRC5,
883        MISCREG_ICH_LRC6,
884        MISCREG_ICH_LRC7,
885        MISCREG_ICH_LRC8,
886        MISCREG_ICH_LRC9,
887        MISCREG_ICH_LRC10,
888        MISCREG_ICH_LRC11,
889        MISCREG_ICH_LRC12,
890        MISCREG_ICH_LRC13,
891        MISCREG_ICH_LRC14,
892        MISCREG_ICH_LRC15,
893
894        // SVE
895        MISCREG_ID_AA64ZFR0_EL1,
896        MISCREG_ZCR_EL3,
897        MISCREG_ZCR_EL2,
898        MISCREG_ZCR_EL12,
899        MISCREG_ZCR_EL1,
900
901        // NUM_PHYS_MISCREGS specifies the number of actual physical
902        // registers, not considering the following pseudo-registers
903        // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
904        // Checkpointing should use this physical index when
905        // saving/restoring register values.
906        NUM_PHYS_MISCREGS,
907
908        // Dummy registers
909        MISCREG_NOP,
910        MISCREG_RAZ,
911        MISCREG_CP14_UNIMPL,
912        MISCREG_CP15_UNIMPL,
913        MISCREG_UNKNOWN,
914
915        // Implementation defined register: this represent
916        // a pool of unimplemented registers whose access can throw
917        // either UNDEFINED or hypervisor trap exception.
918        MISCREG_IMPDEF_UNIMPL,
919
920        // RAS extension (unimplemented)
921        MISCREG_ERRIDR_EL1,
922        MISCREG_ERRSELR_EL1,
923        MISCREG_ERXFR_EL1,
924        MISCREG_ERXCTLR_EL1,
925        MISCREG_ERXSTATUS_EL1,
926        MISCREG_ERXADDR_EL1,
927        MISCREG_ERXMISC0_EL1,
928        MISCREG_ERXMISC1_EL1,
929        MISCREG_DISR_EL1,
930        MISCREG_VSESR_EL2,
931        MISCREG_VDISR_EL2,
932
933        // PSTATE
934        MISCREG_PAN,
935
936        // Total number of Misc Registers: Physical + Dummy
937        NUM_MISCREGS
938    };
939
940    enum MiscRegInfo {
941        MISCREG_IMPLEMENTED,
942        MISCREG_UNVERIFIABLE,   // Does the value change on every read (e.g. a
943                                // arch generic counter)
944        MISCREG_WARN_NOT_FAIL,  // If MISCREG_IMPLEMENTED is deasserted, it
945                                // tells whether the instruction should raise a
946                                // warning or fail
947        MISCREG_MUTEX,  // True if the register corresponds to a pair of
948                        // mutually exclusive registers
949        MISCREG_BANKED,  // True if the register is banked between the two
950                         // security states, and this is the parent node of the
951                         // two banked registers
952        MISCREG_BANKED_CHILD, // The entry is one of the child registers that
953                              // forms a banked set of regs (along with the
954                              // other child regs)
955
956        // Access permissions
957        // User mode
958        MISCREG_USR_NS_RD,
959        MISCREG_USR_NS_WR,
960        MISCREG_USR_S_RD,
961        MISCREG_USR_S_WR,
962        // Privileged modes other than hypervisor or monitor
963        MISCREG_PRI_NS_RD,
964        MISCREG_PRI_NS_WR,
965        MISCREG_PRI_S_RD,
966        MISCREG_PRI_S_WR,
967        // Hypervisor mode
968        MISCREG_HYP_RD,
969        MISCREG_HYP_WR,
970        // Monitor mode, SCR.NS == 0
971        MISCREG_MON_NS0_RD,
972        MISCREG_MON_NS0_WR,
973        // Monitor mode, SCR.NS == 1
974        MISCREG_MON_NS1_RD,
975        MISCREG_MON_NS1_WR,
976
977        NUM_MISCREG_INFOS
978    };
979
980    extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
981
982    // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
983    MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
984                               unsigned crm, unsigned opc2);
985    MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
986                                     unsigned crn, unsigned crm,
987                                     unsigned op2);
988    // Whether a particular AArch64 system register is -always- read only.
989    bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
990
991    // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
992    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
993                               unsigned crm, unsigned opc2);
994
995    // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
996    MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
997
998
999    const char * const miscRegName[] = {
1000        "cpsr",
1001        "spsr",
1002        "spsr_fiq",
1003        "spsr_irq",
1004        "spsr_svc",
1005        "spsr_mon",
1006        "spsr_abt",
1007        "spsr_hyp",
1008        "spsr_und",
1009        "elr_hyp",
1010        "fpsid",
1011        "fpscr",
1012        "mvfr1",
1013        "mvfr0",
1014        "fpexc",
1015
1016        // Helper registers
1017        "cpsr_mode",
1018        "cpsr_q",
1019        "fpscr_exc",
1020        "fpscr_qc",
1021        "lockaddr",
1022        "lockflag",
1023        "prrr_mair0",
1024        "prrr_mair0_ns",
1025        "prrr_mair0_s",
1026        "nmrr_mair1",
1027        "nmrr_mair1_ns",
1028        "nmrr_mair1_s",
1029        "pmxevtyper_pmccfiltr",
1030        "sctlr_rst",
1031        "sev_mailbox",
1032
1033        // AArch32 CP14 registers
1034        "dbgdidr",
1035        "dbgdscrint",
1036        "dbgdccint",
1037        "dbgdtrtxint",
1038        "dbgdtrrxint",
1039        "dbgwfar",
1040        "dbgvcr",
1041        "dbgdtrrxext",
1042        "dbgdscrext",
1043        "dbgdtrtxext",
1044        "dbgoseccr",
1045        "dbgbvr0",
1046        "dbgbvr1",
1047        "dbgbvr2",
1048        "dbgbvr3",
1049        "dbgbvr4",
1050        "dbgbvr5",
1051        "dbgbcr0",
1052        "dbgbcr1",
1053        "dbgbcr2",
1054        "dbgbcr3",
1055        "dbgbcr4",
1056        "dbgbcr5",
1057        "dbgwvr0",
1058        "dbgwvr1",
1059        "dbgwvr2",
1060        "dbgwvr3",
1061        "dbgwcr0",
1062        "dbgwcr1",
1063        "dbgwcr2",
1064        "dbgwcr3",
1065        "dbgdrar",
1066        "dbgbxvr4",
1067        "dbgbxvr5",
1068        "dbgoslar",
1069        "dbgoslsr",
1070        "dbgosdlr",
1071        "dbgprcr",
1072        "dbgdsar",
1073        "dbgclaimset",
1074        "dbgclaimclr",
1075        "dbgauthstatus",
1076        "dbgdevid2",
1077        "dbgdevid1",
1078        "dbgdevid0",
1079        "teecr",
1080        "jidr",
1081        "teehbr",
1082        "joscr",
1083        "jmcr",
1084
1085        // AArch32 CP15 registers
1086        "midr",
1087        "ctr",
1088        "tcmtr",
1089        "tlbtr",
1090        "mpidr",
1091        "revidr",
1092        "id_pfr0",
1093        "id_pfr1",
1094        "id_dfr0",
1095        "id_afr0",
1096        "id_mmfr0",
1097        "id_mmfr1",
1098        "id_mmfr2",
1099        "id_mmfr3",
1100        "id_isar0",
1101        "id_isar1",
1102        "id_isar2",
1103        "id_isar3",
1104        "id_isar4",
1105        "id_isar5",
1106        "ccsidr",
1107        "clidr",
1108        "aidr",
1109        "csselr",
1110        "csselr_ns",
1111        "csselr_s",
1112        "vpidr",
1113        "vmpidr",
1114        "sctlr",
1115        "sctlr_ns",
1116        "sctlr_s",
1117        "actlr",
1118        "actlr_ns",
1119        "actlr_s",
1120        "cpacr",
1121        "scr",
1122        "sder",
1123        "nsacr",
1124        "hsctlr",
1125        "hactlr",
1126        "hcr",
1127        "hdcr",
1128        "hcptr",
1129        "hstr",
1130        "hacr",
1131        "ttbr0",
1132        "ttbr0_ns",
1133        "ttbr0_s",
1134        "ttbr1",
1135        "ttbr1_ns",
1136        "ttbr1_s",
1137        "ttbcr",
1138        "ttbcr_ns",
1139        "ttbcr_s",
1140        "htcr",
1141        "vtcr",
1142        "dacr",
1143        "dacr_ns",
1144        "dacr_s",
1145        "dfsr",
1146        "dfsr_ns",
1147        "dfsr_s",
1148        "ifsr",
1149        "ifsr_ns",
1150        "ifsr_s",
1151        "adfsr",
1152        "adfsr_ns",
1153        "adfsr_s",
1154        "aifsr",
1155        "aifsr_ns",
1156        "aifsr_s",
1157        "hadfsr",
1158        "haifsr",
1159        "hsr",
1160        "dfar",
1161        "dfar_ns",
1162        "dfar_s",
1163        "ifar",
1164        "ifar_ns",
1165        "ifar_s",
1166        "hdfar",
1167        "hifar",
1168        "hpfar",
1169        "icialluis",
1170        "bpiallis",
1171        "par",
1172        "par_ns",
1173        "par_s",
1174        "iciallu",
1175        "icimvau",
1176        "cp15isb",
1177        "bpiall",
1178        "bpimva",
1179        "dcimvac",
1180        "dcisw",
1181        "ats1cpr",
1182        "ats1cpw",
1183        "ats1cur",
1184        "ats1cuw",
1185        "ats12nsopr",
1186        "ats12nsopw",
1187        "ats12nsour",
1188        "ats12nsouw",
1189        "dccmvac",
1190        "dccsw",
1191        "cp15dsb",
1192        "cp15dmb",
1193        "dccmvau",
1194        "dccimvac",
1195        "dccisw",
1196        "ats1hr",
1197        "ats1hw",
1198        "tlbiallis",
1199        "tlbimvais",
1200        "tlbiasidis",
1201        "tlbimvaais",
1202        "tlbimvalis",
1203        "tlbimvaalis",
1204        "itlbiall",
1205        "itlbimva",
1206        "itlbiasid",
1207        "dtlbiall",
1208        "dtlbimva",
1209        "dtlbiasid",
1210        "tlbiall",
1211        "tlbimva",
1212        "tlbiasid",
1213        "tlbimvaa",
1214        "tlbimval",
1215        "tlbimvaal",
1216        "tlbiipas2is",
1217        "tlbiipas2lis",
1218        "tlbiallhis",
1219        "tlbimvahis",
1220        "tlbiallnsnhis",
1221        "tlbimvalhis",
1222        "tlbiipas2",
1223        "tlbiipas2l",
1224        "tlbiallh",
1225        "tlbimvah",
1226        "tlbiallnsnh",
1227        "tlbimvalh",
1228        "pmcr",
1229        "pmcntenset",
1230        "pmcntenclr",
1231        "pmovsr",
1232        "pmswinc",
1233        "pmselr",
1234        "pmceid0",
1235        "pmceid1",
1236        "pmccntr",
1237        "pmxevtyper",
1238        "pmccfiltr",
1239        "pmxevcntr",
1240        "pmuserenr",
1241        "pmintenset",
1242        "pmintenclr",
1243        "pmovsset",
1244        "l2ctlr",
1245        "l2ectlr",
1246        "prrr",
1247        "prrr_ns",
1248        "prrr_s",
1249        "mair0",
1250        "mair0_ns",
1251        "mair0_s",
1252        "nmrr",
1253        "nmrr_ns",
1254        "nmrr_s",
1255        "mair1",
1256        "mair1_ns",
1257        "mair1_s",
1258        "amair0",
1259        "amair0_ns",
1260        "amair0_s",
1261        "amair1",
1262        "amair1_ns",
1263        "amair1_s",
1264        "hmair0",
1265        "hmair1",
1266        "hamair0",
1267        "hamair1",
1268        "vbar",
1269        "vbar_ns",
1270        "vbar_s",
1271        "mvbar",
1272        "rmr",
1273        "isr",
1274        "hvbar",
1275        "fcseidr",
1276        "contextidr",
1277        "contextidr_ns",
1278        "contextidr_s",
1279        "tpidrurw",
1280        "tpidrurw_ns",
1281        "tpidrurw_s",
1282        "tpidruro",
1283        "tpidruro_ns",
1284        "tpidruro_s",
1285        "tpidrprw",
1286        "tpidrprw_ns",
1287        "tpidrprw_s",
1288        "htpidr",
1289        "cntfrq",
1290        "cntkctl",
1291        "cntp_tval",
1292        "cntp_tval_ns",
1293        "cntp_tval_s",
1294        "cntp_ctl",
1295        "cntp_ctl_ns",
1296        "cntp_ctl_s",
1297        "cntv_tval",
1298        "cntv_ctl",
1299        "cnthctl",
1300        "cnthp_tval",
1301        "cnthp_ctl",
1302        "il1data0",
1303        "il1data1",
1304        "il1data2",
1305        "il1data3",
1306        "dl1data0",
1307        "dl1data1",
1308        "dl1data2",
1309        "dl1data3",
1310        "dl1data4",
1311        "ramindex",
1312        "l2actlr",
1313        "cbar",
1314        "httbr",
1315        "vttbr",
1316        "cntpct",
1317        "cntvct",
1318        "cntp_cval",
1319        "cntp_cval_ns",
1320        "cntp_cval_s",
1321        "cntv_cval",
1322        "cntvoff",
1323        "cnthp_cval",
1324        "cpumerrsr",
1325        "l2merrsr",
1326
1327        // AArch64 registers (Op0=2)
1328        "mdccint_el1",
1329        "osdtrrx_el1",
1330        "mdscr_el1",
1331        "osdtrtx_el1",
1332        "oseccr_el1",
1333        "dbgbvr0_el1",
1334        "dbgbvr1_el1",
1335        "dbgbvr2_el1",
1336        "dbgbvr3_el1",
1337        "dbgbvr4_el1",
1338        "dbgbvr5_el1",
1339        "dbgbcr0_el1",
1340        "dbgbcr1_el1",
1341        "dbgbcr2_el1",
1342        "dbgbcr3_el1",
1343        "dbgbcr4_el1",
1344        "dbgbcr5_el1",
1345        "dbgwvr0_el1",
1346        "dbgwvr1_el1",
1347        "dbgwvr2_el1",
1348        "dbgwvr3_el1",
1349        "dbgwcr0_el1",
1350        "dbgwcr1_el1",
1351        "dbgwcr2_el1",
1352        "dbgwcr3_el1",
1353        "mdccsr_el0",
1354        "mddtr_el0",
1355        "mddtrtx_el0",
1356        "mddtrrx_el0",
1357        "dbgvcr32_el2",
1358        "mdrar_el1",
1359        "oslar_el1",
1360        "oslsr_el1",
1361        "osdlr_el1",
1362        "dbgprcr_el1",
1363        "dbgclaimset_el1",
1364        "dbgclaimclr_el1",
1365        "dbgauthstatus_el1",
1366        "teecr32_el1",
1367        "teehbr32_el1",
1368
1369        // AArch64 registers (Op0=1,3)
1370        "midr_el1",
1371        "mpidr_el1",
1372        "revidr_el1",
1373        "id_pfr0_el1",
1374        "id_pfr1_el1",
1375        "id_dfr0_el1",
1376        "id_afr0_el1",
1377        "id_mmfr0_el1",
1378        "id_mmfr1_el1",
1379        "id_mmfr2_el1",
1380        "id_mmfr3_el1",
1381        "id_isar0_el1",
1382        "id_isar1_el1",
1383        "id_isar2_el1",
1384        "id_isar3_el1",
1385        "id_isar4_el1",
1386        "id_isar5_el1",
1387        "mvfr0_el1",
1388        "mvfr1_el1",
1389        "mvfr2_el1",
1390        "id_aa64pfr0_el1",
1391        "id_aa64pfr1_el1",
1392        "id_aa64dfr0_el1",
1393        "id_aa64dfr1_el1",
1394        "id_aa64afr0_el1",
1395        "id_aa64afr1_el1",
1396        "id_aa64isar0_el1",
1397        "id_aa64isar1_el1",
1398        "id_aa64mmfr0_el1",
1399        "id_aa64mmfr1_el1",
1400        "ccsidr_el1",
1401        "clidr_el1",
1402        "aidr_el1",
1403        "csselr_el1",
1404        "ctr_el0",
1405        "dczid_el0",
1406        "vpidr_el2",
1407        "vmpidr_el2",
1408        "sctlr_el1",
1409        "actlr_el1",
1410        "cpacr_el1",
1411        "sctlr_el2",
1412        "actlr_el2",
1413        "hcr_el2",
1414        "mdcr_el2",
1415        "cptr_el2",
1416        "hstr_el2",
1417        "hacr_el2",
1418        "sctlr_el3",
1419        "actlr_el3",
1420        "scr_el3",
1421        "sder32_el3",
1422        "cptr_el3",
1423        "mdcr_el3",
1424        "ttbr0_el1",
1425        "ttbr1_el1",
1426        "tcr_el1",
1427        "ttbr0_el2",
1428        "tcr_el2",
1429        "vttbr_el2",
1430        "vtcr_el2",
1431        "ttbr0_el3",
1432        "tcr_el3",
1433        "dacr32_el2",
1434        "spsr_el1",
1435        "elr_el1",
1436        "sp_el0",
1437        "spsel",
1438        "currentel",
1439        "nzcv",
1440        "daif",
1441        "fpcr",
1442        "fpsr",
1443        "dspsr_el0",
1444        "dlr_el0",
1445        "spsr_el2",
1446        "elr_el2",
1447        "sp_el1",
1448        "spsr_irq_aa64",
1449        "spsr_abt_aa64",
1450        "spsr_und_aa64",
1451        "spsr_fiq_aa64",
1452        "spsr_el3",
1453        "elr_el3",
1454        "sp_el2",
1455        "afsr0_el1",
1456        "afsr1_el1",
1457        "esr_el1",
1458        "ifsr32_el2",
1459        "afsr0_el2",
1460        "afsr1_el2",
1461        "esr_el2",
1462        "fpexc32_el2",
1463        "afsr0_el3",
1464        "afsr1_el3",
1465        "esr_el3",
1466        "far_el1",
1467        "far_el2",
1468        "hpfar_el2",
1469        "far_el3",
1470        "ic_ialluis",
1471        "par_el1",
1472        "ic_iallu",
1473        "dc_ivac_xt",
1474        "dc_isw_xt",
1475        "at_s1e1r_xt",
1476        "at_s1e1w_xt",
1477        "at_s1e0r_xt",
1478        "at_s1e0w_xt",
1479        "dc_csw_xt",
1480        "dc_cisw_xt",
1481        "dc_zva_xt",
1482        "ic_ivau_xt",
1483        "dc_cvac_xt",
1484        "dc_cvau_xt",
1485        "dc_civac_xt",
1486        "at_s1e2r_xt",
1487        "at_s1e2w_xt",
1488        "at_s12e1r_xt",
1489        "at_s12e1w_xt",
1490        "at_s12e0r_xt",
1491        "at_s12e0w_xt",
1492        "at_s1e3r_xt",
1493        "at_s1e3w_xt",
1494        "tlbi_vmalle1is",
1495        "tlbi_vae1is_xt",
1496        "tlbi_aside1is_xt",
1497        "tlbi_vaae1is_xt",
1498        "tlbi_vale1is_xt",
1499        "tlbi_vaale1is_xt",
1500        "tlbi_vmalle1",
1501        "tlbi_vae1_xt",
1502        "tlbi_aside1_xt",
1503        "tlbi_vaae1_xt",
1504        "tlbi_vale1_xt",
1505        "tlbi_vaale1_xt",
1506        "tlbi_ipas2e1is_xt",
1507        "tlbi_ipas2le1is_xt",
1508        "tlbi_alle2is",
1509        "tlbi_vae2is_xt",
1510        "tlbi_alle1is",
1511        "tlbi_vale2is_xt",
1512        "tlbi_vmalls12e1is",
1513        "tlbi_ipas2e1_xt",
1514        "tlbi_ipas2le1_xt",
1515        "tlbi_alle2",
1516        "tlbi_vae2_xt",
1517        "tlbi_alle1",
1518        "tlbi_vale2_xt",
1519        "tlbi_vmalls12e1",
1520        "tlbi_alle3is",
1521        "tlbi_vae3is_xt",
1522        "tlbi_vale3is_xt",
1523        "tlbi_alle3",
1524        "tlbi_vae3_xt",
1525        "tlbi_vale3_xt",
1526        "pmintenset_el1",
1527        "pmintenclr_el1",
1528        "pmcr_el0",
1529        "pmcntenset_el0",
1530        "pmcntenclr_el0",
1531        "pmovsclr_el0",
1532        "pmswinc_el0",
1533        "pmselr_el0",
1534        "pmceid0_el0",
1535        "pmceid1_el0",
1536        "pmccntr_el0",
1537        "pmxevtyper_el0",
1538        "pmccfiltr_el0",
1539        "pmxevcntr_el0",
1540        "pmuserenr_el0",
1541        "pmovsset_el0",
1542        "mair_el1",
1543        "amair_el1",
1544        "mair_el2",
1545        "amair_el2",
1546        "mair_el3",
1547        "amair_el3",
1548        "l2ctlr_el1",
1549        "l2ectlr_el1",
1550        "vbar_el1",
1551        "rvbar_el1",
1552        "isr_el1",
1553        "vbar_el2",
1554        "rvbar_el2",
1555        "vbar_el3",
1556        "rvbar_el3",
1557        "rmr_el3",
1558        "contextidr_el1",
1559        "tpidr_el1",
1560        "tpidr_el0",
1561        "tpidrro_el0",
1562        "tpidr_el2",
1563        "tpidr_el3",
1564        "cntkctl_el1",
1565        "cntfrq_el0",
1566        "cntpct_el0",
1567        "cntvct_el0",
1568        "cntp_tval_el0",
1569        "cntp_ctl_el0",
1570        "cntp_cval_el0",
1571        "cntv_tval_el0",
1572        "cntv_ctl_el0",
1573        "cntv_cval_el0",
1574        "pmevcntr0_el0",
1575        "pmevcntr1_el0",
1576        "pmevcntr2_el0",
1577        "pmevcntr3_el0",
1578        "pmevcntr4_el0",
1579        "pmevcntr5_el0",
1580        "pmevtyper0_el0",
1581        "pmevtyper1_el0",
1582        "pmevtyper2_el0",
1583        "pmevtyper3_el0",
1584        "pmevtyper4_el0",
1585        "pmevtyper5_el0",
1586        "cntvoff_el2",
1587        "cnthctl_el2",
1588        "cnthp_tval_el2",
1589        "cnthp_ctl_el2",
1590        "cnthp_cval_el2",
1591        "cntps_tval_el1",
1592        "cntps_ctl_el1",
1593        "cntps_cval_el1",
1594        "il1data0_el1",
1595        "il1data1_el1",
1596        "il1data2_el1",
1597        "il1data3_el1",
1598        "dl1data0_el1",
1599        "dl1data1_el1",
1600        "dl1data2_el1",
1601        "dl1data3_el1",
1602        "dl1data4_el1",
1603        "l2actlr_el1",
1604        "cpuactlr_el1",
1605        "cpuectlr_el1",
1606        "cpumerrsr_el1",
1607        "l2merrsr_el1",
1608        "cbar_el1",
1609        "contextidr_el2",
1610
1611        "ttbr1_el2",
1612        "cnthv_ctl_el2",
1613        "cnthv_cval_el2",
1614        "cnthv_tval_el2",
1615        "id_aa64mmfr2_el1",
1616
1617        // GICv3, CPU interface
1618        "icc_pmr_el1",
1619        "icc_iar0_el1",
1620        "icc_eoir0_el1",
1621        "icc_hppir0_el1",
1622        "icc_bpr0_el1",
1623        "icc_ap0r0_el1",
1624        "icc_ap0r1_el1",
1625        "icc_ap0r2_el1",
1626        "icc_ap0r3_el1",
1627        "icc_ap1r0_el1",
1628        "icc_ap1r0_el1_ns",
1629        "icc_ap1r0_el1_s",
1630        "icc_ap1r1_el1",
1631        "icc_ap1r1_el1_ns",
1632        "icc_ap1r1_el1_s",
1633        "icc_ap1r2_el1",
1634        "icc_ap1r2_el1_ns",
1635        "icc_ap1r2_el1_s",
1636        "icc_ap1r3_el1",
1637        "icc_ap1r3_el1_ns",
1638        "icc_ap1r3_el1_s",
1639        "icc_dir_el1",
1640        "icc_rpr_el1",
1641        "icc_sgi1r_el1",
1642        "icc_asgi1r_el1",
1643        "icc_sgi0r_el1",
1644        "icc_iar1_el1",
1645        "icc_eoir1_el1",
1646        "icc_hppir1_el1",
1647        "icc_bpr1_el1",
1648        "icc_bpr1_el1_ns",
1649        "icc_bpr1_el1_s",
1650        "icc_ctlr_el1",
1651        "icc_ctlr_el1_ns",
1652        "icc_ctlr_el1_s",
1653        "icc_sre_el1",
1654        "icc_sre_el1_ns",
1655        "icc_sre_el1_s",
1656        "icc_igrpen0_el1",
1657        "icc_igrpen1_el1",
1658        "icc_igrpen1_el1_ns",
1659        "icc_igrpen1_el1_s",
1660        "icc_sre_el2",
1661        "icc_ctlr_el3",
1662        "icc_sre_el3",
1663        "icc_igrpen1_el3",
1664
1665        // GICv3, CPU interface, virtualization
1666        "ich_ap0r0_el2",
1667        "ich_ap0r1_el2",
1668        "ich_ap0r2_el2",
1669        "ich_ap0r3_el2",
1670        "ich_ap1r0_el2",
1671        "ich_ap1r1_el2",
1672        "ich_ap1r2_el2",
1673        "ich_ap1r3_el2",
1674        "ich_hcr_el2",
1675        "ich_vtr_el2",
1676        "ich_misr_el2",
1677        "ich_eisr_el2",
1678        "ich_elrsr_el2",
1679        "ich_vmcr_el2",
1680        "ich_lr0_el2",
1681        "ich_lr1_el2",
1682        "ich_lr2_el2",
1683        "ich_lr3_el2",
1684        "ich_lr4_el2",
1685        "ich_lr5_el2",
1686        "ich_lr6_el2",
1687        "ich_lr7_el2",
1688        "ich_lr8_el2",
1689        "ich_lr9_el2",
1690        "ich_lr10_el2",
1691        "ich_lr11_el2",
1692        "ich_lr12_el2",
1693        "ich_lr13_el2",
1694        "ich_lr14_el2",
1695        "ich_lr15_el2",
1696
1697        "icv_pmr_el1",
1698        "icv_iar0_el1",
1699        "icv_eoir0_el1",
1700        "icv_hppir0_el1",
1701        "icv_bpr0_el1",
1702        "icv_ap0r0_el1",
1703        "icv_ap0r1_el1",
1704        "icv_ap0r2_el1",
1705        "icv_ap0r3_el1",
1706        "icv_ap1r0_el1",
1707        "icv_ap1r0_el1_ns",
1708        "icv_ap1r0_el1_s",
1709        "icv_ap1r1_el1",
1710        "icv_ap1r1_el1_ns",
1711        "icv_ap1r1_el1_s",
1712        "icv_ap1r2_el1",
1713        "icv_ap1r2_el1_ns",
1714        "icv_ap1r2_el1_s",
1715        "icv_ap1r3_el1",
1716        "icv_ap1r3_el1_ns",
1717        "icv_ap1r3_el1_s",
1718        "icv_dir_el1",
1719        "icv_rpr_el1",
1720        "icv_sgi1r_el1",
1721        "icv_asgi1r_el1",
1722        "icv_sgi0r_el1",
1723        "icv_iar1_el1",
1724        "icv_eoir1_el1",
1725        "icv_hppir1_el1",
1726        "icv_bpr1_el1",
1727        "icv_bpr1_el1_ns",
1728        "icv_bpr1_el1_s",
1729        "icv_ctlr_el1",
1730        "icv_ctlr_el1_ns",
1731        "icv_ctlr_el1_s",
1732        "icv_sre_el1",
1733        "icv_sre_el1_ns",
1734        "icv_sre_el1_s",
1735        "icv_igrpen0_el1",
1736        "icv_igrpen1_el1",
1737        "icv_igrpen1_el1_ns",
1738        "icv_igrpen1_el1_s",
1739
1740        "icc_ap0r0",
1741        "icc_ap0r1",
1742        "icc_ap0r2",
1743        "icc_ap0r3",
1744        "icc_ap1r0",
1745        "icc_ap1r0_ns",
1746        "icc_ap1r0_s",
1747        "icc_ap1r1",
1748        "icc_ap1r1_ns",
1749        "icc_ap1r1_s",
1750        "icc_ap1r2",
1751        "icc_ap1r2_ns",
1752        "icc_ap1r2_s",
1753        "icc_ap1r3",
1754        "icc_ap1r3_ns",
1755        "icc_ap1r3_s",
1756        "icc_asgi1r",
1757        "icc_bpr0",
1758        "icc_bpr1",
1759        "icc_bpr1_ns",
1760        "icc_bpr1_s",
1761        "icc_ctlr",
1762        "icc_ctlr_ns",
1763        "icc_ctlr_s",
1764        "icc_dir",
1765        "icc_eoir0",
1766        "icc_eoir1",
1767        "icc_hppir0",
1768        "icc_hppir1",
1769        "icc_hsre",
1770        "icc_iar0",
1771        "icc_iar1",
1772        "icc_igrpen0",
1773        "icc_igrpen1",
1774        "icc_igrpen1_ns",
1775        "icc_igrpen1_s",
1776        "icc_mctlr",
1777        "icc_mgrpen1",
1778        "icc_msre",
1779        "icc_pmr",
1780        "icc_rpr",
1781        "icc_sgi0r",
1782        "icc_sgi1r",
1783        "icc_sre",
1784        "icc_sre_ns",
1785        "icc_sre_s",
1786
1787        "ich_ap0r0",
1788        "ich_ap0r1",
1789        "ich_ap0r2",
1790        "ich_ap0r3",
1791        "ich_ap1r0",
1792        "ich_ap1r1",
1793        "ich_ap1r2",
1794        "ich_ap1r3",
1795        "ich_hcr",
1796        "ich_vtr",
1797        "ich_misr",
1798        "ich_eisr",
1799        "ich_elrsr",
1800        "ich_vmcr",
1801        "ich_lr0",
1802        "ich_lr1",
1803        "ich_lr2",
1804        "ich_lr3",
1805        "ich_lr4",
1806        "ich_lr5",
1807        "ich_lr6",
1808        "ich_lr7",
1809        "ich_lr8",
1810        "ich_lr9",
1811        "ich_lr10",
1812        "ich_lr11",
1813        "ich_lr12",
1814        "ich_lr13",
1815        "ich_lr14",
1816        "ich_lr15",
1817        "ich_lrc0",
1818        "ich_lrc1",
1819        "ich_lrc2",
1820        "ich_lrc3",
1821        "ich_lrc4",
1822        "ich_lrc5",
1823        "ich_lrc6",
1824        "ich_lrc7",
1825        "ich_lrc8",
1826        "ich_lrc9",
1827        "ich_lrc10",
1828        "ich_lrc11",
1829        "ich_lrc12",
1830        "ich_lrc13",
1831        "ich_lrc14",
1832        "ich_lrc15",
1833
1834        "id_aa64zfr0_el1",
1835        "zcr_el3",
1836        "zcr_el2",
1837        "zcr_el12",
1838        "zcr_el1",
1839
1840        "num_phys_regs",
1841
1842        // Dummy registers
1843        "nop",
1844        "raz",
1845        "cp14_unimpl",
1846        "cp15_unimpl",
1847        "unknown",
1848        "impl_defined",
1849        "erridr_el1",
1850        "errselr_el1",
1851        "erxfr_el1",
1852        "erxctlr_el1",
1853        "erxstatus_el1",
1854        "erxaddr_el1",
1855        "erxmisc0_el1",
1856        "erxmisc1_el1",
1857        "disr_el1",
1858        "vsesr_el2",
1859        "vdisr_el2",
1860
1861        // PSTATE
1862        "pan",
1863    };
1864
1865    static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1866                  "The miscRegName array and NUM_MISCREGS are inconsistent.");
1867
1868    // This mask selects bits of the CPSR that actually go in the CondCodes
1869    // integer register to allow renaming.
1870    static const uint32_t CondCodesMask   = 0xF00F0000;
1871    static const uint32_t CpsrMaskQ       = 0x08000000;
1872
1873    // APSR (Application Program Status Register Mask). It is the user level
1874    // alias for the CPSR. The APSR is a subset of the CPSR. Although
1875    // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1876    // APSR:
1877    // Bit[9] returns the value of CPSR.E.
1878    // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1879    static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1880
1881    // CPSR (Current Program Status Register Mask).
1882    static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1883
1884    // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1885    // integer register to allow renaming.
1886    static const uint32_t FpCondCodesMask = 0xF0000000;
1887    // This mask selects the cumulative FP exception flags of the FPSCR.
1888    static const uint32_t FpscrExcMask = 0x0000009F;
1889    // This mask selects the cumulative saturation flag of the FPSCR.
1890    static const uint32_t FpscrQcMask = 0x08000000;
1891
1892    /**
1893     * Check for permission to read coprocessor registers.
1894     *
1895     * Checks whether an instruction at the current program mode has
1896     * permissions to read the coprocessor registers. This function
1897     * returns whether the check is undefined and if not whether the
1898     * read access is permitted.
1899     *
1900     * @param the misc reg indicating the coprocessor
1901     * @param the SCR
1902     * @param the CPSR
1903     * @return a tuple of booleans: can_read, undefined
1904     */
1905    std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1906                                           CPSR cpsr);
1907
1908    /**
1909     * Check for permission to write coprocessor registers.
1910     *
1911     * Checks whether an instruction at the current program mode has
1912     * permissions to write the coprocessor registers. This function
1913     * returns whether the check is undefined and if not whether the
1914     * write access is permitted.
1915     *
1916     * @param the misc reg indicating the coprocessor
1917     * @param the SCR
1918     * @param the CPSR
1919     * @return a tuple of booleans: can_write, undefined
1920     */
1921    std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1922                                             CPSR cpsr);
1923
1924    // Checks read access permissions to AArch64 system registers
1925    bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1926                              ThreadContext *tc);
1927
1928    // Checks write access permissions to AArch64 system registers
1929    bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1930                               ThreadContext *tc);
1931
1932    // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1933    // for MCR/MRC instructions
1934    int
1935    snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
1936
1937    // Flattens a misc reg index using the specified security state. This is
1938    // used for opperations (eg address translations) where the security
1939    // state of the register access may differ from the current state of the
1940    // processor
1941    int
1942    snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
1943
1944    // Takes a misc reg index and returns the root reg if its one of a set of
1945    // banked registers
1946    void
1947    preUnflattenMiscReg();
1948
1949    int
1950    unflattenMiscReg(int reg);
1951
1952}
1953
1954#endif // __ARCH_ARM_MISCREGS_HH__
1955