miscregs.hh revision 11939
12817Sksewell@umich.edu/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2017 ARM Limited 37763SAli.Saidi@ARM.com * All rights reserved 47763SAli.Saidi@ARM.com * 57763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97763SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137763SAli.Saidi@ARM.com * 142817Sksewell@umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 152817Sksewell@umich.edu * All rights reserved. 162817Sksewell@umich.edu * 172817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 182817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 192817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 222817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 232817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 242817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 252817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262817Sksewell@umich.edu * this software without specific prior written permission. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392817Sksewell@umich.edu * 402817Sksewell@umich.edu * Authors: Gabe Black 412817Sksewell@umich.edu * Giacomo Gabrielli 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu#ifndef __ARCH_ARM_MISCREGS_HH__ 448793Sgblack@eecs.umich.edu#define __ARCH_ARM_MISCREGS_HH__ 456329Sgblack@eecs.umich.edu 466658Snate@binkert.org#include <bitset> 472817Sksewell@umich.edu#include <tuple> 482834Sksewell@umich.edu 498232Snate@binkert.org#include "base/bitunion.hh" 502817Sksewell@umich.edu#include "base/compiler.hh" 512817Sksewell@umich.edu 528852Sandreas.hansson@arm.comclass ThreadContext; 538706Sandreas.hansson@arm.com 542817Sksewell@umich.edu 558706Sandreas.hansson@arm.comnamespace ArmISA 562817Sksewell@umich.edu{ 572817Sksewell@umich.edu enum MiscRegIndex { 582817Sksewell@umich.edu MISCREG_CPSR = 0, // 0 592817Sksewell@umich.edu MISCREG_SPSR, // 1 602817Sksewell@umich.edu MISCREG_SPSR_FIQ, // 2 612817Sksewell@umich.edu MISCREG_SPSR_IRQ, // 3 623126Sktlim@umich.edu MISCREG_SPSR_SVC, // 4 632817Sksewell@umich.edu MISCREG_SPSR_MON, // 5 642817Sksewell@umich.edu MISCREG_SPSR_ABT, // 6 652817Sksewell@umich.edu MISCREG_SPSR_HYP, // 7 662817Sksewell@umich.edu MISCREG_SPSR_UND, // 8 672817Sksewell@umich.edu MISCREG_ELR_HYP, // 9 682817Sksewell@umich.edu MISCREG_FPSID, // 10 692817Sksewell@umich.edu MISCREG_FPSCR, // 11 702817Sksewell@umich.edu MISCREG_MVFR1, // 12 712817Sksewell@umich.edu MISCREG_MVFR0, // 13 722817Sksewell@umich.edu MISCREG_FPEXC, // 14 732817Sksewell@umich.edu 742817Sksewell@umich.edu // Helper registers 752817Sksewell@umich.edu MISCREG_CPSR_MODE, // 15 765714Shsul@eecs.umich.edu MISCREG_CPSR_Q, // 16 775715Shsul@eecs.umich.edu MISCREG_FPSCR_EXC, // 17 782817Sksewell@umich.edu MISCREG_FPSCR_QC, // 18 798793Sgblack@eecs.umich.edu MISCREG_LOCKADDR, // 19 808793Sgblack@eecs.umich.edu MISCREG_LOCKFLAG, // 20 818793Sgblack@eecs.umich.edu MISCREG_PRRR_MAIR0, // 21 828793Sgblack@eecs.umich.edu MISCREG_PRRR_MAIR0_NS, // 22 838793Sgblack@eecs.umich.edu MISCREG_PRRR_MAIR0_S, // 23 848793Sgblack@eecs.umich.edu MISCREG_NMRR_MAIR1, // 24 858793Sgblack@eecs.umich.edu MISCREG_NMRR_MAIR1_NS, // 25 868793Sgblack@eecs.umich.edu MISCREG_NMRR_MAIR1_S, // 26 878793Sgblack@eecs.umich.edu MISCREG_PMXEVTYPER_PMCCFILTR, // 27 888793Sgblack@eecs.umich.edu MISCREG_SCTLR_RST, // 28 898793Sgblack@eecs.umich.edu MISCREG_SEV_MAILBOX, // 29 908793Sgblack@eecs.umich.edu 918793Sgblack@eecs.umich.edu // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) 928793Sgblack@eecs.umich.edu MISCREG_DBGDIDR, // 30 938793Sgblack@eecs.umich.edu MISCREG_DBGDSCRint, // 31 948793Sgblack@eecs.umich.edu MISCREG_DBGDCCINT, // 32 952817Sksewell@umich.edu MISCREG_DBGDTRTXint, // 33 962817Sksewell@umich.edu MISCREG_DBGDTRRXint, // 34 976029Ssteve.reinhardt@amd.com MISCREG_DBGWFAR, // 35 982817Sksewell@umich.edu MISCREG_DBGVCR, // 36 999382SAli.Saidi@ARM.com MISCREG_DBGDTRRXext, // 37 1002817Sksewell@umich.edu MISCREG_DBGDSCRext, // 38 1012817Sksewell@umich.edu MISCREG_DBGDTRTXext, // 39 1022817Sksewell@umich.edu MISCREG_DBGOSECCR, // 40 1032817Sksewell@umich.edu MISCREG_DBGBVR0, // 41 1042817Sksewell@umich.edu MISCREG_DBGBVR1, // 42 1059180Sandreas.hansson@arm.com MISCREG_DBGBVR2, // 43 1062817Sksewell@umich.edu MISCREG_DBGBVR3, // 44 1072875Sksewell@umich.edu MISCREG_DBGBVR4, // 45 1085715Shsul@eecs.umich.edu MISCREG_DBGBVR5, // 46 1092817Sksewell@umich.edu MISCREG_DBGBCR0, // 47 1102817Sksewell@umich.edu MISCREG_DBGBCR1, // 48 1112817Sksewell@umich.edu MISCREG_DBGBCR2, // 49 1122817Sksewell@umich.edu MISCREG_DBGBCR3, // 50 1137823Ssteve.reinhardt@amd.com MISCREG_DBGBCR4, // 51 1142817Sksewell@umich.edu MISCREG_DBGBCR5, // 52 1152817Sksewell@umich.edu MISCREG_DBGWVR0, // 53 1162817Sksewell@umich.edu MISCREG_DBGWVR1, // 54 1175715Shsul@eecs.umich.edu MISCREG_DBGWVR2, // 55 1182817Sksewell@umich.edu MISCREG_DBGWVR3, // 56 1192817Sksewell@umich.edu MISCREG_DBGWCR0, // 57 1202817Sksewell@umich.edu MISCREG_DBGWCR1, // 58 1212817Sksewell@umich.edu MISCREG_DBGWCR2, // 59 1229180Sandreas.hansson@arm.com MISCREG_DBGWCR3, // 60 1232817Sksewell@umich.edu MISCREG_DBGDRAR, // 61 1242875Sksewell@umich.edu MISCREG_DBGBXVR4, // 62 1255715Shsul@eecs.umich.edu MISCREG_DBGBXVR5, // 63 1262817Sksewell@umich.edu MISCREG_DBGOSLAR, // 64 1272817Sksewell@umich.edu MISCREG_DBGOSLSR, // 65 1282817Sksewell@umich.edu MISCREG_DBGOSDLR, // 66 1292817Sksewell@umich.edu MISCREG_DBGPRCR, // 67 1307823Ssteve.reinhardt@amd.com MISCREG_DBGDSAR, // 68 1317823Ssteve.reinhardt@amd.com MISCREG_DBGCLAIMSET, // 69 1328793Sgblack@eecs.umich.edu MISCREG_DBGCLAIMCLR, // 70 1332817Sksewell@umich.edu MISCREG_DBGAUTHSTATUS, // 71 1345715Shsul@eecs.umich.edu MISCREG_DBGDEVID2, // 72 1352817Sksewell@umich.edu MISCREG_DBGDEVID1, // 73 1362817Sksewell@umich.edu MISCREG_DBGDEVID0, // 74 1372817Sksewell@umich.edu MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+ 1382817Sksewell@umich.edu MISCREG_JIDR, // 76 1399180Sandreas.hansson@arm.com MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+ 1402817Sksewell@umich.edu MISCREG_JOSCR, // 78 1412875Sksewell@umich.edu MISCREG_JMCR, // 79 1425715Shsul@eecs.umich.edu 1432817Sksewell@umich.edu // AArch32 CP15 registers (system control) 1442817Sksewell@umich.edu MISCREG_MIDR, // 80 1452817Sksewell@umich.edu MISCREG_CTR, // 81 1462817Sksewell@umich.edu MISCREG_TCMTR, // 82 1472817Sksewell@umich.edu MISCREG_TLBTR, // 83 1485715Shsul@eecs.umich.edu MISCREG_MPIDR, // 84 1492817Sksewell@umich.edu MISCREG_REVIDR, // 85 1502817Sksewell@umich.edu MISCREG_ID_PFR0, // 86 1512817Sksewell@umich.edu MISCREG_ID_PFR1, // 87 1522817Sksewell@umich.edu MISCREG_ID_DFR0, // 88 1532817Sksewell@umich.edu MISCREG_ID_AFR0, // 89 1542817Sksewell@umich.edu MISCREG_ID_MMFR0, // 90 1558793Sgblack@eecs.umich.edu MISCREG_ID_MMFR1, // 91 1568793Sgblack@eecs.umich.edu MISCREG_ID_MMFR2, // 92 1578793Sgblack@eecs.umich.edu MISCREG_ID_MMFR3, // 93 1588793Sgblack@eecs.umich.edu MISCREG_ID_ISAR0, // 94 1592817Sksewell@umich.edu MISCREG_ID_ISAR1, // 95 1602817Sksewell@umich.edu MISCREG_ID_ISAR2, // 96 1612817Sksewell@umich.edu MISCREG_ID_ISAR3, // 97 1622817Sksewell@umich.edu MISCREG_ID_ISAR4, // 98 1632817Sksewell@umich.edu MISCREG_ID_ISAR5, // 99 1642817Sksewell@umich.edu MISCREG_CCSIDR, // 100 1658793Sgblack@eecs.umich.edu MISCREG_CLIDR, // 101 1662817Sksewell@umich.edu MISCREG_AIDR, // 102 1672817Sksewell@umich.edu MISCREG_CSSELR, // 103 1682817Sksewell@umich.edu MISCREG_CSSELR_NS, // 104 1692817Sksewell@umich.edu MISCREG_CSSELR_S, // 105 1702817Sksewell@umich.edu MISCREG_VPIDR, // 106 1712817Sksewell@umich.edu MISCREG_VMPIDR, // 107 1722817Sksewell@umich.edu MISCREG_SCTLR, // 108 1738793Sgblack@eecs.umich.edu MISCREG_SCTLR_NS, // 109 1742817Sksewell@umich.edu MISCREG_SCTLR_S, // 110 1752817Sksewell@umich.edu MISCREG_ACTLR, // 111 1762817Sksewell@umich.edu MISCREG_ACTLR_NS, // 112 1772817Sksewell@umich.edu MISCREG_ACTLR_S, // 113 1782817Sksewell@umich.edu MISCREG_CPACR, // 114 1792817Sksewell@umich.edu MISCREG_SCR, // 115 1802817Sksewell@umich.edu MISCREG_SDER, // 116 1812817Sksewell@umich.edu MISCREG_NSACR, // 117 1822817Sksewell@umich.edu MISCREG_HSCTLR, // 118 1832817Sksewell@umich.edu MISCREG_HACTLR, // 119 1842817Sksewell@umich.edu MISCREG_HCR, // 120 1852817Sksewell@umich.edu MISCREG_HDCR, // 121 1862817Sksewell@umich.edu MISCREG_HCPTR, // 122 1872817Sksewell@umich.edu MISCREG_HSTR, // 123 1882817Sksewell@umich.edu MISCREG_HACR, // 124 1892817Sksewell@umich.edu MISCREG_TTBR0, // 125 1902817Sksewell@umich.edu MISCREG_TTBR0_NS, // 126 1912817Sksewell@umich.edu MISCREG_TTBR0_S, // 127 1922817Sksewell@umich.edu MISCREG_TTBR1, // 128 1932817Sksewell@umich.edu MISCREG_TTBR1_NS, // 129 1943126Sktlim@umich.edu MISCREG_TTBR1_S, // 130 1953126Sktlim@umich.edu MISCREG_TTBCR, // 131 1963126Sktlim@umich.edu MISCREG_TTBCR_NS, // 132 1972817Sksewell@umich.edu MISCREG_TTBCR_S, // 133 1982817Sksewell@umich.edu MISCREG_HTCR, // 134 1992817Sksewell@umich.edu MISCREG_VTCR, // 135 2002817Sksewell@umich.edu MISCREG_DACR, // 136 2013126Sktlim@umich.edu MISCREG_DACR_NS, // 137 2023126Sktlim@umich.edu MISCREG_DACR_S, // 138 2033126Sktlim@umich.edu MISCREG_DFSR, // 139 2042817Sksewell@umich.edu MISCREG_DFSR_NS, // 140 2052817Sksewell@umich.edu MISCREG_DFSR_S, // 141 2062817Sksewell@umich.edu MISCREG_IFSR, // 142 2072817Sksewell@umich.edu MISCREG_IFSR_NS, // 143 2082817Sksewell@umich.edu MISCREG_IFSR_S, // 144 2098208SAli.Saidi@ARM.com MISCREG_ADFSR, // 145 2109382SAli.Saidi@ARM.com MISCREG_ADFSR_NS, // 146 2118208SAli.Saidi@ARM.com MISCREG_ADFSR_S, // 147 2129382SAli.Saidi@ARM.com MISCREG_AIFSR, // 148 2132817Sksewell@umich.edu MISCREG_AIFSR_NS, // 149 2148793Sgblack@eecs.umich.edu MISCREG_AIFSR_S, // 150 2158793Sgblack@eecs.umich.edu MISCREG_HADFSR, // 151 2162817Sksewell@umich.edu MISCREG_HAIFSR, // 152 2172817Sksewell@umich.edu MISCREG_HSR, // 153 2182817Sksewell@umich.edu MISCREG_DFAR, // 154 2192817Sksewell@umich.edu MISCREG_DFAR_NS, // 155 2202817Sksewell@umich.edu MISCREG_DFAR_S, // 156 2217763SAli.Saidi@ARM.com MISCREG_IFAR, // 157 2229384SAndreas.Sandberg@arm.com MISCREG_IFAR_NS, // 158 2237763SAli.Saidi@ARM.com MISCREG_IFAR_S, // 159 2242817Sksewell@umich.edu MISCREG_HDFAR, // 160 2252817Sksewell@umich.edu MISCREG_HIFAR, // 161 2262817Sksewell@umich.edu MISCREG_HPFAR, // 162 2272817Sksewell@umich.edu MISCREG_ICIALLUIS, // 163 2282817Sksewell@umich.edu MISCREG_BPIALLIS, // 164 2299384SAndreas.Sandberg@arm.com MISCREG_PAR, // 165 2305715Shsul@eecs.umich.edu MISCREG_PAR_NS, // 166 2312817Sksewell@umich.edu MISCREG_PAR_S, // 167 2322817Sksewell@umich.edu MISCREG_ICIALLU, // 168 2332817Sksewell@umich.edu MISCREG_ICIMVAU, // 169 2342986Sgblack@eecs.umich.edu MISCREG_CP15ISB, // 170 2352817Sksewell@umich.edu MISCREG_BPIALL, // 171 2362817Sksewell@umich.edu MISCREG_BPIMVA, // 172 2379384SAndreas.Sandberg@arm.com MISCREG_DCIMVAC, // 173 2386314Sgblack@eecs.umich.edu MISCREG_DCISW, // 174 2392817Sksewell@umich.edu MISCREG_ATS1CPR, // 175 2402817Sksewell@umich.edu MISCREG_ATS1CPW, // 176 2412817Sksewell@umich.edu MISCREG_ATS1CUR, // 177 2422986Sgblack@eecs.umich.edu MISCREG_ATS1CUW, // 178 2432817Sksewell@umich.edu MISCREG_ATS12NSOPR, // 179 2442817Sksewell@umich.edu MISCREG_ATS12NSOPW, // 180 2459384SAndreas.Sandberg@arm.com MISCREG_ATS12NSOUR, // 181 2465715Shsul@eecs.umich.edu MISCREG_ATS12NSOUW, // 182 2472817Sksewell@umich.edu MISCREG_DCCMVAC, // 183 2482817Sksewell@umich.edu MISCREG_DCCSW, // 184 2492817Sksewell@umich.edu MISCREG_CP15DSB, // 185 2502817Sksewell@umich.edu MISCREG_CP15DMB, // 186 2512817Sksewell@umich.edu MISCREG_DCCMVAU, // 187 2522817Sksewell@umich.edu MISCREG_DCCIMVAC, // 188 2539384SAndreas.Sandberg@arm.com MISCREG_DCCISW, // 189 2545715Shsul@eecs.umich.edu MISCREG_ATS1HR, // 190 2552817Sksewell@umich.edu MISCREG_ATS1HW, // 191 2569382SAli.Saidi@ARM.com MISCREG_TLBIALLIS, // 192 2572817Sksewell@umich.edu MISCREG_TLBIMVAIS, // 193 2582817Sksewell@umich.edu MISCREG_TLBIASIDIS, // 194 2592817Sksewell@umich.edu MISCREG_TLBIMVAAIS, // 195 2602817Sksewell@umich.edu MISCREG_TLBIMVALIS, // 196 2612817Sksewell@umich.edu MISCREG_TLBIMVAALIS, // 197 2622817Sksewell@umich.edu MISCREG_ITLBIALL, // 198 2639384SAndreas.Sandberg@arm.com MISCREG_ITLBIMVA, // 199 2646314Sgblack@eecs.umich.edu MISCREG_ITLBIASID, // 200 2652817Sksewell@umich.edu MISCREG_DTLBIALL, // 201 2669382SAli.Saidi@ARM.com MISCREG_DTLBIMVA, // 202 2672817Sksewell@umich.edu MISCREG_DTLBIASID, // 203 2682817Sksewell@umich.edu MISCREG_TLBIALL, // 204 2692817Sksewell@umich.edu MISCREG_TLBIMVA, // 205 2702817Sksewell@umich.edu MISCREG_TLBIASID, // 206 2712817Sksewell@umich.edu MISCREG_TLBIMVAA, // 207 2722817Sksewell@umich.edu MISCREG_TLBIMVAL, // 208 2739384SAndreas.Sandberg@arm.com MISCREG_TLBIMVAAL, // 209 2745715Shsul@eecs.umich.edu MISCREG_TLBIIPAS2IS, // 210 2752817Sksewell@umich.edu MISCREG_TLBIIPAS2LIS, // 211 2769382SAli.Saidi@ARM.com MISCREG_TLBIALLHIS, // 212 2772817Sksewell@umich.edu MISCREG_TLBIMVAHIS, // 213 2782817Sksewell@umich.edu MISCREG_TLBIALLNSNHIS, // 214 2792817Sksewell@umich.edu MISCREG_TLBIMVALHIS, // 215 2802817Sksewell@umich.edu MISCREG_TLBIIPAS2, // 216 2817720Sgblack@eecs.umich.edu MISCREG_TLBIIPAS2L, // 217 2822817Sksewell@umich.edu MISCREG_TLBIALLH, // 218 2837720Sgblack@eecs.umich.edu MISCREG_TLBIMVAH, // 219 2845258Sksewell@umich.edu MISCREG_TLBIALLNSNH, // 220 2859382SAli.Saidi@ARM.com MISCREG_TLBIMVALH, // 221 2865258Sksewell@umich.edu MISCREG_PMCR, // 222 2875258Sksewell@umich.edu MISCREG_PMCNTENSET, // 223 2888733Sgeoffrey.blake@arm.com MISCREG_PMCNTENCLR, // 224 2898733Sgeoffrey.blake@arm.com MISCREG_PMOVSR, // 225 2908733Sgeoffrey.blake@arm.com MISCREG_PMSWINC, // 226 2918733Sgeoffrey.blake@arm.com MISCREG_PMSELR, // 227 2928733Sgeoffrey.blake@arm.com MISCREG_PMCEID0, // 228 2938733Sgeoffrey.blake@arm.com MISCREG_PMCEID1, // 229 2949382SAli.Saidi@ARM.com MISCREG_PMCCNTR, // 230 2958733Sgeoffrey.blake@arm.com MISCREG_PMXEVTYPER, // 231 2968733Sgeoffrey.blake@arm.com MISCREG_PMCCFILTR, // 232 2975258Sksewell@umich.edu MISCREG_PMXEVCNTR, // 233 2986313Sgblack@eecs.umich.edu MISCREG_PMUSERENR, // 234 2996313Sgblack@eecs.umich.edu MISCREG_PMINTENSET, // 235 3006313Sgblack@eecs.umich.edu MISCREG_PMINTENCLR, // 236 3019384SAndreas.Sandberg@arm.com MISCREG_PMOVSSET, // 237 3026313Sgblack@eecs.umich.edu MISCREG_L2CTLR, // 238 3036313Sgblack@eecs.umich.edu MISCREG_L2ECTLR, // 239 3046313Sgblack@eecs.umich.edu MISCREG_PRRR, // 240 3056313Sgblack@eecs.umich.edu MISCREG_PRRR_NS, // 241 3066313Sgblack@eecs.umich.edu MISCREG_PRRR_S, // 242 3076313Sgblack@eecs.umich.edu MISCREG_MAIR0, // 243 3089384SAndreas.Sandberg@arm.com MISCREG_MAIR0_NS, // 244 3096313Sgblack@eecs.umich.edu MISCREG_MAIR0_S, // 245 3106313Sgblack@eecs.umich.edu MISCREG_NMRR, // 246 3116313Sgblack@eecs.umich.edu MISCREG_NMRR_NS, // 247 3125258Sksewell@umich.edu MISCREG_NMRR_S, // 248 3134172Ssaidi@eecs.umich.edu MISCREG_MAIR1, // 249 3142817Sksewell@umich.edu MISCREG_MAIR1_NS, // 250 3155715Shsul@eecs.umich.edu MISCREG_MAIR1_S, // 251 3162817Sksewell@umich.edu MISCREG_AMAIR0, // 252 3179382SAli.Saidi@ARM.com MISCREG_AMAIR0_NS, // 253 3182817Sksewell@umich.edu MISCREG_AMAIR0_S, // 254 3192817Sksewell@umich.edu MISCREG_AMAIR1, // 255 3202817Sksewell@umich.edu MISCREG_AMAIR1_NS, // 256 3213468Sgblack@eecs.umich.edu MISCREG_AMAIR1_S, // 257 3228518Sgeoffrey.blake@arm.com MISCREG_HMAIR0, // 258 3232817Sksewell@umich.edu MISCREG_HMAIR1, // 259 3245715Shsul@eecs.umich.edu MISCREG_HAMAIR0, // 260 3252817Sksewell@umich.edu MISCREG_HAMAIR1, // 261 3269382SAli.Saidi@ARM.com MISCREG_VBAR, // 262 3272817Sksewell@umich.edu MISCREG_VBAR_NS, // 263 3282817Sksewell@umich.edu MISCREG_VBAR_S, // 264 329 MISCREG_MVBAR, // 265 330 MISCREG_RMR, // 266 331 MISCREG_ISR, // 267 332 MISCREG_HVBAR, // 268 333 MISCREG_FCSEIDR, // 269 334 MISCREG_CONTEXTIDR, // 270 335 MISCREG_CONTEXTIDR_NS, // 271 336 MISCREG_CONTEXTIDR_S, // 272 337 MISCREG_TPIDRURW, // 273 338 MISCREG_TPIDRURW_NS, // 274 339 MISCREG_TPIDRURW_S, // 275 340 MISCREG_TPIDRURO, // 276 341 MISCREG_TPIDRURO_NS, // 277 342 MISCREG_TPIDRURO_S, // 278 343 MISCREG_TPIDRPRW, // 279 344 MISCREG_TPIDRPRW_NS, // 280 345 MISCREG_TPIDRPRW_S, // 281 346 MISCREG_HTPIDR, // 282 347 MISCREG_CNTFRQ, // 283 348 MISCREG_CNTKCTL, // 284 349 MISCREG_CNTP_TVAL, // 285 350 MISCREG_CNTP_TVAL_NS, // 286 351 MISCREG_CNTP_TVAL_S, // 287 352 MISCREG_CNTP_CTL, // 288 353 MISCREG_CNTP_CTL_NS, // 289 354 MISCREG_CNTP_CTL_S, // 290 355 MISCREG_CNTV_TVAL, // 291 356 MISCREG_CNTV_CTL, // 292 357 MISCREG_CNTHCTL, // 293 358 MISCREG_CNTHP_TVAL, // 294 359 MISCREG_CNTHP_CTL, // 295 360 MISCREG_IL1DATA0, // 296 361 MISCREG_IL1DATA1, // 297 362 MISCREG_IL1DATA2, // 298 363 MISCREG_IL1DATA3, // 299 364 MISCREG_DL1DATA0, // 300 365 MISCREG_DL1DATA1, // 301 366 MISCREG_DL1DATA2, // 302 367 MISCREG_DL1DATA3, // 303 368 MISCREG_DL1DATA4, // 304 369 MISCREG_RAMINDEX, // 305 370 MISCREG_L2ACTLR, // 306 371 MISCREG_CBAR, // 307 372 MISCREG_HTTBR, // 308 373 MISCREG_VTTBR, // 309 374 MISCREG_CNTPCT, // 310 375 MISCREG_CNTVCT, // 311 376 MISCREG_CNTP_CVAL, // 312 377 MISCREG_CNTP_CVAL_NS, // 313 378 MISCREG_CNTP_CVAL_S, // 314 379 MISCREG_CNTV_CVAL, // 315 380 MISCREG_CNTVOFF, // 316 381 MISCREG_CNTHP_CVAL, // 317 382 MISCREG_CPUMERRSR, // 318 383 MISCREG_L2MERRSR, // 319 384 385 // AArch64 registers (Op0=2) 386 MISCREG_MDCCINT_EL1, // 320 387 MISCREG_OSDTRRX_EL1, // 321 388 MISCREG_MDSCR_EL1, // 322 389 MISCREG_OSDTRTX_EL1, // 323 390 MISCREG_OSECCR_EL1, // 324 391 MISCREG_DBGBVR0_EL1, // 325 392 MISCREG_DBGBVR1_EL1, // 326 393 MISCREG_DBGBVR2_EL1, // 327 394 MISCREG_DBGBVR3_EL1, // 328 395 MISCREG_DBGBVR4_EL1, // 329 396 MISCREG_DBGBVR5_EL1, // 330 397 MISCREG_DBGBCR0_EL1, // 331 398 MISCREG_DBGBCR1_EL1, // 332 399 MISCREG_DBGBCR2_EL1, // 333 400 MISCREG_DBGBCR3_EL1, // 334 401 MISCREG_DBGBCR4_EL1, // 335 402 MISCREG_DBGBCR5_EL1, // 336 403 MISCREG_DBGWVR0_EL1, // 337 404 MISCREG_DBGWVR1_EL1, // 338 405 MISCREG_DBGWVR2_EL1, // 339 406 MISCREG_DBGWVR3_EL1, // 340 407 MISCREG_DBGWCR0_EL1, // 341 408 MISCREG_DBGWCR1_EL1, // 342 409 MISCREG_DBGWCR2_EL1, // 343 410 MISCREG_DBGWCR3_EL1, // 344 411 MISCREG_MDCCSR_EL0, // 345 412 MISCREG_MDDTR_EL0, // 346 413 MISCREG_MDDTRTX_EL0, // 347 414 MISCREG_MDDTRRX_EL0, // 348 415 MISCREG_DBGVCR32_EL2, // 349 416 MISCREG_MDRAR_EL1, // 350 417 MISCREG_OSLAR_EL1, // 351 418 MISCREG_OSLSR_EL1, // 352 419 MISCREG_OSDLR_EL1, // 353 420 MISCREG_DBGPRCR_EL1, // 354 421 MISCREG_DBGCLAIMSET_EL1, // 355 422 MISCREG_DBGCLAIMCLR_EL1, // 356 423 MISCREG_DBGAUTHSTATUS_EL1, // 357 424 MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+ 425 MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+ 426 427 // AArch64 registers (Op0=1,3) 428 MISCREG_MIDR_EL1, // 360 429 MISCREG_MPIDR_EL1, // 361 430 MISCREG_REVIDR_EL1, // 362 431 MISCREG_ID_PFR0_EL1, // 363 432 MISCREG_ID_PFR1_EL1, // 364 433 MISCREG_ID_DFR0_EL1, // 365 434 MISCREG_ID_AFR0_EL1, // 366 435 MISCREG_ID_MMFR0_EL1, // 367 436 MISCREG_ID_MMFR1_EL1, // 368 437 MISCREG_ID_MMFR2_EL1, // 369 438 MISCREG_ID_MMFR3_EL1, // 370 439 MISCREG_ID_ISAR0_EL1, // 371 440 MISCREG_ID_ISAR1_EL1, // 372 441 MISCREG_ID_ISAR2_EL1, // 373 442 MISCREG_ID_ISAR3_EL1, // 374 443 MISCREG_ID_ISAR4_EL1, // 375 444 MISCREG_ID_ISAR5_EL1, // 376 445 MISCREG_MVFR0_EL1, // 377 446 MISCREG_MVFR1_EL1, // 378 447 MISCREG_MVFR2_EL1, // 379 448 MISCREG_ID_AA64PFR0_EL1, // 380 449 MISCREG_ID_AA64PFR1_EL1, // 381 450 MISCREG_ID_AA64DFR0_EL1, // 382 451 MISCREG_ID_AA64DFR1_EL1, // 383 452 MISCREG_ID_AA64AFR0_EL1, // 384 453 MISCREG_ID_AA64AFR1_EL1, // 385 454 MISCREG_ID_AA64ISAR0_EL1, // 386 455 MISCREG_ID_AA64ISAR1_EL1, // 387 456 MISCREG_ID_AA64MMFR0_EL1, // 388 457 MISCREG_ID_AA64MMFR1_EL1, // 389 458 MISCREG_CCSIDR_EL1, // 390 459 MISCREG_CLIDR_EL1, // 391 460 MISCREG_AIDR_EL1, // 392 461 MISCREG_CSSELR_EL1, // 393 462 MISCREG_CTR_EL0, // 394 463 MISCREG_DCZID_EL0, // 395 464 MISCREG_VPIDR_EL2, // 396 465 MISCREG_VMPIDR_EL2, // 397 466 MISCREG_SCTLR_EL1, // 398 467 MISCREG_ACTLR_EL1, // 399 468 MISCREG_CPACR_EL1, // 400 469 MISCREG_SCTLR_EL2, // 401 470 MISCREG_ACTLR_EL2, // 402 471 MISCREG_HCR_EL2, // 403 472 MISCREG_MDCR_EL2, // 404 473 MISCREG_CPTR_EL2, // 405 474 MISCREG_HSTR_EL2, // 406 475 MISCREG_HACR_EL2, // 407 476 MISCREG_SCTLR_EL3, // 408 477 MISCREG_ACTLR_EL3, // 409 478 MISCREG_SCR_EL3, // 410 479 MISCREG_SDER32_EL3, // 411 480 MISCREG_CPTR_EL3, // 412 481 MISCREG_MDCR_EL3, // 413 482 MISCREG_TTBR0_EL1, // 414 483 MISCREG_TTBR1_EL1, // 415 484 MISCREG_TCR_EL1, // 416 485 MISCREG_TTBR0_EL2, // 417 486 MISCREG_TCR_EL2, // 418 487 MISCREG_VTTBR_EL2, // 419 488 MISCREG_VTCR_EL2, // 420 489 MISCREG_TTBR0_EL3, // 421 490 MISCREG_TCR_EL3, // 422 491 MISCREG_DACR32_EL2, // 423 492 MISCREG_SPSR_EL1, // 424 493 MISCREG_ELR_EL1, // 425 494 MISCREG_SP_EL0, // 426 495 MISCREG_SPSEL, // 427 496 MISCREG_CURRENTEL, // 428 497 MISCREG_NZCV, // 429 498 MISCREG_DAIF, // 430 499 MISCREG_FPCR, // 431 500 MISCREG_FPSR, // 432 501 MISCREG_DSPSR_EL0, // 433 502 MISCREG_DLR_EL0, // 434 503 MISCREG_SPSR_EL2, // 435 504 MISCREG_ELR_EL2, // 436 505 MISCREG_SP_EL1, // 437 506 MISCREG_SPSR_IRQ_AA64, // 438 507 MISCREG_SPSR_ABT_AA64, // 439 508 MISCREG_SPSR_UND_AA64, // 440 509 MISCREG_SPSR_FIQ_AA64, // 441 510 MISCREG_SPSR_EL3, // 442 511 MISCREG_ELR_EL3, // 443 512 MISCREG_SP_EL2, // 444 513 MISCREG_AFSR0_EL1, // 445 514 MISCREG_AFSR1_EL1, // 446 515 MISCREG_ESR_EL1, // 447 516 MISCREG_IFSR32_EL2, // 448 517 MISCREG_AFSR0_EL2, // 449 518 MISCREG_AFSR1_EL2, // 450 519 MISCREG_ESR_EL2, // 451 520 MISCREG_FPEXC32_EL2, // 452 521 MISCREG_AFSR0_EL3, // 453 522 MISCREG_AFSR1_EL3, // 454 523 MISCREG_ESR_EL3, // 455 524 MISCREG_FAR_EL1, // 456 525 MISCREG_FAR_EL2, // 457 526 MISCREG_HPFAR_EL2, // 458 527 MISCREG_FAR_EL3, // 459 528 MISCREG_IC_IALLUIS, // 460 529 MISCREG_PAR_EL1, // 461 530 MISCREG_IC_IALLU, // 462 531 MISCREG_DC_IVAC_Xt, // 463 532 MISCREG_DC_ISW_Xt, // 464 533 MISCREG_AT_S1E1R_Xt, // 465 534 MISCREG_AT_S1E1W_Xt, // 466 535 MISCREG_AT_S1E0R_Xt, // 467 536 MISCREG_AT_S1E0W_Xt, // 468 537 MISCREG_DC_CSW_Xt, // 469 538 MISCREG_DC_CISW_Xt, // 470 539 MISCREG_DC_ZVA_Xt, // 471 540 MISCREG_IC_IVAU_Xt, // 472 541 MISCREG_DC_CVAC_Xt, // 473 542 MISCREG_DC_CVAU_Xt, // 474 543 MISCREG_DC_CIVAC_Xt, // 475 544 MISCREG_AT_S1E2R_Xt, // 476 545 MISCREG_AT_S1E2W_Xt, // 477 546 MISCREG_AT_S12E1R_Xt, // 478 547 MISCREG_AT_S12E1W_Xt, // 479 548 MISCREG_AT_S12E0R_Xt, // 480 549 MISCREG_AT_S12E0W_Xt, // 481 550 MISCREG_AT_S1E3R_Xt, // 482 551 MISCREG_AT_S1E3W_Xt, // 483 552 MISCREG_TLBI_VMALLE1IS, // 484 553 MISCREG_TLBI_VAE1IS_Xt, // 485 554 MISCREG_TLBI_ASIDE1IS_Xt, // 486 555 MISCREG_TLBI_VAAE1IS_Xt, // 487 556 MISCREG_TLBI_VALE1IS_Xt, // 488 557 MISCREG_TLBI_VAALE1IS_Xt, // 489 558 MISCREG_TLBI_VMALLE1, // 490 559 MISCREG_TLBI_VAE1_Xt, // 491 560 MISCREG_TLBI_ASIDE1_Xt, // 492 561 MISCREG_TLBI_VAAE1_Xt, // 493 562 MISCREG_TLBI_VALE1_Xt, // 494 563 MISCREG_TLBI_VAALE1_Xt, // 495 564 MISCREG_TLBI_IPAS2E1IS_Xt, // 496 565 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497 566 MISCREG_TLBI_ALLE2IS, // 498 567 MISCREG_TLBI_VAE2IS_Xt, // 499 568 MISCREG_TLBI_ALLE1IS, // 500 569 MISCREG_TLBI_VALE2IS_Xt, // 501 570 MISCREG_TLBI_VMALLS12E1IS, // 502 571 MISCREG_TLBI_IPAS2E1_Xt, // 503 572 MISCREG_TLBI_IPAS2LE1_Xt, // 504 573 MISCREG_TLBI_ALLE2, // 505 574 MISCREG_TLBI_VAE2_Xt, // 506 575 MISCREG_TLBI_ALLE1, // 507 576 MISCREG_TLBI_VALE2_Xt, // 508 577 MISCREG_TLBI_VMALLS12E1, // 509 578 MISCREG_TLBI_ALLE3IS, // 510 579 MISCREG_TLBI_VAE3IS_Xt, // 511 580 MISCREG_TLBI_VALE3IS_Xt, // 512 581 MISCREG_TLBI_ALLE3, // 513 582 MISCREG_TLBI_VAE3_Xt, // 514 583 MISCREG_TLBI_VALE3_Xt, // 515 584 MISCREG_PMINTENSET_EL1, // 516 585 MISCREG_PMINTENCLR_EL1, // 517 586 MISCREG_PMCR_EL0, // 518 587 MISCREG_PMCNTENSET_EL0, // 519 588 MISCREG_PMCNTENCLR_EL0, // 520 589 MISCREG_PMOVSCLR_EL0, // 521 590 MISCREG_PMSWINC_EL0, // 522 591 MISCREG_PMSELR_EL0, // 523 592 MISCREG_PMCEID0_EL0, // 524 593 MISCREG_PMCEID1_EL0, // 525 594 MISCREG_PMCCNTR_EL0, // 526 595 MISCREG_PMXEVTYPER_EL0, // 527 596 MISCREG_PMCCFILTR_EL0, // 528 597 MISCREG_PMXEVCNTR_EL0, // 529 598 MISCREG_PMUSERENR_EL0, // 530 599 MISCREG_PMOVSSET_EL0, // 531 600 MISCREG_MAIR_EL1, // 532 601 MISCREG_AMAIR_EL1, // 533 602 MISCREG_MAIR_EL2, // 534 603 MISCREG_AMAIR_EL2, // 535 604 MISCREG_MAIR_EL3, // 536 605 MISCREG_AMAIR_EL3, // 537 606 MISCREG_L2CTLR_EL1, // 538 607 MISCREG_L2ECTLR_EL1, // 539 608 MISCREG_VBAR_EL1, // 540 609 MISCREG_RVBAR_EL1, // 541 610 MISCREG_ISR_EL1, // 542 611 MISCREG_VBAR_EL2, // 543 612 MISCREG_RVBAR_EL2, // 544 613 MISCREG_VBAR_EL3, // 545 614 MISCREG_RVBAR_EL3, // 546 615 MISCREG_RMR_EL3, // 547 616 MISCREG_CONTEXTIDR_EL1, // 548 617 MISCREG_TPIDR_EL1, // 549 618 MISCREG_TPIDR_EL0, // 550 619 MISCREG_TPIDRRO_EL0, // 551 620 MISCREG_TPIDR_EL2, // 552 621 MISCREG_TPIDR_EL3, // 553 622 MISCREG_CNTKCTL_EL1, // 554 623 MISCREG_CNTFRQ_EL0, // 555 624 MISCREG_CNTPCT_EL0, // 556 625 MISCREG_CNTVCT_EL0, // 557 626 MISCREG_CNTP_TVAL_EL0, // 558 627 MISCREG_CNTP_CTL_EL0, // 559 628 MISCREG_CNTP_CVAL_EL0, // 560 629 MISCREG_CNTV_TVAL_EL0, // 561 630 MISCREG_CNTV_CTL_EL0, // 562 631 MISCREG_CNTV_CVAL_EL0, // 563 632 MISCREG_PMEVCNTR0_EL0, // 564 633 MISCREG_PMEVCNTR1_EL0, // 565 634 MISCREG_PMEVCNTR2_EL0, // 566 635 MISCREG_PMEVCNTR3_EL0, // 567 636 MISCREG_PMEVCNTR4_EL0, // 568 637 MISCREG_PMEVCNTR5_EL0, // 569 638 MISCREG_PMEVTYPER0_EL0, // 570 639 MISCREG_PMEVTYPER1_EL0, // 571 640 MISCREG_PMEVTYPER2_EL0, // 572 641 MISCREG_PMEVTYPER3_EL0, // 573 642 MISCREG_PMEVTYPER4_EL0, // 574 643 MISCREG_PMEVTYPER5_EL0, // 575 644 MISCREG_CNTVOFF_EL2, // 576 645 MISCREG_CNTHCTL_EL2, // 577 646 MISCREG_CNTHP_TVAL_EL2, // 578 647 MISCREG_CNTHP_CTL_EL2, // 579 648 MISCREG_CNTHP_CVAL_EL2, // 580 649 MISCREG_CNTPS_TVAL_EL1, // 581 650 MISCREG_CNTPS_CTL_EL1, // 582 651 MISCREG_CNTPS_CVAL_EL1, // 583 652 MISCREG_IL1DATA0_EL1, // 584 653 MISCREG_IL1DATA1_EL1, // 585 654 MISCREG_IL1DATA2_EL1, // 586 655 MISCREG_IL1DATA3_EL1, // 587 656 MISCREG_DL1DATA0_EL1, // 588 657 MISCREG_DL1DATA1_EL1, // 589 658 MISCREG_DL1DATA2_EL1, // 590 659 MISCREG_DL1DATA3_EL1, // 591 660 MISCREG_DL1DATA4_EL1, // 592 661 MISCREG_L2ACTLR_EL1, // 593 662 MISCREG_CPUACTLR_EL1, // 594 663 MISCREG_CPUECTLR_EL1, // 595 664 MISCREG_CPUMERRSR_EL1, // 596 665 MISCREG_L2MERRSR_EL1, // 597 666 MISCREG_CBAR_EL1, // 598 667 MISCREG_CONTEXTIDR_EL2, // 599 668 669 // Dummy registers 670 MISCREG_NOP, // 600 671 MISCREG_RAZ, // 601 672 MISCREG_CP14_UNIMPL, // 602 673 MISCREG_CP15_UNIMPL, // 603 674 MISCREG_A64_UNIMPL, // 604 675 MISCREG_UNKNOWN, // 605 676 677 NUM_MISCREGS // 606 678 }; 679 680 enum MiscRegInfo { 681 MISCREG_IMPLEMENTED, 682 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a 683 // arch generic counter) 684 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it 685 // tells whether the instruction should raise a 686 // warning or fail 687 MISCREG_MUTEX, // True if the register corresponds to a pair of 688 // mutually exclusive registers 689 MISCREG_BANKED, // True if the register is banked between the two 690 // security states, and this is the parent node of the 691 // two banked registers 692 MISCREG_BANKED_CHILD, // The entry is one of the child registers that 693 // forms a banked set of regs (along with the 694 // other child regs) 695 696 // Access permissions 697 // User mode 698 MISCREG_USR_NS_RD, 699 MISCREG_USR_NS_WR, 700 MISCREG_USR_S_RD, 701 MISCREG_USR_S_WR, 702 // Privileged modes other than hypervisor or monitor 703 MISCREG_PRI_NS_RD, 704 MISCREG_PRI_NS_WR, 705 MISCREG_PRI_S_RD, 706 MISCREG_PRI_S_WR, 707 // Hypervisor mode 708 MISCREG_HYP_RD, 709 MISCREG_HYP_WR, 710 // Monitor mode, SCR.NS == 0 711 MISCREG_MON_NS0_RD, 712 MISCREG_MON_NS0_WR, 713 // Monitor mode, SCR.NS == 1 714 MISCREG_MON_NS1_RD, 715 MISCREG_MON_NS1_WR, 716 717 NUM_MISCREG_INFOS 718 }; 719 720 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; 721 722 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions 723 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 724 unsigned crm, unsigned opc2); 725 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, 726 unsigned crn, unsigned crm, 727 unsigned op2); 728 // Whether a particular AArch64 system register is -always- read only. 729 bool aarch64SysRegReadOnly(MiscRegIndex miscReg); 730 731 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions 732 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 733 unsigned crm, unsigned opc2); 734 735 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions 736 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1); 737 738 739 const char * const miscRegName[] = { 740 "cpsr", 741 "spsr", 742 "spsr_fiq", 743 "spsr_irq", 744 "spsr_svc", 745 "spsr_mon", 746 "spsr_abt", 747 "spsr_hyp", 748 "spsr_und", 749 "elr_hyp", 750 "fpsid", 751 "fpscr", 752 "mvfr1", 753 "mvfr0", 754 "fpexc", 755 756 // Helper registers 757 "cpsr_mode", 758 "cpsr_q", 759 "fpscr_exc", 760 "fpscr_qc", 761 "lockaddr", 762 "lockflag", 763 "prrr_mair0", 764 "prrr_mair0_ns", 765 "prrr_mair0_s", 766 "nmrr_mair1", 767 "nmrr_mair1_ns", 768 "nmrr_mair1_s", 769 "pmxevtyper_pmccfiltr", 770 "sctlr_rst", 771 "sev_mailbox", 772 773 // AArch32 CP14 registers 774 "dbgdidr", 775 "dbgdscrint", 776 "dbgdccint", 777 "dbgdtrtxint", 778 "dbgdtrrxint", 779 "dbgwfar", 780 "dbgvcr", 781 "dbgdtrrxext", 782 "dbgdscrext", 783 "dbgdtrtxext", 784 "dbgoseccr", 785 "dbgbvr0", 786 "dbgbvr1", 787 "dbgbvr2", 788 "dbgbvr3", 789 "dbgbvr4", 790 "dbgbvr5", 791 "dbgbcr0", 792 "dbgbcr1", 793 "dbgbcr2", 794 "dbgbcr3", 795 "dbgbcr4", 796 "dbgbcr5", 797 "dbgwvr0", 798 "dbgwvr1", 799 "dbgwvr2", 800 "dbgwvr3", 801 "dbgwcr0", 802 "dbgwcr1", 803 "dbgwcr2", 804 "dbgwcr3", 805 "dbgdrar", 806 "dbgbxvr4", 807 "dbgbxvr5", 808 "dbgoslar", 809 "dbgoslsr", 810 "dbgosdlr", 811 "dbgprcr", 812 "dbgdsar", 813 "dbgclaimset", 814 "dbgclaimclr", 815 "dbgauthstatus", 816 "dbgdevid2", 817 "dbgdevid1", 818 "dbgdevid0", 819 "teecr", 820 "jidr", 821 "teehbr", 822 "joscr", 823 "jmcr", 824 825 // AArch32 CP15 registers 826 "midr", 827 "ctr", 828 "tcmtr", 829 "tlbtr", 830 "mpidr", 831 "revidr", 832 "id_pfr0", 833 "id_pfr1", 834 "id_dfr0", 835 "id_afr0", 836 "id_mmfr0", 837 "id_mmfr1", 838 "id_mmfr2", 839 "id_mmfr3", 840 "id_isar0", 841 "id_isar1", 842 "id_isar2", 843 "id_isar3", 844 "id_isar4", 845 "id_isar5", 846 "ccsidr", 847 "clidr", 848 "aidr", 849 "csselr", 850 "csselr_ns", 851 "csselr_s", 852 "vpidr", 853 "vmpidr", 854 "sctlr", 855 "sctlr_ns", 856 "sctlr_s", 857 "actlr", 858 "actlr_ns", 859 "actlr_s", 860 "cpacr", 861 "scr", 862 "sder", 863 "nsacr", 864 "hsctlr", 865 "hactlr", 866 "hcr", 867 "hdcr", 868 "hcptr", 869 "hstr", 870 "hacr", 871 "ttbr0", 872 "ttbr0_ns", 873 "ttbr0_s", 874 "ttbr1", 875 "ttbr1_ns", 876 "ttbr1_s", 877 "ttbcr", 878 "ttbcr_ns", 879 "ttbcr_s", 880 "htcr", 881 "vtcr", 882 "dacr", 883 "dacr_ns", 884 "dacr_s", 885 "dfsr", 886 "dfsr_ns", 887 "dfsr_s", 888 "ifsr", 889 "ifsr_ns", 890 "ifsr_s", 891 "adfsr", 892 "adfsr_ns", 893 "adfsr_s", 894 "aifsr", 895 "aifsr_ns", 896 "aifsr_s", 897 "hadfsr", 898 "haifsr", 899 "hsr", 900 "dfar", 901 "dfar_ns", 902 "dfar_s", 903 "ifar", 904 "ifar_ns", 905 "ifar_s", 906 "hdfar", 907 "hifar", 908 "hpfar", 909 "icialluis", 910 "bpiallis", 911 "par", 912 "par_ns", 913 "par_s", 914 "iciallu", 915 "icimvau", 916 "cp15isb", 917 "bpiall", 918 "bpimva", 919 "dcimvac", 920 "dcisw", 921 "ats1cpr", 922 "ats1cpw", 923 "ats1cur", 924 "ats1cuw", 925 "ats12nsopr", 926 "ats12nsopw", 927 "ats12nsour", 928 "ats12nsouw", 929 "dccmvac", 930 "dccsw", 931 "cp15dsb", 932 "cp15dmb", 933 "dccmvau", 934 "dccimvac", 935 "dccisw", 936 "ats1hr", 937 "ats1hw", 938 "tlbiallis", 939 "tlbimvais", 940 "tlbiasidis", 941 "tlbimvaais", 942 "tlbimvalis", 943 "tlbimvaalis", 944 "itlbiall", 945 "itlbimva", 946 "itlbiasid", 947 "dtlbiall", 948 "dtlbimva", 949 "dtlbiasid", 950 "tlbiall", 951 "tlbimva", 952 "tlbiasid", 953 "tlbimvaa", 954 "tlbimval", 955 "tlbimvaal", 956 "tlbiipas2is", 957 "tlbiipas2lis", 958 "tlbiallhis", 959 "tlbimvahis", 960 "tlbiallnsnhis", 961 "tlbimvalhis", 962 "tlbiipas2", 963 "tlbiipas2l", 964 "tlbiallh", 965 "tlbimvah", 966 "tlbiallnsnh", 967 "tlbimvalh", 968 "pmcr", 969 "pmcntenset", 970 "pmcntenclr", 971 "pmovsr", 972 "pmswinc", 973 "pmselr", 974 "pmceid0", 975 "pmceid1", 976 "pmccntr", 977 "pmxevtyper", 978 "pmccfiltr", 979 "pmxevcntr", 980 "pmuserenr", 981 "pmintenset", 982 "pmintenclr", 983 "pmovsset", 984 "l2ctlr", 985 "l2ectlr", 986 "prrr", 987 "prrr_ns", 988 "prrr_s", 989 "mair0", 990 "mair0_ns", 991 "mair0_s", 992 "nmrr", 993 "nmrr_ns", 994 "nmrr_s", 995 "mair1", 996 "mair1_ns", 997 "mair1_s", 998 "amair0", 999 "amair0_ns", 1000 "amair0_s", 1001 "amair1", 1002 "amair1_ns", 1003 "amair1_s", 1004 "hmair0", 1005 "hmair1", 1006 "hamair0", 1007 "hamair1", 1008 "vbar", 1009 "vbar_ns", 1010 "vbar_s", 1011 "mvbar", 1012 "rmr", 1013 "isr", 1014 "hvbar", 1015 "fcseidr", 1016 "contextidr", 1017 "contextidr_ns", 1018 "contextidr_s", 1019 "tpidrurw", 1020 "tpidrurw_ns", 1021 "tpidrurw_s", 1022 "tpidruro", 1023 "tpidruro_ns", 1024 "tpidruro_s", 1025 "tpidrprw", 1026 "tpidrprw_ns", 1027 "tpidrprw_s", 1028 "htpidr", 1029 "cntfrq", 1030 "cntkctl", 1031 "cntp_tval", 1032 "cntp_tval_ns", 1033 "cntp_tval_s", 1034 "cntp_ctl", 1035 "cntp_ctl_ns", 1036 "cntp_ctl_s", 1037 "cntv_tval", 1038 "cntv_ctl", 1039 "cnthctl", 1040 "cnthp_tval", 1041 "cnthp_ctl", 1042 "il1data0", 1043 "il1data1", 1044 "il1data2", 1045 "il1data3", 1046 "dl1data0", 1047 "dl1data1", 1048 "dl1data2", 1049 "dl1data3", 1050 "dl1data4", 1051 "ramindex", 1052 "l2actlr", 1053 "cbar", 1054 "httbr", 1055 "vttbr", 1056 "cntpct", 1057 "cntvct", 1058 "cntp_cval", 1059 "cntp_cval_ns", 1060 "cntp_cval_s", 1061 "cntv_cval", 1062 "cntvoff", 1063 "cnthp_cval", 1064 "cpumerrsr", 1065 "l2merrsr", 1066 1067 // AArch64 registers (Op0=2) 1068 "mdccint_el1", 1069 "osdtrrx_el1", 1070 "mdscr_el1", 1071 "osdtrtx_el1", 1072 "oseccr_el1", 1073 "dbgbvr0_el1", 1074 "dbgbvr1_el1", 1075 "dbgbvr2_el1", 1076 "dbgbvr3_el1", 1077 "dbgbvr4_el1", 1078 "dbgbvr5_el1", 1079 "dbgbcr0_el1", 1080 "dbgbcr1_el1", 1081 "dbgbcr2_el1", 1082 "dbgbcr3_el1", 1083 "dbgbcr4_el1", 1084 "dbgbcr5_el1", 1085 "dbgwvr0_el1", 1086 "dbgwvr1_el1", 1087 "dbgwvr2_el1", 1088 "dbgwvr3_el1", 1089 "dbgwcr0_el1", 1090 "dbgwcr1_el1", 1091 "dbgwcr2_el1", 1092 "dbgwcr3_el1", 1093 "mdccsr_el0", 1094 "mddtr_el0", 1095 "mddtrtx_el0", 1096 "mddtrrx_el0", 1097 "dbgvcr32_el2", 1098 "mdrar_el1", 1099 "oslar_el1", 1100 "oslsr_el1", 1101 "osdlr_el1", 1102 "dbgprcr_el1", 1103 "dbgclaimset_el1", 1104 "dbgclaimclr_el1", 1105 "dbgauthstatus_el1", 1106 "teecr32_el1", 1107 "teehbr32_el1", 1108 1109 // AArch64 registers (Op0=1,3) 1110 "midr_el1", 1111 "mpidr_el1", 1112 "revidr_el1", 1113 "id_pfr0_el1", 1114 "id_pfr1_el1", 1115 "id_dfr0_el1", 1116 "id_afr0_el1", 1117 "id_mmfr0_el1", 1118 "id_mmfr1_el1", 1119 "id_mmfr2_el1", 1120 "id_mmfr3_el1", 1121 "id_isar0_el1", 1122 "id_isar1_el1", 1123 "id_isar2_el1", 1124 "id_isar3_el1", 1125 "id_isar4_el1", 1126 "id_isar5_el1", 1127 "mvfr0_el1", 1128 "mvfr1_el1", 1129 "mvfr2_el1", 1130 "id_aa64pfr0_el1", 1131 "id_aa64pfr1_el1", 1132 "id_aa64dfr0_el1", 1133 "id_aa64dfr1_el1", 1134 "id_aa64afr0_el1", 1135 "id_aa64afr1_el1", 1136 "id_aa64isar0_el1", 1137 "id_aa64isar1_el1", 1138 "id_aa64mmfr0_el1", 1139 "id_aa64mmfr1_el1", 1140 "ccsidr_el1", 1141 "clidr_el1", 1142 "aidr_el1", 1143 "csselr_el1", 1144 "ctr_el0", 1145 "dczid_el0", 1146 "vpidr_el2", 1147 "vmpidr_el2", 1148 "sctlr_el1", 1149 "actlr_el1", 1150 "cpacr_el1", 1151 "sctlr_el2", 1152 "actlr_el2", 1153 "hcr_el2", 1154 "mdcr_el2", 1155 "cptr_el2", 1156 "hstr_el2", 1157 "hacr_el2", 1158 "sctlr_el3", 1159 "actlr_el3", 1160 "scr_el3", 1161 "sder32_el3", 1162 "cptr_el3", 1163 "mdcr_el3", 1164 "ttbr0_el1", 1165 "ttbr1_el1", 1166 "tcr_el1", 1167 "ttbr0_el2", 1168 "tcr_el2", 1169 "vttbr_el2", 1170 "vtcr_el2", 1171 "ttbr0_el3", 1172 "tcr_el3", 1173 "dacr32_el2", 1174 "spsr_el1", 1175 "elr_el1", 1176 "sp_el0", 1177 "spsel", 1178 "currentel", 1179 "nzcv", 1180 "daif", 1181 "fpcr", 1182 "fpsr", 1183 "dspsr_el0", 1184 "dlr_el0", 1185 "spsr_el2", 1186 "elr_el2", 1187 "sp_el1", 1188 "spsr_irq_aa64", 1189 "spsr_abt_aa64", 1190 "spsr_und_aa64", 1191 "spsr_fiq_aa64", 1192 "spsr_el3", 1193 "elr_el3", 1194 "sp_el2", 1195 "afsr0_el1", 1196 "afsr1_el1", 1197 "esr_el1", 1198 "ifsr32_el2", 1199 "afsr0_el2", 1200 "afsr1_el2", 1201 "esr_el2", 1202 "fpexc32_el2", 1203 "afsr0_el3", 1204 "afsr1_el3", 1205 "esr_el3", 1206 "far_el1", 1207 "far_el2", 1208 "hpfar_el2", 1209 "far_el3", 1210 "ic_ialluis", 1211 "par_el1", 1212 "ic_iallu", 1213 "dc_ivac_xt", 1214 "dc_isw_xt", 1215 "at_s1e1r_xt", 1216 "at_s1e1w_xt", 1217 "at_s1e0r_xt", 1218 "at_s1e0w_xt", 1219 "dc_csw_xt", 1220 "dc_cisw_xt", 1221 "dc_zva_xt", 1222 "ic_ivau_xt", 1223 "dc_cvac_xt", 1224 "dc_cvau_xt", 1225 "dc_civac_xt", 1226 "at_s1e2r_xt", 1227 "at_s1e2w_xt", 1228 "at_s12e1r_xt", 1229 "at_s12e1w_xt", 1230 "at_s12e0r_xt", 1231 "at_s12e0w_xt", 1232 "at_s1e3r_xt", 1233 "at_s1e3w_xt", 1234 "tlbi_vmalle1is", 1235 "tlbi_vae1is_xt", 1236 "tlbi_aside1is_xt", 1237 "tlbi_vaae1is_xt", 1238 "tlbi_vale1is_xt", 1239 "tlbi_vaale1is_xt", 1240 "tlbi_vmalle1", 1241 "tlbi_vae1_xt", 1242 "tlbi_aside1_xt", 1243 "tlbi_vaae1_xt", 1244 "tlbi_vale1_xt", 1245 "tlbi_vaale1_xt", 1246 "tlbi_ipas2e1is_xt", 1247 "tlbi_ipas2le1is_xt", 1248 "tlbi_alle2is", 1249 "tlbi_vae2is_xt", 1250 "tlbi_alle1is", 1251 "tlbi_vale2is_xt", 1252 "tlbi_vmalls12e1is", 1253 "tlbi_ipas2e1_xt", 1254 "tlbi_ipas2le1_xt", 1255 "tlbi_alle2", 1256 "tlbi_vae2_xt", 1257 "tlbi_alle1", 1258 "tlbi_vale2_xt", 1259 "tlbi_vmalls12e1", 1260 "tlbi_alle3is", 1261 "tlbi_vae3is_xt", 1262 "tlbi_vale3is_xt", 1263 "tlbi_alle3", 1264 "tlbi_vae3_xt", 1265 "tlbi_vale3_xt", 1266 "pmintenset_el1", 1267 "pmintenclr_el1", 1268 "pmcr_el0", 1269 "pmcntenset_el0", 1270 "pmcntenclr_el0", 1271 "pmovsclr_el0", 1272 "pmswinc_el0", 1273 "pmselr_el0", 1274 "pmceid0_el0", 1275 "pmceid1_el0", 1276 "pmccntr_el0", 1277 "pmxevtyper_el0", 1278 "pmccfiltr_el0", 1279 "pmxevcntr_el0", 1280 "pmuserenr_el0", 1281 "pmovsset_el0", 1282 "mair_el1", 1283 "amair_el1", 1284 "mair_el2", 1285 "amair_el2", 1286 "mair_el3", 1287 "amair_el3", 1288 "l2ctlr_el1", 1289 "l2ectlr_el1", 1290 "vbar_el1", 1291 "rvbar_el1", 1292 "isr_el1", 1293 "vbar_el2", 1294 "rvbar_el2", 1295 "vbar_el3", 1296 "rvbar_el3", 1297 "rmr_el3", 1298 "contextidr_el1", 1299 "tpidr_el1", 1300 "tpidr_el0", 1301 "tpidrro_el0", 1302 "tpidr_el2", 1303 "tpidr_el3", 1304 "cntkctl_el1", 1305 "cntfrq_el0", 1306 "cntpct_el0", 1307 "cntvct_el0", 1308 "cntp_tval_el0", 1309 "cntp_ctl_el0", 1310 "cntp_cval_el0", 1311 "cntv_tval_el0", 1312 "cntv_ctl_el0", 1313 "cntv_cval_el0", 1314 "pmevcntr0_el0", 1315 "pmevcntr1_el0", 1316 "pmevcntr2_el0", 1317 "pmevcntr3_el0", 1318 "pmevcntr4_el0", 1319 "pmevcntr5_el0", 1320 "pmevtyper0_el0", 1321 "pmevtyper1_el0", 1322 "pmevtyper2_el0", 1323 "pmevtyper3_el0", 1324 "pmevtyper4_el0", 1325 "pmevtyper5_el0", 1326 "cntvoff_el2", 1327 "cnthctl_el2", 1328 "cnthp_tval_el2", 1329 "cnthp_ctl_el2", 1330 "cnthp_cval_el2", 1331 "cntps_tval_el1", 1332 "cntps_ctl_el1", 1333 "cntps_cval_el1", 1334 "il1data0_el1", 1335 "il1data1_el1", 1336 "il1data2_el1", 1337 "il1data3_el1", 1338 "dl1data0_el1", 1339 "dl1data1_el1", 1340 "dl1data2_el1", 1341 "dl1data3_el1", 1342 "dl1data4_el1", 1343 "l2actlr_el1", 1344 "cpuactlr_el1", 1345 "cpuectlr_el1", 1346 "cpumerrsr_el1", 1347 "l2merrsr_el1", 1348 "cbar_el1", 1349 "contextidr_el2", 1350 1351 // Dummy registers 1352 "nop", 1353 "raz", 1354 "cp14_unimpl", 1355 "cp15_unimpl", 1356 "a64_unimpl", 1357 "unknown" 1358 }; 1359 1360 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 1361 "The miscRegName array and NUM_MISCREGS are inconsistent."); 1362 1363 BitUnion32(CPSR) 1364 Bitfield<31, 30> nz; 1365 Bitfield<29> c; 1366 Bitfield<28> v; 1367 Bitfield<27> q; 1368 Bitfield<26, 25> it1; 1369 Bitfield<24> j; 1370 Bitfield<23, 22> res0_23_22; 1371 Bitfield<21> ss; // AArch64 1372 Bitfield<20> il; // AArch64 1373 Bitfield<19, 16> ge; 1374 Bitfield<15, 10> it2; 1375 Bitfield<9> d; // AArch64 1376 Bitfield<9> e; 1377 Bitfield<8> a; 1378 Bitfield<7> i; 1379 Bitfield<6> f; 1380 Bitfield<8, 6> aif; 1381 Bitfield<9, 6> daif; // AArch64 1382 Bitfield<5> t; 1383 Bitfield<4> width; // AArch64 1384 Bitfield<3, 2> el; // AArch64 1385 Bitfield<4, 0> mode; 1386 Bitfield<0> sp; // AArch64 1387 EndBitUnion(CPSR) 1388 1389 // This mask selects bits of the CPSR that actually go in the CondCodes 1390 // integer register to allow renaming. 1391 static const uint32_t CondCodesMask = 0xF00F0000; 1392 static const uint32_t CpsrMaskQ = 0x08000000; 1393 1394 BitUnion32(HDCR) 1395 Bitfield<11> tdra; 1396 Bitfield<10> tdosa; 1397 Bitfield<9> tda; 1398 Bitfield<8> tde; 1399 Bitfield<7> hpme; 1400 Bitfield<6> tpm; 1401 Bitfield<5> tpmcr; 1402 Bitfield<4, 0> hpmn; 1403 EndBitUnion(HDCR) 1404 1405 BitUnion32(HCPTR) 1406 Bitfield<31> tcpac; 1407 Bitfield<20> tta; 1408 Bitfield<15> tase; 1409 Bitfield<13> tcp13; 1410 Bitfield<12> tcp12; 1411 Bitfield<11> tcp11; 1412 Bitfield<10> tcp10; 1413 Bitfield<10> tfp; // AArch64 1414 Bitfield<9> tcp9; 1415 Bitfield<8> tcp8; 1416 Bitfield<7> tcp7; 1417 Bitfield<6> tcp6; 1418 Bitfield<5> tcp5; 1419 Bitfield<4> tcp4; 1420 Bitfield<3> tcp3; 1421 Bitfield<2> tcp2; 1422 Bitfield<1> tcp1; 1423 Bitfield<0> tcp0; 1424 EndBitUnion(HCPTR) 1425 1426 BitUnion32(HSTR) 1427 Bitfield<17> tjdbx; 1428 Bitfield<16> ttee; 1429 Bitfield<15> t15; 1430 Bitfield<13> t13; 1431 Bitfield<12> t12; 1432 Bitfield<11> t11; 1433 Bitfield<10> t10; 1434 Bitfield<9> t9; 1435 Bitfield<8> t8; 1436 Bitfield<7> t7; 1437 Bitfield<6> t6; 1438 Bitfield<5> t5; 1439 Bitfield<4> t4; 1440 Bitfield<3> t3; 1441 Bitfield<2> t2; 1442 Bitfield<1> t1; 1443 Bitfield<0> t0; 1444 EndBitUnion(HSTR) 1445 1446 BitUnion64(HCR) 1447 Bitfield<33> id; // AArch64 1448 Bitfield<32> cd; // AArch64 1449 Bitfield<31> rw; // AArch64 1450 Bitfield<30> trvm; // AArch64 1451 Bitfield<29> hcd; // AArch64 1452 Bitfield<28> tdz; // AArch64 1453 1454 Bitfield<27> tge; 1455 Bitfield<26> tvm; 1456 Bitfield<25> ttlb; 1457 Bitfield<24> tpu; 1458 Bitfield<23> tpc; 1459 Bitfield<22> tsw; 1460 Bitfield<21> tac; 1461 Bitfield<21> tacr; // AArch64 1462 Bitfield<20> tidcp; 1463 Bitfield<19> tsc; 1464 Bitfield<18> tid3; 1465 Bitfield<17> tid2; 1466 Bitfield<16> tid1; 1467 Bitfield<15> tid0; 1468 Bitfield<14> twe; 1469 Bitfield<13> twi; 1470 Bitfield<12> dc; 1471 Bitfield<11, 10> bsu; 1472 Bitfield<9> fb; 1473 Bitfield<8> va; 1474 Bitfield<8> vse; // AArch64 1475 Bitfield<7> vi; 1476 Bitfield<6> vf; 1477 Bitfield<5> amo; 1478 Bitfield<4> imo; 1479 Bitfield<3> fmo; 1480 Bitfield<2> ptw; 1481 Bitfield<1> swio; 1482 Bitfield<0> vm; 1483 EndBitUnion(HCR) 1484 1485 BitUnion32(NSACR) 1486 Bitfield<20> nstrcdis; 1487 Bitfield<19> rfr; 1488 Bitfield<15> nsasedis; 1489 Bitfield<14> nsd32dis; 1490 Bitfield<13> cp13; 1491 Bitfield<12> cp12; 1492 Bitfield<11> cp11; 1493 Bitfield<10> cp10; 1494 Bitfield<9> cp9; 1495 Bitfield<8> cp8; 1496 Bitfield<7> cp7; 1497 Bitfield<6> cp6; 1498 Bitfield<5> cp5; 1499 Bitfield<4> cp4; 1500 Bitfield<3> cp3; 1501 Bitfield<2> cp2; 1502 Bitfield<1> cp1; 1503 Bitfield<0> cp0; 1504 EndBitUnion(NSACR) 1505 1506 BitUnion32(SCR) 1507 Bitfield<13> twe; 1508 Bitfield<12> twi; 1509 Bitfield<11> st; // AArch64 1510 Bitfield<10> rw; // AArch64 1511 Bitfield<9> sif; 1512 Bitfield<8> hce; 1513 Bitfield<7> scd; 1514 Bitfield<7> smd; // AArch64 1515 Bitfield<6> nEt; 1516 Bitfield<5> aw; 1517 Bitfield<4> fw; 1518 Bitfield<3> ea; 1519 Bitfield<2> fiq; 1520 Bitfield<1> irq; 1521 Bitfield<0> ns; 1522 EndBitUnion(SCR) 1523 1524 BitUnion32(SCTLR) 1525 Bitfield<30> te; // Thumb Exception Enable (AArch32 only) 1526 Bitfield<29> afe; // Access flag enable (AArch32 only) 1527 Bitfield<28> tre; // TEX remap enable (AArch32 only) 1528 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only) 1529 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC, 1530 // DC CVAC and IC IVAU instructions 1531 // (AArch64 SCTLR_EL1 only) 1532 Bitfield<25> ee; // Exception Endianness 1533 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only) 1534 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0 1535 // (AArch64 SCTLR_EL1 only) 1536 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7) 1537 Bitfield<22> u; // Alignment (dropped in ARMv7) 1538 Bitfield<21> fi; // Fast interrupts configuration enable 1539 // (ARMv7 only) 1540 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN 1541 // (AArch32 only) 1542 Bitfield<19> dz; // Divide by Zero fault enable 1543 // (dropped in ARMv7) 1544 Bitfield<19> wxn; // Write permission implies XN 1545 Bitfield<18> ntwe; // Not trap WFE 1546 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1547 Bitfield<18> rao2; // Read as one 1548 Bitfield<16> ntwi; // Not trap WFI 1549 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1550 Bitfield<16> rao3; // Read as one 1551 Bitfield<15> uct; // Enable EL0 access to CTR_EL0 1552 // (AArch64 SCTLR_EL1 only) 1553 Bitfield<14> rr; // Round Robin select (ARMv7 only) 1554 Bitfield<14> dze; // Enable EL0 access to DC ZVA 1555 // (AArch64 SCTLR_EL1 only) 1556 Bitfield<13> v; // Vectors bit (AArch32 only) 1557 Bitfield<12> i; // Instruction cache enable 1558 Bitfield<11> z; // Branch prediction enable (ARMv7 only) 1559 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only) 1560 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7) 1561 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only) 1562 Bitfield<8> sed; // SETEND disable 1563 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1564 Bitfield<7> b; // Endianness support (dropped in ARMv7) 1565 Bitfield<7> itd; // IT disable 1566 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1567 Bitfield<6, 3> rao4; // Read as one 1568 Bitfield<6> thee; // ThumbEE enable 1569 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1570 Bitfield<5> cp15ben; // CP15 barrier enable 1571 // (AArch32 and AArch64 SCTLR_EL1 only) 1572 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0 1573 // (AArch64 SCTLR_EL1 only) 1574 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only) 1575 Bitfield<2> c; // Cache enable 1576 Bitfield<1> a; // Alignment check enable 1577 Bitfield<0> m; // MMU enable 1578 EndBitUnion(SCTLR) 1579 1580 BitUnion32(CPACR) 1581 Bitfield<1, 0> cp0; 1582 Bitfield<3, 2> cp1; 1583 Bitfield<5, 4> cp2; 1584 Bitfield<7, 6> cp3; 1585 Bitfield<9, 8> cp4; 1586 Bitfield<11, 10> cp5; 1587 Bitfield<13, 12> cp6; 1588 Bitfield<15, 14> cp7; 1589 Bitfield<17, 16> cp8; 1590 Bitfield<19, 18> cp9; 1591 Bitfield<21, 20> cp10; 1592 Bitfield<21, 20> fpen; // AArch64 1593 Bitfield<23, 22> cp11; 1594 Bitfield<25, 24> cp12; 1595 Bitfield<27, 26> cp13; 1596 Bitfield<29, 28> rsvd; 1597 Bitfield<28> tta; // AArch64 1598 Bitfield<30> d32dis; 1599 Bitfield<31> asedis; 1600 EndBitUnion(CPACR) 1601 1602 BitUnion32(FSR) 1603 Bitfield<3, 0> fsLow; 1604 Bitfield<5, 0> status; // LPAE 1605 Bitfield<7, 4> domain; 1606 Bitfield<9> lpae; 1607 Bitfield<10> fsHigh; 1608 Bitfield<11> wnr; 1609 Bitfield<12> ext; 1610 Bitfield<13> cm; // LPAE 1611 EndBitUnion(FSR) 1612 1613 BitUnion32(FPSCR) 1614 Bitfield<0> ioc; 1615 Bitfield<1> dzc; 1616 Bitfield<2> ofc; 1617 Bitfield<3> ufc; 1618 Bitfield<4> ixc; 1619 Bitfield<7> idc; 1620 Bitfield<8> ioe; 1621 Bitfield<9> dze; 1622 Bitfield<10> ofe; 1623 Bitfield<11> ufe; 1624 Bitfield<12> ixe; 1625 Bitfield<15> ide; 1626 Bitfield<18, 16> len; 1627 Bitfield<21, 20> stride; 1628 Bitfield<23, 22> rMode; 1629 Bitfield<24> fz; 1630 Bitfield<25> dn; 1631 Bitfield<26> ahp; 1632 Bitfield<27> qc; 1633 Bitfield<28> v; 1634 Bitfield<29> c; 1635 Bitfield<30> z; 1636 Bitfield<31> n; 1637 EndBitUnion(FPSCR) 1638 1639 // This mask selects bits of the FPSCR that actually go in the FpCondCodes 1640 // integer register to allow renaming. 1641 static const uint32_t FpCondCodesMask = 0xF0000000; 1642 // This mask selects the cumulative FP exception flags of the FPSCR. 1643 static const uint32_t FpscrExcMask = 0x0000009F; 1644 // This mask selects the cumulative saturation flag of the FPSCR. 1645 static const uint32_t FpscrQcMask = 0x08000000; 1646 1647 BitUnion32(FPEXC) 1648 Bitfield<31> ex; 1649 Bitfield<30> en; 1650 Bitfield<29, 0> subArchDefined; 1651 EndBitUnion(FPEXC) 1652 1653 BitUnion32(MVFR0) 1654 Bitfield<3, 0> advSimdRegisters; 1655 Bitfield<7, 4> singlePrecision; 1656 Bitfield<11, 8> doublePrecision; 1657 Bitfield<15, 12> vfpExceptionTrapping; 1658 Bitfield<19, 16> divide; 1659 Bitfield<23, 20> squareRoot; 1660 Bitfield<27, 24> shortVectors; 1661 Bitfield<31, 28> roundingModes; 1662 EndBitUnion(MVFR0) 1663 1664 BitUnion32(MVFR1) 1665 Bitfield<3, 0> flushToZero; 1666 Bitfield<7, 4> defaultNaN; 1667 Bitfield<11, 8> advSimdLoadStore; 1668 Bitfield<15, 12> advSimdInteger; 1669 Bitfield<19, 16> advSimdSinglePrecision; 1670 Bitfield<23, 20> advSimdHalfPrecision; 1671 Bitfield<27, 24> vfpHalfPrecision; 1672 Bitfield<31, 28> raz; 1673 EndBitUnion(MVFR1) 1674 1675 BitUnion64(TTBCR) 1676 // Short-descriptor translation table format 1677 Bitfield<2, 0> n; 1678 Bitfield<4> pd0; 1679 Bitfield<5> pd1; 1680 // Long-descriptor translation table format 1681 Bitfield<5, 0> t0sz; 1682 Bitfield<7> epd0; 1683 Bitfield<9, 8> irgn0; 1684 Bitfield<11, 10> orgn0; 1685 Bitfield<13, 12> sh0; 1686 Bitfield<14> tg0; 1687 Bitfield<21, 16> t1sz; 1688 Bitfield<22> a1; 1689 Bitfield<23> epd1; 1690 Bitfield<25, 24> irgn1; 1691 Bitfield<27, 26> orgn1; 1692 Bitfield<29, 28> sh1; 1693 Bitfield<30> tg1; 1694 Bitfield<34, 32> ips; 1695 Bitfield<36> as; 1696 Bitfield<37> tbi0; 1697 Bitfield<38> tbi1; 1698 // Common 1699 Bitfield<31> eae; 1700 // TCR_EL2/3 (AArch64) 1701 Bitfield<18, 16> ps; 1702 Bitfield<20> tbi; 1703 EndBitUnion(TTBCR) 1704 1705 // Fields of TCR_EL{1,2,3} (mostly overlapping) 1706 // TCR_EL1 is natively 64 bits, the others are 32 bits 1707 BitUnion64(TCR) 1708 Bitfield<5, 0> t0sz; 1709 Bitfield<7> epd0; // EL1 1710 Bitfield<9, 8> irgn0; 1711 Bitfield<11, 10> orgn0; 1712 Bitfield<13, 12> sh0; 1713 Bitfield<15, 14> tg0; 1714 Bitfield<18, 16> ps; 1715 Bitfield<20> tbi; // EL2/EL3 1716 Bitfield<21, 16> t1sz; // EL1 1717 Bitfield<22> a1; // EL1 1718 Bitfield<23> epd1; // EL1 1719 Bitfield<25, 24> irgn1; // EL1 1720 Bitfield<27, 26> orgn1; // EL1 1721 Bitfield<29, 28> sh1; // EL1 1722 Bitfield<31, 30> tg1; // EL1 1723 Bitfield<34, 32> ips; // EL1 1724 Bitfield<36> as; // EL1 1725 Bitfield<37> tbi0; // EL1 1726 Bitfield<38> tbi1; // EL1 1727 EndBitUnion(TCR) 1728 1729 BitUnion32(HTCR) 1730 Bitfield<2, 0> t0sz; 1731 Bitfield<9, 8> irgn0; 1732 Bitfield<11, 10> orgn0; 1733 Bitfield<13, 12> sh0; 1734 EndBitUnion(HTCR) 1735 1736 BitUnion32(VTCR_t) 1737 Bitfield<3, 0> t0sz; 1738 Bitfield<4> s; 1739 Bitfield<5, 0> t0sz64; 1740 Bitfield<7, 6> sl0; 1741 Bitfield<9, 8> irgn0; 1742 Bitfield<11, 10> orgn0; 1743 Bitfield<13, 12> sh0; 1744 Bitfield<15, 14> tg0; 1745 EndBitUnion(VTCR_t) 1746 1747 BitUnion32(PRRR) 1748 Bitfield<1,0> tr0; 1749 Bitfield<3,2> tr1; 1750 Bitfield<5,4> tr2; 1751 Bitfield<7,6> tr3; 1752 Bitfield<9,8> tr4; 1753 Bitfield<11,10> tr5; 1754 Bitfield<13,12> tr6; 1755 Bitfield<15,14> tr7; 1756 Bitfield<16> ds0; 1757 Bitfield<17> ds1; 1758 Bitfield<18> ns0; 1759 Bitfield<19> ns1; 1760 Bitfield<24> nos0; 1761 Bitfield<25> nos1; 1762 Bitfield<26> nos2; 1763 Bitfield<27> nos3; 1764 Bitfield<28> nos4; 1765 Bitfield<29> nos5; 1766 Bitfield<30> nos6; 1767 Bitfield<31> nos7; 1768 EndBitUnion(PRRR) 1769 1770 BitUnion32(NMRR) 1771 Bitfield<1,0> ir0; 1772 Bitfield<3,2> ir1; 1773 Bitfield<5,4> ir2; 1774 Bitfield<7,6> ir3; 1775 Bitfield<9,8> ir4; 1776 Bitfield<11,10> ir5; 1777 Bitfield<13,12> ir6; 1778 Bitfield<15,14> ir7; 1779 Bitfield<17,16> or0; 1780 Bitfield<19,18> or1; 1781 Bitfield<21,20> or2; 1782 Bitfield<23,22> or3; 1783 Bitfield<25,24> or4; 1784 Bitfield<27,26> or5; 1785 Bitfield<29,28> or6; 1786 Bitfield<31,30> or7; 1787 EndBitUnion(NMRR) 1788 1789 BitUnion32(CONTEXTIDR) 1790 Bitfield<7,0> asid; 1791 Bitfield<31,8> procid; 1792 EndBitUnion(CONTEXTIDR) 1793 1794 BitUnion32(L2CTLR) 1795 Bitfield<2,0> sataRAMLatency; 1796 Bitfield<4,3> reserved_4_3; 1797 Bitfield<5> dataRAMSetup; 1798 Bitfield<8,6> tagRAMLatency; 1799 Bitfield<9> tagRAMSetup; 1800 Bitfield<11,10> dataRAMSlice; 1801 Bitfield<12> tagRAMSlice; 1802 Bitfield<20,13> reserved_20_13; 1803 Bitfield<21> eccandParityEnable; 1804 Bitfield<22> reserved_22; 1805 Bitfield<23> interptCtrlPresent; 1806 Bitfield<25,24> numCPUs; 1807 Bitfield<30,26> reserved_30_26; 1808 Bitfield<31> l2rstDISABLE_monitor; 1809 EndBitUnion(L2CTLR) 1810 1811 BitUnion32(CTR) 1812 Bitfield<3,0> iCacheLineSize; 1813 Bitfield<13,4> raz_13_4; 1814 Bitfield<15,14> l1IndexPolicy; 1815 Bitfield<19,16> dCacheLineSize; 1816 Bitfield<23,20> erg; 1817 Bitfield<27,24> cwg; 1818 Bitfield<28> raz_28; 1819 Bitfield<31,29> format; 1820 EndBitUnion(CTR) 1821 1822 BitUnion32(PMSELR) 1823 Bitfield<4, 0> sel; 1824 EndBitUnion(PMSELR) 1825 1826 BitUnion64(PAR) 1827 // 64-bit format 1828 Bitfield<63, 56> attr; 1829 Bitfield<39, 12> pa; 1830 Bitfield<11> lpae; 1831 Bitfield<9> ns; 1832 Bitfield<8, 7> sh; 1833 Bitfield<0> f; 1834 EndBitUnion(PAR) 1835 1836 BitUnion32(ESR) 1837 Bitfield<31, 26> ec; 1838 Bitfield<25> il; 1839 Bitfield<15, 0> imm16; 1840 EndBitUnion(ESR) 1841 1842 BitUnion32(CPTR) 1843 Bitfield<31> tcpac; 1844 Bitfield<20> tta; 1845 Bitfield<13, 12> res1_13_12_el2; 1846 Bitfield<10> tfp; 1847 Bitfield<9, 0> res1_9_0_el2; 1848 EndBitUnion(CPTR) 1849 1850 1851 /** 1852 * Check for permission to read coprocessor registers. 1853 * 1854 * Checks whether an instruction at the current program mode has 1855 * permissions to read the coprocessor registers. This function 1856 * returns whether the check is undefined and if not whether the 1857 * read access is permitted. 1858 * 1859 * @param the misc reg indicating the coprocessor 1860 * @param the SCR 1861 * @param the CPSR 1862 * @return a tuple of booleans: can_read, undefined 1863 */ 1864 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr, 1865 CPSR cpsr); 1866 1867 /** 1868 * Check for permission to write coprocessor registers. 1869 * 1870 * Checks whether an instruction at the current program mode has 1871 * permissions to write the coprocessor registers. This function 1872 * returns whether the check is undefined and if not whether the 1873 * write access is permitted. 1874 * 1875 * @param the misc reg indicating the coprocessor 1876 * @param the SCR 1877 * @param the CPSR 1878 * @return a tuple of booleans: can_write, undefined 1879 */ 1880 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr, 1881 CPSR cpsr); 1882 1883 // Checks read access permissions to AArch64 system registers 1884 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1885 ThreadContext *tc); 1886 1887 // Checks write access permissions to AArch64 system registers 1888 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1889 ThreadContext *tc); 1890 1891 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful 1892 // for MCR/MRC instructions 1893 int 1894 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc); 1895 1896 // Flattens a misc reg index using the specified security state. This is 1897 // used for opperations (eg address translations) where the security 1898 // state of the register access may differ from the current state of the 1899 // processor 1900 int 1901 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns); 1902 1903 // Takes a misc reg index and returns the root reg if its one of a set of 1904 // banked registers 1905 void 1906 preUnflattenMiscReg(); 1907 1908 int 1909 unflattenMiscReg(int reg); 1910 1911} 1912 1913#endif // __ARCH_ARM_MISCREGS_HH__ 1914