miscregs.hh revision 11514
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 *          Giacomo Gabrielli
42 */
43#ifndef __ARCH_ARM_MISCREGS_HH__
44#define __ARCH_ARM_MISCREGS_HH__
45
46#include <bitset>
47
48#include "base/bitunion.hh"
49#include "base/compiler.hh"
50
51class ThreadContext;
52
53
54namespace ArmISA
55{
56    enum MiscRegIndex {
57        MISCREG_CPSR = 0,               //   0
58        MISCREG_SPSR,                   //   1
59        MISCREG_SPSR_FIQ,               //   2
60        MISCREG_SPSR_IRQ,               //   3
61        MISCREG_SPSR_SVC,               //   4
62        MISCREG_SPSR_MON,               //   5
63        MISCREG_SPSR_ABT,               //   6
64        MISCREG_SPSR_HYP,               //   7
65        MISCREG_SPSR_UND,               //   8
66        MISCREG_ELR_HYP,                //   9
67        MISCREG_FPSID,                  //  10
68        MISCREG_FPSCR,                  //  11
69        MISCREG_MVFR1,                  //  12
70        MISCREG_MVFR0,                  //  13
71        MISCREG_FPEXC,                  //  14
72
73        // Helper registers
74        MISCREG_CPSR_MODE,              //  15
75        MISCREG_CPSR_Q,                 //  16
76        MISCREG_FPSCR_EXC,              //  17
77        MISCREG_FPSCR_QC,               //  18
78        MISCREG_LOCKADDR,               //  19
79        MISCREG_LOCKFLAG,               //  20
80        MISCREG_PRRR_MAIR0,             //  21
81        MISCREG_PRRR_MAIR0_NS,          //  22
82        MISCREG_PRRR_MAIR0_S,           //  23
83        MISCREG_NMRR_MAIR1,             //  24
84        MISCREG_NMRR_MAIR1_NS,          //  25
85        MISCREG_NMRR_MAIR1_S,           //  26
86        MISCREG_PMXEVTYPER_PMCCFILTR,   //  27
87        MISCREG_SCTLR_RST,              //  28
88        MISCREG_SEV_MAILBOX,            //  29
89
90        // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
91        MISCREG_DBGDIDR,                //  30
92        MISCREG_DBGDSCRint,             //  31
93        MISCREG_DBGDCCINT,              //  32
94        MISCREG_DBGDTRTXint,            //  33
95        MISCREG_DBGDTRRXint,            //  34
96        MISCREG_DBGWFAR,                //  35
97        MISCREG_DBGVCR,                 //  36
98        MISCREG_DBGDTRRXext,            //  37
99        MISCREG_DBGDSCRext,             //  38
100        MISCREG_DBGDTRTXext,            //  39
101        MISCREG_DBGOSECCR,              //  40
102        MISCREG_DBGBVR0,                //  41
103        MISCREG_DBGBVR1,                //  42
104        MISCREG_DBGBVR2,                //  43
105        MISCREG_DBGBVR3,                //  44
106        MISCREG_DBGBVR4,                //  45
107        MISCREG_DBGBVR5,                //  46
108        MISCREG_DBGBCR0,                //  47
109        MISCREG_DBGBCR1,                //  48
110        MISCREG_DBGBCR2,                //  49
111        MISCREG_DBGBCR3,                //  50
112        MISCREG_DBGBCR4,                //  51
113        MISCREG_DBGBCR5,                //  52
114        MISCREG_DBGWVR0,                //  53
115        MISCREG_DBGWVR1,                //  54
116        MISCREG_DBGWVR2,                //  55
117        MISCREG_DBGWVR3,                //  56
118        MISCREG_DBGWCR0,                //  57
119        MISCREG_DBGWCR1,                //  58
120        MISCREG_DBGWCR2,                //  59
121        MISCREG_DBGWCR3,                //  60
122        MISCREG_DBGDRAR,                //  61
123        MISCREG_DBGBXVR4,               //  62
124        MISCREG_DBGBXVR5,               //  63
125        MISCREG_DBGOSLAR,               //  64
126        MISCREG_DBGOSLSR,               //  65
127        MISCREG_DBGOSDLR,               //  66
128        MISCREG_DBGPRCR,                //  67
129        MISCREG_DBGDSAR,                //  68
130        MISCREG_DBGCLAIMSET,            //  69
131        MISCREG_DBGCLAIMCLR,            //  70
132        MISCREG_DBGAUTHSTATUS,          //  71
133        MISCREG_DBGDEVID2,              //  72
134        MISCREG_DBGDEVID1,              //  73
135        MISCREG_DBGDEVID0,              //  74
136        MISCREG_TEECR,                  //  75
137        MISCREG_JIDR,                   //  76
138        MISCREG_TEEHBR,                 //  77
139        MISCREG_JOSCR,                  //  78
140        MISCREG_JMCR,                   //  79
141
142        // AArch32 CP15 registers (system control)
143        MISCREG_MIDR,                   //  80
144        MISCREG_CTR,                    //  81
145        MISCREG_TCMTR,                  //  82
146        MISCREG_TLBTR,                  //  83
147        MISCREG_MPIDR,                  //  84
148        MISCREG_REVIDR,                 //  85
149        MISCREG_ID_PFR0,                //  86
150        MISCREG_ID_PFR1,                //  87
151        MISCREG_ID_DFR0,                //  88
152        MISCREG_ID_AFR0,                //  89
153        MISCREG_ID_MMFR0,               //  90
154        MISCREG_ID_MMFR1,               //  91
155        MISCREG_ID_MMFR2,               //  92
156        MISCREG_ID_MMFR3,               //  93
157        MISCREG_ID_ISAR0,               //  94
158        MISCREG_ID_ISAR1,               //  95
159        MISCREG_ID_ISAR2,               //  96
160        MISCREG_ID_ISAR3,               //  97
161        MISCREG_ID_ISAR4,               //  98
162        MISCREG_ID_ISAR5,               //  99
163        MISCREG_CCSIDR,                 // 100
164        MISCREG_CLIDR,                  // 101
165        MISCREG_AIDR,                   // 102
166        MISCREG_CSSELR,                 // 103
167        MISCREG_CSSELR_NS,              // 104
168        MISCREG_CSSELR_S,               // 105
169        MISCREG_VPIDR,                  // 106
170        MISCREG_VMPIDR,                 // 107
171        MISCREG_SCTLR,                  // 108
172        MISCREG_SCTLR_NS,               // 109
173        MISCREG_SCTLR_S,                // 110
174        MISCREG_ACTLR,                  // 111
175        MISCREG_ACTLR_NS,               // 112
176        MISCREG_ACTLR_S,                // 113
177        MISCREG_CPACR,                  // 114
178        MISCREG_SCR,                    // 115
179        MISCREG_SDER,                   // 116
180        MISCREG_NSACR,                  // 117
181        MISCREG_HSCTLR,                 // 118
182        MISCREG_HACTLR,                 // 119
183        MISCREG_HCR,                    // 120
184        MISCREG_HDCR,                   // 121
185        MISCREG_HCPTR,                  // 122
186        MISCREG_HSTR,                   // 123
187        MISCREG_HACR,                   // 124
188        MISCREG_TTBR0,                  // 125
189        MISCREG_TTBR0_NS,               // 126
190        MISCREG_TTBR0_S,                // 127
191        MISCREG_TTBR1,                  // 128
192        MISCREG_TTBR1_NS,               // 129
193        MISCREG_TTBR1_S,                // 130
194        MISCREG_TTBCR,                  // 131
195        MISCREG_TTBCR_NS,               // 132
196        MISCREG_TTBCR_S,                // 133
197        MISCREG_HTCR,                   // 134
198        MISCREG_VTCR,                   // 135
199        MISCREG_DACR,                   // 136
200        MISCREG_DACR_NS,                // 137
201        MISCREG_DACR_S,                 // 138
202        MISCREG_DFSR,                   // 139
203        MISCREG_DFSR_NS,                // 140
204        MISCREG_DFSR_S,                 // 141
205        MISCREG_IFSR,                   // 142
206        MISCREG_IFSR_NS,                // 143
207        MISCREG_IFSR_S,                 // 144
208        MISCREG_ADFSR,                  // 145
209        MISCREG_ADFSR_NS,               // 146
210        MISCREG_ADFSR_S,                // 147
211        MISCREG_AIFSR,                  // 148
212        MISCREG_AIFSR_NS,               // 149
213        MISCREG_AIFSR_S,                // 150
214        MISCREG_HADFSR,                 // 151
215        MISCREG_HAIFSR,                 // 152
216        MISCREG_HSR,                    // 153
217        MISCREG_DFAR,                   // 154
218        MISCREG_DFAR_NS,                // 155
219        MISCREG_DFAR_S,                 // 156
220        MISCREG_IFAR,                   // 157
221        MISCREG_IFAR_NS,                // 158
222        MISCREG_IFAR_S,                 // 159
223        MISCREG_HDFAR,                  // 160
224        MISCREG_HIFAR,                  // 161
225        MISCREG_HPFAR,                  // 162
226        MISCREG_ICIALLUIS,              // 163
227        MISCREG_BPIALLIS,               // 164
228        MISCREG_PAR,                    // 165
229        MISCREG_PAR_NS,                 // 166
230        MISCREG_PAR_S,                  // 167
231        MISCREG_ICIALLU,                // 168
232        MISCREG_ICIMVAU,                // 169
233        MISCREG_CP15ISB,                // 170
234        MISCREG_BPIALL,                 // 171
235        MISCREG_BPIMVA,                 // 172
236        MISCREG_DCIMVAC,                // 173
237        MISCREG_DCISW,                  // 174
238        MISCREG_ATS1CPR,                // 175
239        MISCREG_ATS1CPW,                // 176
240        MISCREG_ATS1CUR,                // 177
241        MISCREG_ATS1CUW,                // 178
242        MISCREG_ATS12NSOPR,             // 179
243        MISCREG_ATS12NSOPW,             // 180
244        MISCREG_ATS12NSOUR,             // 181
245        MISCREG_ATS12NSOUW,             // 182
246        MISCREG_DCCMVAC,                // 183
247        MISCREG_DCCSW,                  // 184
248        MISCREG_CP15DSB,                // 185
249        MISCREG_CP15DMB,                // 186
250        MISCREG_DCCMVAU,                // 187
251        MISCREG_DCCIMVAC,               // 188
252        MISCREG_DCCISW,                 // 189
253        MISCREG_ATS1HR,                 // 190
254        MISCREG_ATS1HW,                 // 191
255        MISCREG_TLBIALLIS,              // 192
256        MISCREG_TLBIMVAIS,              // 193
257        MISCREG_TLBIASIDIS,             // 194
258        MISCREG_TLBIMVAAIS,             // 195
259        MISCREG_TLBIMVALIS,             // 196
260        MISCREG_TLBIMVAALIS,            // 197
261        MISCREG_ITLBIALL,               // 198
262        MISCREG_ITLBIMVA,               // 199
263        MISCREG_ITLBIASID,              // 200
264        MISCREG_DTLBIALL,               // 201
265        MISCREG_DTLBIMVA,               // 202
266        MISCREG_DTLBIASID,              // 203
267        MISCREG_TLBIALL,                // 204
268        MISCREG_TLBIMVA,                // 205
269        MISCREG_TLBIASID,               // 206
270        MISCREG_TLBIMVAA,               // 207
271        MISCREG_TLBIMVAL,               // 208
272        MISCREG_TLBIMVAAL,              // 209
273        MISCREG_TLBIIPAS2IS,            // 210
274        MISCREG_TLBIIPAS2LIS,           // 211
275        MISCREG_TLBIALLHIS,             // 212
276        MISCREG_TLBIMVAHIS,             // 213
277        MISCREG_TLBIALLNSNHIS,          // 214
278        MISCREG_TLBIMVALHIS,            // 215
279        MISCREG_TLBIIPAS2,              // 216
280        MISCREG_TLBIIPAS2L,             // 217
281        MISCREG_TLBIALLH,               // 218
282        MISCREG_TLBIMVAH,               // 219
283        MISCREG_TLBIALLNSNH,            // 220
284        MISCREG_TLBIMVALH,              // 221
285        MISCREG_PMCR,                   // 222
286        MISCREG_PMCNTENSET,             // 223
287        MISCREG_PMCNTENCLR,             // 224
288        MISCREG_PMOVSR,                 // 225
289        MISCREG_PMSWINC,                // 226
290        MISCREG_PMSELR,                 // 227
291        MISCREG_PMCEID0,                // 228
292        MISCREG_PMCEID1,                // 229
293        MISCREG_PMCCNTR,                // 230
294        MISCREG_PMXEVTYPER,             // 231
295        MISCREG_PMCCFILTR,              // 232
296        MISCREG_PMXEVCNTR,              // 233
297        MISCREG_PMUSERENR,              // 234
298        MISCREG_PMINTENSET,             // 235
299        MISCREG_PMINTENCLR,             // 236
300        MISCREG_PMOVSSET,               // 237
301        MISCREG_L2CTLR,                 // 238
302        MISCREG_L2ECTLR,                // 239
303        MISCREG_PRRR,                   // 240
304        MISCREG_PRRR_NS,                // 241
305        MISCREG_PRRR_S,                 // 242
306        MISCREG_MAIR0,                  // 243
307        MISCREG_MAIR0_NS,               // 244
308        MISCREG_MAIR0_S,                // 245
309        MISCREG_NMRR,                   // 246
310        MISCREG_NMRR_NS,                // 247
311        MISCREG_NMRR_S,                 // 248
312        MISCREG_MAIR1,                  // 249
313        MISCREG_MAIR1_NS,               // 250
314        MISCREG_MAIR1_S,                // 251
315        MISCREG_AMAIR0,                 // 252
316        MISCREG_AMAIR0_NS,              // 253
317        MISCREG_AMAIR0_S,               // 254
318        MISCREG_AMAIR1,                 // 255
319        MISCREG_AMAIR1_NS,              // 256
320        MISCREG_AMAIR1_S,               // 257
321        MISCREG_HMAIR0,                 // 258
322        MISCREG_HMAIR1,                 // 259
323        MISCREG_HAMAIR0,                // 260
324        MISCREG_HAMAIR1,                // 261
325        MISCREG_VBAR,                   // 262
326        MISCREG_VBAR_NS,                // 263
327        MISCREG_VBAR_S,                 // 264
328        MISCREG_MVBAR,                  // 265
329        MISCREG_RMR,                    // 266
330        MISCREG_ISR,                    // 267
331        MISCREG_HVBAR,                  // 268
332        MISCREG_FCSEIDR,                // 269
333        MISCREG_CONTEXTIDR,             // 270
334        MISCREG_CONTEXTIDR_NS,          // 271
335        MISCREG_CONTEXTIDR_S,           // 272
336        MISCREG_TPIDRURW,               // 273
337        MISCREG_TPIDRURW_NS,            // 274
338        MISCREG_TPIDRURW_S,             // 275
339        MISCREG_TPIDRURO,               // 276
340        MISCREG_TPIDRURO_NS,            // 277
341        MISCREG_TPIDRURO_S,             // 278
342        MISCREG_TPIDRPRW,               // 279
343        MISCREG_TPIDRPRW_NS,            // 280
344        MISCREG_TPIDRPRW_S,             // 281
345        MISCREG_HTPIDR,                 // 282
346        MISCREG_CNTFRQ,                 // 283
347        MISCREG_CNTKCTL,                // 284
348        MISCREG_CNTP_TVAL,              // 285
349        MISCREG_CNTP_TVAL_NS,           // 286
350        MISCREG_CNTP_TVAL_S,            // 287
351        MISCREG_CNTP_CTL,               // 288
352        MISCREG_CNTP_CTL_NS,            // 289
353        MISCREG_CNTP_CTL_S,             // 290
354        MISCREG_CNTV_TVAL,              // 291
355        MISCREG_CNTV_CTL,               // 292
356        MISCREG_CNTHCTL,                // 293
357        MISCREG_CNTHP_TVAL,             // 294
358        MISCREG_CNTHP_CTL,              // 295
359        MISCREG_IL1DATA0,               // 296
360        MISCREG_IL1DATA1,               // 297
361        MISCREG_IL1DATA2,               // 298
362        MISCREG_IL1DATA3,               // 299
363        MISCREG_DL1DATA0,               // 300
364        MISCREG_DL1DATA1,               // 301
365        MISCREG_DL1DATA2,               // 302
366        MISCREG_DL1DATA3,               // 303
367        MISCREG_DL1DATA4,               // 304
368        MISCREG_RAMINDEX,               // 305
369        MISCREG_L2ACTLR,                // 306
370        MISCREG_CBAR,                   // 307
371        MISCREG_HTTBR,                  // 308
372        MISCREG_VTTBR,                  // 309
373        MISCREG_CNTPCT,                 // 310
374        MISCREG_CNTVCT,                 // 311
375        MISCREG_CNTP_CVAL,              // 312
376        MISCREG_CNTP_CVAL_NS,           // 313
377        MISCREG_CNTP_CVAL_S,            // 314
378        MISCREG_CNTV_CVAL,              // 315
379        MISCREG_CNTVOFF,                // 316
380        MISCREG_CNTHP_CVAL,             // 317
381        MISCREG_CPUMERRSR,              // 318
382        MISCREG_L2MERRSR,               // 319
383
384        // AArch64 registers (Op0=2)
385        MISCREG_MDCCINT_EL1,            // 320
386        MISCREG_OSDTRRX_EL1,            // 321
387        MISCREG_MDSCR_EL1,              // 322
388        MISCREG_OSDTRTX_EL1,            // 323
389        MISCREG_OSECCR_EL1,             // 324
390        MISCREG_DBGBVR0_EL1,            // 325
391        MISCREG_DBGBVR1_EL1,            // 326
392        MISCREG_DBGBVR2_EL1,            // 327
393        MISCREG_DBGBVR3_EL1,            // 328
394        MISCREG_DBGBVR4_EL1,            // 329
395        MISCREG_DBGBVR5_EL1,            // 330
396        MISCREG_DBGBCR0_EL1,            // 331
397        MISCREG_DBGBCR1_EL1,            // 332
398        MISCREG_DBGBCR2_EL1,            // 333
399        MISCREG_DBGBCR3_EL1,            // 334
400        MISCREG_DBGBCR4_EL1,            // 335
401        MISCREG_DBGBCR5_EL1,            // 336
402        MISCREG_DBGWVR0_EL1,            // 337
403        MISCREG_DBGWVR1_EL1,            // 338
404        MISCREG_DBGWVR2_EL1,            // 339
405        MISCREG_DBGWVR3_EL1,            // 340
406        MISCREG_DBGWCR0_EL1,            // 341
407        MISCREG_DBGWCR1_EL1,            // 342
408        MISCREG_DBGWCR2_EL1,            // 343
409        MISCREG_DBGWCR3_EL1,            // 344
410        MISCREG_MDCCSR_EL0,             // 345
411        MISCREG_MDDTR_EL0,              // 346
412        MISCREG_MDDTRTX_EL0,            // 347
413        MISCREG_MDDTRRX_EL0,            // 348
414        MISCREG_DBGVCR32_EL2,           // 349
415        MISCREG_MDRAR_EL1,              // 350
416        MISCREG_OSLAR_EL1,              // 351
417        MISCREG_OSLSR_EL1,              // 352
418        MISCREG_OSDLR_EL1,              // 353
419        MISCREG_DBGPRCR_EL1,            // 354
420        MISCREG_DBGCLAIMSET_EL1,        // 355
421        MISCREG_DBGCLAIMCLR_EL1,        // 356
422        MISCREG_DBGAUTHSTATUS_EL1,      // 357
423        MISCREG_TEECR32_EL1,            // 358
424        MISCREG_TEEHBR32_EL1,           // 359
425
426        // AArch64 registers (Op0=1,3)
427        MISCREG_MIDR_EL1,               // 360
428        MISCREG_MPIDR_EL1,              // 361
429        MISCREG_REVIDR_EL1,             // 362
430        MISCREG_ID_PFR0_EL1,            // 363
431        MISCREG_ID_PFR1_EL1,            // 364
432        MISCREG_ID_DFR0_EL1,            // 365
433        MISCREG_ID_AFR0_EL1,            // 366
434        MISCREG_ID_MMFR0_EL1,           // 367
435        MISCREG_ID_MMFR1_EL1,           // 368
436        MISCREG_ID_MMFR2_EL1,           // 369
437        MISCREG_ID_MMFR3_EL1,           // 370
438        MISCREG_ID_ISAR0_EL1,           // 371
439        MISCREG_ID_ISAR1_EL1,           // 372
440        MISCREG_ID_ISAR2_EL1,           // 373
441        MISCREG_ID_ISAR3_EL1,           // 374
442        MISCREG_ID_ISAR4_EL1,           // 375
443        MISCREG_ID_ISAR5_EL1,           // 376
444        MISCREG_MVFR0_EL1,              // 377
445        MISCREG_MVFR1_EL1,              // 378
446        MISCREG_MVFR2_EL1,              // 379
447        MISCREG_ID_AA64PFR0_EL1,        // 380
448        MISCREG_ID_AA64PFR1_EL1,        // 381
449        MISCREG_ID_AA64DFR0_EL1,        // 382
450        MISCREG_ID_AA64DFR1_EL1,        // 383
451        MISCREG_ID_AA64AFR0_EL1,        // 384
452        MISCREG_ID_AA64AFR1_EL1,        // 385
453        MISCREG_ID_AA64ISAR0_EL1,       // 386
454        MISCREG_ID_AA64ISAR1_EL1,       // 387
455        MISCREG_ID_AA64MMFR0_EL1,       // 388
456        MISCREG_ID_AA64MMFR1_EL1,       // 389
457        MISCREG_CCSIDR_EL1,             // 390
458        MISCREG_CLIDR_EL1,              // 391
459        MISCREG_AIDR_EL1,               // 392
460        MISCREG_CSSELR_EL1,             // 393
461        MISCREG_CTR_EL0,                // 394
462        MISCREG_DCZID_EL0,              // 395
463        MISCREG_VPIDR_EL2,              // 396
464        MISCREG_VMPIDR_EL2,             // 397
465        MISCREG_SCTLR_EL1,              // 398
466        MISCREG_ACTLR_EL1,              // 399
467        MISCREG_CPACR_EL1,              // 400
468        MISCREG_SCTLR_EL2,              // 401
469        MISCREG_ACTLR_EL2,              // 402
470        MISCREG_HCR_EL2,                // 403
471        MISCREG_MDCR_EL2,               // 404
472        MISCREG_CPTR_EL2,               // 405
473        MISCREG_HSTR_EL2,               // 406
474        MISCREG_HACR_EL2,               // 407
475        MISCREG_SCTLR_EL3,              // 408
476        MISCREG_ACTLR_EL3,              // 409
477        MISCREG_SCR_EL3,                // 410
478        MISCREG_SDER32_EL3,             // 411
479        MISCREG_CPTR_EL3,               // 412
480        MISCREG_MDCR_EL3,               // 413
481        MISCREG_TTBR0_EL1,              // 414
482        MISCREG_TTBR1_EL1,              // 415
483        MISCREG_TCR_EL1,                // 416
484        MISCREG_TTBR0_EL2,              // 417
485        MISCREG_TCR_EL2,                // 418
486        MISCREG_VTTBR_EL2,              // 419
487        MISCREG_VTCR_EL2,               // 420
488        MISCREG_TTBR0_EL3,              // 421
489        MISCREG_TCR_EL3,                // 422
490        MISCREG_DACR32_EL2,             // 423
491        MISCREG_SPSR_EL1,               // 424
492        MISCREG_ELR_EL1,                // 425
493        MISCREG_SP_EL0,                 // 426
494        MISCREG_SPSEL,                  // 427
495        MISCREG_CURRENTEL,              // 428
496        MISCREG_NZCV,                   // 429
497        MISCREG_DAIF,                   // 430
498        MISCREG_FPCR,                   // 431
499        MISCREG_FPSR,                   // 432
500        MISCREG_DSPSR_EL0,              // 433
501        MISCREG_DLR_EL0,                // 434
502        MISCREG_SPSR_EL2,               // 435
503        MISCREG_ELR_EL2,                // 436
504        MISCREG_SP_EL1,                 // 437
505        MISCREG_SPSR_IRQ_AA64,          // 438
506        MISCREG_SPSR_ABT_AA64,          // 439
507        MISCREG_SPSR_UND_AA64,          // 440
508        MISCREG_SPSR_FIQ_AA64,          // 441
509        MISCREG_SPSR_EL3,               // 442
510        MISCREG_ELR_EL3,                // 443
511        MISCREG_SP_EL2,                 // 444
512        MISCREG_AFSR0_EL1,              // 445
513        MISCREG_AFSR1_EL1,              // 446
514        MISCREG_ESR_EL1,                // 447
515        MISCREG_IFSR32_EL2,             // 448
516        MISCREG_AFSR0_EL2,              // 449
517        MISCREG_AFSR1_EL2,              // 450
518        MISCREG_ESR_EL2,                // 451
519        MISCREG_FPEXC32_EL2,            // 452
520        MISCREG_AFSR0_EL3,              // 453
521        MISCREG_AFSR1_EL3,              // 454
522        MISCREG_ESR_EL3,                // 455
523        MISCREG_FAR_EL1,                // 456
524        MISCREG_FAR_EL2,                // 457
525        MISCREG_HPFAR_EL2,              // 458
526        MISCREG_FAR_EL3,                // 459
527        MISCREG_IC_IALLUIS,             // 460
528        MISCREG_PAR_EL1,                // 461
529        MISCREG_IC_IALLU,               // 462
530        MISCREG_DC_IVAC_Xt,             // 463
531        MISCREG_DC_ISW_Xt,              // 464
532        MISCREG_AT_S1E1R_Xt,            // 465
533        MISCREG_AT_S1E1W_Xt,            // 466
534        MISCREG_AT_S1E0R_Xt,            // 467
535        MISCREG_AT_S1E0W_Xt,            // 468
536        MISCREG_DC_CSW_Xt,              // 469
537        MISCREG_DC_CISW_Xt,             // 470
538        MISCREG_DC_ZVA_Xt,              // 471
539        MISCREG_IC_IVAU_Xt,             // 472
540        MISCREG_DC_CVAC_Xt,             // 473
541        MISCREG_DC_CVAU_Xt,             // 474
542        MISCREG_DC_CIVAC_Xt,            // 475
543        MISCREG_AT_S1E2R_Xt,            // 476
544        MISCREG_AT_S1E2W_Xt,            // 477
545        MISCREG_AT_S12E1R_Xt,           // 478
546        MISCREG_AT_S12E1W_Xt,           // 479
547        MISCREG_AT_S12E0R_Xt,           // 480
548        MISCREG_AT_S12E0W_Xt,           // 481
549        MISCREG_AT_S1E3R_Xt,            // 482
550        MISCREG_AT_S1E3W_Xt,            // 483
551        MISCREG_TLBI_VMALLE1IS,         // 484
552        MISCREG_TLBI_VAE1IS_Xt,         // 485
553        MISCREG_TLBI_ASIDE1IS_Xt,       // 486
554        MISCREG_TLBI_VAAE1IS_Xt,        // 487
555        MISCREG_TLBI_VALE1IS_Xt,        // 488
556        MISCREG_TLBI_VAALE1IS_Xt,       // 489
557        MISCREG_TLBI_VMALLE1,           // 490
558        MISCREG_TLBI_VAE1_Xt,           // 491
559        MISCREG_TLBI_ASIDE1_Xt,         // 492
560        MISCREG_TLBI_VAAE1_Xt,          // 493
561        MISCREG_TLBI_VALE1_Xt,          // 494
562        MISCREG_TLBI_VAALE1_Xt,         // 495
563        MISCREG_TLBI_IPAS2E1IS_Xt,      // 496
564        MISCREG_TLBI_IPAS2LE1IS_Xt,     // 497
565        MISCREG_TLBI_ALLE2IS,           // 498
566        MISCREG_TLBI_VAE2IS_Xt,         // 499
567        MISCREG_TLBI_ALLE1IS,           // 500
568        MISCREG_TLBI_VALE2IS_Xt,        // 501
569        MISCREG_TLBI_VMALLS12E1IS,      // 502
570        MISCREG_TLBI_IPAS2E1_Xt,        // 503
571        MISCREG_TLBI_IPAS2LE1_Xt,       // 504
572        MISCREG_TLBI_ALLE2,             // 505
573        MISCREG_TLBI_VAE2_Xt,           // 506
574        MISCREG_TLBI_ALLE1,             // 507
575        MISCREG_TLBI_VALE2_Xt,          // 508
576        MISCREG_TLBI_VMALLS12E1,        // 509
577        MISCREG_TLBI_ALLE3IS,           // 510
578        MISCREG_TLBI_VAE3IS_Xt,         // 511
579        MISCREG_TLBI_VALE3IS_Xt,        // 512
580        MISCREG_TLBI_ALLE3,             // 513
581        MISCREG_TLBI_VAE3_Xt,           // 514
582        MISCREG_TLBI_VALE3_Xt,          // 515
583        MISCREG_PMINTENSET_EL1,         // 516
584        MISCREG_PMINTENCLR_EL1,         // 517
585        MISCREG_PMCR_EL0,               // 518
586        MISCREG_PMCNTENSET_EL0,         // 519
587        MISCREG_PMCNTENCLR_EL0,         // 520
588        MISCREG_PMOVSCLR_EL0,           // 521
589        MISCREG_PMSWINC_EL0,            // 522
590        MISCREG_PMSELR_EL0,             // 523
591        MISCREG_PMCEID0_EL0,            // 524
592        MISCREG_PMCEID1_EL0,            // 525
593        MISCREG_PMCCNTR_EL0,            // 526
594        MISCREG_PMXEVTYPER_EL0,         // 527
595        MISCREG_PMCCFILTR_EL0,          // 528
596        MISCREG_PMXEVCNTR_EL0,          // 529
597        MISCREG_PMUSERENR_EL0,          // 530
598        MISCREG_PMOVSSET_EL0,           // 531
599        MISCREG_MAIR_EL1,               // 532
600        MISCREG_AMAIR_EL1,              // 533
601        MISCREG_MAIR_EL2,               // 534
602        MISCREG_AMAIR_EL2,              // 535
603        MISCREG_MAIR_EL3,               // 536
604        MISCREG_AMAIR_EL3,              // 537
605        MISCREG_L2CTLR_EL1,             // 538
606        MISCREG_L2ECTLR_EL1,            // 539
607        MISCREG_VBAR_EL1,               // 540
608        MISCREG_RVBAR_EL1,              // 541
609        MISCREG_ISR_EL1,                // 542
610        MISCREG_VBAR_EL2,               // 543
611        MISCREG_RVBAR_EL2,              // 544
612        MISCREG_VBAR_EL3,               // 545
613        MISCREG_RVBAR_EL3,              // 546
614        MISCREG_RMR_EL3,                // 547
615        MISCREG_CONTEXTIDR_EL1,         // 548
616        MISCREG_TPIDR_EL1,              // 549
617        MISCREG_TPIDR_EL0,              // 550
618        MISCREG_TPIDRRO_EL0,            // 551
619        MISCREG_TPIDR_EL2,              // 552
620        MISCREG_TPIDR_EL3,              // 553
621        MISCREG_CNTKCTL_EL1,            // 554
622        MISCREG_CNTFRQ_EL0,             // 555
623        MISCREG_CNTPCT_EL0,             // 556
624        MISCREG_CNTVCT_EL0,             // 557
625        MISCREG_CNTP_TVAL_EL0,          // 558
626        MISCREG_CNTP_CTL_EL0,           // 559
627        MISCREG_CNTP_CVAL_EL0,          // 560
628        MISCREG_CNTV_TVAL_EL0,          // 561
629        MISCREG_CNTV_CTL_EL0,           // 562
630        MISCREG_CNTV_CVAL_EL0,          // 563
631        MISCREG_PMEVCNTR0_EL0,          // 564
632        MISCREG_PMEVCNTR1_EL0,          // 565
633        MISCREG_PMEVCNTR2_EL0,          // 566
634        MISCREG_PMEVCNTR3_EL0,          // 567
635        MISCREG_PMEVCNTR4_EL0,          // 568
636        MISCREG_PMEVCNTR5_EL0,          // 569
637        MISCREG_PMEVTYPER0_EL0,         // 570
638        MISCREG_PMEVTYPER1_EL0,         // 571
639        MISCREG_PMEVTYPER2_EL0,         // 572
640        MISCREG_PMEVTYPER3_EL0,         // 573
641        MISCREG_PMEVTYPER4_EL0,         // 574
642        MISCREG_PMEVTYPER5_EL0,         // 575
643        MISCREG_CNTVOFF_EL2,            // 576
644        MISCREG_CNTHCTL_EL2,            // 577
645        MISCREG_CNTHP_TVAL_EL2,         // 578
646        MISCREG_CNTHP_CTL_EL2,          // 579
647        MISCREG_CNTHP_CVAL_EL2,         // 580
648        MISCREG_CNTPS_TVAL_EL1,         // 581
649        MISCREG_CNTPS_CTL_EL1,          // 582
650        MISCREG_CNTPS_CVAL_EL1,         // 583
651        MISCREG_IL1DATA0_EL1,           // 584
652        MISCREG_IL1DATA1_EL1,           // 585
653        MISCREG_IL1DATA2_EL1,           // 586
654        MISCREG_IL1DATA3_EL1,           // 587
655        MISCREG_DL1DATA0_EL1,           // 588
656        MISCREG_DL1DATA1_EL1,           // 589
657        MISCREG_DL1DATA2_EL1,           // 590
658        MISCREG_DL1DATA3_EL1,           // 591
659        MISCREG_DL1DATA4_EL1,           // 592
660        MISCREG_L2ACTLR_EL1,            // 593
661        MISCREG_CPUACTLR_EL1,           // 594
662        MISCREG_CPUECTLR_EL1,           // 595
663        MISCREG_CPUMERRSR_EL1,          // 596
664        MISCREG_L2MERRSR_EL1,           // 597
665        MISCREG_CBAR_EL1,               // 598
666        MISCREG_CONTEXTIDR_EL2,         // 599
667
668        // Dummy registers
669        MISCREG_NOP,                    // 600
670        MISCREG_RAZ,                    // 601
671        MISCREG_CP14_UNIMPL,            // 602
672        MISCREG_CP15_UNIMPL,            // 603
673        MISCREG_A64_UNIMPL,             // 604
674        MISCREG_UNKNOWN,                // 605
675
676        NUM_MISCREGS                    // 606
677    };
678
679    enum MiscRegInfo {
680        MISCREG_IMPLEMENTED,
681        MISCREG_UNVERIFIABLE,   // Does the value change on every read (e.g. a
682                                // arch generic counter)
683        MISCREG_WARN_NOT_FAIL,  // If MISCREG_IMPLEMENTED is deasserted, it
684                                // tells whether the instruction should raise a
685                                // warning or fail
686        MISCREG_MUTEX,  // True if the register corresponds to a pair of
687                        // mutually exclusive registers
688        MISCREG_BANKED,  // True if the register is banked between the two
689                         // security states, and this is the parent node of the
690                         // two banked registers
691        MISCREG_BANKED_CHILD, // The entry is one of the child registers that
692                              // forms a banked set of regs (along with the
693                              // other child regs)
694
695        // Access permissions
696        // User mode
697        MISCREG_USR_NS_RD,
698        MISCREG_USR_NS_WR,
699        MISCREG_USR_S_RD,
700        MISCREG_USR_S_WR,
701        // Privileged modes other than hypervisor or monitor
702        MISCREG_PRI_NS_RD,
703        MISCREG_PRI_NS_WR,
704        MISCREG_PRI_S_RD,
705        MISCREG_PRI_S_WR,
706        // Hypervisor mode
707        MISCREG_HYP_RD,
708        MISCREG_HYP_WR,
709        // Monitor mode, SCR.NS == 0
710        MISCREG_MON_NS0_RD,
711        MISCREG_MON_NS0_WR,
712        // Monitor mode, SCR.NS == 1
713        MISCREG_MON_NS1_RD,
714        MISCREG_MON_NS1_WR,
715
716        NUM_MISCREG_INFOS
717    };
718
719    extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
720
721    // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
722    MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
723                               unsigned crm, unsigned opc2);
724    MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
725                                     unsigned crn, unsigned crm,
726                                     unsigned op2);
727    // Whether a particular AArch64 system register is -always- read only.
728    bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
729
730    // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
731    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
732                               unsigned crm, unsigned opc2);
733
734    // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
735    MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
736
737
738    const char * const miscRegName[] = {
739        "cpsr",
740        "spsr",
741        "spsr_fiq",
742        "spsr_irq",
743        "spsr_svc",
744        "spsr_mon",
745        "spsr_abt",
746        "spsr_hyp",
747        "spsr_und",
748        "elr_hyp",
749        "fpsid",
750        "fpscr",
751        "mvfr1",
752        "mvfr0",
753        "fpexc",
754
755        // Helper registers
756        "cpsr_mode",
757        "cpsr_q",
758        "fpscr_exc",
759        "fpscr_qc",
760        "lockaddr",
761        "lockflag",
762        "prrr_mair0",
763        "prrr_mair0_ns",
764        "prrr_mair0_s",
765        "nmrr_mair1",
766        "nmrr_mair1_ns",
767        "nmrr_mair1_s",
768        "pmxevtyper_pmccfiltr",
769        "sctlr_rst",
770        "sev_mailbox",
771
772        // AArch32 CP14 registers
773        "dbgdidr",
774        "dbgdscrint",
775        "dbgdccint",
776        "dbgdtrtxint",
777        "dbgdtrrxint",
778        "dbgwfar",
779        "dbgvcr",
780        "dbgdtrrxext",
781        "dbgdscrext",
782        "dbgdtrtxext",
783        "dbgoseccr",
784        "dbgbvr0",
785        "dbgbvr1",
786        "dbgbvr2",
787        "dbgbvr3",
788        "dbgbvr4",
789        "dbgbvr5",
790        "dbgbcr0",
791        "dbgbcr1",
792        "dbgbcr2",
793        "dbgbcr3",
794        "dbgbcr4",
795        "dbgbcr5",
796        "dbgwvr0",
797        "dbgwvr1",
798        "dbgwvr2",
799        "dbgwvr3",
800        "dbgwcr0",
801        "dbgwcr1",
802        "dbgwcr2",
803        "dbgwcr3",
804        "dbgdrar",
805        "dbgbxvr4",
806        "dbgbxvr5",
807        "dbgoslar",
808        "dbgoslsr",
809        "dbgosdlr",
810        "dbgprcr",
811        "dbgdsar",
812        "dbgclaimset",
813        "dbgclaimclr",
814        "dbgauthstatus",
815        "dbgdevid2",
816        "dbgdevid1",
817        "dbgdevid0",
818        "teecr",
819        "jidr",
820        "teehbr",
821        "joscr",
822        "jmcr",
823
824        // AArch32 CP15 registers
825        "midr",
826        "ctr",
827        "tcmtr",
828        "tlbtr",
829        "mpidr",
830        "revidr",
831        "id_pfr0",
832        "id_pfr1",
833        "id_dfr0",
834        "id_afr0",
835        "id_mmfr0",
836        "id_mmfr1",
837        "id_mmfr2",
838        "id_mmfr3",
839        "id_isar0",
840        "id_isar1",
841        "id_isar2",
842        "id_isar3",
843        "id_isar4",
844        "id_isar5",
845        "ccsidr",
846        "clidr",
847        "aidr",
848        "csselr",
849        "csselr_ns",
850        "csselr_s",
851        "vpidr",
852        "vmpidr",
853        "sctlr",
854        "sctlr_ns",
855        "sctlr_s",
856        "actlr",
857        "actlr_ns",
858        "actlr_s",
859        "cpacr",
860        "scr",
861        "sder",
862        "nsacr",
863        "hsctlr",
864        "hactlr",
865        "hcr",
866        "hdcr",
867        "hcptr",
868        "hstr",
869        "hacr",
870        "ttbr0",
871        "ttbr0_ns",
872        "ttbr0_s",
873        "ttbr1",
874        "ttbr1_ns",
875        "ttbr1_s",
876        "ttbcr",
877        "ttbcr_ns",
878        "ttbcr_s",
879        "htcr",
880        "vtcr",
881        "dacr",
882        "dacr_ns",
883        "dacr_s",
884        "dfsr",
885        "dfsr_ns",
886        "dfsr_s",
887        "ifsr",
888        "ifsr_ns",
889        "ifsr_s",
890        "adfsr",
891        "adfsr_ns",
892        "adfsr_s",
893        "aifsr",
894        "aifsr_ns",
895        "aifsr_s",
896        "hadfsr",
897        "haifsr",
898        "hsr",
899        "dfar",
900        "dfar_ns",
901        "dfar_s",
902        "ifar",
903        "ifar_ns",
904        "ifar_s",
905        "hdfar",
906        "hifar",
907        "hpfar",
908        "icialluis",
909        "bpiallis",
910        "par",
911        "par_ns",
912        "par_s",
913        "iciallu",
914        "icimvau",
915        "cp15isb",
916        "bpiall",
917        "bpimva",
918        "dcimvac",
919        "dcisw",
920        "ats1cpr",
921        "ats1cpw",
922        "ats1cur",
923        "ats1cuw",
924        "ats12nsopr",
925        "ats12nsopw",
926        "ats12nsour",
927        "ats12nsouw",
928        "dccmvac",
929        "dccsw",
930        "cp15dsb",
931        "cp15dmb",
932        "dccmvau",
933        "dccimvac",
934        "dccisw",
935        "ats1hr",
936        "ats1hw",
937        "tlbiallis",
938        "tlbimvais",
939        "tlbiasidis",
940        "tlbimvaais",
941        "tlbimvalis",
942        "tlbimvaalis",
943        "itlbiall",
944        "itlbimva",
945        "itlbiasid",
946        "dtlbiall",
947        "dtlbimva",
948        "dtlbiasid",
949        "tlbiall",
950        "tlbimva",
951        "tlbiasid",
952        "tlbimvaa",
953        "tlbimval",
954        "tlbimvaal",
955        "tlbiipas2is",
956        "tlbiipas2lis",
957        "tlbiallhis",
958        "tlbimvahis",
959        "tlbiallnsnhis",
960        "tlbimvalhis",
961        "tlbiipas2",
962        "tlbiipas2l",
963        "tlbiallh",
964        "tlbimvah",
965        "tlbiallnsnh",
966        "tlbimvalh",
967        "pmcr",
968        "pmcntenset",
969        "pmcntenclr",
970        "pmovsr",
971        "pmswinc",
972        "pmselr",
973        "pmceid0",
974        "pmceid1",
975        "pmccntr",
976        "pmxevtyper",
977        "pmccfiltr",
978        "pmxevcntr",
979        "pmuserenr",
980        "pmintenset",
981        "pmintenclr",
982        "pmovsset",
983        "l2ctlr",
984        "l2ectlr",
985        "prrr",
986        "prrr_ns",
987        "prrr_s",
988        "mair0",
989        "mair0_ns",
990        "mair0_s",
991        "nmrr",
992        "nmrr_ns",
993        "nmrr_s",
994        "mair1",
995        "mair1_ns",
996        "mair1_s",
997        "amair0",
998        "amair0_ns",
999        "amair0_s",
1000        "amair1",
1001        "amair1_ns",
1002        "amair1_s",
1003        "hmair0",
1004        "hmair1",
1005        "hamair0",
1006        "hamair1",
1007        "vbar",
1008        "vbar_ns",
1009        "vbar_s",
1010        "mvbar",
1011        "rmr",
1012        "isr",
1013        "hvbar",
1014        "fcseidr",
1015        "contextidr",
1016        "contextidr_ns",
1017        "contextidr_s",
1018        "tpidrurw",
1019        "tpidrurw_ns",
1020        "tpidrurw_s",
1021        "tpidruro",
1022        "tpidruro_ns",
1023        "tpidruro_s",
1024        "tpidrprw",
1025        "tpidrprw_ns",
1026        "tpidrprw_s",
1027        "htpidr",
1028        "cntfrq",
1029        "cntkctl",
1030        "cntp_tval",
1031        "cntp_tval_ns",
1032        "cntp_tval_s",
1033        "cntp_ctl",
1034        "cntp_ctl_ns",
1035        "cntp_ctl_s",
1036        "cntv_tval",
1037        "cntv_ctl",
1038        "cnthctl",
1039        "cnthp_tval",
1040        "cnthp_ctl",
1041        "il1data0",
1042        "il1data1",
1043        "il1data2",
1044        "il1data3",
1045        "dl1data0",
1046        "dl1data1",
1047        "dl1data2",
1048        "dl1data3",
1049        "dl1data4",
1050        "ramindex",
1051        "l2actlr",
1052        "cbar",
1053        "httbr",
1054        "vttbr",
1055        "cntpct",
1056        "cntvct",
1057        "cntp_cval",
1058        "cntp_cval_ns",
1059        "cntp_cval_s",
1060        "cntv_cval",
1061        "cntvoff",
1062        "cnthp_cval",
1063        "cpumerrsr",
1064        "l2merrsr",
1065
1066        // AArch64 registers (Op0=2)
1067        "mdccint_el1",
1068        "osdtrrx_el1",
1069        "mdscr_el1",
1070        "osdtrtx_el1",
1071        "oseccr_el1",
1072        "dbgbvr0_el1",
1073        "dbgbvr1_el1",
1074        "dbgbvr2_el1",
1075        "dbgbvr3_el1",
1076        "dbgbvr4_el1",
1077        "dbgbvr5_el1",
1078        "dbgbcr0_el1",
1079        "dbgbcr1_el1",
1080        "dbgbcr2_el1",
1081        "dbgbcr3_el1",
1082        "dbgbcr4_el1",
1083        "dbgbcr5_el1",
1084        "dbgwvr0_el1",
1085        "dbgwvr1_el1",
1086        "dbgwvr2_el1",
1087        "dbgwvr3_el1",
1088        "dbgwcr0_el1",
1089        "dbgwcr1_el1",
1090        "dbgwcr2_el1",
1091        "dbgwcr3_el1",
1092        "mdccsr_el0",
1093        "mddtr_el0",
1094        "mddtrtx_el0",
1095        "mddtrrx_el0",
1096        "dbgvcr32_el2",
1097        "mdrar_el1",
1098        "oslar_el1",
1099        "oslsr_el1",
1100        "osdlr_el1",
1101        "dbgprcr_el1",
1102        "dbgclaimset_el1",
1103        "dbgclaimclr_el1",
1104        "dbgauthstatus_el1",
1105        "teecr32_el1",
1106        "teehbr32_el1",
1107
1108        // AArch64 registers (Op0=1,3)
1109        "midr_el1",
1110        "mpidr_el1",
1111        "revidr_el1",
1112        "id_pfr0_el1",
1113        "id_pfr1_el1",
1114        "id_dfr0_el1",
1115        "id_afr0_el1",
1116        "id_mmfr0_el1",
1117        "id_mmfr1_el1",
1118        "id_mmfr2_el1",
1119        "id_mmfr3_el1",
1120        "id_isar0_el1",
1121        "id_isar1_el1",
1122        "id_isar2_el1",
1123        "id_isar3_el1",
1124        "id_isar4_el1",
1125        "id_isar5_el1",
1126        "mvfr0_el1",
1127        "mvfr1_el1",
1128        "mvfr2_el1",
1129        "id_aa64pfr0_el1",
1130        "id_aa64pfr1_el1",
1131        "id_aa64dfr0_el1",
1132        "id_aa64dfr1_el1",
1133        "id_aa64afr0_el1",
1134        "id_aa64afr1_el1",
1135        "id_aa64isar0_el1",
1136        "id_aa64isar1_el1",
1137        "id_aa64mmfr0_el1",
1138        "id_aa64mmfr1_el1",
1139        "ccsidr_el1",
1140        "clidr_el1",
1141        "aidr_el1",
1142        "csselr_el1",
1143        "ctr_el0",
1144        "dczid_el0",
1145        "vpidr_el2",
1146        "vmpidr_el2",
1147        "sctlr_el1",
1148        "actlr_el1",
1149        "cpacr_el1",
1150        "sctlr_el2",
1151        "actlr_el2",
1152        "hcr_el2",
1153        "mdcr_el2",
1154        "cptr_el2",
1155        "hstr_el2",
1156        "hacr_el2",
1157        "sctlr_el3",
1158        "actlr_el3",
1159        "scr_el3",
1160        "sder32_el3",
1161        "cptr_el3",
1162        "mdcr_el3",
1163        "ttbr0_el1",
1164        "ttbr1_el1",
1165        "tcr_el1",
1166        "ttbr0_el2",
1167        "tcr_el2",
1168        "vttbr_el2",
1169        "vtcr_el2",
1170        "ttbr0_el3",
1171        "tcr_el3",
1172        "dacr32_el2",
1173        "spsr_el1",
1174        "elr_el1",
1175        "sp_el0",
1176        "spsel",
1177        "currentel",
1178        "nzcv",
1179        "daif",
1180        "fpcr",
1181        "fpsr",
1182        "dspsr_el0",
1183        "dlr_el0",
1184        "spsr_el2",
1185        "elr_el2",
1186        "sp_el1",
1187        "spsr_irq_aa64",
1188        "spsr_abt_aa64",
1189        "spsr_und_aa64",
1190        "spsr_fiq_aa64",
1191        "spsr_el3",
1192        "elr_el3",
1193        "sp_el2",
1194        "afsr0_el1",
1195        "afsr1_el1",
1196        "esr_el1",
1197        "ifsr32_el2",
1198        "afsr0_el2",
1199        "afsr1_el2",
1200        "esr_el2",
1201        "fpexc32_el2",
1202        "afsr0_el3",
1203        "afsr1_el3",
1204        "esr_el3",
1205        "far_el1",
1206        "far_el2",
1207        "hpfar_el2",
1208        "far_el3",
1209        "ic_ialluis",
1210        "par_el1",
1211        "ic_iallu",
1212        "dc_ivac_xt",
1213        "dc_isw_xt",
1214        "at_s1e1r_xt",
1215        "at_s1e1w_xt",
1216        "at_s1e0r_xt",
1217        "at_s1e0w_xt",
1218        "dc_csw_xt",
1219        "dc_cisw_xt",
1220        "dc_zva_xt",
1221        "ic_ivau_xt",
1222        "dc_cvac_xt",
1223        "dc_cvau_xt",
1224        "dc_civac_xt",
1225        "at_s1e2r_xt",
1226        "at_s1e2w_xt",
1227        "at_s12e1r_xt",
1228        "at_s12e1w_xt",
1229        "at_s12e0r_xt",
1230        "at_s12e0w_xt",
1231        "at_s1e3r_xt",
1232        "at_s1e3w_xt",
1233        "tlbi_vmalle1is",
1234        "tlbi_vae1is_xt",
1235        "tlbi_aside1is_xt",
1236        "tlbi_vaae1is_xt",
1237        "tlbi_vale1is_xt",
1238        "tlbi_vaale1is_xt",
1239        "tlbi_vmalle1",
1240        "tlbi_vae1_xt",
1241        "tlbi_aside1_xt",
1242        "tlbi_vaae1_xt",
1243        "tlbi_vale1_xt",
1244        "tlbi_vaale1_xt",
1245        "tlbi_ipas2e1is_xt",
1246        "tlbi_ipas2le1is_xt",
1247        "tlbi_alle2is",
1248        "tlbi_vae2is_xt",
1249        "tlbi_alle1is",
1250        "tlbi_vale2is_xt",
1251        "tlbi_vmalls12e1is",
1252        "tlbi_ipas2e1_xt",
1253        "tlbi_ipas2le1_xt",
1254        "tlbi_alle2",
1255        "tlbi_vae2_xt",
1256        "tlbi_alle1",
1257        "tlbi_vale2_xt",
1258        "tlbi_vmalls12e1",
1259        "tlbi_alle3is",
1260        "tlbi_vae3is_xt",
1261        "tlbi_vale3is_xt",
1262        "tlbi_alle3",
1263        "tlbi_vae3_xt",
1264        "tlbi_vale3_xt",
1265        "pmintenset_el1",
1266        "pmintenclr_el1",
1267        "pmcr_el0",
1268        "pmcntenset_el0",
1269        "pmcntenclr_el0",
1270        "pmovsclr_el0",
1271        "pmswinc_el0",
1272        "pmselr_el0",
1273        "pmceid0_el0",
1274        "pmceid1_el0",
1275        "pmccntr_el0",
1276        "pmxevtyper_el0",
1277        "pmccfiltr_el0",
1278        "pmxevcntr_el0",
1279        "pmuserenr_el0",
1280        "pmovsset_el0",
1281        "mair_el1",
1282        "amair_el1",
1283        "mair_el2",
1284        "amair_el2",
1285        "mair_el3",
1286        "amair_el3",
1287        "l2ctlr_el1",
1288        "l2ectlr_el1",
1289        "vbar_el1",
1290        "rvbar_el1",
1291        "isr_el1",
1292        "vbar_el2",
1293        "rvbar_el2",
1294        "vbar_el3",
1295        "rvbar_el3",
1296        "rmr_el3",
1297        "contextidr_el1",
1298        "tpidr_el1",
1299        "tpidr_el0",
1300        "tpidrro_el0",
1301        "tpidr_el2",
1302        "tpidr_el3",
1303        "cntkctl_el1",
1304        "cntfrq_el0",
1305        "cntpct_el0",
1306        "cntvct_el0",
1307        "cntp_tval_el0",
1308        "cntp_ctl_el0",
1309        "cntp_cval_el0",
1310        "cntv_tval_el0",
1311        "cntv_ctl_el0",
1312        "cntv_cval_el0",
1313        "pmevcntr0_el0",
1314        "pmevcntr1_el0",
1315        "pmevcntr2_el0",
1316        "pmevcntr3_el0",
1317        "pmevcntr4_el0",
1318        "pmevcntr5_el0",
1319        "pmevtyper0_el0",
1320        "pmevtyper1_el0",
1321        "pmevtyper2_el0",
1322        "pmevtyper3_el0",
1323        "pmevtyper4_el0",
1324        "pmevtyper5_el0",
1325        "cntvoff_el2",
1326        "cnthctl_el2",
1327        "cnthp_tval_el2",
1328        "cnthp_ctl_el2",
1329        "cnthp_cval_el2",
1330        "cntps_tval_el1",
1331        "cntps_ctl_el1",
1332        "cntps_cval_el1",
1333        "il1data0_el1",
1334        "il1data1_el1",
1335        "il1data2_el1",
1336        "il1data3_el1",
1337        "dl1data0_el1",
1338        "dl1data1_el1",
1339        "dl1data2_el1",
1340        "dl1data3_el1",
1341        "dl1data4_el1",
1342        "l2actlr_el1",
1343        "cpuactlr_el1",
1344        "cpuectlr_el1",
1345        "cpumerrsr_el1",
1346        "l2merrsr_el1",
1347        "cbar_el1",
1348        "contextidr_el2",
1349
1350        // Dummy registers
1351        "nop",
1352        "raz",
1353        "cp14_unimpl",
1354        "cp15_unimpl",
1355        "a64_unimpl",
1356        "unknown"
1357    };
1358
1359    static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1360                  "The miscRegName array and NUM_MISCREGS are inconsistent.");
1361
1362    BitUnion32(CPSR)
1363        Bitfield<31, 30> nz;
1364        Bitfield<29> c;
1365        Bitfield<28> v;
1366        Bitfield<27> q;
1367        Bitfield<26, 25> it1;
1368        Bitfield<24> j;
1369        Bitfield<23, 22> res0_23_22;
1370        Bitfield<21> ss;        // AArch64
1371        Bitfield<20> il;        // AArch64
1372        Bitfield<19, 16> ge;
1373        Bitfield<15, 10> it2;
1374        Bitfield<9> d;          // AArch64
1375        Bitfield<9> e;
1376        Bitfield<8> a;
1377        Bitfield<7> i;
1378        Bitfield<6> f;
1379        Bitfield<8, 6> aif;
1380        Bitfield<9, 6> daif;    // AArch64
1381        Bitfield<5> t;
1382        Bitfield<4> width;      // AArch64
1383        Bitfield<3, 2> el;      // AArch64
1384        Bitfield<4, 0> mode;
1385        Bitfield<0> sp;         // AArch64
1386    EndBitUnion(CPSR)
1387
1388    // This mask selects bits of the CPSR that actually go in the CondCodes
1389    // integer register to allow renaming.
1390    static const uint32_t CondCodesMask   = 0xF00F0000;
1391    static const uint32_t CpsrMaskQ       = 0x08000000;
1392
1393    BitUnion32(HDCR)
1394        Bitfield<11>   tdra;
1395        Bitfield<10>   tdosa;
1396        Bitfield<9>    tda;
1397        Bitfield<8>    tde;
1398        Bitfield<7>    hpme;
1399        Bitfield<6>    tpm;
1400        Bitfield<5>    tpmcr;
1401        Bitfield<4, 0> hpmn;
1402    EndBitUnion(HDCR)
1403
1404    BitUnion32(HCPTR)
1405        Bitfield<31> tcpac;
1406        Bitfield<20> tta;
1407        Bitfield<15> tase;
1408        Bitfield<13> tcp13;
1409        Bitfield<12> tcp12;
1410        Bitfield<11> tcp11;
1411        Bitfield<10> tcp10;
1412        Bitfield<10> tfp;  // AArch64
1413        Bitfield<9>  tcp9;
1414        Bitfield<8>  tcp8;
1415        Bitfield<7>  tcp7;
1416        Bitfield<6>  tcp6;
1417        Bitfield<5>  tcp5;
1418        Bitfield<4>  tcp4;
1419        Bitfield<3>  tcp3;
1420        Bitfield<2>  tcp2;
1421        Bitfield<1>  tcp1;
1422        Bitfield<0>  tcp0;
1423    EndBitUnion(HCPTR)
1424
1425    BitUnion32(HSTR)
1426        Bitfield<17> tjdbx;
1427        Bitfield<16> ttee;
1428        Bitfield<15> t15;
1429        Bitfield<13> t13;
1430        Bitfield<12> t12;
1431        Bitfield<11> t11;
1432        Bitfield<10> t10;
1433        Bitfield<9>  t9;
1434        Bitfield<8>  t8;
1435        Bitfield<7>  t7;
1436        Bitfield<6>  t6;
1437        Bitfield<5>  t5;
1438        Bitfield<4>  t4;
1439        Bitfield<3>  t3;
1440        Bitfield<2>  t2;
1441        Bitfield<1>  t1;
1442        Bitfield<0>  t0;
1443    EndBitUnion(HSTR)
1444
1445    BitUnion64(HCR)
1446        Bitfield<33>     id;    // AArch64
1447        Bitfield<32>     cd;    // AArch64
1448        Bitfield<31>     rw;    // AArch64
1449        Bitfield<30>     trvm;  // AArch64
1450        Bitfield<29>     hcd;   // AArch64
1451        Bitfield<28>     tdz;   // AArch64
1452
1453        Bitfield<27>     tge;
1454        Bitfield<26>     tvm;
1455        Bitfield<25>     ttlb;
1456        Bitfield<24>     tpu;
1457        Bitfield<23>     tpc;
1458        Bitfield<22>     tsw;
1459        Bitfield<21>     tac;
1460        Bitfield<21>     tacr;  // AArch64
1461        Bitfield<20>     tidcp;
1462        Bitfield<19>     tsc;
1463        Bitfield<18>     tid3;
1464        Bitfield<17>     tid2;
1465        Bitfield<16>     tid1;
1466        Bitfield<15>     tid0;
1467        Bitfield<14>     twe;
1468        Bitfield<13>     twi;
1469        Bitfield<12>     dc;
1470        Bitfield<11, 10> bsu;
1471        Bitfield<9>      fb;
1472        Bitfield<8>      va;
1473        Bitfield<8>      vse;   // AArch64
1474        Bitfield<7>      vi;
1475        Bitfield<6>      vf;
1476        Bitfield<5>      amo;
1477        Bitfield<4>      imo;
1478        Bitfield<3>      fmo;
1479        Bitfield<2>      ptw;
1480        Bitfield<1>      swio;
1481        Bitfield<0>      vm;
1482    EndBitUnion(HCR)
1483
1484    BitUnion32(NSACR)
1485        Bitfield<20> nstrcdis;
1486        Bitfield<19> rfr;
1487        Bitfield<15> nsasedis;
1488        Bitfield<14> nsd32dis;
1489        Bitfield<13> cp13;
1490        Bitfield<12> cp12;
1491        Bitfield<11> cp11;
1492        Bitfield<10> cp10;
1493        Bitfield<9>  cp9;
1494        Bitfield<8>  cp8;
1495        Bitfield<7>  cp7;
1496        Bitfield<6>  cp6;
1497        Bitfield<5>  cp5;
1498        Bitfield<4>  cp4;
1499        Bitfield<3>  cp3;
1500        Bitfield<2>  cp2;
1501        Bitfield<1>  cp1;
1502        Bitfield<0>  cp0;
1503    EndBitUnion(NSACR)
1504
1505    BitUnion32(SCR)
1506        Bitfield<13> twe;
1507        Bitfield<12> twi;
1508        Bitfield<11> st;  // AArch64
1509        Bitfield<10> rw;  // AArch64
1510        Bitfield<9> sif;
1511        Bitfield<8> hce;
1512        Bitfield<7> scd;
1513        Bitfield<7> smd;  // AArch64
1514        Bitfield<6> nEt;
1515        Bitfield<5> aw;
1516        Bitfield<4> fw;
1517        Bitfield<3> ea;
1518        Bitfield<2> fiq;
1519        Bitfield<1> irq;
1520        Bitfield<0> ns;
1521    EndBitUnion(SCR)
1522
1523    BitUnion32(SCTLR)
1524        Bitfield<30>   te;      // Thumb Exception Enable (AArch32 only)
1525        Bitfield<29>   afe;     // Access flag enable (AArch32 only)
1526        Bitfield<28>   tre;     // TEX remap enable (AArch32 only)
1527        Bitfield<27>   nmfi;    // Non-maskable FIQ support (ARMv7 only)
1528        Bitfield<26>   uci;     // Enable EL0 access to DC CVAU, DC CIVAC,
1529                                // DC CVAC and IC IVAU instructions
1530                                // (AArch64 SCTLR_EL1 only)
1531        Bitfield<25>   ee;      // Exception Endianness
1532        Bitfield<24>   ve;      // Interrupt Vectors Enable (ARMv7 only)
1533        Bitfield<24>   e0e;     // Endianness of explicit data accesses at EL0
1534                                // (AArch64 SCTLR_EL1 only)
1535        Bitfield<23>   xp;      // Extended page table enable (dropped in ARMv7)
1536        Bitfield<22>   u;       // Alignment (dropped in ARMv7)
1537        Bitfield<21>   fi;      // Fast interrupts configuration enable
1538                                // (ARMv7 only)
1539        Bitfield<20>   uwxn;    // Unprivileged write permission implies EL1 XN
1540                                // (AArch32 only)
1541        Bitfield<19>   dz;      // Divide by Zero fault enable
1542                                // (dropped in ARMv7)
1543        Bitfield<19>   wxn;     // Write permission implies XN
1544        Bitfield<18>   ntwe;    // Not trap WFE
1545                                // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1546        Bitfield<18>   rao2;    // Read as one
1547        Bitfield<16>   ntwi;    // Not trap WFI
1548                                // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1549        Bitfield<16>   rao3;    // Read as one
1550        Bitfield<15>   uct;     // Enable EL0 access to CTR_EL0
1551                                // (AArch64 SCTLR_EL1 only)
1552        Bitfield<14>   rr;      // Round Robin select (ARMv7 only)
1553        Bitfield<14>   dze;     // Enable EL0 access to DC ZVA
1554                                // (AArch64 SCTLR_EL1 only)
1555        Bitfield<13>   v;       // Vectors bit (AArch32 only)
1556        Bitfield<12>   i;       // Instruction cache enable
1557        Bitfield<11>   z;       // Branch prediction enable (ARMv7 only)
1558        Bitfield<10>   sw;      // SWP/SWPB enable (ARMv7 only)
1559        Bitfield<9, 8> rs;      // Deprecated protection bits (dropped in ARMv7)
1560        Bitfield<9>    uma;     // User mask access (AArch64 SCTLR_EL1 only)
1561        Bitfield<8>    sed;     // SETEND disable
1562                                // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1563        Bitfield<7>    b;       // Endianness support (dropped in ARMv7)
1564        Bitfield<7>    itd;     // IT disable
1565                                // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1566        Bitfield<6, 3> rao4;    // Read as one
1567        Bitfield<6>    thee;    // ThumbEE enable
1568                                // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1569        Bitfield<5>    cp15ben; // CP15 barrier enable
1570                                // (AArch32 and AArch64 SCTLR_EL1 only)
1571        Bitfield<4>    sa0;     // Stack Alignment Check Enable for EL0
1572                                // (AArch64 SCTLR_EL1 only)
1573        Bitfield<3>    sa;      // Stack Alignment Check Enable (AArch64 only)
1574        Bitfield<2>    c;       // Cache enable
1575        Bitfield<1>    a;       // Alignment check enable
1576        Bitfield<0>    m;       // MMU enable
1577    EndBitUnion(SCTLR)
1578
1579    BitUnion32(CPACR)
1580        Bitfield<1, 0> cp0;
1581        Bitfield<3, 2> cp1;
1582        Bitfield<5, 4> cp2;
1583        Bitfield<7, 6> cp3;
1584        Bitfield<9, 8> cp4;
1585        Bitfield<11, 10> cp5;
1586        Bitfield<13, 12> cp6;
1587        Bitfield<15, 14> cp7;
1588        Bitfield<17, 16> cp8;
1589        Bitfield<19, 18> cp9;
1590        Bitfield<21, 20> cp10;
1591        Bitfield<21, 20> fpen;  // AArch64
1592        Bitfield<23, 22> cp11;
1593        Bitfield<25, 24> cp12;
1594        Bitfield<27, 26> cp13;
1595        Bitfield<29, 28> rsvd;
1596        Bitfield<28> tta;  // AArch64
1597        Bitfield<30> d32dis;
1598        Bitfield<31> asedis;
1599    EndBitUnion(CPACR)
1600
1601    BitUnion32(FSR)
1602        Bitfield<3, 0> fsLow;
1603        Bitfield<5, 0> status;  // LPAE
1604        Bitfield<7, 4> domain;
1605        Bitfield<9> lpae;
1606        Bitfield<10> fsHigh;
1607        Bitfield<11> wnr;
1608        Bitfield<12> ext;
1609        Bitfield<13> cm;  // LPAE
1610    EndBitUnion(FSR)
1611
1612    BitUnion32(FPSCR)
1613        Bitfield<0> ioc;
1614        Bitfield<1> dzc;
1615        Bitfield<2> ofc;
1616        Bitfield<3> ufc;
1617        Bitfield<4> ixc;
1618        Bitfield<7> idc;
1619        Bitfield<8> ioe;
1620        Bitfield<9> dze;
1621        Bitfield<10> ofe;
1622        Bitfield<11> ufe;
1623        Bitfield<12> ixe;
1624        Bitfield<15> ide;
1625        Bitfield<18, 16> len;
1626        Bitfield<21, 20> stride;
1627        Bitfield<23, 22> rMode;
1628        Bitfield<24> fz;
1629        Bitfield<25> dn;
1630        Bitfield<26> ahp;
1631        Bitfield<27> qc;
1632        Bitfield<28> v;
1633        Bitfield<29> c;
1634        Bitfield<30> z;
1635        Bitfield<31> n;
1636    EndBitUnion(FPSCR)
1637
1638    // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1639    // integer register to allow renaming.
1640    static const uint32_t FpCondCodesMask = 0xF0000000;
1641    // This mask selects the cumulative FP exception flags of the FPSCR.
1642    static const uint32_t FpscrExcMask = 0x0000009F;
1643    // This mask selects the cumulative saturation flag of the FPSCR.
1644    static const uint32_t FpscrQcMask = 0x08000000;
1645
1646    BitUnion32(FPEXC)
1647        Bitfield<31> ex;
1648        Bitfield<30> en;
1649        Bitfield<29, 0> subArchDefined;
1650    EndBitUnion(FPEXC)
1651
1652    BitUnion32(MVFR0)
1653        Bitfield<3, 0> advSimdRegisters;
1654        Bitfield<7, 4> singlePrecision;
1655        Bitfield<11, 8> doublePrecision;
1656        Bitfield<15, 12> vfpExceptionTrapping;
1657        Bitfield<19, 16> divide;
1658        Bitfield<23, 20> squareRoot;
1659        Bitfield<27, 24> shortVectors;
1660        Bitfield<31, 28> roundingModes;
1661    EndBitUnion(MVFR0)
1662
1663    BitUnion32(MVFR1)
1664        Bitfield<3, 0> flushToZero;
1665        Bitfield<7, 4> defaultNaN;
1666        Bitfield<11, 8> advSimdLoadStore;
1667        Bitfield<15, 12> advSimdInteger;
1668        Bitfield<19, 16> advSimdSinglePrecision;
1669        Bitfield<23, 20> advSimdHalfPrecision;
1670        Bitfield<27, 24> vfpHalfPrecision;
1671        Bitfield<31, 28> raz;
1672    EndBitUnion(MVFR1)
1673
1674    BitUnion64(TTBCR)
1675        // Short-descriptor translation table format
1676        Bitfield<2, 0> n;
1677        Bitfield<4> pd0;
1678        Bitfield<5> pd1;
1679        // Long-descriptor translation table format
1680        Bitfield<5, 0> t0sz;
1681        Bitfield<7> epd0;
1682        Bitfield<9, 8> irgn0;
1683        Bitfield<11, 10> orgn0;
1684        Bitfield<13, 12> sh0;
1685        Bitfield<14> tg0;
1686        Bitfield<21, 16> t1sz;
1687        Bitfield<22> a1;
1688        Bitfield<23> epd1;
1689        Bitfield<25, 24> irgn1;
1690        Bitfield<27, 26> orgn1;
1691        Bitfield<29, 28> sh1;
1692        Bitfield<30> tg1;
1693        Bitfield<34, 32> ips;
1694        Bitfield<36> as;
1695        Bitfield<37> tbi0;
1696        Bitfield<38> tbi1;
1697        // Common
1698        Bitfield<31> eae;
1699        // TCR_EL2/3 (AArch64)
1700        Bitfield<18, 16> ps;
1701        Bitfield<20> tbi;
1702    EndBitUnion(TTBCR)
1703
1704    // Fields of TCR_EL{1,2,3} (mostly overlapping)
1705    // TCR_EL1 is natively 64 bits, the others are 32 bits
1706    BitUnion64(TCR)
1707        Bitfield<5, 0> t0sz;
1708        Bitfield<7> epd0; // EL1
1709        Bitfield<9, 8> irgn0;
1710        Bitfield<11, 10> orgn0;
1711        Bitfield<13, 12> sh0;
1712        Bitfield<15, 14> tg0;
1713        Bitfield<18, 16> ps;
1714        Bitfield<20> tbi; // EL2/EL3
1715        Bitfield<21, 16> t1sz; // EL1
1716        Bitfield<22> a1; // EL1
1717        Bitfield<23> epd1; // EL1
1718        Bitfield<25, 24> irgn1; // EL1
1719        Bitfield<27, 26> orgn1; // EL1
1720        Bitfield<29, 28> sh1; // EL1
1721        Bitfield<31, 30> tg1; // EL1
1722        Bitfield<34, 32> ips; // EL1
1723        Bitfield<36> as; // EL1
1724        Bitfield<37> tbi0; // EL1
1725        Bitfield<38> tbi1; // EL1
1726    EndBitUnion(TCR)
1727
1728    BitUnion32(HTCR)
1729        Bitfield<2, 0> t0sz;
1730        Bitfield<9, 8> irgn0;
1731        Bitfield<11, 10> orgn0;
1732        Bitfield<13, 12> sh0;
1733    EndBitUnion(HTCR)
1734
1735    BitUnion32(VTCR_t)
1736        Bitfield<3, 0> t0sz;
1737        Bitfield<4> s;
1738        Bitfield<7, 6> sl0;
1739        Bitfield<9, 8> irgn0;
1740        Bitfield<11, 10> orgn0;
1741        Bitfield<13, 12> sh0;
1742    EndBitUnion(VTCR_t)
1743
1744    BitUnion32(PRRR)
1745       Bitfield<1,0> tr0;
1746       Bitfield<3,2> tr1;
1747       Bitfield<5,4> tr2;
1748       Bitfield<7,6> tr3;
1749       Bitfield<9,8> tr4;
1750       Bitfield<11,10> tr5;
1751       Bitfield<13,12> tr6;
1752       Bitfield<15,14> tr7;
1753       Bitfield<16> ds0;
1754       Bitfield<17> ds1;
1755       Bitfield<18> ns0;
1756       Bitfield<19> ns1;
1757       Bitfield<24> nos0;
1758       Bitfield<25> nos1;
1759       Bitfield<26> nos2;
1760       Bitfield<27> nos3;
1761       Bitfield<28> nos4;
1762       Bitfield<29> nos5;
1763       Bitfield<30> nos6;
1764       Bitfield<31> nos7;
1765   EndBitUnion(PRRR)
1766
1767   BitUnion32(NMRR)
1768       Bitfield<1,0> ir0;
1769       Bitfield<3,2> ir1;
1770       Bitfield<5,4> ir2;
1771       Bitfield<7,6> ir3;
1772       Bitfield<9,8> ir4;
1773       Bitfield<11,10> ir5;
1774       Bitfield<13,12> ir6;
1775       Bitfield<15,14> ir7;
1776       Bitfield<17,16> or0;
1777       Bitfield<19,18> or1;
1778       Bitfield<21,20> or2;
1779       Bitfield<23,22> or3;
1780       Bitfield<25,24> or4;
1781       Bitfield<27,26> or5;
1782       Bitfield<29,28> or6;
1783       Bitfield<31,30> or7;
1784   EndBitUnion(NMRR)
1785
1786   BitUnion32(CONTEXTIDR)
1787      Bitfield<7,0>  asid;
1788      Bitfield<31,8> procid;
1789   EndBitUnion(CONTEXTIDR)
1790
1791   BitUnion32(L2CTLR)
1792      Bitfield<2,0>   sataRAMLatency;
1793      Bitfield<4,3>   reserved_4_3;
1794      Bitfield<5>     dataRAMSetup;
1795      Bitfield<8,6>   tagRAMLatency;
1796      Bitfield<9>     tagRAMSetup;
1797      Bitfield<11,10> dataRAMSlice;
1798      Bitfield<12>    tagRAMSlice;
1799      Bitfield<20,13> reserved_20_13;
1800      Bitfield<21>    eccandParityEnable;
1801      Bitfield<22>    reserved_22;
1802      Bitfield<23>    interptCtrlPresent;
1803      Bitfield<25,24> numCPUs;
1804      Bitfield<30,26> reserved_30_26;
1805      Bitfield<31>    l2rstDISABLE_monitor;
1806   EndBitUnion(L2CTLR)
1807
1808   BitUnion32(CTR)
1809      Bitfield<3,0>   iCacheLineSize;
1810      Bitfield<13,4>  raz_13_4;
1811      Bitfield<15,14> l1IndexPolicy;
1812      Bitfield<19,16> dCacheLineSize;
1813      Bitfield<23,20> erg;
1814      Bitfield<27,24> cwg;
1815      Bitfield<28>    raz_28;
1816      Bitfield<31,29> format;
1817   EndBitUnion(CTR)
1818
1819   BitUnion32(PMSELR)
1820      Bitfield<4, 0> sel;
1821   EndBitUnion(PMSELR)
1822
1823    BitUnion64(PAR)
1824        // 64-bit format
1825        Bitfield<63, 56> attr;
1826        Bitfield<39, 12> pa;
1827        Bitfield<11>     lpae;
1828        Bitfield<9>      ns;
1829        Bitfield<8, 7>   sh;
1830        Bitfield<0>      f;
1831   EndBitUnion(PAR)
1832
1833   BitUnion32(ESR)
1834        Bitfield<31, 26> ec;
1835        Bitfield<25> il;
1836        Bitfield<15, 0> imm16;
1837   EndBitUnion(ESR)
1838
1839   BitUnion32(CPTR)
1840        Bitfield<31> tcpac;
1841        Bitfield<20> tta;
1842        Bitfield<13, 12> res1_13_12_el2;
1843        Bitfield<10> tfp;
1844        Bitfield<9, 0> res1_9_0_el2;
1845   EndBitUnion(CPTR)
1846
1847
1848    // Checks read access permissions to coproc. registers
1849    bool canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1850                          ThreadContext *tc);
1851
1852    // Checks write access permissions to coproc. registers
1853    bool canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1854                           ThreadContext *tc);
1855
1856    // Checks read access permissions to AArch64 system registers
1857    bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1858                              ThreadContext *tc);
1859
1860    // Checks write access permissions to AArch64 system registers
1861    bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1862                               ThreadContext *tc);
1863
1864    // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1865    // for MCR/MRC instructions
1866    int
1867    flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc);
1868
1869    // Flattens a misc reg index using the specified security state. This is
1870    // used for opperations (eg address translations) where the security
1871    // state of the register access may differ from the current state of the
1872    // processor
1873    int
1874    flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns);
1875
1876    // Takes a misc reg index and returns the root reg if its one of a set of
1877    // banked registers
1878    void
1879    preUnflattenMiscReg();
1880
1881    int
1882    unflattenMiscReg(int reg);
1883
1884}
1885
1886#endif // __ARCH_ARM_MISCREGS_HH__
1887