miscregs.hh revision 9256
16242Sgblack@eecs.umich.edu/* 28868SMatt.Horsnell@arm.com * Copyright (c) 2010-2012 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146242Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156242Sgblack@eecs.umich.edu * All rights reserved. 166242Sgblack@eecs.umich.edu * 176242Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186242Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196242Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216242Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236242Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246242Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256242Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266242Sgblack@eecs.umich.edu * this software without specific prior written permission. 276242Sgblack@eecs.umich.edu * 286242Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296242Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306242Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316242Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326242Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336242Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346242Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356242Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366242Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376242Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386242Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396242Sgblack@eecs.umich.edu * 406242Sgblack@eecs.umich.edu * Authors: Gabe Black 416242Sgblack@eecs.umich.edu */ 426242Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MISCREGS_HH__ 436242Sgblack@eecs.umich.edu#define __ARCH_ARM_MISCREGS_HH__ 446242Sgblack@eecs.umich.edu 456242Sgblack@eecs.umich.edu#include "base/bitunion.hh" 469256SAndreas.Sandberg@arm.com#include "base/compiler.hh" 476242Sgblack@eecs.umich.edu 486242Sgblack@eecs.umich.edunamespace ArmISA 496242Sgblack@eecs.umich.edu{ 506242Sgblack@eecs.umich.edu enum ConditionCode { 516242Sgblack@eecs.umich.edu COND_EQ = 0, 526242Sgblack@eecs.umich.edu COND_NE, // 1 536242Sgblack@eecs.umich.edu COND_CS, // 2 546242Sgblack@eecs.umich.edu COND_CC, // 3 556242Sgblack@eecs.umich.edu COND_MI, // 4 566242Sgblack@eecs.umich.edu COND_PL, // 5 576242Sgblack@eecs.umich.edu COND_VS, // 6 586242Sgblack@eecs.umich.edu COND_VC, // 7 596242Sgblack@eecs.umich.edu COND_HI, // 8 606242Sgblack@eecs.umich.edu COND_LS, // 9 616242Sgblack@eecs.umich.edu COND_GE, // 10 626242Sgblack@eecs.umich.edu COND_LT, // 11 636242Sgblack@eecs.umich.edu COND_GT, // 12 646242Sgblack@eecs.umich.edu COND_LE, // 13 656242Sgblack@eecs.umich.edu COND_AL, // 14 667111Sgblack@eecs.umich.edu COND_UC // 15 676242Sgblack@eecs.umich.edu }; 686242Sgblack@eecs.umich.edu 696242Sgblack@eecs.umich.edu enum MiscRegIndex { 706242Sgblack@eecs.umich.edu MISCREG_CPSR = 0, 718302SAli.Saidi@ARM.com MISCREG_CPSR_Q, 726735Sgblack@eecs.umich.edu MISCREG_SPSR, 736242Sgblack@eecs.umich.edu MISCREG_SPSR_FIQ, 746242Sgblack@eecs.umich.edu MISCREG_SPSR_IRQ, 756242Sgblack@eecs.umich.edu MISCREG_SPSR_SVC, 766723Sgblack@eecs.umich.edu MISCREG_SPSR_MON, 776242Sgblack@eecs.umich.edu MISCREG_SPSR_UND, 786242Sgblack@eecs.umich.edu MISCREG_SPSR_ABT, 796261Sgblack@eecs.umich.edu MISCREG_FPSR, 806403Sgblack@eecs.umich.edu MISCREG_FPSID, 816403Sgblack@eecs.umich.edu MISCREG_FPSCR, 827783SGiacomo.Gabrielli@arm.com MISCREG_FPSCR_QC, // Cumulative saturation flag 837783SGiacomo.Gabrielli@arm.com MISCREG_FPSCR_EXC, // Cumulative FP exception flags 846403Sgblack@eecs.umich.edu MISCREG_FPEXC, 857325Sgblack@eecs.umich.edu MISCREG_MVFR0, 867325Sgblack@eecs.umich.edu MISCREG_MVFR1, 877400SAli.Saidi@ARM.com MISCREG_SCTLR_RST, 887350SAli.Saidi@ARM.com MISCREG_SEV_MAILBOX, 897259Sgblack@eecs.umich.edu 908868SMatt.Horsnell@arm.com // CP14 registers 918868SMatt.Horsnell@arm.com MISCREG_CP14_START, 928868SMatt.Horsnell@arm.com MISCREG_DBGDIDR = MISCREG_CP14_START, 938868SMatt.Horsnell@arm.com MISCREG_DBGDSCR_INT, 948868SMatt.Horsnell@arm.com MISCREG_DBGDTRRX_INT, 958868SMatt.Horsnell@arm.com MISCREG_DBGTRTX_INT, 968868SMatt.Horsnell@arm.com MISCREG_DBGWFAR, 978868SMatt.Horsnell@arm.com MISCREG_DBGVCR, 988868SMatt.Horsnell@arm.com MISCREG_DBGECR, 998868SMatt.Horsnell@arm.com MISCREG_DBGDSCCR, 1008868SMatt.Horsnell@arm.com MISCREG_DBGSMCR, 1018868SMatt.Horsnell@arm.com MISCREG_DBGDTRRX_EXT, 1028868SMatt.Horsnell@arm.com MISCREG_DBGDSCR_EXT, 1038868SMatt.Horsnell@arm.com MISCREG_DBGDTRTX_EXT, 1048868SMatt.Horsnell@arm.com MISCREG_DBGDRCR, 1058868SMatt.Horsnell@arm.com MISCREG_DBGBVR, 1068868SMatt.Horsnell@arm.com MISCREG_DBGBCR, 1078868SMatt.Horsnell@arm.com MISCREG_DBGBVR_M, 1088868SMatt.Horsnell@arm.com MISCREG_DBGBCR_M, 1098868SMatt.Horsnell@arm.com MISCREG_DBGDRAR, 1108868SMatt.Horsnell@arm.com MISCREG_DBGBXVR_M, 1118868SMatt.Horsnell@arm.com MISCREG_DBGOSLAR, 1128868SMatt.Horsnell@arm.com MISCREG_DBGOSSRR, 1138868SMatt.Horsnell@arm.com MISCREG_DBGOSDLR, 1148868SMatt.Horsnell@arm.com MISCREG_DBGPRCR, 1158868SMatt.Horsnell@arm.com MISCREG_DBGPRSR, 1168868SMatt.Horsnell@arm.com MISCREG_DBGDSAR, 1178868SMatt.Horsnell@arm.com MISCREG_DBGITCTRL, 1188868SMatt.Horsnell@arm.com MISCREG_DBGCLAIMSET, 1198868SMatt.Horsnell@arm.com MISCREG_DBGCLAIMCLR, 1208868SMatt.Horsnell@arm.com MISCREG_DBGAUTHSTATUS, 1218868SMatt.Horsnell@arm.com MISCREG_DBGDEVID2, 1228868SMatt.Horsnell@arm.com MISCREG_DBGDEVID1, 1238868SMatt.Horsnell@arm.com MISCREG_DBGDEVID, 1248868SMatt.Horsnell@arm.com 1257259Sgblack@eecs.umich.edu // CP15 registers 1267259Sgblack@eecs.umich.edu MISCREG_CP15_START, 1277259Sgblack@eecs.umich.edu MISCREG_SCTLR = MISCREG_CP15_START, 1287264Sgblack@eecs.umich.edu MISCREG_DCCISW, 1297267Sgblack@eecs.umich.edu MISCREG_DCCIMVAC, 1307285Sgblack@eecs.umich.edu MISCREG_DCCMVAC, 1317265Sgblack@eecs.umich.edu MISCREG_CONTEXTIDR, 1327266Sgblack@eecs.umich.edu MISCREG_TPIDRURW, 1337266Sgblack@eecs.umich.edu MISCREG_TPIDRURO, 1347266Sgblack@eecs.umich.edu MISCREG_TPIDRPRW, 1357268Sgblack@eecs.umich.edu MISCREG_CP15ISB, 1367272Sgblack@eecs.umich.edu MISCREG_CP15DSB, 1377272Sgblack@eecs.umich.edu MISCREG_CP15DMB, 1387271Sgblack@eecs.umich.edu MISCREG_CPACR, 1397273Sgblack@eecs.umich.edu MISCREG_CLIDR, 1407287Sgblack@eecs.umich.edu MISCREG_CCSIDR, 1417287Sgblack@eecs.umich.edu MISCREG_CSSELR, 1427274Sgblack@eecs.umich.edu MISCREG_ICIALLUIS, 1437275Sgblack@eecs.umich.edu MISCREG_ICIALLU, 1447276Sgblack@eecs.umich.edu MISCREG_ICIMVAU, 1457286Sgblack@eecs.umich.edu MISCREG_BPIMVA, 1467297Sgblack@eecs.umich.edu MISCREG_BPIALLIS, 1477297Sgblack@eecs.umich.edu MISCREG_BPIALL, 1487298Sgblack@eecs.umich.edu MISCREG_MIDR, 1497352Sgblack@eecs.umich.edu MISCREG_TTBR0, 1507352Sgblack@eecs.umich.edu MISCREG_TTBR1, 1517354Sgblack@eecs.umich.edu MISCREG_TLBTR, 1527353Sgblack@eecs.umich.edu MISCREG_DACR, 1537355Sgblack@eecs.umich.edu MISCREG_TLBIALLIS, 1547355Sgblack@eecs.umich.edu MISCREG_TLBIMVAIS, 1557355Sgblack@eecs.umich.edu MISCREG_TLBIASIDIS, 1567355Sgblack@eecs.umich.edu MISCREG_TLBIMVAAIS, 1577355Sgblack@eecs.umich.edu MISCREG_ITLBIALL, 1587355Sgblack@eecs.umich.edu MISCREG_ITLBIMVA, 1597355Sgblack@eecs.umich.edu MISCREG_ITLBIASID, 1607355Sgblack@eecs.umich.edu MISCREG_DTLBIALL, 1617355Sgblack@eecs.umich.edu MISCREG_DTLBIMVA, 1627355Sgblack@eecs.umich.edu MISCREG_DTLBIASID, 1637355Sgblack@eecs.umich.edu MISCREG_TLBIALL, 1647355Sgblack@eecs.umich.edu MISCREG_TLBIMVA, 1657355Sgblack@eecs.umich.edu MISCREG_TLBIASID, 1667355Sgblack@eecs.umich.edu MISCREG_TLBIMVAA, 1677362Sgblack@eecs.umich.edu MISCREG_DFSR, 1687362Sgblack@eecs.umich.edu MISCREG_IFSR, 1697362Sgblack@eecs.umich.edu MISCREG_DFAR, 1707362Sgblack@eecs.umich.edu MISCREG_IFAR, 1717390Sgblack@eecs.umich.edu MISCREG_MPIDR, 1727404SAli.Saidi@ARM.com MISCREG_PRRR, 1737404SAli.Saidi@ARM.com MISCREG_NMRR, 1747404SAli.Saidi@ARM.com MISCREG_TTBCR, 1757404SAli.Saidi@ARM.com MISCREG_ID_PFR0, 1767406SAli.Saidi@ARM.com MISCREG_CTR, 1777406SAli.Saidi@ARM.com MISCREG_SCR, 1787406SAli.Saidi@ARM.com MISCREG_SDER, 1797436Sdam.sunwoo@arm.com MISCREG_PAR, 1807436Sdam.sunwoo@arm.com MISCREG_V2PCWPR, 1817436Sdam.sunwoo@arm.com MISCREG_V2PCWPW, 1827436Sdam.sunwoo@arm.com MISCREG_V2PCWUR, 1837436Sdam.sunwoo@arm.com MISCREG_V2PCWUW, 1847436Sdam.sunwoo@arm.com MISCREG_V2POWPR, 1857436Sdam.sunwoo@arm.com MISCREG_V2POWPW, 1867436Sdam.sunwoo@arm.com MISCREG_V2POWUR, 1877436Sdam.sunwoo@arm.com MISCREG_V2POWUW, 1887583SAli.Saidi@arm.com MISCREG_ID_MMFR0, 1898468Swade.walker@arm.com MISCREG_ID_MMFR2, 1908284SAli.Saidi@ARM.com MISCREG_ID_MMFR3, 1917583SAli.Saidi@arm.com MISCREG_ACTLR, 1927583SAli.Saidi@arm.com MISCREG_PMCR, 1937583SAli.Saidi@arm.com MISCREG_PMCCNTR, 1947583SAli.Saidi@arm.com MISCREG_PMCNTENSET, 1957583SAli.Saidi@arm.com MISCREG_PMCNTENCLR, 1967583SAli.Saidi@arm.com MISCREG_PMOVSR, 1977583SAli.Saidi@arm.com MISCREG_PMSWINC, 1987583SAli.Saidi@arm.com MISCREG_PMSELR, 1997583SAli.Saidi@arm.com MISCREG_PMCEID0, 2007583SAli.Saidi@arm.com MISCREG_PMCEID1, 2017583SAli.Saidi@arm.com MISCREG_PMC_OTHER, 2027583SAli.Saidi@arm.com MISCREG_PMXEVCNTR, 2037583SAli.Saidi@arm.com MISCREG_PMUSERENR, 2047583SAli.Saidi@arm.com MISCREG_PMINTENSET, 2057583SAli.Saidi@arm.com MISCREG_PMINTENCLR, 2068147SAli.Saidi@ARM.com MISCREG_ID_ISAR0, 2078147SAli.Saidi@ARM.com MISCREG_ID_ISAR1, 2088147SAli.Saidi@ARM.com MISCREG_ID_ISAR2, 2098147SAli.Saidi@ARM.com MISCREG_ID_ISAR3, 2108147SAli.Saidi@ARM.com MISCREG_ID_ISAR4, 2118147SAli.Saidi@ARM.com MISCREG_ID_ISAR5, 2128208SAli.Saidi@ARM.com MISCREG_CPSR_MODE, 2138209SAli.Saidi@ARM.com MISCREG_LOCKFLAG, 2148209SAli.Saidi@ARM.com MISCREG_LOCKADDR, 2158299Schander.sudanthi@arm.com MISCREG_ID_PFR1, 2168549Sdaniel.johnson@arm.com MISCREG_L2CTLR, 2177259Sgblack@eecs.umich.edu MISCREG_CP15_UNIMP_START, 2187406SAli.Saidi@ARM.com MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 2197259Sgblack@eecs.umich.edu MISCREG_ID_DFR0, 2207259Sgblack@eecs.umich.edu MISCREG_ID_AFR0, 2217259Sgblack@eecs.umich.edu MISCREG_ID_MMFR1, 2227259Sgblack@eecs.umich.edu MISCREG_AIDR, 2237259Sgblack@eecs.umich.edu MISCREG_ADFSR, 2247259Sgblack@eecs.umich.edu MISCREG_AIFSR, 2257259Sgblack@eecs.umich.edu MISCREG_DCIMVAC, 2267259Sgblack@eecs.umich.edu MISCREG_DCISW, 2277259Sgblack@eecs.umich.edu MISCREG_MCCSW, 2287259Sgblack@eecs.umich.edu MISCREG_DCCMVAU, 2297351Sgblack@eecs.umich.edu MISCREG_NSACR, 2307351Sgblack@eecs.umich.edu MISCREG_VBAR, 2317351Sgblack@eecs.umich.edu MISCREG_MVBAR, 2327351Sgblack@eecs.umich.edu MISCREG_ISR, 2337351Sgblack@eecs.umich.edu MISCREG_FCEIDR, 2348058SAli.Saidi@ARM.com MISCREG_L2LATENCY, 2358550SChander.Sudanthi@ARM.com MISCREG_CRN15, 2367351Sgblack@eecs.umich.edu 2377259Sgblack@eecs.umich.edu 2387259Sgblack@eecs.umich.edu MISCREG_CP15_END, 2397259Sgblack@eecs.umich.edu 2407259Sgblack@eecs.umich.edu // Dummy indices 2417259Sgblack@eecs.umich.edu MISCREG_NOP = MISCREG_CP15_END, 2427259Sgblack@eecs.umich.edu MISCREG_RAZ, 2437259Sgblack@eecs.umich.edu 2446735Sgblack@eecs.umich.edu NUM_MISCREGS 2456261Sgblack@eecs.umich.edu }; 2466261Sgblack@eecs.umich.edu 2478868SMatt.Horsnell@arm.com MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 2488868SMatt.Horsnell@arm.com unsigned crm, unsigned opc2); 2498868SMatt.Horsnell@arm.com 2507259Sgblack@eecs.umich.edu MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 2517259Sgblack@eecs.umich.edu unsigned crm, unsigned opc2); 2527259Sgblack@eecs.umich.edu 2538868SMatt.Horsnell@arm.com 2549256SAndreas.Sandberg@arm.com const char * const miscRegName[] = { 2558302SAli.Saidi@ARM.com "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 2567259Sgblack@eecs.umich.edu "spsr_mon", "spsr_und", "spsr_abt", 2577783SGiacomo.Gabrielli@arm.com "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 2587783SGiacomo.Gabrielli@arm.com "mvfr0", "mvfr1", 2597400SAli.Saidi@ARM.com "sctlr_rst", "sev_mailbox", 2608868SMatt.Horsnell@arm.com "DBGDIDR", 2618868SMatt.Horsnell@arm.com "DBGDSCR_INT", 2628868SMatt.Horsnell@arm.com "DBGDTRRX_INT", 2638868SMatt.Horsnell@arm.com "DBGTRTX_INT", 2648868SMatt.Horsnell@arm.com "DBGWFAR", 2658868SMatt.Horsnell@arm.com "DBGVCR", 2668868SMatt.Horsnell@arm.com "DBGECR", 2678868SMatt.Horsnell@arm.com "DBGDSCCR", 2688868SMatt.Horsnell@arm.com "DBGSMCR", 2698868SMatt.Horsnell@arm.com "DBGDTRRX_EXT", 2708868SMatt.Horsnell@arm.com "DBGDSCR_EXT", 2718868SMatt.Horsnell@arm.com "DBGDTRTX_EXT", 2728868SMatt.Horsnell@arm.com "DBGDRCR", 2738868SMatt.Horsnell@arm.com "DBGBVR", 2748868SMatt.Horsnell@arm.com "DBGBCR", 2758868SMatt.Horsnell@arm.com "DBGBVR_M", 2768868SMatt.Horsnell@arm.com "DBGBCR_M", 2778868SMatt.Horsnell@arm.com "DBGDRAR", 2788868SMatt.Horsnell@arm.com "DBGBXVR_M", 2798868SMatt.Horsnell@arm.com "DBGOSLAR", 2808868SMatt.Horsnell@arm.com "DBGOSSRR", 2818868SMatt.Horsnell@arm.com "DBGOSDLR", 2828868SMatt.Horsnell@arm.com "DBGPRCR", 2838868SMatt.Horsnell@arm.com "DBGPRSR", 2848868SMatt.Horsnell@arm.com "DBGDSAR", 2858868SMatt.Horsnell@arm.com "DBGITCTRL", 2868868SMatt.Horsnell@arm.com "DBGCLAIMSET", 2878868SMatt.Horsnell@arm.com "DBGCLAIMCLR", 2888868SMatt.Horsnell@arm.com "DBGAUTHSTATUS", 2898868SMatt.Horsnell@arm.com "DBGDEVID2", 2908868SMatt.Horsnell@arm.com "DBGDEVID1", 2918868SMatt.Horsnell@arm.com "DBGDEVID", 2927285Sgblack@eecs.umich.edu "sctlr", "dccisw", "dccimvac", "dccmvac", 2937267Sgblack@eecs.umich.edu "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 2947287Sgblack@eecs.umich.edu "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 2957287Sgblack@eecs.umich.edu "clidr", "ccsidr", "csselr", 2967297Sgblack@eecs.umich.edu "icialluis", "iciallu", "icimvau", 2977297Sgblack@eecs.umich.edu "bpimva", "bpiallis", "bpiall", 2987355Sgblack@eecs.umich.edu "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 2997355Sgblack@eecs.umich.edu "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 3007355Sgblack@eecs.umich.edu "itlbiall", "itlbimva", "itlbiasid", 3017355Sgblack@eecs.umich.edu "dtlbiall", "dtlbimva", "dtlbiasid", 3027355Sgblack@eecs.umich.edu "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 3037390Sgblack@eecs.umich.edu "dfsr", "ifsr", "dfar", "ifar", "mpidr", 3047436Sdam.sunwoo@arm.com "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 3057436Sdam.sunwoo@arm.com "scr", "sder", "par", 3067436Sdam.sunwoo@arm.com "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 3077436Sdam.sunwoo@arm.com "v2powpr", "v2powpw", "v2powur", "v2powuw", 3088468Swade.walker@arm.com "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr", 3097583SAli.Saidi@arm.com "pmcntenset", "pmcntenclr", "pmovsr", 3107583SAli.Saidi@arm.com "pmswinc", "pmselr", "pmceid0", 3117583SAli.Saidi@arm.com "pmceid1", "pmc_other", "pmxevcntr", 3127583SAli.Saidi@arm.com "pmuserenr", "pmintenset", "pmintenclr", 3138147SAli.Saidi@ARM.com "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 3148299Schander.sudanthi@arm.com "cpsr_mode", "lockflag", "lockaddr", "id_pfr1", 3158549Sdaniel.johnson@arm.com "l2ctlr", 3167583SAli.Saidi@arm.com // Unimplemented below 3177406SAli.Saidi@ARM.com "tcmtr", 3188299Schander.sudanthi@arm.com "id_dfr0", "id_afr0", 3198468Swade.walker@arm.com "id_mmfr1", 3208147SAli.Saidi@ARM.com "aidr", "adfsr", "aifsr", 3217297Sgblack@eecs.umich.edu "dcimvac", "dcisw", "mccsw", 3227272Sgblack@eecs.umich.edu "dccmvau", 3237406SAli.Saidi@ARM.com "nsacr", 3248179Sgblack@eecs.umich.edu "vbar", "mvbar", "isr", "fceidr", "l2latency", 3258550SChander.Sudanthi@ARM.com "crn15", 3267259Sgblack@eecs.umich.edu "nop", "raz" 3276242Sgblack@eecs.umich.edu }; 3286242Sgblack@eecs.umich.edu 3299256SAndreas.Sandberg@arm.com static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 3309256SAndreas.Sandberg@arm.com "The miscRegName array and NUM_MISCREGS are inconsistent."); 3319256SAndreas.Sandberg@arm.com 3326242Sgblack@eecs.umich.edu BitUnion32(CPSR) 3338303SAli.Saidi@ARM.com Bitfield<31,30> nz; 3346242Sgblack@eecs.umich.edu Bitfield<29> c; 3356242Sgblack@eecs.umich.edu Bitfield<28> v; 3366242Sgblack@eecs.umich.edu Bitfield<27> q; 3376735Sgblack@eecs.umich.edu Bitfield<26,25> it1; 3386242Sgblack@eecs.umich.edu Bitfield<24> j; 3396242Sgblack@eecs.umich.edu Bitfield<19, 16> ge; 3406735Sgblack@eecs.umich.edu Bitfield<15,10> it2; 3416242Sgblack@eecs.umich.edu Bitfield<9> e; 3426242Sgblack@eecs.umich.edu Bitfield<8> a; 3436242Sgblack@eecs.umich.edu Bitfield<7> i; 3446242Sgblack@eecs.umich.edu Bitfield<6> f; 3456242Sgblack@eecs.umich.edu Bitfield<5> t; 3466242Sgblack@eecs.umich.edu Bitfield<4, 0> mode; 3476242Sgblack@eecs.umich.edu EndBitUnion(CPSR) 3486735Sgblack@eecs.umich.edu 3496750Sgblack@eecs.umich.edu // This mask selects bits of the CPSR that actually go in the CondCodes 3506750Sgblack@eecs.umich.edu // integer register to allow renaming. 3518302SAli.Saidi@ARM.com static const uint32_t CondCodesMask = 0xF00F0000; 3528302SAli.Saidi@ARM.com static const uint32_t CpsrMaskQ = 0x08000000; 3536750Sgblack@eecs.umich.edu 3546735Sgblack@eecs.umich.edu BitUnion32(SCTLR) 3557360Sgblack@eecs.umich.edu Bitfield<31> ie; // Instruction endianness 3566735Sgblack@eecs.umich.edu Bitfield<30> te; // Thumb Exception Enable 3576735Sgblack@eecs.umich.edu Bitfield<29> afe; // Access flag enable 3589051Schander.sudanthi@arm.com Bitfield<28> tre; // TEX Remap bit 3596735Sgblack@eecs.umich.edu Bitfield<27> nmfi;// Non-maskable fast interrupts enable 3606735Sgblack@eecs.umich.edu Bitfield<25> ee; // Exception Endianness bit 3616735Sgblack@eecs.umich.edu Bitfield<24> ve; // Interrupt vectors enable 3627406SAli.Saidi@ARM.com Bitfield<23> xp; // Extended page table enable bit 3636735Sgblack@eecs.umich.edu Bitfield<22> u; // Alignment (now unused) 3646735Sgblack@eecs.umich.edu Bitfield<21> fi; // Fast interrupts configuration enable 3657360Sgblack@eecs.umich.edu Bitfield<19> dz; // Divide by Zero fault enable bit 3666735Sgblack@eecs.umich.edu Bitfield<18> rao2;// Read as one 3677360Sgblack@eecs.umich.edu Bitfield<17> br; // Background region bit 3686735Sgblack@eecs.umich.edu Bitfield<16> rao3;// Read as one 3696735Sgblack@eecs.umich.edu Bitfield<14> rr; // Round robin cache replacement 3706735Sgblack@eecs.umich.edu Bitfield<13> v; // Base address for exception vectors 3716735Sgblack@eecs.umich.edu Bitfield<12> i; // instruction cache enable 3726735Sgblack@eecs.umich.edu Bitfield<11> z; // branch prediction enable bit 3736735Sgblack@eecs.umich.edu Bitfield<10> sw; // Enable swp/swpb 3747406SAli.Saidi@ARM.com Bitfield<9,8> rs; // deprecated protection bits 3756735Sgblack@eecs.umich.edu Bitfield<6,3> rao4;// Read as one 3769051Schander.sudanthi@arm.com Bitfield<7> b; // Endianness support (unused) 3776735Sgblack@eecs.umich.edu Bitfield<2> c; // Cache enable bit 3786735Sgblack@eecs.umich.edu Bitfield<1> a; // Alignment fault checking 3799051Schander.sudanthi@arm.com Bitfield<0> m; // MMU enable bit 3806735Sgblack@eecs.umich.edu EndBitUnion(SCTLR) 3817320Sgblack@eecs.umich.edu 3827320Sgblack@eecs.umich.edu BitUnion32(CPACR) 3837320Sgblack@eecs.umich.edu Bitfield<1, 0> cp0; 3847320Sgblack@eecs.umich.edu Bitfield<3, 2> cp1; 3857320Sgblack@eecs.umich.edu Bitfield<5, 4> cp2; 3867320Sgblack@eecs.umich.edu Bitfield<7, 6> cp3; 3877320Sgblack@eecs.umich.edu Bitfield<9, 8> cp4; 3887320Sgblack@eecs.umich.edu Bitfield<11, 10> cp5; 3897320Sgblack@eecs.umich.edu Bitfield<13, 12> cp6; 3907320Sgblack@eecs.umich.edu Bitfield<15, 14> cp7; 3917320Sgblack@eecs.umich.edu Bitfield<17, 16> cp8; 3927320Sgblack@eecs.umich.edu Bitfield<19, 18> cp9; 3937320Sgblack@eecs.umich.edu Bitfield<21, 20> cp10; 3947320Sgblack@eecs.umich.edu Bitfield<23, 22> cp11; 3957320Sgblack@eecs.umich.edu Bitfield<25, 24> cp12; 3967320Sgblack@eecs.umich.edu Bitfield<27, 26> cp13; 3978206SWilliam.Wang@arm.com Bitfield<29, 28> rsvd; 3987320Sgblack@eecs.umich.edu Bitfield<30> d32dis; 3997320Sgblack@eecs.umich.edu Bitfield<31> asedis; 4007320Sgblack@eecs.umich.edu EndBitUnion(CPACR) 4017362Sgblack@eecs.umich.edu 4027362Sgblack@eecs.umich.edu BitUnion32(FSR) 4037362Sgblack@eecs.umich.edu Bitfield<3, 0> fsLow; 4047362Sgblack@eecs.umich.edu Bitfield<7, 4> domain; 4057362Sgblack@eecs.umich.edu Bitfield<10> fsHigh; 4067362Sgblack@eecs.umich.edu Bitfield<11> wnr; 4077362Sgblack@eecs.umich.edu Bitfield<12> ext; 4087362Sgblack@eecs.umich.edu EndBitUnion(FSR) 4097376Sgblack@eecs.umich.edu 4107376Sgblack@eecs.umich.edu BitUnion32(FPSCR) 4117376Sgblack@eecs.umich.edu Bitfield<0> ioc; 4127376Sgblack@eecs.umich.edu Bitfield<1> dzc; 4137376Sgblack@eecs.umich.edu Bitfield<2> ofc; 4147376Sgblack@eecs.umich.edu Bitfield<3> ufc; 4157376Sgblack@eecs.umich.edu Bitfield<4> ixc; 4167376Sgblack@eecs.umich.edu Bitfield<7> idc; 4177376Sgblack@eecs.umich.edu Bitfield<8> ioe; 4187376Sgblack@eecs.umich.edu Bitfield<9> dze; 4197376Sgblack@eecs.umich.edu Bitfield<10> ofe; 4207376Sgblack@eecs.umich.edu Bitfield<11> ufe; 4217376Sgblack@eecs.umich.edu Bitfield<12> ixe; 4227376Sgblack@eecs.umich.edu Bitfield<15> ide; 4237376Sgblack@eecs.umich.edu Bitfield<18, 16> len; 4247376Sgblack@eecs.umich.edu Bitfield<21, 20> stride; 4257376Sgblack@eecs.umich.edu Bitfield<23, 22> rMode; 4267376Sgblack@eecs.umich.edu Bitfield<24> fz; 4277376Sgblack@eecs.umich.edu Bitfield<25> dn; 4287376Sgblack@eecs.umich.edu Bitfield<26> ahp; 4297376Sgblack@eecs.umich.edu Bitfield<27> qc; 4307376Sgblack@eecs.umich.edu Bitfield<28> v; 4317376Sgblack@eecs.umich.edu Bitfield<29> c; 4327376Sgblack@eecs.umich.edu Bitfield<30> z; 4337376Sgblack@eecs.umich.edu Bitfield<31> n; 4347376Sgblack@eecs.umich.edu EndBitUnion(FPSCR) 4357383Sgblack@eecs.umich.edu 4367643Sgblack@eecs.umich.edu // This mask selects bits of the FPSCR that actually go in the FpCondCodes 4377643Sgblack@eecs.umich.edu // integer register to allow renaming. 4387783SGiacomo.Gabrielli@arm.com static const uint32_t FpCondCodesMask = 0xF0000000; 4397783SGiacomo.Gabrielli@arm.com // This mask selects the cumulative FP exception flags of the FPSCR. 4407783SGiacomo.Gabrielli@arm.com static const uint32_t FpscrExcMask = 0x0000009F; 4417783SGiacomo.Gabrielli@arm.com // This mask selects the cumulative saturation flag of the FPSCR. 4427783SGiacomo.Gabrielli@arm.com static const uint32_t FpscrQcMask = 0x08000000; 4437643Sgblack@eecs.umich.edu 4447640Sgblack@eecs.umich.edu BitUnion32(FPEXC) 4457640Sgblack@eecs.umich.edu Bitfield<31> ex; 4467640Sgblack@eecs.umich.edu Bitfield<30> en; 4477640Sgblack@eecs.umich.edu Bitfield<29, 0> subArchDefined; 4487640Sgblack@eecs.umich.edu EndBitUnion(FPEXC) 4497640Sgblack@eecs.umich.edu 4507383Sgblack@eecs.umich.edu BitUnion32(MVFR0) 4517383Sgblack@eecs.umich.edu Bitfield<3, 0> advSimdRegisters; 4527383Sgblack@eecs.umich.edu Bitfield<7, 4> singlePrecision; 4537383Sgblack@eecs.umich.edu Bitfield<11, 8> doublePrecision; 4547383Sgblack@eecs.umich.edu Bitfield<15, 12> vfpExceptionTrapping; 4557383Sgblack@eecs.umich.edu Bitfield<19, 16> divide; 4567383Sgblack@eecs.umich.edu Bitfield<23, 20> squareRoot; 4577383Sgblack@eecs.umich.edu Bitfield<27, 24> shortVectors; 4587383Sgblack@eecs.umich.edu Bitfield<31, 28> roundingModes; 4597383Sgblack@eecs.umich.edu EndBitUnion(MVFR0) 4607383Sgblack@eecs.umich.edu 4617383Sgblack@eecs.umich.edu BitUnion32(MVFR1) 4627383Sgblack@eecs.umich.edu Bitfield<3, 0> flushToZero; 4637383Sgblack@eecs.umich.edu Bitfield<7, 4> defaultNaN; 4647383Sgblack@eecs.umich.edu Bitfield<11, 8> advSimdLoadStore; 4657383Sgblack@eecs.umich.edu Bitfield<15, 12> advSimdInteger; 4667383Sgblack@eecs.umich.edu Bitfield<19, 16> advSimdSinglePrecision; 4677383Sgblack@eecs.umich.edu Bitfield<23, 20> advSimdHalfPrecision; 4687383Sgblack@eecs.umich.edu Bitfield<27, 24> vfpHalfPrecision; 4697383Sgblack@eecs.umich.edu Bitfield<31, 28> raz; 4707383Sgblack@eecs.umich.edu EndBitUnion(MVFR1) 4717404SAli.Saidi@ARM.com 4727404SAli.Saidi@ARM.com BitUnion32(PRRR) 4737404SAli.Saidi@ARM.com Bitfield<1,0> tr0; 4747404SAli.Saidi@ARM.com Bitfield<3,2> tr1; 4757404SAli.Saidi@ARM.com Bitfield<5,4> tr2; 4767404SAli.Saidi@ARM.com Bitfield<7,6> tr3; 4777404SAli.Saidi@ARM.com Bitfield<9,8> tr4; 4787404SAli.Saidi@ARM.com Bitfield<11,10> tr5; 4797404SAli.Saidi@ARM.com Bitfield<13,12> tr6; 4807404SAli.Saidi@ARM.com Bitfield<15,14> tr7; 4817404SAli.Saidi@ARM.com Bitfield<16> ds0; 4827404SAli.Saidi@ARM.com Bitfield<17> ds1; 4837404SAli.Saidi@ARM.com Bitfield<18> ns0; 4847404SAli.Saidi@ARM.com Bitfield<19> ns1; 4857404SAli.Saidi@ARM.com Bitfield<24> nos0; 4867404SAli.Saidi@ARM.com Bitfield<25> nos1; 4877404SAli.Saidi@ARM.com Bitfield<26> nos2; 4887404SAli.Saidi@ARM.com Bitfield<27> nos3; 4897404SAli.Saidi@ARM.com Bitfield<28> nos4; 4907404SAli.Saidi@ARM.com Bitfield<29> nos5; 4917404SAli.Saidi@ARM.com Bitfield<30> nos6; 4927404SAli.Saidi@ARM.com Bitfield<31> nos7; 4937404SAli.Saidi@ARM.com EndBitUnion(PRRR) 4947404SAli.Saidi@ARM.com 4957404SAli.Saidi@ARM.com BitUnion32(NMRR) 4967404SAli.Saidi@ARM.com Bitfield<1,0> ir0; 4977404SAli.Saidi@ARM.com Bitfield<3,2> ir1; 4987404SAli.Saidi@ARM.com Bitfield<5,4> ir2; 4997404SAli.Saidi@ARM.com Bitfield<7,6> ir3; 5007404SAli.Saidi@ARM.com Bitfield<9,8> ir4; 5017404SAli.Saidi@ARM.com Bitfield<11,10> ir5; 5027404SAli.Saidi@ARM.com Bitfield<13,12> ir6; 5037404SAli.Saidi@ARM.com Bitfield<15,14> ir7; 5047404SAli.Saidi@ARM.com Bitfield<17,16> or0; 5057404SAli.Saidi@ARM.com Bitfield<19,18> or1; 5067404SAli.Saidi@ARM.com Bitfield<21,20> or2; 5077404SAli.Saidi@ARM.com Bitfield<23,22> or3; 5087404SAli.Saidi@ARM.com Bitfield<25,24> or4; 5097404SAli.Saidi@ARM.com Bitfield<27,26> or5; 5107404SAli.Saidi@ARM.com Bitfield<29,28> or6; 5117404SAli.Saidi@ARM.com Bitfield<31,30> or7; 5127404SAli.Saidi@ARM.com EndBitUnion(NMRR) 5137404SAli.Saidi@ARM.com 5148552Sdaniel.johnson@arm.com BitUnion32(CONTEXTIDR) 5158552Sdaniel.johnson@arm.com Bitfield<7,0> asid; 5168552Sdaniel.johnson@arm.com Bitfield<31,8> procid; 5178552Sdaniel.johnson@arm.com EndBitUnion(CONTEXTIDR) 5188552Sdaniel.johnson@arm.com 5198549Sdaniel.johnson@arm.com BitUnion32(L2CTLR) 5208549Sdaniel.johnson@arm.com Bitfield<2,0> sataRAMLatency; 5218549Sdaniel.johnson@arm.com Bitfield<4,3> reserved_4_3; 5228549Sdaniel.johnson@arm.com Bitfield<5> dataRAMSetup; 5238549Sdaniel.johnson@arm.com Bitfield<8,6> tagRAMLatency; 5248549Sdaniel.johnson@arm.com Bitfield<9> tagRAMSetup; 5258549Sdaniel.johnson@arm.com Bitfield<11,10> dataRAMSlice; 5268549Sdaniel.johnson@arm.com Bitfield<12> tagRAMSlice; 5278549Sdaniel.johnson@arm.com Bitfield<20,13> reserved_20_13; 5288549Sdaniel.johnson@arm.com Bitfield<21> eccandParityEnable; 5298549Sdaniel.johnson@arm.com Bitfield<22> reserved_22; 5308549Sdaniel.johnson@arm.com Bitfield<23> interptCtrlPresent; 5318549Sdaniel.johnson@arm.com Bitfield<25,24> numCPUs; 5328549Sdaniel.johnson@arm.com Bitfield<30,26> reserved_30_26; 5338549Sdaniel.johnson@arm.com Bitfield<31> l2rstDISABLE_monitor; 5348549Sdaniel.johnson@arm.com EndBitUnion(L2CTLR) 5358549Sdaniel.johnson@arm.com 5369130Satgutier@umich.edu BitUnion32(CTR) 5379130Satgutier@umich.edu Bitfield<3,0> iCacheLineSize; 5389130Satgutier@umich.edu Bitfield<13,4> raz_13_4; 5399130Satgutier@umich.edu Bitfield<15,14> l1IndexPolicy; 5409130Satgutier@umich.edu Bitfield<19,16> dCacheLineSize; 5419130Satgutier@umich.edu Bitfield<23,20> erg; 5429130Satgutier@umich.edu Bitfield<27,24> cwg; 5439130Satgutier@umich.edu Bitfield<28> raz_28; 5449130Satgutier@umich.edu Bitfield<31,29> format; 5459130Satgutier@umich.edu EndBitUnion(CTR) 5468902Sandreas.hansson@arm.com} 5476242Sgblack@eecs.umich.edu 5486242Sgblack@eecs.umich.edu#endif // __ARCH_ARM_MISCREGS_HH__ 549