miscregs.hh revision 8299
14309Sgblack@eecs.umich.edu/* 24309Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 34309Sgblack@eecs.umich.edu * All rights reserved 44309Sgblack@eecs.umich.edu * 54309Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 64309Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 74309Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 84309Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 94309Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 104309Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 114309Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 124309Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 134309Sgblack@eecs.umich.edu * 144309Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 154309Sgblack@eecs.umich.edu * All rights reserved. 164309Sgblack@eecs.umich.edu * 174309Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 184309Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 194309Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 204309Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 214309Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 224309Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 234309Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 244309Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 254309Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 264309Sgblack@eecs.umich.edu * this software without specific prior written permission. 274309Sgblack@eecs.umich.edu * 284309Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294309Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304309Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314309Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324309Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334309Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344309Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354309Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364309Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374309Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384309Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394309Sgblack@eecs.umich.edu * 404309Sgblack@eecs.umich.edu * Authors: Gabe Black 414309Sgblack@eecs.umich.edu */ 424309Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MISCREGS_HH__ 434309Sgblack@eecs.umich.edu#define __ARCH_ARM_MISCREGS_HH__ 444309Sgblack@eecs.umich.edu 454309Sgblack@eecs.umich.edu#include "base/bitunion.hh" 464309Sgblack@eecs.umich.edu 474309Sgblack@eecs.umich.edunamespace ArmISA 484309Sgblack@eecs.umich.edu{ 494309Sgblack@eecs.umich.edu enum ConditionCode { 504309Sgblack@eecs.umich.edu COND_EQ = 0, 514309Sgblack@eecs.umich.edu COND_NE, // 1 524309Sgblack@eecs.umich.edu COND_CS, // 2 534309Sgblack@eecs.umich.edu COND_CC, // 3 544309Sgblack@eecs.umich.edu COND_MI, // 4 554309Sgblack@eecs.umich.edu COND_PL, // 5 564309Sgblack@eecs.umich.edu COND_VS, // 6 574309Sgblack@eecs.umich.edu COND_VC, // 7 584309Sgblack@eecs.umich.edu COND_HI, // 8 594309Sgblack@eecs.umich.edu COND_LS, // 9 604309Sgblack@eecs.umich.edu COND_GE, // 10 614309Sgblack@eecs.umich.edu COND_LT, // 11 624309Sgblack@eecs.umich.edu COND_GT, // 12 634309Sgblack@eecs.umich.edu COND_LE, // 13 644309Sgblack@eecs.umich.edu COND_AL, // 14 654309Sgblack@eecs.umich.edu COND_UC // 15 664309Sgblack@eecs.umich.edu }; 674309Sgblack@eecs.umich.edu 684309Sgblack@eecs.umich.edu enum MiscRegIndex { 694309Sgblack@eecs.umich.edu MISCREG_CPSR = 0, 704309Sgblack@eecs.umich.edu MISCREG_SPSR, 714309Sgblack@eecs.umich.edu MISCREG_SPSR_FIQ, 724309Sgblack@eecs.umich.edu MISCREG_SPSR_IRQ, 734309Sgblack@eecs.umich.edu MISCREG_SPSR_SVC, 744309Sgblack@eecs.umich.edu MISCREG_SPSR_MON, 754309Sgblack@eecs.umich.edu MISCREG_SPSR_UND, 764309Sgblack@eecs.umich.edu MISCREG_SPSR_ABT, 774309Sgblack@eecs.umich.edu MISCREG_FPSR, 784309Sgblack@eecs.umich.edu MISCREG_FPSID, 794309Sgblack@eecs.umich.edu MISCREG_FPSCR, 804309Sgblack@eecs.umich.edu MISCREG_FPSCR_QC, // Cumulative saturation flag 814309Sgblack@eecs.umich.edu MISCREG_FPSCR_EXC, // Cumulative FP exception flags 824309Sgblack@eecs.umich.edu MISCREG_FPEXC, 834309Sgblack@eecs.umich.edu MISCREG_MVFR0, 844309Sgblack@eecs.umich.edu MISCREG_MVFR1, 854309Sgblack@eecs.umich.edu MISCREG_SCTLR_RST, 864309Sgblack@eecs.umich.edu MISCREG_SEV_MAILBOX, 874309Sgblack@eecs.umich.edu 884309Sgblack@eecs.umich.edu // CP15 registers 894309Sgblack@eecs.umich.edu MISCREG_CP15_START, 904309Sgblack@eecs.umich.edu MISCREG_SCTLR = MISCREG_CP15_START, 914309Sgblack@eecs.umich.edu MISCREG_DCCISW, 924309Sgblack@eecs.umich.edu MISCREG_DCCIMVAC, 934309Sgblack@eecs.umich.edu MISCREG_DCCMVAC, 944309Sgblack@eecs.umich.edu MISCREG_CONTEXTIDR, 954309Sgblack@eecs.umich.edu MISCREG_TPIDRURW, 964309Sgblack@eecs.umich.edu MISCREG_TPIDRURO, 974309Sgblack@eecs.umich.edu MISCREG_TPIDRPRW, 984309Sgblack@eecs.umich.edu MISCREG_CP15ISB, 994309Sgblack@eecs.umich.edu MISCREG_CP15DSB, 1004309Sgblack@eecs.umich.edu MISCREG_CP15DMB, 1014309Sgblack@eecs.umich.edu MISCREG_CPACR, 1024309Sgblack@eecs.umich.edu MISCREG_CLIDR, 1034309Sgblack@eecs.umich.edu MISCREG_CCSIDR, 1044309Sgblack@eecs.umich.edu MISCREG_CSSELR, 1054309Sgblack@eecs.umich.edu MISCREG_ICIALLUIS, 1064309Sgblack@eecs.umich.edu MISCREG_ICIALLU, 1074309Sgblack@eecs.umich.edu MISCREG_ICIMVAU, 1084309Sgblack@eecs.umich.edu MISCREG_BPIMVA, 1094309Sgblack@eecs.umich.edu MISCREG_BPIALLIS, 1104309Sgblack@eecs.umich.edu MISCREG_BPIALL, 1114309Sgblack@eecs.umich.edu MISCREG_MIDR, 1124309Sgblack@eecs.umich.edu MISCREG_TTBR0, 1134309Sgblack@eecs.umich.edu MISCREG_TTBR1, 1144309Sgblack@eecs.umich.edu MISCREG_TLBTR, 1154309Sgblack@eecs.umich.edu MISCREG_DACR, 1164309Sgblack@eecs.umich.edu MISCREG_TLBIALLIS, 1174309Sgblack@eecs.umich.edu MISCREG_TLBIMVAIS, 1184309Sgblack@eecs.umich.edu MISCREG_TLBIASIDIS, 1194309Sgblack@eecs.umich.edu MISCREG_TLBIMVAAIS, 1204309Sgblack@eecs.umich.edu MISCREG_ITLBIALL, 1214309Sgblack@eecs.umich.edu MISCREG_ITLBIMVA, 1224309Sgblack@eecs.umich.edu MISCREG_ITLBIASID, 1234309Sgblack@eecs.umich.edu MISCREG_DTLBIALL, 1244309Sgblack@eecs.umich.edu MISCREG_DTLBIMVA, 1254309Sgblack@eecs.umich.edu MISCREG_DTLBIASID, 1264309Sgblack@eecs.umich.edu MISCREG_TLBIALL, 1274309Sgblack@eecs.umich.edu MISCREG_TLBIMVA, 1284309Sgblack@eecs.umich.edu MISCREG_TLBIASID, 1294309Sgblack@eecs.umich.edu MISCREG_TLBIMVAA, 1304309Sgblack@eecs.umich.edu MISCREG_DFSR, 1314309Sgblack@eecs.umich.edu MISCREG_IFSR, 1324309Sgblack@eecs.umich.edu MISCREG_DFAR, 1334309Sgblack@eecs.umich.edu MISCREG_IFAR, 1344309Sgblack@eecs.umich.edu MISCREG_MPIDR, 1354309Sgblack@eecs.umich.edu MISCREG_PRRR, 1364309Sgblack@eecs.umich.edu MISCREG_NMRR, 1374309Sgblack@eecs.umich.edu MISCREG_TTBCR, 1384309Sgblack@eecs.umich.edu MISCREG_ID_PFR0, 1394309Sgblack@eecs.umich.edu MISCREG_CTR, 1404309Sgblack@eecs.umich.edu MISCREG_SCR, 1414309Sgblack@eecs.umich.edu MISCREG_SDER, 1424309Sgblack@eecs.umich.edu MISCREG_PAR, 1434309Sgblack@eecs.umich.edu MISCREG_V2PCWPR, 1444309Sgblack@eecs.umich.edu MISCREG_V2PCWPW, 1454309Sgblack@eecs.umich.edu MISCREG_V2PCWUR, 1464309Sgblack@eecs.umich.edu MISCREG_V2PCWUW, 1474309Sgblack@eecs.umich.edu MISCREG_V2POWPR, 1484309Sgblack@eecs.umich.edu MISCREG_V2POWPW, 1494309Sgblack@eecs.umich.edu MISCREG_V2POWUR, 1504309Sgblack@eecs.umich.edu MISCREG_V2POWUW, 1514309Sgblack@eecs.umich.edu MISCREG_ID_MMFR0, 1524309Sgblack@eecs.umich.edu MISCREG_ID_MMFR3, 1534309Sgblack@eecs.umich.edu MISCREG_ACTLR, 1544309Sgblack@eecs.umich.edu MISCREG_PMCR, 1554309Sgblack@eecs.umich.edu MISCREG_PMCCNTR, 1564309Sgblack@eecs.umich.edu MISCREG_PMCNTENSET, 1574309Sgblack@eecs.umich.edu MISCREG_PMCNTENCLR, 1584309Sgblack@eecs.umich.edu MISCREG_PMOVSR, 1594309Sgblack@eecs.umich.edu MISCREG_PMSWINC, 1604309Sgblack@eecs.umich.edu MISCREG_PMSELR, 1614309Sgblack@eecs.umich.edu MISCREG_PMCEID0, 1624309Sgblack@eecs.umich.edu MISCREG_PMCEID1, 1634309Sgblack@eecs.umich.edu MISCREG_PMC_OTHER, 1644309Sgblack@eecs.umich.edu MISCREG_PMXEVCNTR, 1654309Sgblack@eecs.umich.edu MISCREG_PMUSERENR, 1664309Sgblack@eecs.umich.edu MISCREG_PMINTENSET, 1674309Sgblack@eecs.umich.edu MISCREG_PMINTENCLR, 1684309Sgblack@eecs.umich.edu MISCREG_ID_ISAR0, 1694309Sgblack@eecs.umich.edu MISCREG_ID_ISAR1, 1704309Sgblack@eecs.umich.edu MISCREG_ID_ISAR2, 1714309Sgblack@eecs.umich.edu MISCREG_ID_ISAR3, 1724309Sgblack@eecs.umich.edu MISCREG_ID_ISAR4, 173 MISCREG_ID_ISAR5, 174 MISCREG_CPSR_MODE, 175 MISCREG_LOCKFLAG, 176 MISCREG_LOCKADDR, 177 MISCREG_ID_PFR1, 178 MISCREG_CP15_UNIMP_START, 179 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 180 MISCREG_ID_DFR0, 181 MISCREG_ID_AFR0, 182 MISCREG_ID_MMFR1, 183 MISCREG_ID_MMFR2, 184 MISCREG_AIDR, 185 MISCREG_ADFSR, 186 MISCREG_AIFSR, 187 MISCREG_DCIMVAC, 188 MISCREG_DCISW, 189 MISCREG_MCCSW, 190 MISCREG_DCCMVAU, 191 MISCREG_NSACR, 192 MISCREG_VBAR, 193 MISCREG_MVBAR, 194 MISCREG_ISR, 195 MISCREG_FCEIDR, 196 MISCREG_L2LATENCY, 197 198 199 MISCREG_CP15_END, 200 201 // Dummy indices 202 MISCREG_NOP = MISCREG_CP15_END, 203 MISCREG_RAZ, 204 205 NUM_MISCREGS 206 }; 207 208 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 209 unsigned crm, unsigned opc2); 210 211 const char * const miscRegName[NUM_MISCREGS] = { 212 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 213 "spsr_mon", "spsr_und", "spsr_abt", 214 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 215 "mvfr0", "mvfr1", 216 "sctlr_rst", "sev_mailbox", 217 "sctlr", "dccisw", "dccimvac", "dccmvac", 218 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 219 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 220 "clidr", "ccsidr", "csselr", 221 "icialluis", "iciallu", "icimvau", 222 "bpimva", "bpiallis", "bpiall", 223 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 224 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 225 "itlbiall", "itlbimva", "itlbiasid", 226 "dtlbiall", "dtlbimva", "dtlbiasid", 227 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 228 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 229 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 230 "scr", "sder", "par", 231 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 232 "v2powpr", "v2powpw", "v2powur", "v2powuw", 233 "id_mmfr0", "id_mmfr3", "actlr", "pmcr", "pmccntr", 234 "pmcntenset", "pmcntenclr", "pmovsr", 235 "pmswinc", "pmselr", "pmceid0", 236 "pmceid1", "pmc_other", "pmxevcntr", 237 "pmuserenr", "pmintenset", "pmintenclr", 238 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 239 "cpsr_mode", "lockflag", "lockaddr", "id_pfr1", 240 // Unimplemented below 241 "tcmtr", 242 "id_dfr0", "id_afr0", 243 "id_mmfr1", "id_mmfr2", 244 "aidr", "adfsr", "aifsr", 245 "dcimvac", "dcisw", "mccsw", 246 "dccmvau", 247 "nsacr", 248 "vbar", "mvbar", "isr", "fceidr", "l2latency", 249 "nop", "raz" 250 }; 251 252 BitUnion32(CPSR) 253 Bitfield<31> n; 254 Bitfield<30> z; 255 Bitfield<29> c; 256 Bitfield<28> v; 257 Bitfield<27> q; 258 Bitfield<26,25> it1; 259 Bitfield<24> j; 260 Bitfield<19, 16> ge; 261 Bitfield<15,10> it2; 262 Bitfield<9> e; 263 Bitfield<8> a; 264 Bitfield<7> i; 265 Bitfield<6> f; 266 Bitfield<5> t; 267 Bitfield<4, 0> mode; 268 EndBitUnion(CPSR) 269 270 // This mask selects bits of the CPSR that actually go in the CondCodes 271 // integer register to allow renaming. 272 static const uint32_t CondCodesMask = 0xF80F0000; 273 274 BitUnion32(SCTLR) 275 Bitfield<31> ie; // Instruction endianness 276 Bitfield<30> te; // Thumb Exception Enable 277 Bitfield<29> afe; // Access flag enable 278 Bitfield<28> tre; // TEX Remap bit 279 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 280 Bitfield<25> ee; // Exception Endianness bit 281 Bitfield<24> ve; // Interrupt vectors enable 282 Bitfield<23> xp; // Extended page table enable bit 283 Bitfield<22> u; // Alignment (now unused) 284 Bitfield<21> fi; // Fast interrupts configuration enable 285 Bitfield<19> dz; // Divide by Zero fault enable bit 286 Bitfield<18> rao2;// Read as one 287 Bitfield<17> br; // Background region bit 288 Bitfield<16> rao3;// Read as one 289 Bitfield<14> rr; // Round robin cache replacement 290 Bitfield<13> v; // Base address for exception vectors 291 Bitfield<12> i; // instruction cache enable 292 Bitfield<11> z; // branch prediction enable bit 293 Bitfield<10> sw; // Enable swp/swpb 294 Bitfield<9,8> rs; // deprecated protection bits 295 Bitfield<6,3> rao4;// Read as one 296 Bitfield<7> b; // Endianness support (unused) 297 Bitfield<2> c; // Cache enable bit 298 Bitfield<1> a; // Alignment fault checking 299 Bitfield<0> m; // MMU enable bit 300 EndBitUnion(SCTLR) 301 302 BitUnion32(CPACR) 303 Bitfield<1, 0> cp0; 304 Bitfield<3, 2> cp1; 305 Bitfield<5, 4> cp2; 306 Bitfield<7, 6> cp3; 307 Bitfield<9, 8> cp4; 308 Bitfield<11, 10> cp5; 309 Bitfield<13, 12> cp6; 310 Bitfield<15, 14> cp7; 311 Bitfield<17, 16> cp8; 312 Bitfield<19, 18> cp9; 313 Bitfield<21, 20> cp10; 314 Bitfield<23, 22> cp11; 315 Bitfield<25, 24> cp12; 316 Bitfield<27, 26> cp13; 317 Bitfield<29, 28> rsvd; 318 Bitfield<30> d32dis; 319 Bitfield<31> asedis; 320 EndBitUnion(CPACR) 321 322 BitUnion32(FSR) 323 Bitfield<3, 0> fsLow; 324 Bitfield<7, 4> domain; 325 Bitfield<10> fsHigh; 326 Bitfield<11> wnr; 327 Bitfield<12> ext; 328 EndBitUnion(FSR) 329 330 BitUnion32(FPSCR) 331 Bitfield<0> ioc; 332 Bitfield<1> dzc; 333 Bitfield<2> ofc; 334 Bitfield<3> ufc; 335 Bitfield<4> ixc; 336 Bitfield<7> idc; 337 Bitfield<8> ioe; 338 Bitfield<9> dze; 339 Bitfield<10> ofe; 340 Bitfield<11> ufe; 341 Bitfield<12> ixe; 342 Bitfield<15> ide; 343 Bitfield<18, 16> len; 344 Bitfield<21, 20> stride; 345 Bitfield<23, 22> rMode; 346 Bitfield<24> fz; 347 Bitfield<25> dn; 348 Bitfield<26> ahp; 349 Bitfield<27> qc; 350 Bitfield<28> v; 351 Bitfield<29> c; 352 Bitfield<30> z; 353 Bitfield<31> n; 354 EndBitUnion(FPSCR) 355 356 // This mask selects bits of the FPSCR that actually go in the FpCondCodes 357 // integer register to allow renaming. 358 static const uint32_t FpCondCodesMask = 0xF0000000; 359 // This mask selects the cumulative FP exception flags of the FPSCR. 360 static const uint32_t FpscrExcMask = 0x0000009F; 361 // This mask selects the cumulative saturation flag of the FPSCR. 362 static const uint32_t FpscrQcMask = 0x08000000; 363 364 BitUnion32(FPEXC) 365 Bitfield<31> ex; 366 Bitfield<30> en; 367 Bitfield<29, 0> subArchDefined; 368 EndBitUnion(FPEXC) 369 370 BitUnion32(MVFR0) 371 Bitfield<3, 0> advSimdRegisters; 372 Bitfield<7, 4> singlePrecision; 373 Bitfield<11, 8> doublePrecision; 374 Bitfield<15, 12> vfpExceptionTrapping; 375 Bitfield<19, 16> divide; 376 Bitfield<23, 20> squareRoot; 377 Bitfield<27, 24> shortVectors; 378 Bitfield<31, 28> roundingModes; 379 EndBitUnion(MVFR0) 380 381 BitUnion32(MVFR1) 382 Bitfield<3, 0> flushToZero; 383 Bitfield<7, 4> defaultNaN; 384 Bitfield<11, 8> advSimdLoadStore; 385 Bitfield<15, 12> advSimdInteger; 386 Bitfield<19, 16> advSimdSinglePrecision; 387 Bitfield<23, 20> advSimdHalfPrecision; 388 Bitfield<27, 24> vfpHalfPrecision; 389 Bitfield<31, 28> raz; 390 EndBitUnion(MVFR1) 391 392 BitUnion32(PRRR) 393 Bitfield<1,0> tr0; 394 Bitfield<3,2> tr1; 395 Bitfield<5,4> tr2; 396 Bitfield<7,6> tr3; 397 Bitfield<9,8> tr4; 398 Bitfield<11,10> tr5; 399 Bitfield<13,12> tr6; 400 Bitfield<15,14> tr7; 401 Bitfield<16> ds0; 402 Bitfield<17> ds1; 403 Bitfield<18> ns0; 404 Bitfield<19> ns1; 405 Bitfield<24> nos0; 406 Bitfield<25> nos1; 407 Bitfield<26> nos2; 408 Bitfield<27> nos3; 409 Bitfield<28> nos4; 410 Bitfield<29> nos5; 411 Bitfield<30> nos6; 412 Bitfield<31> nos7; 413 EndBitUnion(PRRR) 414 415 BitUnion32(NMRR) 416 Bitfield<1,0> ir0; 417 Bitfield<3,2> ir1; 418 Bitfield<5,4> ir2; 419 Bitfield<7,6> ir3; 420 Bitfield<9,8> ir4; 421 Bitfield<11,10> ir5; 422 Bitfield<13,12> ir6; 423 Bitfield<15,14> ir7; 424 Bitfield<17,16> or0; 425 Bitfield<19,18> or1; 426 Bitfield<21,20> or2; 427 Bitfield<23,22> or3; 428 Bitfield<25,24> or4; 429 Bitfield<27,26> or5; 430 Bitfield<29,28> or6; 431 Bitfield<31,30> or7; 432 EndBitUnion(NMRR) 433 434}; 435 436#endif // __ARCH_ARM_MISCREGS_HH__ 437