miscregs.hh revision 7111
16242Sgblack@eecs.umich.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146242Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156242Sgblack@eecs.umich.edu * All rights reserved. 166242Sgblack@eecs.umich.edu * 176242Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186242Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196242Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216242Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236242Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246242Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256242Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266242Sgblack@eecs.umich.edu * this software without specific prior written permission. 276242Sgblack@eecs.umich.edu * 286242Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296242Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306242Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316242Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326242Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336242Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346242Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356242Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366242Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376242Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386242Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396242Sgblack@eecs.umich.edu * 406242Sgblack@eecs.umich.edu * Authors: Gabe Black 416242Sgblack@eecs.umich.edu */ 426242Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MISCREGS_HH__ 436242Sgblack@eecs.umich.edu#define __ARCH_ARM_MISCREGS_HH__ 446242Sgblack@eecs.umich.edu 456242Sgblack@eecs.umich.edu#include "base/bitunion.hh" 466242Sgblack@eecs.umich.edu 476242Sgblack@eecs.umich.edunamespace ArmISA 486242Sgblack@eecs.umich.edu{ 496242Sgblack@eecs.umich.edu enum ConditionCode { 506242Sgblack@eecs.umich.edu COND_EQ = 0, 516242Sgblack@eecs.umich.edu COND_NE, // 1 526242Sgblack@eecs.umich.edu COND_CS, // 2 536242Sgblack@eecs.umich.edu COND_CC, // 3 546242Sgblack@eecs.umich.edu COND_MI, // 4 556242Sgblack@eecs.umich.edu COND_PL, // 5 566242Sgblack@eecs.umich.edu COND_VS, // 6 576242Sgblack@eecs.umich.edu COND_VC, // 7 586242Sgblack@eecs.umich.edu COND_HI, // 8 596242Sgblack@eecs.umich.edu COND_LS, // 9 606242Sgblack@eecs.umich.edu COND_GE, // 10 616242Sgblack@eecs.umich.edu COND_LT, // 11 626242Sgblack@eecs.umich.edu COND_GT, // 12 636242Sgblack@eecs.umich.edu COND_LE, // 13 646242Sgblack@eecs.umich.edu COND_AL, // 14 657111Sgblack@eecs.umich.edu COND_UC // 15 666242Sgblack@eecs.umich.edu }; 676242Sgblack@eecs.umich.edu 686242Sgblack@eecs.umich.edu enum MiscRegIndex { 696242Sgblack@eecs.umich.edu MISCREG_CPSR = 0, 706735Sgblack@eecs.umich.edu MISCREG_SPSR, 716242Sgblack@eecs.umich.edu MISCREG_SPSR_FIQ, 726242Sgblack@eecs.umich.edu MISCREG_SPSR_IRQ, 736242Sgblack@eecs.umich.edu MISCREG_SPSR_SVC, 746723Sgblack@eecs.umich.edu MISCREG_SPSR_MON, 756242Sgblack@eecs.umich.edu MISCREG_SPSR_UND, 766242Sgblack@eecs.umich.edu MISCREG_SPSR_ABT, 776261Sgblack@eecs.umich.edu MISCREG_FPSR, 786403Sgblack@eecs.umich.edu MISCREG_FPSID, 796403Sgblack@eecs.umich.edu MISCREG_FPSCR, 806403Sgblack@eecs.umich.edu MISCREG_FPEXC, 816735Sgblack@eecs.umich.edu MISCREG_SCTLR, 826735Sgblack@eecs.umich.edu NUM_MISCREGS 836261Sgblack@eecs.umich.edu }; 846261Sgblack@eecs.umich.edu 856261Sgblack@eecs.umich.edu const char * const miscRegName[NUM_MISCREGS] = { 866735Sgblack@eecs.umich.edu "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", 876735Sgblack@eecs.umich.edu "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr" 886242Sgblack@eecs.umich.edu }; 896242Sgblack@eecs.umich.edu 906242Sgblack@eecs.umich.edu BitUnion32(CPSR) 916242Sgblack@eecs.umich.edu Bitfield<31> n; 926242Sgblack@eecs.umich.edu Bitfield<30> z; 936242Sgblack@eecs.umich.edu Bitfield<29> c; 946242Sgblack@eecs.umich.edu Bitfield<28> v; 956242Sgblack@eecs.umich.edu Bitfield<27> q; 966735Sgblack@eecs.umich.edu Bitfield<26,25> it1; 976242Sgblack@eecs.umich.edu Bitfield<24> j; 986242Sgblack@eecs.umich.edu Bitfield<19, 16> ge; 996735Sgblack@eecs.umich.edu Bitfield<15,10> it2; 1006242Sgblack@eecs.umich.edu Bitfield<9> e; 1016242Sgblack@eecs.umich.edu Bitfield<8> a; 1026242Sgblack@eecs.umich.edu Bitfield<7> i; 1036242Sgblack@eecs.umich.edu Bitfield<6> f; 1046242Sgblack@eecs.umich.edu Bitfield<5> t; 1056242Sgblack@eecs.umich.edu Bitfield<4, 0> mode; 1066242Sgblack@eecs.umich.edu EndBitUnion(CPSR) 1076735Sgblack@eecs.umich.edu 1086750Sgblack@eecs.umich.edu // This mask selects bits of the CPSR that actually go in the CondCodes 1096750Sgblack@eecs.umich.edu // integer register to allow renaming. 1106750Sgblack@eecs.umich.edu static const uint32_t CondCodesMask = 0xF80F0000; 1116750Sgblack@eecs.umich.edu 1127093Sgblack@eecs.umich.edu // These otherwise unused bits of the PC are used to select a mode 1137093Sgblack@eecs.umich.edu // like the J and T bits of the CPSR. 1147093Sgblack@eecs.umich.edu static const Addr PcJBitShift = 33; 1157093Sgblack@eecs.umich.edu static const Addr PcTBitShift = 34; 1167093Sgblack@eecs.umich.edu static const Addr PcModeMask = (ULL(1) << PcJBitShift) | 1177093Sgblack@eecs.umich.edu (ULL(1) << PcTBitShift); 1187093Sgblack@eecs.umich.edu 1196735Sgblack@eecs.umich.edu BitUnion32(SCTLR) 1206735Sgblack@eecs.umich.edu Bitfield<30> te; // Thumb Exception Enable 1216735Sgblack@eecs.umich.edu Bitfield<29> afe; // Access flag enable 1226735Sgblack@eecs.umich.edu Bitfield<28> tre; // TEX Remap bit 1236735Sgblack@eecs.umich.edu Bitfield<27> nmfi;// Non-maskable fast interrupts enable 1246735Sgblack@eecs.umich.edu Bitfield<25> ee; // Exception Endianness bit 1256735Sgblack@eecs.umich.edu Bitfield<24> ve; // Interrupt vectors enable 1266735Sgblack@eecs.umich.edu Bitfield<23> rao1;// Read as one 1276735Sgblack@eecs.umich.edu Bitfield<22> u; // Alignment (now unused) 1286735Sgblack@eecs.umich.edu Bitfield<21> fi; // Fast interrupts configuration enable 1296735Sgblack@eecs.umich.edu Bitfield<18> rao2;// Read as one 1306735Sgblack@eecs.umich.edu Bitfield<17> ha; // Hardware access flag enable 1316735Sgblack@eecs.umich.edu Bitfield<16> rao3;// Read as one 1326735Sgblack@eecs.umich.edu Bitfield<14> rr; // Round robin cache replacement 1336735Sgblack@eecs.umich.edu Bitfield<13> v; // Base address for exception vectors 1346735Sgblack@eecs.umich.edu Bitfield<12> i; // instruction cache enable 1356735Sgblack@eecs.umich.edu Bitfield<11> z; // branch prediction enable bit 1366735Sgblack@eecs.umich.edu Bitfield<10> sw; // Enable swp/swpb 1376735Sgblack@eecs.umich.edu Bitfield<6,3> rao4;// Read as one 1386735Sgblack@eecs.umich.edu Bitfield<7> b; // Endianness support (unused) 1396735Sgblack@eecs.umich.edu Bitfield<2> c; // Cache enable bit 1406735Sgblack@eecs.umich.edu Bitfield<1> a; // Alignment fault checking 1416735Sgblack@eecs.umich.edu Bitfield<0> m; // MMU enable bit 1426735Sgblack@eecs.umich.edu EndBitUnion(SCTLR) 1436242Sgblack@eecs.umich.edu}; 1446242Sgblack@eecs.umich.edu 1456242Sgblack@eecs.umich.edu#endif // __ARCH_ARM_MISCREGS_HH__ 146