miscregs.hh revision 6735
16242Sgblack@eecs.umich.edu/*
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66242Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
76242Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
86242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
96242Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
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146242Sgblack@eecs.umich.edu * this software without specific prior written permission.
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276242Sgblack@eecs.umich.edu *
286242Sgblack@eecs.umich.edu * Authors: Gabe Black
296242Sgblack@eecs.umich.edu */
306242Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MISCREGS_HH__
316242Sgblack@eecs.umich.edu#define __ARCH_ARM_MISCREGS_HH__
326242Sgblack@eecs.umich.edu
336242Sgblack@eecs.umich.edu#include "base/bitunion.hh"
346242Sgblack@eecs.umich.edu
356242Sgblack@eecs.umich.edunamespace ArmISA
366242Sgblack@eecs.umich.edu{
376242Sgblack@eecs.umich.edu    enum ConditionCode {
386242Sgblack@eecs.umich.edu        COND_EQ  =   0,
396242Sgblack@eecs.umich.edu        COND_NE, //  1
406242Sgblack@eecs.umich.edu        COND_CS, //  2
416242Sgblack@eecs.umich.edu        COND_CC, //  3
426242Sgblack@eecs.umich.edu        COND_MI, //  4
436242Sgblack@eecs.umich.edu        COND_PL, //  5
446242Sgblack@eecs.umich.edu        COND_VS, //  6
456242Sgblack@eecs.umich.edu        COND_VC, //  7
466242Sgblack@eecs.umich.edu        COND_HI, //  8
476242Sgblack@eecs.umich.edu        COND_LS, //  9
486242Sgblack@eecs.umich.edu        COND_GE, // 10
496242Sgblack@eecs.umich.edu        COND_LT, // 11
506242Sgblack@eecs.umich.edu        COND_GT, // 12
516242Sgblack@eecs.umich.edu        COND_LE, // 13
526242Sgblack@eecs.umich.edu        COND_AL, // 14
536242Sgblack@eecs.umich.edu        COND_NV  // 15
546242Sgblack@eecs.umich.edu    };
556242Sgblack@eecs.umich.edu
566242Sgblack@eecs.umich.edu    enum MiscRegIndex {
576242Sgblack@eecs.umich.edu        MISCREG_CPSR = 0,
586735Sgblack@eecs.umich.edu        MISCREG_SPSR,
596242Sgblack@eecs.umich.edu        MISCREG_SPSR_FIQ,
606242Sgblack@eecs.umich.edu        MISCREG_SPSR_IRQ,
616242Sgblack@eecs.umich.edu        MISCREG_SPSR_SVC,
626723Sgblack@eecs.umich.edu        MISCREG_SPSR_MON,
636242Sgblack@eecs.umich.edu        MISCREG_SPSR_UND,
646242Sgblack@eecs.umich.edu        MISCREG_SPSR_ABT,
656261Sgblack@eecs.umich.edu        MISCREG_FPSR,
666403Sgblack@eecs.umich.edu        MISCREG_FPSID,
676403Sgblack@eecs.umich.edu        MISCREG_FPSCR,
686403Sgblack@eecs.umich.edu        MISCREG_FPEXC,
696735Sgblack@eecs.umich.edu        MISCREG_SCTLR,
706735Sgblack@eecs.umich.edu        NUM_MISCREGS
716261Sgblack@eecs.umich.edu    };
726261Sgblack@eecs.umich.edu
736261Sgblack@eecs.umich.edu    const char * const miscRegName[NUM_MISCREGS] = {
746735Sgblack@eecs.umich.edu        "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
756735Sgblack@eecs.umich.edu        "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
766242Sgblack@eecs.umich.edu    };
776242Sgblack@eecs.umich.edu
786242Sgblack@eecs.umich.edu    BitUnion32(CPSR)
796242Sgblack@eecs.umich.edu        Bitfield<31> n;
806242Sgblack@eecs.umich.edu        Bitfield<30> z;
816242Sgblack@eecs.umich.edu        Bitfield<29> c;
826242Sgblack@eecs.umich.edu        Bitfield<28> v;
836242Sgblack@eecs.umich.edu        Bitfield<27> q;
846735Sgblack@eecs.umich.edu        Bitfield<26,25> it1;
856242Sgblack@eecs.umich.edu        Bitfield<24> j;
866242Sgblack@eecs.umich.edu        Bitfield<19, 16> ge;
876735Sgblack@eecs.umich.edu        Bitfield<15,10> it2;
886242Sgblack@eecs.umich.edu        Bitfield<9> e;
896242Sgblack@eecs.umich.edu        Bitfield<8> a;
906242Sgblack@eecs.umich.edu        Bitfield<7> i;
916242Sgblack@eecs.umich.edu        Bitfield<6> f;
926242Sgblack@eecs.umich.edu        Bitfield<5> t;
936242Sgblack@eecs.umich.edu        Bitfield<4, 0> mode;
946242Sgblack@eecs.umich.edu    EndBitUnion(CPSR)
956735Sgblack@eecs.umich.edu
966735Sgblack@eecs.umich.edu    BitUnion32(SCTLR)
976735Sgblack@eecs.umich.edu        Bitfield<30> te;  // Thumb Exception Enable
986735Sgblack@eecs.umich.edu        Bitfield<29> afe; // Access flag enable
996735Sgblack@eecs.umich.edu        Bitfield<28> tre; // TEX Remap bit
1006735Sgblack@eecs.umich.edu        Bitfield<27> nmfi;// Non-maskable fast interrupts enable
1016735Sgblack@eecs.umich.edu        Bitfield<25> ee;  // Exception Endianness bit
1026735Sgblack@eecs.umich.edu        Bitfield<24> ve;  // Interrupt vectors enable
1036735Sgblack@eecs.umich.edu        Bitfield<23> rao1;// Read as one
1046735Sgblack@eecs.umich.edu        Bitfield<22> u;   // Alignment (now unused)
1056735Sgblack@eecs.umich.edu        Bitfield<21> fi;  // Fast interrupts configuration enable
1066735Sgblack@eecs.umich.edu        Bitfield<18> rao2;// Read as one
1076735Sgblack@eecs.umich.edu        Bitfield<17> ha;  // Hardware access flag enable
1086735Sgblack@eecs.umich.edu        Bitfield<16> rao3;// Read as one
1096735Sgblack@eecs.umich.edu        Bitfield<14> rr;  // Round robin cache replacement
1106735Sgblack@eecs.umich.edu        Bitfield<13> v;   // Base address for exception vectors
1116735Sgblack@eecs.umich.edu        Bitfield<12> i;   // instruction cache enable
1126735Sgblack@eecs.umich.edu        Bitfield<11> z;   // branch prediction enable bit
1136735Sgblack@eecs.umich.edu        Bitfield<10> sw;  // Enable swp/swpb
1146735Sgblack@eecs.umich.edu        Bitfield<6,3> rao4;// Read as one
1156735Sgblack@eecs.umich.edu        Bitfield<7>  b;   // Endianness support (unused)
1166735Sgblack@eecs.umich.edu        Bitfield<2>  c;   // Cache enable bit
1176735Sgblack@eecs.umich.edu        Bitfield<1>  a;   // Alignment fault checking
1186735Sgblack@eecs.umich.edu        Bitfield<0>  m;   // MMU enable bit
1196735Sgblack@eecs.umich.edu    EndBitUnion(SCTLR)
1206242Sgblack@eecs.umich.edu};
1216242Sgblack@eecs.umich.edu
1226242Sgblack@eecs.umich.edu#endif // __ARCH_ARM_MISCREGS_HH__
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