miscregs.hh revision 13531
17860SN/A/* 27860SN/A * Copyright (c) 2010-2018 ARM Limited 37860SN/A * All rights reserved 410036SAli.Saidi@ARM.com * 58835SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 610036SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77935SN/A * property including but not limited to intellectual property relating 87935SN/A * to a hardware implementation of the functionality of the software 97935SN/A * licensed hereunder. You may use the software subject to the license 107860SN/A * terms below provided that you ensure that this notice is replicated 117860SN/A * unmodified and in its entirety in all distributions of the software, 127860SN/A * modified or unmodified, in source code or in binary form. 1310315Snilay@cs.wisc.edu * 148835SAli.Saidi@ARM.com * Copyright (c) 2009 The Regents of The University of Michigan 159885Sstever@gmail.com * All rights reserved. 169885Sstever@gmail.com * 1711570SCurtis.Dunham@arm.com * Redistribution and use in source and binary forms, with or without 1810036SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 1911312Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 208835SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 218835SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 2210315Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer in the 238835SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 2410038SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 259481Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 269481Snilay@cs.wisc.edu * this software without specific prior written permission. 278721SN/A * 2810736Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911219Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 308721SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111570SCurtis.Dunham@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211570SCurtis.Dunham@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311570SCurtis.Dunham@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411570SCurtis.Dunham@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 358835SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 368835SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711440SCurtis.Dunham@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811440SCurtis.Dunham@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397935SN/A * 407935SN/A * Authors: Gabe Black 417935SN/A * Giacomo Gabrielli 427935SN/A */ 437935SN/A#ifndef __ARCH_ARM_MISCREGS_HH__ 447935SN/A#define __ARCH_ARM_MISCREGS_HH__ 457935SN/A 468893Ssaidi@eecs.umich.edu#include <bitset> 477860SN/A#include <tuple> 489885Sstever@gmail.com 499885Sstever@gmail.com#include "arch/arm/miscregs_types.hh" 509885Sstever@gmail.com#include "base/compiler.hh" 5110315Snilay@cs.wisc.edu 5210036SAli.Saidi@ARM.comclass ThreadContext; 5310315Snilay@cs.wisc.edu 549885Sstever@gmail.com 559885Sstever@gmail.comnamespace ArmISA 567860SN/A{ 577860SN/A enum MiscRegIndex { 5810038SAli.Saidi@ARM.com MISCREG_CPSR = 0, 5910315Snilay@cs.wisc.edu MISCREG_SPSR, 607860SN/A MISCREG_SPSR_FIQ, 619885Sstever@gmail.com MISCREG_SPSR_IRQ, 627860SN/A MISCREG_SPSR_SVC, 6311570SCurtis.Dunham@arm.com MISCREG_SPSR_MON, 647860SN/A MISCREG_SPSR_ABT, 658835SAli.Saidi@ARM.com MISCREG_SPSR_HYP, 667860SN/A MISCREG_SPSR_UND, 6710038SAli.Saidi@ARM.com MISCREG_ELR_HYP, 687860SN/A MISCREG_FPSID, 6910036SAli.Saidi@ARM.com MISCREG_FPSCR, 707860SN/A MISCREG_MVFR1, 717860SN/A MISCREG_MVFR0, 728835SAli.Saidi@ARM.com MISCREG_FPEXC, 739481Snilay@cs.wisc.edu 7410038SAli.Saidi@ARM.com // Helper registers 757860SN/A MISCREG_CPSR_MODE, 767860SN/A MISCREG_CPSR_Q, 777860SN/A MISCREG_FPSCR_EXC, 787860SN/A MISCREG_FPSCR_QC, 797860SN/A MISCREG_LOCKADDR, 807860SN/A MISCREG_LOCKFLAG, 8111570SCurtis.Dunham@arm.com MISCREG_PRRR_MAIR0, 8211570SCurtis.Dunham@arm.com MISCREG_PRRR_MAIR0_NS, 8311570SCurtis.Dunham@arm.com MISCREG_PRRR_MAIR0_S, 8411570SCurtis.Dunham@arm.com MISCREG_NMRR_MAIR1, 858835SAli.Saidi@ARM.com MISCREG_NMRR_MAIR1_NS, 867860SN/A MISCREG_NMRR_MAIR1_S, 879885Sstever@gmail.com MISCREG_PMXEVTYPER_PMCCFILTR, 8810315Snilay@cs.wisc.edu MISCREG_SCTLR_RST, 899481Snilay@cs.wisc.edu MISCREG_SEV_MAILBOX, 9011960Sgabeblack@google.com 917860SN/A // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) 927860SN/A MISCREG_DBGDIDR, 937860SN/A MISCREG_DBGDSCRint, 947860SN/A MISCREG_DBGDCCINT, 957860SN/A MISCREG_DBGDTRTXint, 967860SN/A MISCREG_DBGDTRRXint, 977860SN/A MISCREG_DBGWFAR, 9811066Snilay@cs.wisc.edu MISCREG_DBGVCR, 999885Sstever@gmail.com MISCREG_DBGDTRRXext, 10011960Sgabeblack@google.com MISCREG_DBGDSCRext, 1017860SN/A MISCREG_DBGDTRTXext, 1029885Sstever@gmail.com MISCREG_DBGOSECCR, 10311219Snilay@cs.wisc.edu MISCREG_DBGBVR0, 10411960Sgabeblack@google.com MISCREG_DBGBVR1, 10511570SCurtis.Dunham@arm.com MISCREG_DBGBVR2, 10610736Snilay@cs.wisc.edu MISCREG_DBGBVR3, 10710036SAli.Saidi@ARM.com MISCREG_DBGBVR4, 10811066Snilay@cs.wisc.edu MISCREG_DBGBVR5, 1097860SN/A MISCREG_DBGBCR0, 1109481Snilay@cs.wisc.edu MISCREG_DBGBCR1, 11111570SCurtis.Dunham@arm.com MISCREG_DBGBCR2, 11211570SCurtis.Dunham@arm.com MISCREG_DBGBCR3, 11311570SCurtis.Dunham@arm.com MISCREG_DBGBCR4, 11411570SCurtis.Dunham@arm.com MISCREG_DBGBCR5, 1157860SN/A MISCREG_DBGWVR0, 1168835SAli.Saidi@ARM.com MISCREG_DBGWVR1, 1179481Snilay@cs.wisc.edu MISCREG_DBGWVR2, 11810036SAli.Saidi@ARM.com MISCREG_DBGWVR3, 1197860SN/A MISCREG_DBGWCR0, 1208835SAli.Saidi@ARM.com MISCREG_DBGWCR1, 12111960Sgabeblack@google.com MISCREG_DBGWCR2, 1229885Sstever@gmail.com MISCREG_DBGWCR3, 1239481Snilay@cs.wisc.edu MISCREG_DBGDRAR, 1247860SN/A MISCREG_DBGBXVR4, 12511219Snilay@cs.wisc.edu MISCREG_DBGBXVR5, 1267860SN/A MISCREG_DBGOSLAR, 1278893Ssaidi@eecs.umich.edu MISCREG_DBGOSLSR, 1287860SN/A MISCREG_DBGOSDLR, 1299885Sstever@gmail.com MISCREG_DBGPRCR, 1309885Sstever@gmail.com MISCREG_DBGDSAR, 1319885Sstever@gmail.com MISCREG_DBGCLAIMSET, 1329885Sstever@gmail.com MISCREG_DBGCLAIMCLR, 1339885Sstever@gmail.com MISCREG_DBGAUTHSTATUS, 13411960Sgabeblack@google.com MISCREG_DBGDEVID2, 13511570SCurtis.Dunham@arm.com MISCREG_DBGDEVID1, 13610036SAli.Saidi@ARM.com MISCREG_DBGDEVID0, 13711570SCurtis.Dunham@arm.com MISCREG_TEECR, // not in ARM DDI 0487A.b+ 13811570SCurtis.Dunham@arm.com MISCREG_JIDR, 13911570SCurtis.Dunham@arm.com MISCREG_TEEHBR, // not in ARM DDI 0487A.b+ 14011570SCurtis.Dunham@arm.com MISCREG_JOSCR, 14110036SAli.Saidi@ARM.com MISCREG_JMCR, 1429885Sstever@gmail.com 14311960Sgabeblack@google.com // AArch32 CP15 registers (system control) 1449885Sstever@gmail.com MISCREG_MIDR, 14510038SAli.Saidi@ARM.com MISCREG_CTR, 14610038SAli.Saidi@ARM.com MISCREG_TCMTR, 14710038SAli.Saidi@ARM.com MISCREG_TLBTR, 14810038SAli.Saidi@ARM.com MISCREG_MPIDR, 14910038SAli.Saidi@ARM.com MISCREG_REVIDR, 15010736Snilay@cs.wisc.edu MISCREG_ID_PFR0, 15110038SAli.Saidi@ARM.com MISCREG_ID_PFR1, 15210038SAli.Saidi@ARM.com MISCREG_ID_DFR0, 15310038SAli.Saidi@ARM.com MISCREG_ID_AFR0, 15410038SAli.Saidi@ARM.com MISCREG_ID_MMFR0, 15510038SAli.Saidi@ARM.com MISCREG_ID_MMFR1, 15610038SAli.Saidi@ARM.com MISCREG_ID_MMFR2, 15710038SAli.Saidi@ARM.com MISCREG_ID_MMFR3, 15810038SAli.Saidi@ARM.com MISCREG_ID_ISAR0, 15910038SAli.Saidi@ARM.com MISCREG_ID_ISAR1, 16010038SAli.Saidi@ARM.com MISCREG_ID_ISAR2, 16110038SAli.Saidi@ARM.com MISCREG_ID_ISAR3, 16210038SAli.Saidi@ARM.com MISCREG_ID_ISAR4, 16310038SAli.Saidi@ARM.com MISCREG_ID_ISAR5, 16411570SCurtis.Dunham@arm.com MISCREG_CCSIDR, 16510038SAli.Saidi@ARM.com MISCREG_CLIDR, 16610038SAli.Saidi@ARM.com MISCREG_AIDR, 16710038SAli.Saidi@ARM.com MISCREG_CSSELR, 16811570SCurtis.Dunham@arm.com MISCREG_CSSELR_NS, 16911570SCurtis.Dunham@arm.com MISCREG_CSSELR_S, 17011570SCurtis.Dunham@arm.com MISCREG_VPIDR, 17111570SCurtis.Dunham@arm.com MISCREG_VMPIDR, 17210038SAli.Saidi@ARM.com MISCREG_SCTLR, 17310038SAli.Saidi@ARM.com MISCREG_SCTLR_NS, 1747860SN/A MISCREG_SCTLR_S, 1757860SN/A MISCREG_ACTLR, 1768835SAli.Saidi@ARM.com MISCREG_ACTLR_NS, 17710036SAli.Saidi@ARM.com MISCREG_ACTLR_S, 17810038SAli.Saidi@ARM.com MISCREG_CPACR, 1797860SN/A MISCREG_SCR, 1808835SAli.Saidi@ARM.com MISCREG_SDER, 1818835SAli.Saidi@ARM.com MISCREG_NSACR, 1828835SAli.Saidi@ARM.com MISCREG_HSCTLR, 1838835SAli.Saidi@ARM.com MISCREG_HACTLR, 1849885Sstever@gmail.com MISCREG_HCR, 18511570SCurtis.Dunham@arm.com MISCREG_HDCR, 18610036SAli.Saidi@ARM.com MISCREG_HCPTR, 18710038SAli.Saidi@ARM.com MISCREG_HSTR, 1889265SAli.Saidi@ARM.com MISCREG_HACR, 18911570SCurtis.Dunham@arm.com MISCREG_TTBR0, 19011570SCurtis.Dunham@arm.com MISCREG_TTBR0_NS, 19111570SCurtis.Dunham@arm.com MISCREG_TTBR0_S, 19211570SCurtis.Dunham@arm.com MISCREG_TTBR1, 1938835SAli.Saidi@ARM.com MISCREG_TTBR1_NS, 1948893Ssaidi@eecs.umich.edu MISCREG_TTBR1_S, 1957860SN/A MISCREG_TTBCR, 1967860SN/A MISCREG_TTBCR_NS, 19711066Snilay@cs.wisc.edu MISCREG_TTBCR_S, 1989885Sstever@gmail.com MISCREG_HTCR, 19911960Sgabeblack@google.com MISCREG_VTCR, 2007860SN/A MISCREG_DACR, 2019885Sstever@gmail.com MISCREG_DACR_NS, 20211219Snilay@cs.wisc.edu MISCREG_DACR_S, 20311960Sgabeblack@google.com MISCREG_DFSR, 20411570SCurtis.Dunham@arm.com MISCREG_DFSR_NS, 20510736Snilay@cs.wisc.edu MISCREG_DFSR_S, 20610036SAli.Saidi@ARM.com MISCREG_IFSR, 20711066Snilay@cs.wisc.edu MISCREG_IFSR_NS, 2087860SN/A MISCREG_IFSR_S, 2099481Snilay@cs.wisc.edu MISCREG_ADFSR, 21011570SCurtis.Dunham@arm.com MISCREG_ADFSR_NS, 21111570SCurtis.Dunham@arm.com MISCREG_ADFSR_S, 21211570SCurtis.Dunham@arm.com MISCREG_AIFSR, 21311570SCurtis.Dunham@arm.com MISCREG_AIFSR_NS, 2147860SN/A MISCREG_AIFSR_S, 2158835SAli.Saidi@ARM.com MISCREG_HADFSR, 2169481Snilay@cs.wisc.edu MISCREG_HAIFSR, 21710036SAli.Saidi@ARM.com MISCREG_HSR, 2187860SN/A MISCREG_DFAR, 2198835SAli.Saidi@ARM.com MISCREG_DFAR_NS, 22011960Sgabeblack@google.com MISCREG_DFAR_S, 2219885Sstever@gmail.com MISCREG_IFAR, 2229481Snilay@cs.wisc.edu MISCREG_IFAR_NS, 2237860SN/A MISCREG_IFAR_S, 22411219Snilay@cs.wisc.edu MISCREG_HDFAR, 2257860SN/A MISCREG_HIFAR, 2268893Ssaidi@eecs.umich.edu MISCREG_HPFAR, 2277860SN/A MISCREG_ICIALLUIS, 2289885Sstever@gmail.com MISCREG_BPIALLIS, 2299885Sstever@gmail.com MISCREG_PAR, 2309885Sstever@gmail.com MISCREG_PAR_NS, 2319885Sstever@gmail.com MISCREG_PAR_S, 2329885Sstever@gmail.com MISCREG_ICIALLU, 23311960Sgabeblack@google.com MISCREG_ICIMVAU, 23411570SCurtis.Dunham@arm.com MISCREG_CP15ISB, 23510036SAli.Saidi@ARM.com MISCREG_BPIALL, 23611570SCurtis.Dunham@arm.com MISCREG_BPIMVA, 23711570SCurtis.Dunham@arm.com MISCREG_DCIMVAC, 23811570SCurtis.Dunham@arm.com MISCREG_DCISW, 23911570SCurtis.Dunham@arm.com MISCREG_ATS1CPR, 24010036SAli.Saidi@ARM.com MISCREG_ATS1CPW, 2419885Sstever@gmail.com MISCREG_ATS1CUR, 24211960Sgabeblack@google.com MISCREG_ATS1CUW, 2439885Sstever@gmail.com MISCREG_ATS12NSOPR, 2448835SAli.Saidi@ARM.com MISCREG_ATS12NSOPW, 2458835SAli.Saidi@ARM.com MISCREG_ATS12NSOUR, 24610036SAli.Saidi@ARM.com MISCREG_ATS12NSOUW, 2478835SAli.Saidi@ARM.com MISCREG_DCCMVAC, 2489481Snilay@cs.wisc.edu MISCREG_DCCSW, 2499481Snilay@cs.wisc.edu MISCREG_CP15DSB, 25011219Snilay@cs.wisc.edu MISCREG_CP15DMB, 25110036SAli.Saidi@ARM.com MISCREG_DCCMVAU, 2529481Snilay@cs.wisc.edu MISCREG_DCCIMVAC, 25310038SAli.Saidi@ARM.com MISCREG_DCCISW, 25410038SAli.Saidi@ARM.com MISCREG_ATS1HR, 25510038SAli.Saidi@ARM.com MISCREG_ATS1HW, 25610038SAli.Saidi@ARM.com MISCREG_TLBIALLIS, 25710038SAli.Saidi@ARM.com MISCREG_TLBIMVAIS, 25810038SAli.Saidi@ARM.com MISCREG_TLBIASIDIS, 25910038SAli.Saidi@ARM.com MISCREG_TLBIMVAAIS, 26010038SAli.Saidi@ARM.com MISCREG_TLBIMVALIS, 2619481Snilay@cs.wisc.edu MISCREG_TLBIMVAALIS, 2629481Snilay@cs.wisc.edu MISCREG_ITLBIALL, 2639481Snilay@cs.wisc.edu MISCREG_ITLBIMVA, 2649481Snilay@cs.wisc.edu MISCREG_ITLBIASID, 2659481Snilay@cs.wisc.edu MISCREG_DTLBIALL, 2669481Snilay@cs.wisc.edu MISCREG_DTLBIMVA, 26710038SAli.Saidi@ARM.com MISCREG_DTLBIASID, 2689481Snilay@cs.wisc.edu MISCREG_TLBIALL, 2699481Snilay@cs.wisc.edu MISCREG_TLBIMVA, 27010038SAli.Saidi@ARM.com MISCREG_TLBIASID, 27110038SAli.Saidi@ARM.com MISCREG_TLBIMVAA, 27210736Snilay@cs.wisc.edu MISCREG_TLBIMVAL, 27310038SAli.Saidi@ARM.com MISCREG_TLBIMVAAL, 27410038SAli.Saidi@ARM.com MISCREG_TLBIIPAS2IS, 27510038SAli.Saidi@ARM.com MISCREG_TLBIIPAS2LIS, 27610038SAli.Saidi@ARM.com MISCREG_TLBIALLHIS, 27710038SAli.Saidi@ARM.com MISCREG_TLBIMVAHIS, 27810038SAli.Saidi@ARM.com MISCREG_TLBIALLNSNHIS, 27910038SAli.Saidi@ARM.com MISCREG_TLBIMVALHIS, 28010736Snilay@cs.wisc.edu MISCREG_TLBIIPAS2, 28110038SAli.Saidi@ARM.com MISCREG_TLBIIPAS2L, 28210038SAli.Saidi@ARM.com MISCREG_TLBIALLH, 28310038SAli.Saidi@ARM.com MISCREG_TLBIMVAH, 28410038SAli.Saidi@ARM.com MISCREG_TLBIALLNSNH, 28510038SAli.Saidi@ARM.com MISCREG_TLBIMVALH, 28610038SAli.Saidi@ARM.com MISCREG_PMCR, 28710038SAli.Saidi@ARM.com MISCREG_PMCNTENSET, 28810038SAli.Saidi@ARM.com MISCREG_PMCNTENCLR, 28910038SAli.Saidi@ARM.com MISCREG_PMOVSR, 29010038SAli.Saidi@ARM.com MISCREG_PMSWINC, 29110038SAli.Saidi@ARM.com MISCREG_PMSELR, 29210038SAli.Saidi@ARM.com MISCREG_PMCEID0, 29310038SAli.Saidi@ARM.com MISCREG_PMCEID1, 29411570SCurtis.Dunham@arm.com MISCREG_PMCCNTR, 29510038SAli.Saidi@ARM.com MISCREG_PMXEVTYPER, 29610038SAli.Saidi@ARM.com MISCREG_PMCCFILTR, 29710038SAli.Saidi@ARM.com MISCREG_PMXEVCNTR, 29811570SCurtis.Dunham@arm.com MISCREG_PMUSERENR, 29911570SCurtis.Dunham@arm.com MISCREG_PMINTENSET, 30011570SCurtis.Dunham@arm.com MISCREG_PMINTENCLR, 30111570SCurtis.Dunham@arm.com MISCREG_PMOVSSET, 30210038SAli.Saidi@ARM.com MISCREG_L2CTLR, 3039481Snilay@cs.wisc.edu MISCREG_L2ECTLR, 3047860SN/A MISCREG_PRRR, 3057860SN/A MISCREG_PRRR_NS, 3068835SAli.Saidi@ARM.com MISCREG_PRRR_S, 30710036SAli.Saidi@ARM.com MISCREG_MAIR0, 30810038SAli.Saidi@ARM.com MISCREG_MAIR0_NS, 3097860SN/A MISCREG_MAIR0_S, 3108835SAli.Saidi@ARM.com MISCREG_NMRR, 3118835SAli.Saidi@ARM.com MISCREG_NMRR_NS, 3128835SAli.Saidi@ARM.com MISCREG_NMRR_S, 3138835SAli.Saidi@ARM.com MISCREG_MAIR1, 3149885Sstever@gmail.com MISCREG_MAIR1_NS, 31511570SCurtis.Dunham@arm.com MISCREG_MAIR1_S, 31610036SAli.Saidi@ARM.com MISCREG_AMAIR0, 31710038SAli.Saidi@ARM.com MISCREG_AMAIR0_NS, 3189265SAli.Saidi@ARM.com MISCREG_AMAIR0_S, 31911570SCurtis.Dunham@arm.com MISCREG_AMAIR1, 32011570SCurtis.Dunham@arm.com MISCREG_AMAIR1_NS, 32111570SCurtis.Dunham@arm.com MISCREG_AMAIR1_S, 32211570SCurtis.Dunham@arm.com MISCREG_HMAIR0, 3238835SAli.Saidi@ARM.com MISCREG_HMAIR1, 3248893Ssaidi@eecs.umich.edu MISCREG_HAMAIR0, 3257860SN/A MISCREG_HAMAIR1, 3267860SN/A MISCREG_VBAR, 32711066Snilay@cs.wisc.edu MISCREG_VBAR_NS, 3289885Sstever@gmail.com MISCREG_VBAR_S, 32911960Sgabeblack@google.com MISCREG_MVBAR, 3309481Snilay@cs.wisc.edu MISCREG_RMR, 3319885Sstever@gmail.com MISCREG_ISR, 33211219Snilay@cs.wisc.edu MISCREG_HVBAR, 33311960Sgabeblack@google.com MISCREG_FCSEIDR, 33411570SCurtis.Dunham@arm.com MISCREG_CONTEXTIDR, 33510736Snilay@cs.wisc.edu MISCREG_CONTEXTIDR_NS, 33610036SAli.Saidi@ARM.com MISCREG_CONTEXTIDR_S, 33711066Snilay@cs.wisc.edu MISCREG_TPIDRURW, 3387860SN/A MISCREG_TPIDRURW_NS, 3399481Snilay@cs.wisc.edu MISCREG_TPIDRURW_S, 34011570SCurtis.Dunham@arm.com MISCREG_TPIDRURO, 34111570SCurtis.Dunham@arm.com MISCREG_TPIDRURO_NS, 34211570SCurtis.Dunham@arm.com MISCREG_TPIDRURO_S, 34311570SCurtis.Dunham@arm.com MISCREG_TPIDRPRW, 3447860SN/A MISCREG_TPIDRPRW_NS, 3458835SAli.Saidi@ARM.com MISCREG_TPIDRPRW_S, 3469481Snilay@cs.wisc.edu MISCREG_HTPIDR, 34710036SAli.Saidi@ARM.com MISCREG_CNTFRQ, 3487860SN/A MISCREG_CNTKCTL, 3498835SAli.Saidi@ARM.com MISCREG_CNTP_TVAL, 35011960Sgabeblack@google.com MISCREG_CNTP_TVAL_NS, 3519885Sstever@gmail.com MISCREG_CNTP_TVAL_S, 3529481Snilay@cs.wisc.edu MISCREG_CNTP_CTL, 3537860SN/A MISCREG_CNTP_CTL_NS, 35411219Snilay@cs.wisc.edu MISCREG_CNTP_CTL_S, 3558893Ssaidi@eecs.umich.edu MISCREG_CNTV_TVAL, 3568893Ssaidi@eecs.umich.edu MISCREG_CNTV_CTL, 3577860SN/A MISCREG_CNTHCTL, 3589885Sstever@gmail.com MISCREG_CNTHP_TVAL, 3599885Sstever@gmail.com MISCREG_CNTHP_CTL, 3609885Sstever@gmail.com MISCREG_IL1DATA0, 3619885Sstever@gmail.com MISCREG_IL1DATA1, 3629885Sstever@gmail.com MISCREG_IL1DATA2, 36311960Sgabeblack@google.com MISCREG_IL1DATA3, 36411570SCurtis.Dunham@arm.com MISCREG_DL1DATA0, 36510036SAli.Saidi@ARM.com MISCREG_DL1DATA1, 36611570SCurtis.Dunham@arm.com MISCREG_DL1DATA2, 36711570SCurtis.Dunham@arm.com MISCREG_DL1DATA3, 36811570SCurtis.Dunham@arm.com MISCREG_DL1DATA4, 36911570SCurtis.Dunham@arm.com MISCREG_RAMINDEX, 37010036SAli.Saidi@ARM.com MISCREG_L2ACTLR, 3719885Sstever@gmail.com MISCREG_CBAR, 37211960Sgabeblack@google.com MISCREG_HTTBR, 3739885Sstever@gmail.com MISCREG_VTTBR, 3747860SN/A MISCREG_CNTPCT, 37510451Snilay@cs.wisc.edu MISCREG_CNTVCT, 37611219Snilay@cs.wisc.edu MISCREG_CNTP_CVAL, 3779885Sstever@gmail.com MISCREG_CNTP_CVAL_NS, 37811570SCurtis.Dunham@arm.com MISCREG_CNTP_CVAL_S, 37910036SAli.Saidi@ARM.com MISCREG_CNTV_CVAL, 38010736Snilay@cs.wisc.edu MISCREG_CNTVOFF, 38110736Snilay@cs.wisc.edu MISCREG_CNTHP_CVAL, 38211570SCurtis.Dunham@arm.com MISCREG_CPUMERRSR, 38311570SCurtis.Dunham@arm.com MISCREG_L2MERRSR, 38411570SCurtis.Dunham@arm.com 38511440SCurtis.Dunham@arm.com // AArch64 registers (Op0=2) 38611570SCurtis.Dunham@arm.com MISCREG_MDCCINT_EL1, 38710736Snilay@cs.wisc.edu MISCREG_OSDTRRX_EL1, 38811219Snilay@cs.wisc.edu MISCREG_MDSCR_EL1, 38910736Snilay@cs.wisc.edu MISCREG_OSDTRTX_EL1, 3909885Sstever@gmail.com MISCREG_OSECCR_EL1, 3917860SN/A MISCREG_DBGBVR0_EL1, 3929481Snilay@cs.wisc.edu MISCREG_DBGBVR1_EL1, 3938893Ssaidi@eecs.umich.edu MISCREG_DBGBVR2_EL1, 39410736Snilay@cs.wisc.edu MISCREG_DBGBVR3_EL1, 3957860SN/A MISCREG_DBGBVR4_EL1, 39611219Snilay@cs.wisc.edu MISCREG_DBGBVR5_EL1, 39711219Snilay@cs.wisc.edu MISCREG_DBGBCR0_EL1, 39811219Snilay@cs.wisc.edu MISCREG_DBGBCR1_EL1, 39911219Snilay@cs.wisc.edu MISCREG_DBGBCR2_EL1, 40011219Snilay@cs.wisc.edu MISCREG_DBGBCR3_EL1, 40111219Snilay@cs.wisc.edu MISCREG_DBGBCR4_EL1, 40211219Snilay@cs.wisc.edu MISCREG_DBGBCR5_EL1, 4037860SN/A MISCREG_DBGWVR0_EL1, 4047860SN/A MISCREG_DBGWVR1_EL1, 40510036SAli.Saidi@ARM.com MISCREG_DBGWVR2_EL1, 4067860SN/A MISCREG_DBGWVR3_EL1, 4077860SN/A MISCREG_DBGWCR0_EL1, 40811960Sgabeblack@google.com MISCREG_DBGWCR1_EL1, 4097860SN/A MISCREG_DBGWCR2_EL1, 4107860SN/A MISCREG_DBGWCR3_EL1, 41110736Snilay@cs.wisc.edu MISCREG_MDCCSR_EL0, 4127860SN/A MISCREG_MDDTR_EL0, 4137860SN/A MISCREG_MDDTRTX_EL0, 4147860SN/A MISCREG_MDDTRRX_EL0, 4157860SN/A MISCREG_DBGVCR32_EL2, 41610036SAli.Saidi@ARM.com MISCREG_MDRAR_EL1, 41711960Sgabeblack@google.com MISCREG_OSLAR_EL1, 4187860SN/A MISCREG_OSLSR_EL1, 4197860SN/A MISCREG_OSDLR_EL1, 42010736Snilay@cs.wisc.edu MISCREG_DBGPRCR_EL1, 42111960Sgabeblack@google.com MISCREG_DBGCLAIMSET_EL1, 4227860SN/A MISCREG_DBGCLAIMCLR_EL1, 42311960Sgabeblack@google.com MISCREG_DBGAUTHSTATUS_EL1, 4247860SN/A MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+ 42511960Sgabeblack@google.com MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+ 4267860SN/A 4277860SN/A // AArch64 registers (Op0=1,3) 4287860SN/A MISCREG_MIDR_EL1, 42910451Snilay@cs.wisc.edu MISCREG_MPIDR_EL1, 4307860SN/A MISCREG_REVIDR_EL1, 4319885Sstever@gmail.com MISCREG_ID_PFR0_EL1, 4329885Sstever@gmail.com MISCREG_ID_PFR1_EL1, 4339885Sstever@gmail.com MISCREG_ID_DFR0_EL1, 43410315Snilay@cs.wisc.edu MISCREG_ID_AFR0_EL1, 43510036SAli.Saidi@ARM.com MISCREG_ID_MMFR0_EL1, 43610315Snilay@cs.wisc.edu MISCREG_ID_MMFR1_EL1, 4379885Sstever@gmail.com MISCREG_ID_MMFR2_EL1, 4389885Sstever@gmail.com MISCREG_ID_MMFR3_EL1, 43910315Snilay@cs.wisc.edu MISCREG_ID_ISAR0_EL1, 44010315Snilay@cs.wisc.edu MISCREG_ID_ISAR1_EL1, 44110315Snilay@cs.wisc.edu MISCREG_ID_ISAR2_EL1, 44210315Snilay@cs.wisc.edu MISCREG_ID_ISAR3_EL1, 44310315Snilay@cs.wisc.edu MISCREG_ID_ISAR4_EL1, 44410315Snilay@cs.wisc.edu MISCREG_ID_ISAR5_EL1, 44510315Snilay@cs.wisc.edu MISCREG_MVFR0_EL1, 44610315Snilay@cs.wisc.edu MISCREG_MVFR1_EL1, 4477860SN/A MISCREG_MVFR2_EL1, 44810451Snilay@cs.wisc.edu MISCREG_ID_AA64PFR0_EL1, 44911960Sgabeblack@google.com MISCREG_ID_AA64PFR1_EL1, 4509885Sstever@gmail.com MISCREG_ID_AA64DFR0_EL1, 45111570SCurtis.Dunham@arm.com MISCREG_ID_AA64DFR1_EL1, 45210036SAli.Saidi@ARM.com MISCREG_ID_AA64AFR0_EL1, 45310736Snilay@cs.wisc.edu MISCREG_ID_AA64AFR1_EL1, 45410736Snilay@cs.wisc.edu MISCREG_ID_AA64ISAR0_EL1, 45511570SCurtis.Dunham@arm.com MISCREG_ID_AA64ISAR1_EL1, 45611570SCurtis.Dunham@arm.com MISCREG_ID_AA64MMFR0_EL1, 45711570SCurtis.Dunham@arm.com MISCREG_ID_AA64MMFR1_EL1, 45811440SCurtis.Dunham@arm.com MISCREG_CCSIDR_EL1, 45911570SCurtis.Dunham@arm.com MISCREG_CLIDR_EL1, 46010736Snilay@cs.wisc.edu MISCREG_AIDR_EL1, 46111960Sgabeblack@google.com MISCREG_CSSELR_EL1, 46210736Snilay@cs.wisc.edu MISCREG_CTR_EL0, 4639885Sstever@gmail.com MISCREG_DCZID_EL0, 4647860SN/A MISCREG_VPIDR_EL2, 46510736Snilay@cs.wisc.edu MISCREG_VMPIDR_EL2, 4669265SAli.Saidi@ARM.com MISCREG_SCTLR_EL1, 4678893Ssaidi@eecs.umich.edu MISCREG_ACTLR_EL1, 4687860SN/A MISCREG_CPACR_EL1, 46911960Sgabeblack@google.com MISCREG_SCTLR_EL2, 47011960Sgabeblack@google.com MISCREG_ACTLR_EL2, 47111960Sgabeblack@google.com MISCREG_HCR_EL2, 47211960Sgabeblack@google.com MISCREG_MDCR_EL2, 47311960Sgabeblack@google.com MISCREG_CPTR_EL2, 47411960Sgabeblack@google.com MISCREG_HSTR_EL2, 47511960Sgabeblack@google.com MISCREG_HACR_EL2, 4767860SN/A MISCREG_SCTLR_EL3, 4778983Snate@binkert.org MISCREG_ACTLR_EL3, 4789265SAli.Saidi@ARM.com MISCREG_SCR_EL3, 4799885Sstever@gmail.com MISCREG_SDER32_EL3, 4809885Sstever@gmail.com MISCREG_CPTR_EL3, 48111570SCurtis.Dunham@arm.com MISCREG_MDCR_EL3, 48210036SAli.Saidi@ARM.com MISCREG_TTBR0_EL1, 4838983Snate@binkert.org MISCREG_TTBR1_EL1, 48411960Sgabeblack@google.com MISCREG_TCR_EL1, 4857860SN/A MISCREG_TTBR0_EL2, 4867860SN/A MISCREG_TCR_EL2, 4877860SN/A MISCREG_VTTBR_EL2, 48811570SCurtis.Dunham@arm.com MISCREG_VTCR_EL2, 48911570SCurtis.Dunham@arm.com MISCREG_TTBR0_EL3, 49011570SCurtis.Dunham@arm.com MISCREG_TCR_EL3, 49111570SCurtis.Dunham@arm.com MISCREG_DACR32_EL2, 49211960Sgabeblack@google.com MISCREG_SPSR_EL1, 4938893Ssaidi@eecs.umich.edu MISCREG_ELR_EL1, 4947860SN/A MISCREG_SP_EL0, 4959885Sstever@gmail.com MISCREG_SPSEL, 4969885Sstever@gmail.com MISCREG_CURRENTEL, 49710036SAli.Saidi@ARM.com MISCREG_NZCV, 4989885Sstever@gmail.com MISCREG_DAIF, 4999885Sstever@gmail.com MISCREG_FPCR, 500 MISCREG_FPSR, 501 MISCREG_DSPSR_EL0, 502 MISCREG_DLR_EL0, 503 MISCREG_SPSR_EL2, 504 MISCREG_ELR_EL2, 505 MISCREG_SP_EL1, 506 MISCREG_SPSR_IRQ_AA64, 507 MISCREG_SPSR_ABT_AA64, 508 MISCREG_SPSR_UND_AA64, 509 MISCREG_SPSR_FIQ_AA64, 510 MISCREG_SPSR_EL3, 511 MISCREG_ELR_EL3, 512 MISCREG_SP_EL2, 513 MISCREG_AFSR0_EL1, 514 MISCREG_AFSR1_EL1, 515 MISCREG_ESR_EL1, 516 MISCREG_IFSR32_EL2, 517 MISCREG_AFSR0_EL2, 518 MISCREG_AFSR1_EL2, 519 MISCREG_ESR_EL2, 520 MISCREG_FPEXC32_EL2, 521 MISCREG_AFSR0_EL3, 522 MISCREG_AFSR1_EL3, 523 MISCREG_ESR_EL3, 524 MISCREG_FAR_EL1, 525 MISCREG_FAR_EL2, 526 MISCREG_HPFAR_EL2, 527 MISCREG_FAR_EL3, 528 MISCREG_IC_IALLUIS, 529 MISCREG_PAR_EL1, 530 MISCREG_IC_IALLU, 531 MISCREG_DC_IVAC_Xt, 532 MISCREG_DC_ISW_Xt, 533 MISCREG_AT_S1E1R_Xt, 534 MISCREG_AT_S1E1W_Xt, 535 MISCREG_AT_S1E0R_Xt, 536 MISCREG_AT_S1E0W_Xt, 537 MISCREG_DC_CSW_Xt, 538 MISCREG_DC_CISW_Xt, 539 MISCREG_DC_ZVA_Xt, 540 MISCREG_IC_IVAU_Xt, 541 MISCREG_DC_CVAC_Xt, 542 MISCREG_DC_CVAU_Xt, 543 MISCREG_DC_CIVAC_Xt, 544 MISCREG_AT_S1E2R_Xt, 545 MISCREG_AT_S1E2W_Xt, 546 MISCREG_AT_S12E1R_Xt, 547 MISCREG_AT_S12E1W_Xt, 548 MISCREG_AT_S12E0R_Xt, 549 MISCREG_AT_S12E0W_Xt, 550 MISCREG_AT_S1E3R_Xt, 551 MISCREG_AT_S1E3W_Xt, 552 MISCREG_TLBI_VMALLE1IS, 553 MISCREG_TLBI_VAE1IS_Xt, 554 MISCREG_TLBI_ASIDE1IS_Xt, 555 MISCREG_TLBI_VAAE1IS_Xt, 556 MISCREG_TLBI_VALE1IS_Xt, 557 MISCREG_TLBI_VAALE1IS_Xt, 558 MISCREG_TLBI_VMALLE1, 559 MISCREG_TLBI_VAE1_Xt, 560 MISCREG_TLBI_ASIDE1_Xt, 561 MISCREG_TLBI_VAAE1_Xt, 562 MISCREG_TLBI_VALE1_Xt, 563 MISCREG_TLBI_VAALE1_Xt, 564 MISCREG_TLBI_IPAS2E1IS_Xt, 565 MISCREG_TLBI_IPAS2LE1IS_Xt, 566 MISCREG_TLBI_ALLE2IS, 567 MISCREG_TLBI_VAE2IS_Xt, 568 MISCREG_TLBI_ALLE1IS, 569 MISCREG_TLBI_VALE2IS_Xt, 570 MISCREG_TLBI_VMALLS12E1IS, 571 MISCREG_TLBI_IPAS2E1_Xt, 572 MISCREG_TLBI_IPAS2LE1_Xt, 573 MISCREG_TLBI_ALLE2, 574 MISCREG_TLBI_VAE2_Xt, 575 MISCREG_TLBI_ALLE1, 576 MISCREG_TLBI_VALE2_Xt, 577 MISCREG_TLBI_VMALLS12E1, 578 MISCREG_TLBI_ALLE3IS, 579 MISCREG_TLBI_VAE3IS_Xt, 580 MISCREG_TLBI_VALE3IS_Xt, 581 MISCREG_TLBI_ALLE3, 582 MISCREG_TLBI_VAE3_Xt, 583 MISCREG_TLBI_VALE3_Xt, 584 MISCREG_PMINTENSET_EL1, 585 MISCREG_PMINTENCLR_EL1, 586 MISCREG_PMCR_EL0, 587 MISCREG_PMCNTENSET_EL0, 588 MISCREG_PMCNTENCLR_EL0, 589 MISCREG_PMOVSCLR_EL0, 590 MISCREG_PMSWINC_EL0, 591 MISCREG_PMSELR_EL0, 592 MISCREG_PMCEID0_EL0, 593 MISCREG_PMCEID1_EL0, 594 MISCREG_PMCCNTR_EL0, 595 MISCREG_PMXEVTYPER_EL0, 596 MISCREG_PMCCFILTR_EL0, 597 MISCREG_PMXEVCNTR_EL0, 598 MISCREG_PMUSERENR_EL0, 599 MISCREG_PMOVSSET_EL0, 600 MISCREG_MAIR_EL1, 601 MISCREG_AMAIR_EL1, 602 MISCREG_MAIR_EL2, 603 MISCREG_AMAIR_EL2, 604 MISCREG_MAIR_EL3, 605 MISCREG_AMAIR_EL3, 606 MISCREG_L2CTLR_EL1, 607 MISCREG_L2ECTLR_EL1, 608 MISCREG_VBAR_EL1, 609 MISCREG_RVBAR_EL1, 610 MISCREG_ISR_EL1, 611 MISCREG_VBAR_EL2, 612 MISCREG_RVBAR_EL2, 613 MISCREG_VBAR_EL3, 614 MISCREG_RVBAR_EL3, 615 MISCREG_RMR_EL3, 616 MISCREG_CONTEXTIDR_EL1, 617 MISCREG_TPIDR_EL1, 618 MISCREG_TPIDR_EL0, 619 MISCREG_TPIDRRO_EL0, 620 MISCREG_TPIDR_EL2, 621 MISCREG_TPIDR_EL3, 622 MISCREG_CNTKCTL_EL1, 623 MISCREG_CNTFRQ_EL0, 624 MISCREG_CNTPCT_EL0, 625 MISCREG_CNTVCT_EL0, 626 MISCREG_CNTP_TVAL_EL0, 627 MISCREG_CNTP_CTL_EL0, 628 MISCREG_CNTP_CVAL_EL0, 629 MISCREG_CNTV_TVAL_EL0, 630 MISCREG_CNTV_CTL_EL0, 631 MISCREG_CNTV_CVAL_EL0, 632 MISCREG_PMEVCNTR0_EL0, 633 MISCREG_PMEVCNTR1_EL0, 634 MISCREG_PMEVCNTR2_EL0, 635 MISCREG_PMEVCNTR3_EL0, 636 MISCREG_PMEVCNTR4_EL0, 637 MISCREG_PMEVCNTR5_EL0, 638 MISCREG_PMEVTYPER0_EL0, 639 MISCREG_PMEVTYPER1_EL0, 640 MISCREG_PMEVTYPER2_EL0, 641 MISCREG_PMEVTYPER3_EL0, 642 MISCREG_PMEVTYPER4_EL0, 643 MISCREG_PMEVTYPER5_EL0, 644 MISCREG_CNTVOFF_EL2, 645 MISCREG_CNTHCTL_EL2, 646 MISCREG_CNTHP_TVAL_EL2, 647 MISCREG_CNTHP_CTL_EL2, 648 MISCREG_CNTHP_CVAL_EL2, 649 MISCREG_CNTPS_TVAL_EL1, 650 MISCREG_CNTPS_CTL_EL1, 651 MISCREG_CNTPS_CVAL_EL1, 652 MISCREG_IL1DATA0_EL1, 653 MISCREG_IL1DATA1_EL1, 654 MISCREG_IL1DATA2_EL1, 655 MISCREG_IL1DATA3_EL1, 656 MISCREG_DL1DATA0_EL1, 657 MISCREG_DL1DATA1_EL1, 658 MISCREG_DL1DATA2_EL1, 659 MISCREG_DL1DATA3_EL1, 660 MISCREG_DL1DATA4_EL1, 661 MISCREG_L2ACTLR_EL1, 662 MISCREG_CPUACTLR_EL1, 663 MISCREG_CPUECTLR_EL1, 664 MISCREG_CPUMERRSR_EL1, 665 MISCREG_L2MERRSR_EL1, 666 MISCREG_CBAR_EL1, 667 MISCREG_CONTEXTIDR_EL2, 668 669 // Introduced in ARMv8.1 670 MISCREG_TTBR1_EL2, 671 MISCREG_CNTHV_CTL_EL2, 672 MISCREG_CNTHV_CVAL_EL2, 673 MISCREG_CNTHV_TVAL_EL2, 674 675 MISCREG_ID_AA64MMFR2_EL1, 676 677 // GICv3, CPU interface 678 MISCREG_ICC_PMR_EL1, 679 MISCREG_ICC_IAR0_EL1, 680 MISCREG_ICC_EOIR0_EL1, 681 MISCREG_ICC_HPPIR0_EL1, 682 MISCREG_ICC_BPR0_EL1, 683 MISCREG_ICC_AP0R0_EL1, 684 MISCREG_ICC_AP0R1_EL1, 685 MISCREG_ICC_AP0R2_EL1, 686 MISCREG_ICC_AP0R3_EL1, 687 MISCREG_ICC_AP1R0_EL1, 688 MISCREG_ICC_AP1R0_EL1_NS, 689 MISCREG_ICC_AP1R0_EL1_S, 690 MISCREG_ICC_AP1R1_EL1, 691 MISCREG_ICC_AP1R1_EL1_NS, 692 MISCREG_ICC_AP1R1_EL1_S, 693 MISCREG_ICC_AP1R2_EL1, 694 MISCREG_ICC_AP1R2_EL1_NS, 695 MISCREG_ICC_AP1R2_EL1_S, 696 MISCREG_ICC_AP1R3_EL1, 697 MISCREG_ICC_AP1R3_EL1_NS, 698 MISCREG_ICC_AP1R3_EL1_S, 699 MISCREG_ICC_DIR_EL1, 700 MISCREG_ICC_RPR_EL1, 701 MISCREG_ICC_SGI1R_EL1, 702 MISCREG_ICC_ASGI1R_EL1, 703 MISCREG_ICC_SGI0R_EL1, 704 MISCREG_ICC_IAR1_EL1, 705 MISCREG_ICC_EOIR1_EL1, 706 MISCREG_ICC_HPPIR1_EL1, 707 MISCREG_ICC_BPR1_EL1, 708 MISCREG_ICC_BPR1_EL1_NS, 709 MISCREG_ICC_BPR1_EL1_S, 710 MISCREG_ICC_CTLR_EL1, 711 MISCREG_ICC_CTLR_EL1_NS, 712 MISCREG_ICC_CTLR_EL1_S, 713 MISCREG_ICC_SRE_EL1, 714 MISCREG_ICC_SRE_EL1_NS, 715 MISCREG_ICC_SRE_EL1_S, 716 MISCREG_ICC_IGRPEN0_EL1, 717 MISCREG_ICC_IGRPEN1_EL1, 718 MISCREG_ICC_IGRPEN1_EL1_NS, 719 MISCREG_ICC_IGRPEN1_EL1_S, 720 MISCREG_ICC_SRE_EL2, 721 MISCREG_ICC_CTLR_EL3, 722 MISCREG_ICC_SRE_EL3, 723 MISCREG_ICC_IGRPEN1_EL3, 724 725 // GICv3, CPU interface, virtualization 726 MISCREG_ICH_AP0R0_EL2, 727 MISCREG_ICH_AP0R1_EL2, 728 MISCREG_ICH_AP0R2_EL2, 729 MISCREG_ICH_AP0R3_EL2, 730 MISCREG_ICH_AP1R0_EL2, 731 MISCREG_ICH_AP1R1_EL2, 732 MISCREG_ICH_AP1R2_EL2, 733 MISCREG_ICH_AP1R3_EL2, 734 MISCREG_ICH_HCR_EL2, 735 MISCREG_ICH_VTR_EL2, 736 MISCREG_ICH_MISR_EL2, 737 MISCREG_ICH_EISR_EL2, 738 MISCREG_ICH_ELRSR_EL2, 739 MISCREG_ICH_VMCR_EL2, 740 MISCREG_ICH_LR0_EL2, 741 MISCREG_ICH_LR1_EL2, 742 MISCREG_ICH_LR2_EL2, 743 MISCREG_ICH_LR3_EL2, 744 MISCREG_ICH_LR4_EL2, 745 MISCREG_ICH_LR5_EL2, 746 MISCREG_ICH_LR6_EL2, 747 MISCREG_ICH_LR7_EL2, 748 MISCREG_ICH_LR8_EL2, 749 MISCREG_ICH_LR9_EL2, 750 MISCREG_ICH_LR10_EL2, 751 MISCREG_ICH_LR11_EL2, 752 MISCREG_ICH_LR12_EL2, 753 MISCREG_ICH_LR13_EL2, 754 MISCREG_ICH_LR14_EL2, 755 MISCREG_ICH_LR15_EL2, 756 757 MISCREG_ICV_PMR_EL1, 758 MISCREG_ICV_IAR0_EL1, 759 MISCREG_ICV_EOIR0_EL1, 760 MISCREG_ICV_HPPIR0_EL1, 761 MISCREG_ICV_BPR0_EL1, 762 MISCREG_ICV_AP0R0_EL1, 763 MISCREG_ICV_AP0R1_EL1, 764 MISCREG_ICV_AP0R2_EL1, 765 MISCREG_ICV_AP0R3_EL1, 766 MISCREG_ICV_AP1R0_EL1, 767 MISCREG_ICV_AP1R0_EL1_NS, 768 MISCREG_ICV_AP1R0_EL1_S, 769 MISCREG_ICV_AP1R1_EL1, 770 MISCREG_ICV_AP1R1_EL1_NS, 771 MISCREG_ICV_AP1R1_EL1_S, 772 MISCREG_ICV_AP1R2_EL1, 773 MISCREG_ICV_AP1R2_EL1_NS, 774 MISCREG_ICV_AP1R2_EL1_S, 775 MISCREG_ICV_AP1R3_EL1, 776 MISCREG_ICV_AP1R3_EL1_NS, 777 MISCREG_ICV_AP1R3_EL1_S, 778 MISCREG_ICV_DIR_EL1, 779 MISCREG_ICV_RPR_EL1, 780 MISCREG_ICV_SGI1R_EL1, 781 MISCREG_ICV_ASGI1R_EL1, 782 MISCREG_ICV_SGI0R_EL1, 783 MISCREG_ICV_IAR1_EL1, 784 MISCREG_ICV_EOIR1_EL1, 785 MISCREG_ICV_HPPIR1_EL1, 786 MISCREG_ICV_BPR1_EL1, 787 MISCREG_ICV_BPR1_EL1_NS, 788 MISCREG_ICV_BPR1_EL1_S, 789 MISCREG_ICV_CTLR_EL1, 790 MISCREG_ICV_CTLR_EL1_NS, 791 MISCREG_ICV_CTLR_EL1_S, 792 MISCREG_ICV_SRE_EL1, 793 MISCREG_ICV_SRE_EL1_NS, 794 MISCREG_ICV_SRE_EL1_S, 795 MISCREG_ICV_IGRPEN0_EL1, 796 MISCREG_ICV_IGRPEN1_EL1, 797 MISCREG_ICV_IGRPEN1_EL1_NS, 798 MISCREG_ICV_IGRPEN1_EL1_S, 799 800 MISCREG_ICC_AP0R0, 801 MISCREG_ICC_AP0R1, 802 MISCREG_ICC_AP0R2, 803 MISCREG_ICC_AP0R3, 804 MISCREG_ICC_AP1R0, 805 MISCREG_ICC_AP1R0_NS, 806 MISCREG_ICC_AP1R0_S, 807 MISCREG_ICC_AP1R1, 808 MISCREG_ICC_AP1R1_NS, 809 MISCREG_ICC_AP1R1_S, 810 MISCREG_ICC_AP1R2, 811 MISCREG_ICC_AP1R2_NS, 812 MISCREG_ICC_AP1R2_S, 813 MISCREG_ICC_AP1R3, 814 MISCREG_ICC_AP1R3_NS, 815 MISCREG_ICC_AP1R3_S, 816 MISCREG_ICC_ASGI1R, 817 MISCREG_ICC_BPR0, 818 MISCREG_ICC_BPR1, 819 MISCREG_ICC_BPR1_NS, 820 MISCREG_ICC_BPR1_S, 821 MISCREG_ICC_CTLR, 822 MISCREG_ICC_CTLR_NS, 823 MISCREG_ICC_CTLR_S, 824 MISCREG_ICC_DIR, 825 MISCREG_ICC_EOIR0, 826 MISCREG_ICC_EOIR1, 827 MISCREG_ICC_HPPIR0, 828 MISCREG_ICC_HPPIR1, 829 MISCREG_ICC_HSRE, 830 MISCREG_ICC_IAR0, 831 MISCREG_ICC_IAR1, 832 MISCREG_ICC_IGRPEN0, 833 MISCREG_ICC_IGRPEN1, 834 MISCREG_ICC_IGRPEN1_NS, 835 MISCREG_ICC_IGRPEN1_S, 836 MISCREG_ICC_MCTLR, 837 MISCREG_ICC_MGRPEN1, 838 MISCREG_ICC_MSRE, 839 MISCREG_ICC_PMR, 840 MISCREG_ICC_RPR, 841 MISCREG_ICC_SGI0R, 842 MISCREG_ICC_SGI1R, 843 MISCREG_ICC_SRE, 844 MISCREG_ICC_SRE_NS, 845 MISCREG_ICC_SRE_S, 846 847 MISCREG_ICH_AP0R0, 848 MISCREG_ICH_AP0R1, 849 MISCREG_ICH_AP0R2, 850 MISCREG_ICH_AP0R3, 851 MISCREG_ICH_AP1R0, 852 MISCREG_ICH_AP1R1, 853 MISCREG_ICH_AP1R2, 854 MISCREG_ICH_AP1R3, 855 MISCREG_ICH_HCR, 856 MISCREG_ICH_VTR, 857 MISCREG_ICH_MISR, 858 MISCREG_ICH_EISR, 859 MISCREG_ICH_ELRSR, 860 MISCREG_ICH_VMCR, 861 MISCREG_ICH_LR0, 862 MISCREG_ICH_LR1, 863 MISCREG_ICH_LR2, 864 MISCREG_ICH_LR3, 865 MISCREG_ICH_LR4, 866 MISCREG_ICH_LR5, 867 MISCREG_ICH_LR6, 868 MISCREG_ICH_LR7, 869 MISCREG_ICH_LR8, 870 MISCREG_ICH_LR9, 871 MISCREG_ICH_LR10, 872 MISCREG_ICH_LR11, 873 MISCREG_ICH_LR12, 874 MISCREG_ICH_LR13, 875 MISCREG_ICH_LR14, 876 MISCREG_ICH_LR15, 877 MISCREG_ICH_LRC0, 878 MISCREG_ICH_LRC1, 879 MISCREG_ICH_LRC2, 880 MISCREG_ICH_LRC3, 881 MISCREG_ICH_LRC4, 882 MISCREG_ICH_LRC5, 883 MISCREG_ICH_LRC6, 884 MISCREG_ICH_LRC7, 885 MISCREG_ICH_LRC8, 886 MISCREG_ICH_LRC9, 887 MISCREG_ICH_LRC10, 888 MISCREG_ICH_LRC11, 889 MISCREG_ICH_LRC12, 890 MISCREG_ICH_LRC13, 891 MISCREG_ICH_LRC14, 892 MISCREG_ICH_LRC15, 893 894 // These MISCREG_FREESLOT are available Misc Register 895 // slots for future registers to be implemented. 896 MISCREG_FREESLOT_1, 897 898 // NUM_PHYS_MISCREGS specifies the number of actual physical 899 // registers, not considering the following pseudo-registers 900 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. 901 // Checkpointing should use this physical index when 902 // saving/restoring register values. 903 NUM_PHYS_MISCREGS, 904 905 // Dummy registers 906 MISCREG_NOP, 907 MISCREG_RAZ, 908 MISCREG_CP14_UNIMPL, 909 MISCREG_CP15_UNIMPL, 910 MISCREG_UNKNOWN, 911 912 // Implementation defined register: this represent 913 // a pool of unimplemented registers whose access can throw 914 // either UNDEFINED or hypervisor trap exception. 915 MISCREG_IMPDEF_UNIMPL, 916 917 // RAS extension (unimplemented) 918 MISCREG_ERRIDR_EL1, 919 MISCREG_ERRSELR_EL1, 920 MISCREG_ERXFR_EL1, 921 MISCREG_ERXCTLR_EL1, 922 MISCREG_ERXSTATUS_EL1, 923 MISCREG_ERXADDR_EL1, 924 MISCREG_ERXMISC0_EL1, 925 MISCREG_ERXMISC1_EL1, 926 MISCREG_DISR_EL1, 927 MISCREG_VSESR_EL2, 928 MISCREG_VDISR_EL2, 929 930 // Total number of Misc Registers: Physical + Dummy 931 NUM_MISCREGS 932 }; 933 934 enum MiscRegInfo { 935 MISCREG_IMPLEMENTED, 936 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a 937 // arch generic counter) 938 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it 939 // tells whether the instruction should raise a 940 // warning or fail 941 MISCREG_MUTEX, // True if the register corresponds to a pair of 942 // mutually exclusive registers 943 MISCREG_BANKED, // True if the register is banked between the two 944 // security states, and this is the parent node of the 945 // two banked registers 946 MISCREG_BANKED_CHILD, // The entry is one of the child registers that 947 // forms a banked set of regs (along with the 948 // other child regs) 949 950 // Access permissions 951 // User mode 952 MISCREG_USR_NS_RD, 953 MISCREG_USR_NS_WR, 954 MISCREG_USR_S_RD, 955 MISCREG_USR_S_WR, 956 // Privileged modes other than hypervisor or monitor 957 MISCREG_PRI_NS_RD, 958 MISCREG_PRI_NS_WR, 959 MISCREG_PRI_S_RD, 960 MISCREG_PRI_S_WR, 961 // Hypervisor mode 962 MISCREG_HYP_RD, 963 MISCREG_HYP_WR, 964 // Monitor mode, SCR.NS == 0 965 MISCREG_MON_NS0_RD, 966 MISCREG_MON_NS0_WR, 967 // Monitor mode, SCR.NS == 1 968 MISCREG_MON_NS1_RD, 969 MISCREG_MON_NS1_WR, 970 971 NUM_MISCREG_INFOS 972 }; 973 974 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; 975 976 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions 977 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 978 unsigned crm, unsigned opc2); 979 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, 980 unsigned crn, unsigned crm, 981 unsigned op2); 982 // Whether a particular AArch64 system register is -always- read only. 983 bool aarch64SysRegReadOnly(MiscRegIndex miscReg); 984 985 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions 986 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 987 unsigned crm, unsigned opc2); 988 989 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions 990 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1); 991 992 993 const char * const miscRegName[] = { 994 "cpsr", 995 "spsr", 996 "spsr_fiq", 997 "spsr_irq", 998 "spsr_svc", 999 "spsr_mon", 1000 "spsr_abt", 1001 "spsr_hyp", 1002 "spsr_und", 1003 "elr_hyp", 1004 "fpsid", 1005 "fpscr", 1006 "mvfr1", 1007 "mvfr0", 1008 "fpexc", 1009 1010 // Helper registers 1011 "cpsr_mode", 1012 "cpsr_q", 1013 "fpscr_exc", 1014 "fpscr_qc", 1015 "lockaddr", 1016 "lockflag", 1017 "prrr_mair0", 1018 "prrr_mair0_ns", 1019 "prrr_mair0_s", 1020 "nmrr_mair1", 1021 "nmrr_mair1_ns", 1022 "nmrr_mair1_s", 1023 "pmxevtyper_pmccfiltr", 1024 "sctlr_rst", 1025 "sev_mailbox", 1026 1027 // AArch32 CP14 registers 1028 "dbgdidr", 1029 "dbgdscrint", 1030 "dbgdccint", 1031 "dbgdtrtxint", 1032 "dbgdtrrxint", 1033 "dbgwfar", 1034 "dbgvcr", 1035 "dbgdtrrxext", 1036 "dbgdscrext", 1037 "dbgdtrtxext", 1038 "dbgoseccr", 1039 "dbgbvr0", 1040 "dbgbvr1", 1041 "dbgbvr2", 1042 "dbgbvr3", 1043 "dbgbvr4", 1044 "dbgbvr5", 1045 "dbgbcr0", 1046 "dbgbcr1", 1047 "dbgbcr2", 1048 "dbgbcr3", 1049 "dbgbcr4", 1050 "dbgbcr5", 1051 "dbgwvr0", 1052 "dbgwvr1", 1053 "dbgwvr2", 1054 "dbgwvr3", 1055 "dbgwcr0", 1056 "dbgwcr1", 1057 "dbgwcr2", 1058 "dbgwcr3", 1059 "dbgdrar", 1060 "dbgbxvr4", 1061 "dbgbxvr5", 1062 "dbgoslar", 1063 "dbgoslsr", 1064 "dbgosdlr", 1065 "dbgprcr", 1066 "dbgdsar", 1067 "dbgclaimset", 1068 "dbgclaimclr", 1069 "dbgauthstatus", 1070 "dbgdevid2", 1071 "dbgdevid1", 1072 "dbgdevid0", 1073 "teecr", 1074 "jidr", 1075 "teehbr", 1076 "joscr", 1077 "jmcr", 1078 1079 // AArch32 CP15 registers 1080 "midr", 1081 "ctr", 1082 "tcmtr", 1083 "tlbtr", 1084 "mpidr", 1085 "revidr", 1086 "id_pfr0", 1087 "id_pfr1", 1088 "id_dfr0", 1089 "id_afr0", 1090 "id_mmfr0", 1091 "id_mmfr1", 1092 "id_mmfr2", 1093 "id_mmfr3", 1094 "id_isar0", 1095 "id_isar1", 1096 "id_isar2", 1097 "id_isar3", 1098 "id_isar4", 1099 "id_isar5", 1100 "ccsidr", 1101 "clidr", 1102 "aidr", 1103 "csselr", 1104 "csselr_ns", 1105 "csselr_s", 1106 "vpidr", 1107 "vmpidr", 1108 "sctlr", 1109 "sctlr_ns", 1110 "sctlr_s", 1111 "actlr", 1112 "actlr_ns", 1113 "actlr_s", 1114 "cpacr", 1115 "scr", 1116 "sder", 1117 "nsacr", 1118 "hsctlr", 1119 "hactlr", 1120 "hcr", 1121 "hdcr", 1122 "hcptr", 1123 "hstr", 1124 "hacr", 1125 "ttbr0", 1126 "ttbr0_ns", 1127 "ttbr0_s", 1128 "ttbr1", 1129 "ttbr1_ns", 1130 "ttbr1_s", 1131 "ttbcr", 1132 "ttbcr_ns", 1133 "ttbcr_s", 1134 "htcr", 1135 "vtcr", 1136 "dacr", 1137 "dacr_ns", 1138 "dacr_s", 1139 "dfsr", 1140 "dfsr_ns", 1141 "dfsr_s", 1142 "ifsr", 1143 "ifsr_ns", 1144 "ifsr_s", 1145 "adfsr", 1146 "adfsr_ns", 1147 "adfsr_s", 1148 "aifsr", 1149 "aifsr_ns", 1150 "aifsr_s", 1151 "hadfsr", 1152 "haifsr", 1153 "hsr", 1154 "dfar", 1155 "dfar_ns", 1156 "dfar_s", 1157 "ifar", 1158 "ifar_ns", 1159 "ifar_s", 1160 "hdfar", 1161 "hifar", 1162 "hpfar", 1163 "icialluis", 1164 "bpiallis", 1165 "par", 1166 "par_ns", 1167 "par_s", 1168 "iciallu", 1169 "icimvau", 1170 "cp15isb", 1171 "bpiall", 1172 "bpimva", 1173 "dcimvac", 1174 "dcisw", 1175 "ats1cpr", 1176 "ats1cpw", 1177 "ats1cur", 1178 "ats1cuw", 1179 "ats12nsopr", 1180 "ats12nsopw", 1181 "ats12nsour", 1182 "ats12nsouw", 1183 "dccmvac", 1184 "dccsw", 1185 "cp15dsb", 1186 "cp15dmb", 1187 "dccmvau", 1188 "dccimvac", 1189 "dccisw", 1190 "ats1hr", 1191 "ats1hw", 1192 "tlbiallis", 1193 "tlbimvais", 1194 "tlbiasidis", 1195 "tlbimvaais", 1196 "tlbimvalis", 1197 "tlbimvaalis", 1198 "itlbiall", 1199 "itlbimva", 1200 "itlbiasid", 1201 "dtlbiall", 1202 "dtlbimva", 1203 "dtlbiasid", 1204 "tlbiall", 1205 "tlbimva", 1206 "tlbiasid", 1207 "tlbimvaa", 1208 "tlbimval", 1209 "tlbimvaal", 1210 "tlbiipas2is", 1211 "tlbiipas2lis", 1212 "tlbiallhis", 1213 "tlbimvahis", 1214 "tlbiallnsnhis", 1215 "tlbimvalhis", 1216 "tlbiipas2", 1217 "tlbiipas2l", 1218 "tlbiallh", 1219 "tlbimvah", 1220 "tlbiallnsnh", 1221 "tlbimvalh", 1222 "pmcr", 1223 "pmcntenset", 1224 "pmcntenclr", 1225 "pmovsr", 1226 "pmswinc", 1227 "pmselr", 1228 "pmceid0", 1229 "pmceid1", 1230 "pmccntr", 1231 "pmxevtyper", 1232 "pmccfiltr", 1233 "pmxevcntr", 1234 "pmuserenr", 1235 "pmintenset", 1236 "pmintenclr", 1237 "pmovsset", 1238 "l2ctlr", 1239 "l2ectlr", 1240 "prrr", 1241 "prrr_ns", 1242 "prrr_s", 1243 "mair0", 1244 "mair0_ns", 1245 "mair0_s", 1246 "nmrr", 1247 "nmrr_ns", 1248 "nmrr_s", 1249 "mair1", 1250 "mair1_ns", 1251 "mair1_s", 1252 "amair0", 1253 "amair0_ns", 1254 "amair0_s", 1255 "amair1", 1256 "amair1_ns", 1257 "amair1_s", 1258 "hmair0", 1259 "hmair1", 1260 "hamair0", 1261 "hamair1", 1262 "vbar", 1263 "vbar_ns", 1264 "vbar_s", 1265 "mvbar", 1266 "rmr", 1267 "isr", 1268 "hvbar", 1269 "fcseidr", 1270 "contextidr", 1271 "contextidr_ns", 1272 "contextidr_s", 1273 "tpidrurw", 1274 "tpidrurw_ns", 1275 "tpidrurw_s", 1276 "tpidruro", 1277 "tpidruro_ns", 1278 "tpidruro_s", 1279 "tpidrprw", 1280 "tpidrprw_ns", 1281 "tpidrprw_s", 1282 "htpidr", 1283 "cntfrq", 1284 "cntkctl", 1285 "cntp_tval", 1286 "cntp_tval_ns", 1287 "cntp_tval_s", 1288 "cntp_ctl", 1289 "cntp_ctl_ns", 1290 "cntp_ctl_s", 1291 "cntv_tval", 1292 "cntv_ctl", 1293 "cnthctl", 1294 "cnthp_tval", 1295 "cnthp_ctl", 1296 "il1data0", 1297 "il1data1", 1298 "il1data2", 1299 "il1data3", 1300 "dl1data0", 1301 "dl1data1", 1302 "dl1data2", 1303 "dl1data3", 1304 "dl1data4", 1305 "ramindex", 1306 "l2actlr", 1307 "cbar", 1308 "httbr", 1309 "vttbr", 1310 "cntpct", 1311 "cntvct", 1312 "cntp_cval", 1313 "cntp_cval_ns", 1314 "cntp_cval_s", 1315 "cntv_cval", 1316 "cntvoff", 1317 "cnthp_cval", 1318 "cpumerrsr", 1319 "l2merrsr", 1320 1321 // AArch64 registers (Op0=2) 1322 "mdccint_el1", 1323 "osdtrrx_el1", 1324 "mdscr_el1", 1325 "osdtrtx_el1", 1326 "oseccr_el1", 1327 "dbgbvr0_el1", 1328 "dbgbvr1_el1", 1329 "dbgbvr2_el1", 1330 "dbgbvr3_el1", 1331 "dbgbvr4_el1", 1332 "dbgbvr5_el1", 1333 "dbgbcr0_el1", 1334 "dbgbcr1_el1", 1335 "dbgbcr2_el1", 1336 "dbgbcr3_el1", 1337 "dbgbcr4_el1", 1338 "dbgbcr5_el1", 1339 "dbgwvr0_el1", 1340 "dbgwvr1_el1", 1341 "dbgwvr2_el1", 1342 "dbgwvr3_el1", 1343 "dbgwcr0_el1", 1344 "dbgwcr1_el1", 1345 "dbgwcr2_el1", 1346 "dbgwcr3_el1", 1347 "mdccsr_el0", 1348 "mddtr_el0", 1349 "mddtrtx_el0", 1350 "mddtrrx_el0", 1351 "dbgvcr32_el2", 1352 "mdrar_el1", 1353 "oslar_el1", 1354 "oslsr_el1", 1355 "osdlr_el1", 1356 "dbgprcr_el1", 1357 "dbgclaimset_el1", 1358 "dbgclaimclr_el1", 1359 "dbgauthstatus_el1", 1360 "teecr32_el1", 1361 "teehbr32_el1", 1362 1363 // AArch64 registers (Op0=1,3) 1364 "midr_el1", 1365 "mpidr_el1", 1366 "revidr_el1", 1367 "id_pfr0_el1", 1368 "id_pfr1_el1", 1369 "id_dfr0_el1", 1370 "id_afr0_el1", 1371 "id_mmfr0_el1", 1372 "id_mmfr1_el1", 1373 "id_mmfr2_el1", 1374 "id_mmfr3_el1", 1375 "id_isar0_el1", 1376 "id_isar1_el1", 1377 "id_isar2_el1", 1378 "id_isar3_el1", 1379 "id_isar4_el1", 1380 "id_isar5_el1", 1381 "mvfr0_el1", 1382 "mvfr1_el1", 1383 "mvfr2_el1", 1384 "id_aa64pfr0_el1", 1385 "id_aa64pfr1_el1", 1386 "id_aa64dfr0_el1", 1387 "id_aa64dfr1_el1", 1388 "id_aa64afr0_el1", 1389 "id_aa64afr1_el1", 1390 "id_aa64isar0_el1", 1391 "id_aa64isar1_el1", 1392 "id_aa64mmfr0_el1", 1393 "id_aa64mmfr1_el1", 1394 "ccsidr_el1", 1395 "clidr_el1", 1396 "aidr_el1", 1397 "csselr_el1", 1398 "ctr_el0", 1399 "dczid_el0", 1400 "vpidr_el2", 1401 "vmpidr_el2", 1402 "sctlr_el1", 1403 "actlr_el1", 1404 "cpacr_el1", 1405 "sctlr_el2", 1406 "actlr_el2", 1407 "hcr_el2", 1408 "mdcr_el2", 1409 "cptr_el2", 1410 "hstr_el2", 1411 "hacr_el2", 1412 "sctlr_el3", 1413 "actlr_el3", 1414 "scr_el3", 1415 "sder32_el3", 1416 "cptr_el3", 1417 "mdcr_el3", 1418 "ttbr0_el1", 1419 "ttbr1_el1", 1420 "tcr_el1", 1421 "ttbr0_el2", 1422 "tcr_el2", 1423 "vttbr_el2", 1424 "vtcr_el2", 1425 "ttbr0_el3", 1426 "tcr_el3", 1427 "dacr32_el2", 1428 "spsr_el1", 1429 "elr_el1", 1430 "sp_el0", 1431 "spsel", 1432 "currentel", 1433 "nzcv", 1434 "daif", 1435 "fpcr", 1436 "fpsr", 1437 "dspsr_el0", 1438 "dlr_el0", 1439 "spsr_el2", 1440 "elr_el2", 1441 "sp_el1", 1442 "spsr_irq_aa64", 1443 "spsr_abt_aa64", 1444 "spsr_und_aa64", 1445 "spsr_fiq_aa64", 1446 "spsr_el3", 1447 "elr_el3", 1448 "sp_el2", 1449 "afsr0_el1", 1450 "afsr1_el1", 1451 "esr_el1", 1452 "ifsr32_el2", 1453 "afsr0_el2", 1454 "afsr1_el2", 1455 "esr_el2", 1456 "fpexc32_el2", 1457 "afsr0_el3", 1458 "afsr1_el3", 1459 "esr_el3", 1460 "far_el1", 1461 "far_el2", 1462 "hpfar_el2", 1463 "far_el3", 1464 "ic_ialluis", 1465 "par_el1", 1466 "ic_iallu", 1467 "dc_ivac_xt", 1468 "dc_isw_xt", 1469 "at_s1e1r_xt", 1470 "at_s1e1w_xt", 1471 "at_s1e0r_xt", 1472 "at_s1e0w_xt", 1473 "dc_csw_xt", 1474 "dc_cisw_xt", 1475 "dc_zva_xt", 1476 "ic_ivau_xt", 1477 "dc_cvac_xt", 1478 "dc_cvau_xt", 1479 "dc_civac_xt", 1480 "at_s1e2r_xt", 1481 "at_s1e2w_xt", 1482 "at_s12e1r_xt", 1483 "at_s12e1w_xt", 1484 "at_s12e0r_xt", 1485 "at_s12e0w_xt", 1486 "at_s1e3r_xt", 1487 "at_s1e3w_xt", 1488 "tlbi_vmalle1is", 1489 "tlbi_vae1is_xt", 1490 "tlbi_aside1is_xt", 1491 "tlbi_vaae1is_xt", 1492 "tlbi_vale1is_xt", 1493 "tlbi_vaale1is_xt", 1494 "tlbi_vmalle1", 1495 "tlbi_vae1_xt", 1496 "tlbi_aside1_xt", 1497 "tlbi_vaae1_xt", 1498 "tlbi_vale1_xt", 1499 "tlbi_vaale1_xt", 1500 "tlbi_ipas2e1is_xt", 1501 "tlbi_ipas2le1is_xt", 1502 "tlbi_alle2is", 1503 "tlbi_vae2is_xt", 1504 "tlbi_alle1is", 1505 "tlbi_vale2is_xt", 1506 "tlbi_vmalls12e1is", 1507 "tlbi_ipas2e1_xt", 1508 "tlbi_ipas2le1_xt", 1509 "tlbi_alle2", 1510 "tlbi_vae2_xt", 1511 "tlbi_alle1", 1512 "tlbi_vale2_xt", 1513 "tlbi_vmalls12e1", 1514 "tlbi_alle3is", 1515 "tlbi_vae3is_xt", 1516 "tlbi_vale3is_xt", 1517 "tlbi_alle3", 1518 "tlbi_vae3_xt", 1519 "tlbi_vale3_xt", 1520 "pmintenset_el1", 1521 "pmintenclr_el1", 1522 "pmcr_el0", 1523 "pmcntenset_el0", 1524 "pmcntenclr_el0", 1525 "pmovsclr_el0", 1526 "pmswinc_el0", 1527 "pmselr_el0", 1528 "pmceid0_el0", 1529 "pmceid1_el0", 1530 "pmccntr_el0", 1531 "pmxevtyper_el0", 1532 "pmccfiltr_el0", 1533 "pmxevcntr_el0", 1534 "pmuserenr_el0", 1535 "pmovsset_el0", 1536 "mair_el1", 1537 "amair_el1", 1538 "mair_el2", 1539 "amair_el2", 1540 "mair_el3", 1541 "amair_el3", 1542 "l2ctlr_el1", 1543 "l2ectlr_el1", 1544 "vbar_el1", 1545 "rvbar_el1", 1546 "isr_el1", 1547 "vbar_el2", 1548 "rvbar_el2", 1549 "vbar_el3", 1550 "rvbar_el3", 1551 "rmr_el3", 1552 "contextidr_el1", 1553 "tpidr_el1", 1554 "tpidr_el0", 1555 "tpidrro_el0", 1556 "tpidr_el2", 1557 "tpidr_el3", 1558 "cntkctl_el1", 1559 "cntfrq_el0", 1560 "cntpct_el0", 1561 "cntvct_el0", 1562 "cntp_tval_el0", 1563 "cntp_ctl_el0", 1564 "cntp_cval_el0", 1565 "cntv_tval_el0", 1566 "cntv_ctl_el0", 1567 "cntv_cval_el0", 1568 "pmevcntr0_el0", 1569 "pmevcntr1_el0", 1570 "pmevcntr2_el0", 1571 "pmevcntr3_el0", 1572 "pmevcntr4_el0", 1573 "pmevcntr5_el0", 1574 "pmevtyper0_el0", 1575 "pmevtyper1_el0", 1576 "pmevtyper2_el0", 1577 "pmevtyper3_el0", 1578 "pmevtyper4_el0", 1579 "pmevtyper5_el0", 1580 "cntvoff_el2", 1581 "cnthctl_el2", 1582 "cnthp_tval_el2", 1583 "cnthp_ctl_el2", 1584 "cnthp_cval_el2", 1585 "cntps_tval_el1", 1586 "cntps_ctl_el1", 1587 "cntps_cval_el1", 1588 "il1data0_el1", 1589 "il1data1_el1", 1590 "il1data2_el1", 1591 "il1data3_el1", 1592 "dl1data0_el1", 1593 "dl1data1_el1", 1594 "dl1data2_el1", 1595 "dl1data3_el1", 1596 "dl1data4_el1", 1597 "l2actlr_el1", 1598 "cpuactlr_el1", 1599 "cpuectlr_el1", 1600 "cpumerrsr_el1", 1601 "l2merrsr_el1", 1602 "cbar_el1", 1603 "contextidr_el2", 1604 1605 "ttbr1_el2", 1606 "cnthv_ctl_el2", 1607 "cnthv_cval_el2", 1608 "cnthv_tval_el2", 1609 "id_aa64mmfr2_el1", 1610 1611 // GICv3, CPU interface 1612 "icc_pmr_el1", 1613 "icc_iar0_el1", 1614 "icc_eoir0_el1", 1615 "icc_hppir0_el1", 1616 "icc_bpr0_el1", 1617 "icc_ap0r0_el1", 1618 "icc_ap0r1_el1", 1619 "icc_ap0r2_el1", 1620 "icc_ap0r3_el1", 1621 "icc_ap1r0_el1", 1622 "icc_ap1r0_el1_ns", 1623 "icc_ap1r0_el1_s", 1624 "icc_ap1r1_el1", 1625 "icc_ap1r1_el1_ns", 1626 "icc_ap1r1_el1_s", 1627 "icc_ap1r2_el1", 1628 "icc_ap1r2_el1_ns", 1629 "icc_ap1r2_el1_s", 1630 "icc_ap1r3_el1", 1631 "icc_ap1r3_el1_ns", 1632 "icc_ap1r3_el1_s", 1633 "icc_dir_el1", 1634 "icc_rpr_el1", 1635 "icc_sgi1r_el1", 1636 "icc_asgi1r_el1", 1637 "icc_sgi0r_el1", 1638 "icc_iar1_el1", 1639 "icc_eoir1_el1", 1640 "icc_hppir1_el1", 1641 "icc_bpr1_el1", 1642 "icc_bpr1_el1_ns", 1643 "icc_bpr1_el1_s", 1644 "icc_ctlr_el1", 1645 "icc_ctlr_el1_ns", 1646 "icc_ctlr_el1_s", 1647 "icc_sre_el1", 1648 "icc_sre_el1_ns", 1649 "icc_sre_el1_s", 1650 "icc_igrpen0_el1", 1651 "icc_igrpen1_el1", 1652 "icc_igrpen1_el1_ns", 1653 "icc_igrpen1_el1_s", 1654 "icc_sre_el2", 1655 "icc_ctlr_el3", 1656 "icc_sre_el3", 1657 "icc_igrpen1_el3", 1658 1659 // GICv3, CPU interface, virtualization 1660 "ich_ap0r0_el2", 1661 "ich_ap0r1_el2", 1662 "ich_ap0r2_el2", 1663 "ich_ap0r3_el2", 1664 "ich_ap1r0_el2", 1665 "ich_ap1r1_el2", 1666 "ich_ap1r2_el2", 1667 "ich_ap1r3_el2", 1668 "ich_hcr_el2", 1669 "ich_vtr_el2", 1670 "ich_misr_el2", 1671 "ich_eisr_el2", 1672 "ich_elrsr_el2", 1673 "ich_vmcr_el2", 1674 "ich_lr0_el2", 1675 "ich_lr1_el2", 1676 "ich_lr2_el2", 1677 "ich_lr3_el2", 1678 "ich_lr4_el2", 1679 "ich_lr5_el2", 1680 "ich_lr6_el2", 1681 "ich_lr7_el2", 1682 "ich_lr8_el2", 1683 "ich_lr9_el2", 1684 "ich_lr10_el2", 1685 "ich_lr11_el2", 1686 "ich_lr12_el2", 1687 "ich_lr13_el2", 1688 "ich_lr14_el2", 1689 "ich_lr15_el2", 1690 1691 "icv_pmr_el1", 1692 "icv_iar0_el1", 1693 "icv_eoir0_el1", 1694 "icv_hppir0_el1", 1695 "icv_bpr0_el1", 1696 "icv_ap0r0_el1", 1697 "icv_ap0r1_el1", 1698 "icv_ap0r2_el1", 1699 "icv_ap0r3_el1", 1700 "icv_ap1r0_el1", 1701 "icv_ap1r0_el1_ns", 1702 "icv_ap1r0_el1_s", 1703 "icv_ap1r1_el1", 1704 "icv_ap1r1_el1_ns", 1705 "icv_ap1r1_el1_s", 1706 "icv_ap1r2_el1", 1707 "icv_ap1r2_el1_ns", 1708 "icv_ap1r2_el1_s", 1709 "icv_ap1r3_el1", 1710 "icv_ap1r3_el1_ns", 1711 "icv_ap1r3_el1_s", 1712 "icv_dir_el1", 1713 "icv_rpr_el1", 1714 "icv_sgi1r_el1", 1715 "icv_asgi1r_el1", 1716 "icv_sgi0r_el1", 1717 "icv_iar1_el1", 1718 "icv_eoir1_el1", 1719 "icv_hppir1_el1", 1720 "icv_bpr1_el1", 1721 "icv_bpr1_el1_ns", 1722 "icv_bpr1_el1_s", 1723 "icv_ctlr_el1", 1724 "icv_ctlr_el1_ns", 1725 "icv_ctlr_el1_s", 1726 "icv_sre_el1", 1727 "icv_sre_el1_ns", 1728 "icv_sre_el1_s", 1729 "icv_igrpen0_el1", 1730 "icv_igrpen1_el1", 1731 "icv_igrpen1_el1_ns", 1732 "icv_igrpen1_el1_s", 1733 1734 "icc_ap0r0", 1735 "icc_ap0r1", 1736 "icc_ap0r2", 1737 "icc_ap0r3", 1738 "icc_ap1r0", 1739 "icc_ap1r0_ns", 1740 "icc_ap1r0_s", 1741 "icc_ap1r1", 1742 "icc_ap1r1_ns", 1743 "icc_ap1r1_s", 1744 "icc_ap1r2", 1745 "icc_ap1r2_ns", 1746 "icc_ap1r2_s", 1747 "icc_ap1r3", 1748 "icc_ap1r3_ns", 1749 "icc_ap1r3_s", 1750 "icc_asgi1r", 1751 "icc_bpr0", 1752 "icc_bpr1", 1753 "icc_bpr1_ns", 1754 "icc_bpr1_s", 1755 "icc_ctlr", 1756 "icc_ctlr_ns", 1757 "icc_ctlr_s", 1758 "icc_dir", 1759 "icc_eoir0", 1760 "icc_eoir1", 1761 "icc_hppir0", 1762 "icc_hppir1", 1763 "icc_hsre", 1764 "icc_iar0", 1765 "icc_iar1", 1766 "icc_igrpen0", 1767 "icc_igrpen1", 1768 "icc_igrpen1_ns", 1769 "icc_igrpen1_s", 1770 "icc_mctlr", 1771 "icc_mgrpen1", 1772 "icc_msre", 1773 "icc_pmr", 1774 "icc_rpr", 1775 "icc_sgi0r", 1776 "icc_sgi1r", 1777 "icc_sre", 1778 "icc_sre_ns", 1779 "icc_sre_s", 1780 1781 "ich_ap0r0", 1782 "ich_ap0r1", 1783 "ich_ap0r2", 1784 "ich_ap0r3", 1785 "ich_ap1r0", 1786 "ich_ap1r1", 1787 "ich_ap1r2", 1788 "ich_ap1r3", 1789 "ich_hcr", 1790 "ich_vtr", 1791 "ich_misr", 1792 "ich_eisr", 1793 "ich_elrsr", 1794 "ich_vmcr", 1795 "ich_lr0", 1796 "ich_lr1", 1797 "ich_lr2", 1798 "ich_lr3", 1799 "ich_lr4", 1800 "ich_lr5", 1801 "ich_lr6", 1802 "ich_lr7", 1803 "ich_lr8", 1804 "ich_lr9", 1805 "ich_lr10", 1806 "ich_lr11", 1807 "ich_lr12", 1808 "ich_lr13", 1809 "ich_lr14", 1810 "ich_lr15", 1811 "ich_lrc0", 1812 "ich_lrc1", 1813 "ich_lrc2", 1814 "ich_lrc3", 1815 "ich_lrc4", 1816 "ich_lrc5", 1817 "ich_lrc6", 1818 "ich_lrc7", 1819 "ich_lrc8", 1820 "ich_lrc9", 1821 "ich_lrc10", 1822 "ich_lrc11", 1823 "ich_lrc12", 1824 "ich_lrc13", 1825 "ich_lrc14", 1826 "ich_lrc15", 1827 1828 "freeslot2", 1829 1830 "num_phys_regs", 1831 1832 // Dummy registers 1833 "nop", 1834 "raz", 1835 "cp14_unimpl", 1836 "cp15_unimpl", 1837 "unknown", 1838 "impl_defined", 1839 "erridr_el1", 1840 "errselr_el1", 1841 "erxfr_el1", 1842 "erxctlr_el1", 1843 "erxstatus_el1", 1844 "erxaddr_el1", 1845 "erxmisc0_el1", 1846 "erxmisc1_el1", 1847 "disr_el1", 1848 "vsesr_el2", 1849 "vdisr_el2", 1850 }; 1851 1852 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 1853 "The miscRegName array and NUM_MISCREGS are inconsistent."); 1854 1855 // This mask selects bits of the CPSR that actually go in the CondCodes 1856 // integer register to allow renaming. 1857 static const uint32_t CondCodesMask = 0xF00F0000; 1858 static const uint32_t CpsrMaskQ = 0x08000000; 1859 1860 // APSR (Application Program Status Register Mask). It is the user level 1861 // alias for the CPSR. The APSR is a subset of the CPSR. Although 1862 // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of 1863 // APSR: 1864 // Bit[9] returns the value of CPSR.E. 1865 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits. 1866 static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0; 1867 1868 // CPSR (Current Program Status Register Mask). 1869 static const uint32_t CpsrMask = ApsrMask | 0x00F003DF; 1870 1871 // This mask selects bits of the FPSCR that actually go in the FpCondCodes 1872 // integer register to allow renaming. 1873 static const uint32_t FpCondCodesMask = 0xF0000000; 1874 // This mask selects the cumulative FP exception flags of the FPSCR. 1875 static const uint32_t FpscrExcMask = 0x0000009F; 1876 // This mask selects the cumulative saturation flag of the FPSCR. 1877 static const uint32_t FpscrQcMask = 0x08000000; 1878 1879 /** 1880 * Check for permission to read coprocessor registers. 1881 * 1882 * Checks whether an instruction at the current program mode has 1883 * permissions to read the coprocessor registers. This function 1884 * returns whether the check is undefined and if not whether the 1885 * read access is permitted. 1886 * 1887 * @param the misc reg indicating the coprocessor 1888 * @param the SCR 1889 * @param the CPSR 1890 * @return a tuple of booleans: can_read, undefined 1891 */ 1892 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr, 1893 CPSR cpsr); 1894 1895 /** 1896 * Check for permission to write coprocessor registers. 1897 * 1898 * Checks whether an instruction at the current program mode has 1899 * permissions to write the coprocessor registers. This function 1900 * returns whether the check is undefined and if not whether the 1901 * write access is permitted. 1902 * 1903 * @param the misc reg indicating the coprocessor 1904 * @param the SCR 1905 * @param the CPSR 1906 * @return a tuple of booleans: can_write, undefined 1907 */ 1908 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr, 1909 CPSR cpsr); 1910 1911 // Checks read access permissions to AArch64 system registers 1912 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1913 ThreadContext *tc); 1914 1915 // Checks write access permissions to AArch64 system registers 1916 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1917 ThreadContext *tc); 1918 1919 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful 1920 // for MCR/MRC instructions 1921 int 1922 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc); 1923 1924 // Flattens a misc reg index using the specified security state. This is 1925 // used for opperations (eg address translations) where the security 1926 // state of the register access may differ from the current state of the 1927 // processor 1928 int 1929 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns); 1930 1931 // Takes a misc reg index and returns the root reg if its one of a set of 1932 // banked registers 1933 void 1934 preUnflattenMiscReg(); 1935 1936 int 1937 unflattenMiscReg(int reg); 1938 1939} 1940 1941#endif // __ARCH_ARM_MISCREGS_HH__ 1942