miscregs.hh revision 13392
16242Sgblack@eecs.umich.edu/* 212529Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2018 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146242Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156242Sgblack@eecs.umich.edu * All rights reserved. 166242Sgblack@eecs.umich.edu * 176242Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186242Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196242Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216242Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236242Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246242Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256242Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266242Sgblack@eecs.umich.edu * this software without specific prior written permission. 276242Sgblack@eecs.umich.edu * 286242Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296242Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306242Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316242Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326242Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336242Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346242Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356242Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366242Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376242Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386242Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396242Sgblack@eecs.umich.edu * 406242Sgblack@eecs.umich.edu * Authors: Gabe Black 4110037SARM gem5 Developers * Giacomo Gabrielli 426242Sgblack@eecs.umich.edu */ 436242Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MISCREGS_HH__ 446242Sgblack@eecs.umich.edu#define __ARCH_ARM_MISCREGS_HH__ 456242Sgblack@eecs.umich.edu 4610037SARM gem5 Developers#include <bitset> 4711939Snikos.nikoleris@arm.com#include <tuple> 4810037SARM gem5 Developers 4913115Sgiacomo.travaglini@arm.com#include "arch/arm/miscregs_types.hh" 509256SAndreas.Sandberg@arm.com#include "base/compiler.hh" 516242Sgblack@eecs.umich.edu 5210037SARM gem5 Developersclass ThreadContext; 5310037SARM gem5 Developers 5410037SARM gem5 Developers 556242Sgblack@eecs.umich.edunamespace ArmISA 566242Sgblack@eecs.umich.edu{ 576242Sgblack@eecs.umich.edu enum MiscRegIndex { 5813392Sgiacomo.travaglini@arm.com MISCREG_CPSR = 0, 5913392Sgiacomo.travaglini@arm.com MISCREG_SPSR, 6013392Sgiacomo.travaglini@arm.com MISCREG_SPSR_FIQ, 6113392Sgiacomo.travaglini@arm.com MISCREG_SPSR_IRQ, 6213392Sgiacomo.travaglini@arm.com MISCREG_SPSR_SVC, 6313392Sgiacomo.travaglini@arm.com MISCREG_SPSR_MON, 6413392Sgiacomo.travaglini@arm.com MISCREG_SPSR_ABT, 6513392Sgiacomo.travaglini@arm.com MISCREG_SPSR_HYP, 6613392Sgiacomo.travaglini@arm.com MISCREG_SPSR_UND, 6713392Sgiacomo.travaglini@arm.com MISCREG_ELR_HYP, 6813392Sgiacomo.travaglini@arm.com MISCREG_FPSID, 6913392Sgiacomo.travaglini@arm.com MISCREG_FPSCR, 7013392Sgiacomo.travaglini@arm.com MISCREG_MVFR1, 7113392Sgiacomo.travaglini@arm.com MISCREG_MVFR0, 7213392Sgiacomo.travaglini@arm.com MISCREG_FPEXC, 737259Sgblack@eecs.umich.edu 7410037SARM gem5 Developers // Helper registers 7513392Sgiacomo.travaglini@arm.com MISCREG_CPSR_MODE, 7613392Sgiacomo.travaglini@arm.com MISCREG_CPSR_Q, 7713392Sgiacomo.travaglini@arm.com MISCREG_FPSCR_EXC, 7813392Sgiacomo.travaglini@arm.com MISCREG_FPSCR_QC, 7913392Sgiacomo.travaglini@arm.com MISCREG_LOCKADDR, 8013392Sgiacomo.travaglini@arm.com MISCREG_LOCKFLAG, 8113392Sgiacomo.travaglini@arm.com MISCREG_PRRR_MAIR0, 8213392Sgiacomo.travaglini@arm.com MISCREG_PRRR_MAIR0_NS, 8313392Sgiacomo.travaglini@arm.com MISCREG_PRRR_MAIR0_S, 8413392Sgiacomo.travaglini@arm.com MISCREG_NMRR_MAIR1, 8513392Sgiacomo.travaglini@arm.com MISCREG_NMRR_MAIR1_NS, 8613392Sgiacomo.travaglini@arm.com MISCREG_NMRR_MAIR1_S, 8713392Sgiacomo.travaglini@arm.com MISCREG_PMXEVTYPER_PMCCFILTR, 8813392Sgiacomo.travaglini@arm.com MISCREG_SCTLR_RST, 8913392Sgiacomo.travaglini@arm.com MISCREG_SEV_MAILBOX, 908868SMatt.Horsnell@arm.com 9110037SARM gem5 Developers // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) 9213392Sgiacomo.travaglini@arm.com MISCREG_DBGDIDR, 9313392Sgiacomo.travaglini@arm.com MISCREG_DBGDSCRint, 9413392Sgiacomo.travaglini@arm.com MISCREG_DBGDCCINT, 9513392Sgiacomo.travaglini@arm.com MISCREG_DBGDTRTXint, 9613392Sgiacomo.travaglini@arm.com MISCREG_DBGDTRRXint, 9713392Sgiacomo.travaglini@arm.com MISCREG_DBGWFAR, 9813392Sgiacomo.travaglini@arm.com MISCREG_DBGVCR, 9913392Sgiacomo.travaglini@arm.com MISCREG_DBGDTRRXext, 10013392Sgiacomo.travaglini@arm.com MISCREG_DBGDSCRext, 10113392Sgiacomo.travaglini@arm.com MISCREG_DBGDTRTXext, 10213392Sgiacomo.travaglini@arm.com MISCREG_DBGOSECCR, 10313392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR0, 10413392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR1, 10513392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR2, 10613392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR3, 10713392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR4, 10813392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR5, 10913392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR0, 11013392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR1, 11113392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR2, 11213392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR3, 11313392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR4, 11413392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR5, 11513392Sgiacomo.travaglini@arm.com MISCREG_DBGWVR0, 11613392Sgiacomo.travaglini@arm.com MISCREG_DBGWVR1, 11713392Sgiacomo.travaglini@arm.com MISCREG_DBGWVR2, 11813392Sgiacomo.travaglini@arm.com MISCREG_DBGWVR3, 11913392Sgiacomo.travaglini@arm.com MISCREG_DBGWCR0, 12013392Sgiacomo.travaglini@arm.com MISCREG_DBGWCR1, 12113392Sgiacomo.travaglini@arm.com MISCREG_DBGWCR2, 12213392Sgiacomo.travaglini@arm.com MISCREG_DBGWCR3, 12313392Sgiacomo.travaglini@arm.com MISCREG_DBGDRAR, 12413392Sgiacomo.travaglini@arm.com MISCREG_DBGBXVR4, 12513392Sgiacomo.travaglini@arm.com MISCREG_DBGBXVR5, 12613392Sgiacomo.travaglini@arm.com MISCREG_DBGOSLAR, 12713392Sgiacomo.travaglini@arm.com MISCREG_DBGOSLSR, 12813392Sgiacomo.travaglini@arm.com MISCREG_DBGOSDLR, 12913392Sgiacomo.travaglini@arm.com MISCREG_DBGPRCR, 13013392Sgiacomo.travaglini@arm.com MISCREG_DBGDSAR, 13113392Sgiacomo.travaglini@arm.com MISCREG_DBGCLAIMSET, 13213392Sgiacomo.travaglini@arm.com MISCREG_DBGCLAIMCLR, 13313392Sgiacomo.travaglini@arm.com MISCREG_DBGAUTHSTATUS, 13413392Sgiacomo.travaglini@arm.com MISCREG_DBGDEVID2, 13513392Sgiacomo.travaglini@arm.com MISCREG_DBGDEVID1, 13613392Sgiacomo.travaglini@arm.com MISCREG_DBGDEVID0, 13713392Sgiacomo.travaglini@arm.com MISCREG_TEECR, // not in ARM DDI 0487A.b+ 13813392Sgiacomo.travaglini@arm.com MISCREG_JIDR, 13913392Sgiacomo.travaglini@arm.com MISCREG_TEEHBR, // not in ARM DDI 0487A.b+ 14013392Sgiacomo.travaglini@arm.com MISCREG_JOSCR, 14113392Sgiacomo.travaglini@arm.com MISCREG_JMCR, 1427351Sgblack@eecs.umich.edu 14310037SARM gem5 Developers // AArch32 CP15 registers (system control) 14413392Sgiacomo.travaglini@arm.com MISCREG_MIDR, 14513392Sgiacomo.travaglini@arm.com MISCREG_CTR, 14613392Sgiacomo.travaglini@arm.com MISCREG_TCMTR, 14713392Sgiacomo.travaglini@arm.com MISCREG_TLBTR, 14813392Sgiacomo.travaglini@arm.com MISCREG_MPIDR, 14913392Sgiacomo.travaglini@arm.com MISCREG_REVIDR, 15013392Sgiacomo.travaglini@arm.com MISCREG_ID_PFR0, 15113392Sgiacomo.travaglini@arm.com MISCREG_ID_PFR1, 15213392Sgiacomo.travaglini@arm.com MISCREG_ID_DFR0, 15313392Sgiacomo.travaglini@arm.com MISCREG_ID_AFR0, 15413392Sgiacomo.travaglini@arm.com MISCREG_ID_MMFR0, 15513392Sgiacomo.travaglini@arm.com MISCREG_ID_MMFR1, 15613392Sgiacomo.travaglini@arm.com MISCREG_ID_MMFR2, 15713392Sgiacomo.travaglini@arm.com MISCREG_ID_MMFR3, 15813392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR0, 15913392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR1, 16013392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR2, 16113392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR3, 16213392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR4, 16313392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR5, 16413392Sgiacomo.travaglini@arm.com MISCREG_CCSIDR, 16513392Sgiacomo.travaglini@arm.com MISCREG_CLIDR, 16613392Sgiacomo.travaglini@arm.com MISCREG_AIDR, 16713392Sgiacomo.travaglini@arm.com MISCREG_CSSELR, 16813392Sgiacomo.travaglini@arm.com MISCREG_CSSELR_NS, 16913392Sgiacomo.travaglini@arm.com MISCREG_CSSELR_S, 17013392Sgiacomo.travaglini@arm.com MISCREG_VPIDR, 17113392Sgiacomo.travaglini@arm.com MISCREG_VMPIDR, 17213392Sgiacomo.travaglini@arm.com MISCREG_SCTLR, 17313392Sgiacomo.travaglini@arm.com MISCREG_SCTLR_NS, 17413392Sgiacomo.travaglini@arm.com MISCREG_SCTLR_S, 17513392Sgiacomo.travaglini@arm.com MISCREG_ACTLR, 17613392Sgiacomo.travaglini@arm.com MISCREG_ACTLR_NS, 17713392Sgiacomo.travaglini@arm.com MISCREG_ACTLR_S, 17813392Sgiacomo.travaglini@arm.com MISCREG_CPACR, 17913392Sgiacomo.travaglini@arm.com MISCREG_SCR, 18013392Sgiacomo.travaglini@arm.com MISCREG_SDER, 18113392Sgiacomo.travaglini@arm.com MISCREG_NSACR, 18213392Sgiacomo.travaglini@arm.com MISCREG_HSCTLR, 18313392Sgiacomo.travaglini@arm.com MISCREG_HACTLR, 18413392Sgiacomo.travaglini@arm.com MISCREG_HCR, 18513392Sgiacomo.travaglini@arm.com MISCREG_HDCR, 18613392Sgiacomo.travaglini@arm.com MISCREG_HCPTR, 18713392Sgiacomo.travaglini@arm.com MISCREG_HSTR, 18813392Sgiacomo.travaglini@arm.com MISCREG_HACR, 18913392Sgiacomo.travaglini@arm.com MISCREG_TTBR0, 19013392Sgiacomo.travaglini@arm.com MISCREG_TTBR0_NS, 19113392Sgiacomo.travaglini@arm.com MISCREG_TTBR0_S, 19213392Sgiacomo.travaglini@arm.com MISCREG_TTBR1, 19313392Sgiacomo.travaglini@arm.com MISCREG_TTBR1_NS, 19413392Sgiacomo.travaglini@arm.com MISCREG_TTBR1_S, 19513392Sgiacomo.travaglini@arm.com MISCREG_TTBCR, 19613392Sgiacomo.travaglini@arm.com MISCREG_TTBCR_NS, 19713392Sgiacomo.travaglini@arm.com MISCREG_TTBCR_S, 19813392Sgiacomo.travaglini@arm.com MISCREG_HTCR, 19913392Sgiacomo.travaglini@arm.com MISCREG_VTCR, 20013392Sgiacomo.travaglini@arm.com MISCREG_DACR, 20113392Sgiacomo.travaglini@arm.com MISCREG_DACR_NS, 20213392Sgiacomo.travaglini@arm.com MISCREG_DACR_S, 20313392Sgiacomo.travaglini@arm.com MISCREG_DFSR, 20413392Sgiacomo.travaglini@arm.com MISCREG_DFSR_NS, 20513392Sgiacomo.travaglini@arm.com MISCREG_DFSR_S, 20613392Sgiacomo.travaglini@arm.com MISCREG_IFSR, 20713392Sgiacomo.travaglini@arm.com MISCREG_IFSR_NS, 20813392Sgiacomo.travaglini@arm.com MISCREG_IFSR_S, 20913392Sgiacomo.travaglini@arm.com MISCREG_ADFSR, 21013392Sgiacomo.travaglini@arm.com MISCREG_ADFSR_NS, 21113392Sgiacomo.travaglini@arm.com MISCREG_ADFSR_S, 21213392Sgiacomo.travaglini@arm.com MISCREG_AIFSR, 21313392Sgiacomo.travaglini@arm.com MISCREG_AIFSR_NS, 21413392Sgiacomo.travaglini@arm.com MISCREG_AIFSR_S, 21513392Sgiacomo.travaglini@arm.com MISCREG_HADFSR, 21613392Sgiacomo.travaglini@arm.com MISCREG_HAIFSR, 21713392Sgiacomo.travaglini@arm.com MISCREG_HSR, 21813392Sgiacomo.travaglini@arm.com MISCREG_DFAR, 21913392Sgiacomo.travaglini@arm.com MISCREG_DFAR_NS, 22013392Sgiacomo.travaglini@arm.com MISCREG_DFAR_S, 22113392Sgiacomo.travaglini@arm.com MISCREG_IFAR, 22213392Sgiacomo.travaglini@arm.com MISCREG_IFAR_NS, 22313392Sgiacomo.travaglini@arm.com MISCREG_IFAR_S, 22413392Sgiacomo.travaglini@arm.com MISCREG_HDFAR, 22513392Sgiacomo.travaglini@arm.com MISCREG_HIFAR, 22613392Sgiacomo.travaglini@arm.com MISCREG_HPFAR, 22713392Sgiacomo.travaglini@arm.com MISCREG_ICIALLUIS, 22813392Sgiacomo.travaglini@arm.com MISCREG_BPIALLIS, 22913392Sgiacomo.travaglini@arm.com MISCREG_PAR, 23013392Sgiacomo.travaglini@arm.com MISCREG_PAR_NS, 23113392Sgiacomo.travaglini@arm.com MISCREG_PAR_S, 23213392Sgiacomo.travaglini@arm.com MISCREG_ICIALLU, 23313392Sgiacomo.travaglini@arm.com MISCREG_ICIMVAU, 23413392Sgiacomo.travaglini@arm.com MISCREG_CP15ISB, 23513392Sgiacomo.travaglini@arm.com MISCREG_BPIALL, 23613392Sgiacomo.travaglini@arm.com MISCREG_BPIMVA, 23713392Sgiacomo.travaglini@arm.com MISCREG_DCIMVAC, 23813392Sgiacomo.travaglini@arm.com MISCREG_DCISW, 23913392Sgiacomo.travaglini@arm.com MISCREG_ATS1CPR, 24013392Sgiacomo.travaglini@arm.com MISCREG_ATS1CPW, 24113392Sgiacomo.travaglini@arm.com MISCREG_ATS1CUR, 24213392Sgiacomo.travaglini@arm.com MISCREG_ATS1CUW, 24313392Sgiacomo.travaglini@arm.com MISCREG_ATS12NSOPR, 24413392Sgiacomo.travaglini@arm.com MISCREG_ATS12NSOPW, 24513392Sgiacomo.travaglini@arm.com MISCREG_ATS12NSOUR, 24613392Sgiacomo.travaglini@arm.com MISCREG_ATS12NSOUW, 24713392Sgiacomo.travaglini@arm.com MISCREG_DCCMVAC, 24813392Sgiacomo.travaglini@arm.com MISCREG_DCCSW, 24913392Sgiacomo.travaglini@arm.com MISCREG_CP15DSB, 25013392Sgiacomo.travaglini@arm.com MISCREG_CP15DMB, 25113392Sgiacomo.travaglini@arm.com MISCREG_DCCMVAU, 25213392Sgiacomo.travaglini@arm.com MISCREG_DCCIMVAC, 25313392Sgiacomo.travaglini@arm.com MISCREG_DCCISW, 25413392Sgiacomo.travaglini@arm.com MISCREG_ATS1HR, 25513392Sgiacomo.travaglini@arm.com MISCREG_ATS1HW, 25613392Sgiacomo.travaglini@arm.com MISCREG_TLBIALLIS, 25713392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVAIS, 25813392Sgiacomo.travaglini@arm.com MISCREG_TLBIASIDIS, 25913392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVAAIS, 26013392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVALIS, 26113392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVAALIS, 26213392Sgiacomo.travaglini@arm.com MISCREG_ITLBIALL, 26313392Sgiacomo.travaglini@arm.com MISCREG_ITLBIMVA, 26413392Sgiacomo.travaglini@arm.com MISCREG_ITLBIASID, 26513392Sgiacomo.travaglini@arm.com MISCREG_DTLBIALL, 26613392Sgiacomo.travaglini@arm.com MISCREG_DTLBIMVA, 26713392Sgiacomo.travaglini@arm.com MISCREG_DTLBIASID, 26813392Sgiacomo.travaglini@arm.com MISCREG_TLBIALL, 26913392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVA, 27013392Sgiacomo.travaglini@arm.com MISCREG_TLBIASID, 27113392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVAA, 27213392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVAL, 27313392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVAAL, 27413392Sgiacomo.travaglini@arm.com MISCREG_TLBIIPAS2IS, 27513392Sgiacomo.travaglini@arm.com MISCREG_TLBIIPAS2LIS, 27613392Sgiacomo.travaglini@arm.com MISCREG_TLBIALLHIS, 27713392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVAHIS, 27813392Sgiacomo.travaglini@arm.com MISCREG_TLBIALLNSNHIS, 27913392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVALHIS, 28013392Sgiacomo.travaglini@arm.com MISCREG_TLBIIPAS2, 28113392Sgiacomo.travaglini@arm.com MISCREG_TLBIIPAS2L, 28213392Sgiacomo.travaglini@arm.com MISCREG_TLBIALLH, 28313392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVAH, 28413392Sgiacomo.travaglini@arm.com MISCREG_TLBIALLNSNH, 28513392Sgiacomo.travaglini@arm.com MISCREG_TLBIMVALH, 28613392Sgiacomo.travaglini@arm.com MISCREG_PMCR, 28713392Sgiacomo.travaglini@arm.com MISCREG_PMCNTENSET, 28813392Sgiacomo.travaglini@arm.com MISCREG_PMCNTENCLR, 28913392Sgiacomo.travaglini@arm.com MISCREG_PMOVSR, 29013392Sgiacomo.travaglini@arm.com MISCREG_PMSWINC, 29113392Sgiacomo.travaglini@arm.com MISCREG_PMSELR, 29213392Sgiacomo.travaglini@arm.com MISCREG_PMCEID0, 29313392Sgiacomo.travaglini@arm.com MISCREG_PMCEID1, 29413392Sgiacomo.travaglini@arm.com MISCREG_PMCCNTR, 29513392Sgiacomo.travaglini@arm.com MISCREG_PMXEVTYPER, 29613392Sgiacomo.travaglini@arm.com MISCREG_PMCCFILTR, 29713392Sgiacomo.travaglini@arm.com MISCREG_PMXEVCNTR, 29813392Sgiacomo.travaglini@arm.com MISCREG_PMUSERENR, 29913392Sgiacomo.travaglini@arm.com MISCREG_PMINTENSET, 30013392Sgiacomo.travaglini@arm.com MISCREG_PMINTENCLR, 30113392Sgiacomo.travaglini@arm.com MISCREG_PMOVSSET, 30213392Sgiacomo.travaglini@arm.com MISCREG_L2CTLR, 30313392Sgiacomo.travaglini@arm.com MISCREG_L2ECTLR, 30413392Sgiacomo.travaglini@arm.com MISCREG_PRRR, 30513392Sgiacomo.travaglini@arm.com MISCREG_PRRR_NS, 30613392Sgiacomo.travaglini@arm.com MISCREG_PRRR_S, 30713392Sgiacomo.travaglini@arm.com MISCREG_MAIR0, 30813392Sgiacomo.travaglini@arm.com MISCREG_MAIR0_NS, 30913392Sgiacomo.travaglini@arm.com MISCREG_MAIR0_S, 31013392Sgiacomo.travaglini@arm.com MISCREG_NMRR, 31113392Sgiacomo.travaglini@arm.com MISCREG_NMRR_NS, 31213392Sgiacomo.travaglini@arm.com MISCREG_NMRR_S, 31313392Sgiacomo.travaglini@arm.com MISCREG_MAIR1, 31413392Sgiacomo.travaglini@arm.com MISCREG_MAIR1_NS, 31513392Sgiacomo.travaglini@arm.com MISCREG_MAIR1_S, 31613392Sgiacomo.travaglini@arm.com MISCREG_AMAIR0, 31713392Sgiacomo.travaglini@arm.com MISCREG_AMAIR0_NS, 31813392Sgiacomo.travaglini@arm.com MISCREG_AMAIR0_S, 31913392Sgiacomo.travaglini@arm.com MISCREG_AMAIR1, 32013392Sgiacomo.travaglini@arm.com MISCREG_AMAIR1_NS, 32113392Sgiacomo.travaglini@arm.com MISCREG_AMAIR1_S, 32213392Sgiacomo.travaglini@arm.com MISCREG_HMAIR0, 32313392Sgiacomo.travaglini@arm.com MISCREG_HMAIR1, 32413392Sgiacomo.travaglini@arm.com MISCREG_HAMAIR0, 32513392Sgiacomo.travaglini@arm.com MISCREG_HAMAIR1, 32613392Sgiacomo.travaglini@arm.com MISCREG_VBAR, 32713392Sgiacomo.travaglini@arm.com MISCREG_VBAR_NS, 32813392Sgiacomo.travaglini@arm.com MISCREG_VBAR_S, 32913392Sgiacomo.travaglini@arm.com MISCREG_MVBAR, 33013392Sgiacomo.travaglini@arm.com MISCREG_RMR, 33113392Sgiacomo.travaglini@arm.com MISCREG_ISR, 33213392Sgiacomo.travaglini@arm.com MISCREG_HVBAR, 33313392Sgiacomo.travaglini@arm.com MISCREG_FCSEIDR, 33413392Sgiacomo.travaglini@arm.com MISCREG_CONTEXTIDR, 33513392Sgiacomo.travaglini@arm.com MISCREG_CONTEXTIDR_NS, 33613392Sgiacomo.travaglini@arm.com MISCREG_CONTEXTIDR_S, 33713392Sgiacomo.travaglini@arm.com MISCREG_TPIDRURW, 33813392Sgiacomo.travaglini@arm.com MISCREG_TPIDRURW_NS, 33913392Sgiacomo.travaglini@arm.com MISCREG_TPIDRURW_S, 34013392Sgiacomo.travaglini@arm.com MISCREG_TPIDRURO, 34113392Sgiacomo.travaglini@arm.com MISCREG_TPIDRURO_NS, 34213392Sgiacomo.travaglini@arm.com MISCREG_TPIDRURO_S, 34313392Sgiacomo.travaglini@arm.com MISCREG_TPIDRPRW, 34413392Sgiacomo.travaglini@arm.com MISCREG_TPIDRPRW_NS, 34513392Sgiacomo.travaglini@arm.com MISCREG_TPIDRPRW_S, 34613392Sgiacomo.travaglini@arm.com MISCREG_HTPIDR, 34713392Sgiacomo.travaglini@arm.com MISCREG_CNTFRQ, 34813392Sgiacomo.travaglini@arm.com MISCREG_CNTKCTL, 34913392Sgiacomo.travaglini@arm.com MISCREG_CNTP_TVAL, 35013392Sgiacomo.travaglini@arm.com MISCREG_CNTP_TVAL_NS, 35113392Sgiacomo.travaglini@arm.com MISCREG_CNTP_TVAL_S, 35213392Sgiacomo.travaglini@arm.com MISCREG_CNTP_CTL, 35313392Sgiacomo.travaglini@arm.com MISCREG_CNTP_CTL_NS, 35413392Sgiacomo.travaglini@arm.com MISCREG_CNTP_CTL_S, 35513392Sgiacomo.travaglini@arm.com MISCREG_CNTV_TVAL, 35613392Sgiacomo.travaglini@arm.com MISCREG_CNTV_CTL, 35713392Sgiacomo.travaglini@arm.com MISCREG_CNTHCTL, 35813392Sgiacomo.travaglini@arm.com MISCREG_CNTHP_TVAL, 35913392Sgiacomo.travaglini@arm.com MISCREG_CNTHP_CTL, 36013392Sgiacomo.travaglini@arm.com MISCREG_IL1DATA0, 36113392Sgiacomo.travaglini@arm.com MISCREG_IL1DATA1, 36213392Sgiacomo.travaglini@arm.com MISCREG_IL1DATA2, 36313392Sgiacomo.travaglini@arm.com MISCREG_IL1DATA3, 36413392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA0, 36513392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA1, 36613392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA2, 36713392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA3, 36813392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA4, 36913392Sgiacomo.travaglini@arm.com MISCREG_RAMINDEX, 37013392Sgiacomo.travaglini@arm.com MISCREG_L2ACTLR, 37113392Sgiacomo.travaglini@arm.com MISCREG_CBAR, 37213392Sgiacomo.travaglini@arm.com MISCREG_HTTBR, 37313392Sgiacomo.travaglini@arm.com MISCREG_VTTBR, 37413392Sgiacomo.travaglini@arm.com MISCREG_CNTPCT, 37513392Sgiacomo.travaglini@arm.com MISCREG_CNTVCT, 37613392Sgiacomo.travaglini@arm.com MISCREG_CNTP_CVAL, 37713392Sgiacomo.travaglini@arm.com MISCREG_CNTP_CVAL_NS, 37813392Sgiacomo.travaglini@arm.com MISCREG_CNTP_CVAL_S, 37913392Sgiacomo.travaglini@arm.com MISCREG_CNTV_CVAL, 38013392Sgiacomo.travaglini@arm.com MISCREG_CNTVOFF, 38113392Sgiacomo.travaglini@arm.com MISCREG_CNTHP_CVAL, 38213392Sgiacomo.travaglini@arm.com MISCREG_CPUMERRSR, 38313392Sgiacomo.travaglini@arm.com MISCREG_L2MERRSR, 3847259Sgblack@eecs.umich.edu 38510037SARM gem5 Developers // AArch64 registers (Op0=2) 38613392Sgiacomo.travaglini@arm.com MISCREG_MDCCINT_EL1, 38713392Sgiacomo.travaglini@arm.com MISCREG_OSDTRRX_EL1, 38813392Sgiacomo.travaglini@arm.com MISCREG_MDSCR_EL1, 38913392Sgiacomo.travaglini@arm.com MISCREG_OSDTRTX_EL1, 39013392Sgiacomo.travaglini@arm.com MISCREG_OSECCR_EL1, 39113392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR0_EL1, 39213392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR1_EL1, 39313392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR2_EL1, 39413392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR3_EL1, 39513392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR4_EL1, 39613392Sgiacomo.travaglini@arm.com MISCREG_DBGBVR5_EL1, 39713392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR0_EL1, 39813392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR1_EL1, 39913392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR2_EL1, 40013392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR3_EL1, 40113392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR4_EL1, 40213392Sgiacomo.travaglini@arm.com MISCREG_DBGBCR5_EL1, 40313392Sgiacomo.travaglini@arm.com MISCREG_DBGWVR0_EL1, 40413392Sgiacomo.travaglini@arm.com MISCREG_DBGWVR1_EL1, 40513392Sgiacomo.travaglini@arm.com MISCREG_DBGWVR2_EL1, 40613392Sgiacomo.travaglini@arm.com MISCREG_DBGWVR3_EL1, 40713392Sgiacomo.travaglini@arm.com MISCREG_DBGWCR0_EL1, 40813392Sgiacomo.travaglini@arm.com MISCREG_DBGWCR1_EL1, 40913392Sgiacomo.travaglini@arm.com MISCREG_DBGWCR2_EL1, 41013392Sgiacomo.travaglini@arm.com MISCREG_DBGWCR3_EL1, 41113392Sgiacomo.travaglini@arm.com MISCREG_MDCCSR_EL0, 41213392Sgiacomo.travaglini@arm.com MISCREG_MDDTR_EL0, 41313392Sgiacomo.travaglini@arm.com MISCREG_MDDTRTX_EL0, 41413392Sgiacomo.travaglini@arm.com MISCREG_MDDTRRX_EL0, 41513392Sgiacomo.travaglini@arm.com MISCREG_DBGVCR32_EL2, 41613392Sgiacomo.travaglini@arm.com MISCREG_MDRAR_EL1, 41713392Sgiacomo.travaglini@arm.com MISCREG_OSLAR_EL1, 41813392Sgiacomo.travaglini@arm.com MISCREG_OSLSR_EL1, 41913392Sgiacomo.travaglini@arm.com MISCREG_OSDLR_EL1, 42013392Sgiacomo.travaglini@arm.com MISCREG_DBGPRCR_EL1, 42113392Sgiacomo.travaglini@arm.com MISCREG_DBGCLAIMSET_EL1, 42213392Sgiacomo.travaglini@arm.com MISCREG_DBGCLAIMCLR_EL1, 42313392Sgiacomo.travaglini@arm.com MISCREG_DBGAUTHSTATUS_EL1, 42413392Sgiacomo.travaglini@arm.com MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+ 42513392Sgiacomo.travaglini@arm.com MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+ 4267259Sgblack@eecs.umich.edu 42710037SARM gem5 Developers // AArch64 registers (Op0=1,3) 42813392Sgiacomo.travaglini@arm.com MISCREG_MIDR_EL1, 42913392Sgiacomo.travaglini@arm.com MISCREG_MPIDR_EL1, 43013392Sgiacomo.travaglini@arm.com MISCREG_REVIDR_EL1, 43113392Sgiacomo.travaglini@arm.com MISCREG_ID_PFR0_EL1, 43213392Sgiacomo.travaglini@arm.com MISCREG_ID_PFR1_EL1, 43313392Sgiacomo.travaglini@arm.com MISCREG_ID_DFR0_EL1, 43413392Sgiacomo.travaglini@arm.com MISCREG_ID_AFR0_EL1, 43513392Sgiacomo.travaglini@arm.com MISCREG_ID_MMFR0_EL1, 43613392Sgiacomo.travaglini@arm.com MISCREG_ID_MMFR1_EL1, 43713392Sgiacomo.travaglini@arm.com MISCREG_ID_MMFR2_EL1, 43813392Sgiacomo.travaglini@arm.com MISCREG_ID_MMFR3_EL1, 43913392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR0_EL1, 44013392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR1_EL1, 44113392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR2_EL1, 44213392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR3_EL1, 44313392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR4_EL1, 44413392Sgiacomo.travaglini@arm.com MISCREG_ID_ISAR5_EL1, 44513392Sgiacomo.travaglini@arm.com MISCREG_MVFR0_EL1, 44613392Sgiacomo.travaglini@arm.com MISCREG_MVFR1_EL1, 44713392Sgiacomo.travaglini@arm.com MISCREG_MVFR2_EL1, 44813392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64PFR0_EL1, 44913392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64PFR1_EL1, 45013392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64DFR0_EL1, 45113392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64DFR1_EL1, 45213392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64AFR0_EL1, 45313392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64AFR1_EL1, 45413392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64ISAR0_EL1, 45513392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64ISAR1_EL1, 45613392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64MMFR0_EL1, 45713392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64MMFR1_EL1, 45813392Sgiacomo.travaglini@arm.com MISCREG_CCSIDR_EL1, 45913392Sgiacomo.travaglini@arm.com MISCREG_CLIDR_EL1, 46013392Sgiacomo.travaglini@arm.com MISCREG_AIDR_EL1, 46113392Sgiacomo.travaglini@arm.com MISCREG_CSSELR_EL1, 46213392Sgiacomo.travaglini@arm.com MISCREG_CTR_EL0, 46313392Sgiacomo.travaglini@arm.com MISCREG_DCZID_EL0, 46413392Sgiacomo.travaglini@arm.com MISCREG_VPIDR_EL2, 46513392Sgiacomo.travaglini@arm.com MISCREG_VMPIDR_EL2, 46613392Sgiacomo.travaglini@arm.com MISCREG_SCTLR_EL1, 46713392Sgiacomo.travaglini@arm.com MISCREG_ACTLR_EL1, 46813392Sgiacomo.travaglini@arm.com MISCREG_CPACR_EL1, 46913392Sgiacomo.travaglini@arm.com MISCREG_SCTLR_EL2, 47013392Sgiacomo.travaglini@arm.com MISCREG_ACTLR_EL2, 47113392Sgiacomo.travaglini@arm.com MISCREG_HCR_EL2, 47213392Sgiacomo.travaglini@arm.com MISCREG_MDCR_EL2, 47313392Sgiacomo.travaglini@arm.com MISCREG_CPTR_EL2, 47413392Sgiacomo.travaglini@arm.com MISCREG_HSTR_EL2, 47513392Sgiacomo.travaglini@arm.com MISCREG_HACR_EL2, 47613392Sgiacomo.travaglini@arm.com MISCREG_SCTLR_EL3, 47713392Sgiacomo.travaglini@arm.com MISCREG_ACTLR_EL3, 47813392Sgiacomo.travaglini@arm.com MISCREG_SCR_EL3, 47913392Sgiacomo.travaglini@arm.com MISCREG_SDER32_EL3, 48013392Sgiacomo.travaglini@arm.com MISCREG_CPTR_EL3, 48113392Sgiacomo.travaglini@arm.com MISCREG_MDCR_EL3, 48213392Sgiacomo.travaglini@arm.com MISCREG_TTBR0_EL1, 48313392Sgiacomo.travaglini@arm.com MISCREG_TTBR1_EL1, 48413392Sgiacomo.travaglini@arm.com MISCREG_TCR_EL1, 48513392Sgiacomo.travaglini@arm.com MISCREG_TTBR0_EL2, 48613392Sgiacomo.travaglini@arm.com MISCREG_TCR_EL2, 48713392Sgiacomo.travaglini@arm.com MISCREG_VTTBR_EL2, 48813392Sgiacomo.travaglini@arm.com MISCREG_VTCR_EL2, 48913392Sgiacomo.travaglini@arm.com MISCREG_TTBR0_EL3, 49013392Sgiacomo.travaglini@arm.com MISCREG_TCR_EL3, 49113392Sgiacomo.travaglini@arm.com MISCREG_DACR32_EL2, 49213392Sgiacomo.travaglini@arm.com MISCREG_SPSR_EL1, 49313392Sgiacomo.travaglini@arm.com MISCREG_ELR_EL1, 49413392Sgiacomo.travaglini@arm.com MISCREG_SP_EL0, 49513392Sgiacomo.travaglini@arm.com MISCREG_SPSEL, 49613392Sgiacomo.travaglini@arm.com MISCREG_CURRENTEL, 49713392Sgiacomo.travaglini@arm.com MISCREG_NZCV, 49813392Sgiacomo.travaglini@arm.com MISCREG_DAIF, 49913392Sgiacomo.travaglini@arm.com MISCREG_FPCR, 50013392Sgiacomo.travaglini@arm.com MISCREG_FPSR, 50113392Sgiacomo.travaglini@arm.com MISCREG_DSPSR_EL0, 50213392Sgiacomo.travaglini@arm.com MISCREG_DLR_EL0, 50313392Sgiacomo.travaglini@arm.com MISCREG_SPSR_EL2, 50413392Sgiacomo.travaglini@arm.com MISCREG_ELR_EL2, 50513392Sgiacomo.travaglini@arm.com MISCREG_SP_EL1, 50613392Sgiacomo.travaglini@arm.com MISCREG_SPSR_IRQ_AA64, 50713392Sgiacomo.travaglini@arm.com MISCREG_SPSR_ABT_AA64, 50813392Sgiacomo.travaglini@arm.com MISCREG_SPSR_UND_AA64, 50913392Sgiacomo.travaglini@arm.com MISCREG_SPSR_FIQ_AA64, 51013392Sgiacomo.travaglini@arm.com MISCREG_SPSR_EL3, 51113392Sgiacomo.travaglini@arm.com MISCREG_ELR_EL3, 51213392Sgiacomo.travaglini@arm.com MISCREG_SP_EL2, 51313392Sgiacomo.travaglini@arm.com MISCREG_AFSR0_EL1, 51413392Sgiacomo.travaglini@arm.com MISCREG_AFSR1_EL1, 51513392Sgiacomo.travaglini@arm.com MISCREG_ESR_EL1, 51613392Sgiacomo.travaglini@arm.com MISCREG_IFSR32_EL2, 51713392Sgiacomo.travaglini@arm.com MISCREG_AFSR0_EL2, 51813392Sgiacomo.travaglini@arm.com MISCREG_AFSR1_EL2, 51913392Sgiacomo.travaglini@arm.com MISCREG_ESR_EL2, 52013392Sgiacomo.travaglini@arm.com MISCREG_FPEXC32_EL2, 52113392Sgiacomo.travaglini@arm.com MISCREG_AFSR0_EL3, 52213392Sgiacomo.travaglini@arm.com MISCREG_AFSR1_EL3, 52313392Sgiacomo.travaglini@arm.com MISCREG_ESR_EL3, 52413392Sgiacomo.travaglini@arm.com MISCREG_FAR_EL1, 52513392Sgiacomo.travaglini@arm.com MISCREG_FAR_EL2, 52613392Sgiacomo.travaglini@arm.com MISCREG_HPFAR_EL2, 52713392Sgiacomo.travaglini@arm.com MISCREG_FAR_EL3, 52813392Sgiacomo.travaglini@arm.com MISCREG_IC_IALLUIS, 52913392Sgiacomo.travaglini@arm.com MISCREG_PAR_EL1, 53013392Sgiacomo.travaglini@arm.com MISCREG_IC_IALLU, 53113392Sgiacomo.travaglini@arm.com MISCREG_DC_IVAC_Xt, 53213392Sgiacomo.travaglini@arm.com MISCREG_DC_ISW_Xt, 53313392Sgiacomo.travaglini@arm.com MISCREG_AT_S1E1R_Xt, 53413392Sgiacomo.travaglini@arm.com MISCREG_AT_S1E1W_Xt, 53513392Sgiacomo.travaglini@arm.com MISCREG_AT_S1E0R_Xt, 53613392Sgiacomo.travaglini@arm.com MISCREG_AT_S1E0W_Xt, 53713392Sgiacomo.travaglini@arm.com MISCREG_DC_CSW_Xt, 53813392Sgiacomo.travaglini@arm.com MISCREG_DC_CISW_Xt, 53913392Sgiacomo.travaglini@arm.com MISCREG_DC_ZVA_Xt, 54013392Sgiacomo.travaglini@arm.com MISCREG_IC_IVAU_Xt, 54113392Sgiacomo.travaglini@arm.com MISCREG_DC_CVAC_Xt, 54213392Sgiacomo.travaglini@arm.com MISCREG_DC_CVAU_Xt, 54313392Sgiacomo.travaglini@arm.com MISCREG_DC_CIVAC_Xt, 54413392Sgiacomo.travaglini@arm.com MISCREG_AT_S1E2R_Xt, 54513392Sgiacomo.travaglini@arm.com MISCREG_AT_S1E2W_Xt, 54613392Sgiacomo.travaglini@arm.com MISCREG_AT_S12E1R_Xt, 54713392Sgiacomo.travaglini@arm.com MISCREG_AT_S12E1W_Xt, 54813392Sgiacomo.travaglini@arm.com MISCREG_AT_S12E0R_Xt, 54913392Sgiacomo.travaglini@arm.com MISCREG_AT_S12E0W_Xt, 55013392Sgiacomo.travaglini@arm.com MISCREG_AT_S1E3R_Xt, 55113392Sgiacomo.travaglini@arm.com MISCREG_AT_S1E3W_Xt, 55213392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VMALLE1IS, 55313392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAE1IS_Xt, 55413392Sgiacomo.travaglini@arm.com MISCREG_TLBI_ASIDE1IS_Xt, 55513392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAAE1IS_Xt, 55613392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VALE1IS_Xt, 55713392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAALE1IS_Xt, 55813392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VMALLE1, 55913392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAE1_Xt, 56013392Sgiacomo.travaglini@arm.com MISCREG_TLBI_ASIDE1_Xt, 56113392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAAE1_Xt, 56213392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VALE1_Xt, 56313392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAALE1_Xt, 56413392Sgiacomo.travaglini@arm.com MISCREG_TLBI_IPAS2E1IS_Xt, 56513392Sgiacomo.travaglini@arm.com MISCREG_TLBI_IPAS2LE1IS_Xt, 56613392Sgiacomo.travaglini@arm.com MISCREG_TLBI_ALLE2IS, 56713392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAE2IS_Xt, 56813392Sgiacomo.travaglini@arm.com MISCREG_TLBI_ALLE1IS, 56913392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VALE2IS_Xt, 57013392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VMALLS12E1IS, 57113392Sgiacomo.travaglini@arm.com MISCREG_TLBI_IPAS2E1_Xt, 57213392Sgiacomo.travaglini@arm.com MISCREG_TLBI_IPAS2LE1_Xt, 57313392Sgiacomo.travaglini@arm.com MISCREG_TLBI_ALLE2, 57413392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAE2_Xt, 57513392Sgiacomo.travaglini@arm.com MISCREG_TLBI_ALLE1, 57613392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VALE2_Xt, 57713392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VMALLS12E1, 57813392Sgiacomo.travaglini@arm.com MISCREG_TLBI_ALLE3IS, 57913392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAE3IS_Xt, 58013392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VALE3IS_Xt, 58113392Sgiacomo.travaglini@arm.com MISCREG_TLBI_ALLE3, 58213392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VAE3_Xt, 58313392Sgiacomo.travaglini@arm.com MISCREG_TLBI_VALE3_Xt, 58413392Sgiacomo.travaglini@arm.com MISCREG_PMINTENSET_EL1, 58513392Sgiacomo.travaglini@arm.com MISCREG_PMINTENCLR_EL1, 58613392Sgiacomo.travaglini@arm.com MISCREG_PMCR_EL0, 58713392Sgiacomo.travaglini@arm.com MISCREG_PMCNTENSET_EL0, 58813392Sgiacomo.travaglini@arm.com MISCREG_PMCNTENCLR_EL0, 58913392Sgiacomo.travaglini@arm.com MISCREG_PMOVSCLR_EL0, 59013392Sgiacomo.travaglini@arm.com MISCREG_PMSWINC_EL0, 59113392Sgiacomo.travaglini@arm.com MISCREG_PMSELR_EL0, 59213392Sgiacomo.travaglini@arm.com MISCREG_PMCEID0_EL0, 59313392Sgiacomo.travaglini@arm.com MISCREG_PMCEID1_EL0, 59413392Sgiacomo.travaglini@arm.com MISCREG_PMCCNTR_EL0, 59513392Sgiacomo.travaglini@arm.com MISCREG_PMXEVTYPER_EL0, 59613392Sgiacomo.travaglini@arm.com MISCREG_PMCCFILTR_EL0, 59713392Sgiacomo.travaglini@arm.com MISCREG_PMXEVCNTR_EL0, 59813392Sgiacomo.travaglini@arm.com MISCREG_PMUSERENR_EL0, 59913392Sgiacomo.travaglini@arm.com MISCREG_PMOVSSET_EL0, 60013392Sgiacomo.travaglini@arm.com MISCREG_MAIR_EL1, 60113392Sgiacomo.travaglini@arm.com MISCREG_AMAIR_EL1, 60213392Sgiacomo.travaglini@arm.com MISCREG_MAIR_EL2, 60313392Sgiacomo.travaglini@arm.com MISCREG_AMAIR_EL2, 60413392Sgiacomo.travaglini@arm.com MISCREG_MAIR_EL3, 60513392Sgiacomo.travaglini@arm.com MISCREG_AMAIR_EL3, 60613392Sgiacomo.travaglini@arm.com MISCREG_L2CTLR_EL1, 60713392Sgiacomo.travaglini@arm.com MISCREG_L2ECTLR_EL1, 60813392Sgiacomo.travaglini@arm.com MISCREG_VBAR_EL1, 60913392Sgiacomo.travaglini@arm.com MISCREG_RVBAR_EL1, 61013392Sgiacomo.travaglini@arm.com MISCREG_ISR_EL1, 61113392Sgiacomo.travaglini@arm.com MISCREG_VBAR_EL2, 61213392Sgiacomo.travaglini@arm.com MISCREG_RVBAR_EL2, 61313392Sgiacomo.travaglini@arm.com MISCREG_VBAR_EL3, 61413392Sgiacomo.travaglini@arm.com MISCREG_RVBAR_EL3, 61513392Sgiacomo.travaglini@arm.com MISCREG_RMR_EL3, 61613392Sgiacomo.travaglini@arm.com MISCREG_CONTEXTIDR_EL1, 61713392Sgiacomo.travaglini@arm.com MISCREG_TPIDR_EL1, 61813392Sgiacomo.travaglini@arm.com MISCREG_TPIDR_EL0, 61913392Sgiacomo.travaglini@arm.com MISCREG_TPIDRRO_EL0, 62013392Sgiacomo.travaglini@arm.com MISCREG_TPIDR_EL2, 62113392Sgiacomo.travaglini@arm.com MISCREG_TPIDR_EL3, 62213392Sgiacomo.travaglini@arm.com MISCREG_CNTKCTL_EL1, 62313392Sgiacomo.travaglini@arm.com MISCREG_CNTFRQ_EL0, 62413392Sgiacomo.travaglini@arm.com MISCREG_CNTPCT_EL0, 62513392Sgiacomo.travaglini@arm.com MISCREG_CNTVCT_EL0, 62613392Sgiacomo.travaglini@arm.com MISCREG_CNTP_TVAL_EL0, 62713392Sgiacomo.travaglini@arm.com MISCREG_CNTP_CTL_EL0, 62813392Sgiacomo.travaglini@arm.com MISCREG_CNTP_CVAL_EL0, 62913392Sgiacomo.travaglini@arm.com MISCREG_CNTV_TVAL_EL0, 63013392Sgiacomo.travaglini@arm.com MISCREG_CNTV_CTL_EL0, 63113392Sgiacomo.travaglini@arm.com MISCREG_CNTV_CVAL_EL0, 63213392Sgiacomo.travaglini@arm.com MISCREG_PMEVCNTR0_EL0, 63313392Sgiacomo.travaglini@arm.com MISCREG_PMEVCNTR1_EL0, 63413392Sgiacomo.travaglini@arm.com MISCREG_PMEVCNTR2_EL0, 63513392Sgiacomo.travaglini@arm.com MISCREG_PMEVCNTR3_EL0, 63613392Sgiacomo.travaglini@arm.com MISCREG_PMEVCNTR4_EL0, 63713392Sgiacomo.travaglini@arm.com MISCREG_PMEVCNTR5_EL0, 63813392Sgiacomo.travaglini@arm.com MISCREG_PMEVTYPER0_EL0, 63913392Sgiacomo.travaglini@arm.com MISCREG_PMEVTYPER1_EL0, 64013392Sgiacomo.travaglini@arm.com MISCREG_PMEVTYPER2_EL0, 64113392Sgiacomo.travaglini@arm.com MISCREG_PMEVTYPER3_EL0, 64213392Sgiacomo.travaglini@arm.com MISCREG_PMEVTYPER4_EL0, 64313392Sgiacomo.travaglini@arm.com MISCREG_PMEVTYPER5_EL0, 64413392Sgiacomo.travaglini@arm.com MISCREG_CNTVOFF_EL2, 64513392Sgiacomo.travaglini@arm.com MISCREG_CNTHCTL_EL2, 64613392Sgiacomo.travaglini@arm.com MISCREG_CNTHP_TVAL_EL2, 64713392Sgiacomo.travaglini@arm.com MISCREG_CNTHP_CTL_EL2, 64813392Sgiacomo.travaglini@arm.com MISCREG_CNTHP_CVAL_EL2, 64913392Sgiacomo.travaglini@arm.com MISCREG_CNTPS_TVAL_EL1, 65013392Sgiacomo.travaglini@arm.com MISCREG_CNTPS_CTL_EL1, 65113392Sgiacomo.travaglini@arm.com MISCREG_CNTPS_CVAL_EL1, 65213392Sgiacomo.travaglini@arm.com MISCREG_IL1DATA0_EL1, 65313392Sgiacomo.travaglini@arm.com MISCREG_IL1DATA1_EL1, 65413392Sgiacomo.travaglini@arm.com MISCREG_IL1DATA2_EL1, 65513392Sgiacomo.travaglini@arm.com MISCREG_IL1DATA3_EL1, 65613392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA0_EL1, 65713392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA1_EL1, 65813392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA2_EL1, 65913392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA3_EL1, 66013392Sgiacomo.travaglini@arm.com MISCREG_DL1DATA4_EL1, 66113392Sgiacomo.travaglini@arm.com MISCREG_L2ACTLR_EL1, 66213392Sgiacomo.travaglini@arm.com MISCREG_CPUACTLR_EL1, 66313392Sgiacomo.travaglini@arm.com MISCREG_CPUECTLR_EL1, 66413392Sgiacomo.travaglini@arm.com MISCREG_CPUMERRSR_EL1, 66513392Sgiacomo.travaglini@arm.com MISCREG_L2MERRSR_EL1, 66613392Sgiacomo.travaglini@arm.com MISCREG_CBAR_EL1, 66713392Sgiacomo.travaglini@arm.com MISCREG_CONTEXTIDR_EL2, 6687259Sgblack@eecs.umich.edu 66912675Sgiacomo.travaglini@arm.com // Introduced in ARMv8.1 67013392Sgiacomo.travaglini@arm.com MISCREG_TTBR1_EL2, 67113392Sgiacomo.travaglini@arm.com MISCREG_CNTHV_CTL_EL2, 67213392Sgiacomo.travaglini@arm.com MISCREG_CNTHV_CVAL_EL2, 67313392Sgiacomo.travaglini@arm.com MISCREG_CNTHV_TVAL_EL2, 67412675Sgiacomo.travaglini@arm.com 67513392Sgiacomo.travaglini@arm.com MISCREG_ID_AA64MMFR2_EL1, 67612529Sgiacomo.travaglini@arm.com // These MISCREG_FREESLOT are available Misc Register 67712529Sgiacomo.travaglini@arm.com // slots for future registers to be implemented. 67813392Sgiacomo.travaglini@arm.com MISCREG_FREESLOT_1, 67912529Sgiacomo.travaglini@arm.com 68012529Sgiacomo.travaglini@arm.com // NUM_PHYS_MISCREGS specifies the number of actual physical 68112529Sgiacomo.travaglini@arm.com // registers, not considering the following pseudo-registers 68212530Sgiacomo.travaglini@arm.com // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. 68312529Sgiacomo.travaglini@arm.com // Checkpointing should use this physical index when 68412529Sgiacomo.travaglini@arm.com // saving/restoring register values. 68513392Sgiacomo.travaglini@arm.com NUM_PHYS_MISCREGS, 68612529Sgiacomo.travaglini@arm.com 68710037SARM gem5 Developers // Dummy registers 68812529Sgiacomo.travaglini@arm.com MISCREG_NOP, 68912529Sgiacomo.travaglini@arm.com MISCREG_RAZ, 69012529Sgiacomo.travaglini@arm.com MISCREG_CP14_UNIMPL, 69112529Sgiacomo.travaglini@arm.com MISCREG_CP15_UNIMPL, 69212529Sgiacomo.travaglini@arm.com MISCREG_UNKNOWN, 69310037SARM gem5 Developers 69412530Sgiacomo.travaglini@arm.com // Implementation defined register: this represent 69512530Sgiacomo.travaglini@arm.com // a pool of unimplemented registers whose access can throw 69612530Sgiacomo.travaglini@arm.com // either UNDEFINED or hypervisor trap exception. 69712530Sgiacomo.travaglini@arm.com MISCREG_IMPDEF_UNIMPL, 69812530Sgiacomo.travaglini@arm.com 69912815Sgiacomo.travaglini@arm.com // RAS extension (unimplemented) 70012815Sgiacomo.travaglini@arm.com MISCREG_ERRIDR_EL1, 70112815Sgiacomo.travaglini@arm.com MISCREG_ERRSELR_EL1, 70212815Sgiacomo.travaglini@arm.com MISCREG_ERXFR_EL1, 70312815Sgiacomo.travaglini@arm.com MISCREG_ERXCTLR_EL1, 70412815Sgiacomo.travaglini@arm.com MISCREG_ERXSTATUS_EL1, 70512815Sgiacomo.travaglini@arm.com MISCREG_ERXADDR_EL1, 70612815Sgiacomo.travaglini@arm.com MISCREG_ERXMISC0_EL1, 70712815Sgiacomo.travaglini@arm.com MISCREG_ERXMISC1_EL1, 70812815Sgiacomo.travaglini@arm.com MISCREG_DISR_EL1, 70912815Sgiacomo.travaglini@arm.com MISCREG_VSESR_EL2, 71012815Sgiacomo.travaglini@arm.com MISCREG_VDISR_EL2, 71112815Sgiacomo.travaglini@arm.com 71212529Sgiacomo.travaglini@arm.com // Total number of Misc Registers: Physical + Dummy 71312529Sgiacomo.travaglini@arm.com NUM_MISCREGS 7146261Sgblack@eecs.umich.edu }; 7156261Sgblack@eecs.umich.edu 71610037SARM gem5 Developers enum MiscRegInfo { 71710037SARM gem5 Developers MISCREG_IMPLEMENTED, 71810506SAli.Saidi@ARM.com MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a 71910506SAli.Saidi@ARM.com // arch generic counter) 72010037SARM gem5 Developers MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it 72110037SARM gem5 Developers // tells whether the instruction should raise a 72210037SARM gem5 Developers // warning or fail 72310037SARM gem5 Developers MISCREG_MUTEX, // True if the register corresponds to a pair of 72410037SARM gem5 Developers // mutually exclusive registers 72510037SARM gem5 Developers MISCREG_BANKED, // True if the register is banked between the two 72610037SARM gem5 Developers // security states, and this is the parent node of the 72710037SARM gem5 Developers // two banked registers 72810037SARM gem5 Developers MISCREG_BANKED_CHILD, // The entry is one of the child registers that 72910037SARM gem5 Developers // forms a banked set of regs (along with the 73010037SARM gem5 Developers // other child regs) 73110037SARM gem5 Developers 73210037SARM gem5 Developers // Access permissions 73310037SARM gem5 Developers // User mode 73410037SARM gem5 Developers MISCREG_USR_NS_RD, 73510037SARM gem5 Developers MISCREG_USR_NS_WR, 73610037SARM gem5 Developers MISCREG_USR_S_RD, 73710037SARM gem5 Developers MISCREG_USR_S_WR, 73810037SARM gem5 Developers // Privileged modes other than hypervisor or monitor 73910037SARM gem5 Developers MISCREG_PRI_NS_RD, 74010037SARM gem5 Developers MISCREG_PRI_NS_WR, 74110037SARM gem5 Developers MISCREG_PRI_S_RD, 74210037SARM gem5 Developers MISCREG_PRI_S_WR, 74310037SARM gem5 Developers // Hypervisor mode 74410037SARM gem5 Developers MISCREG_HYP_RD, 74510037SARM gem5 Developers MISCREG_HYP_WR, 74610037SARM gem5 Developers // Monitor mode, SCR.NS == 0 74710037SARM gem5 Developers MISCREG_MON_NS0_RD, 74810037SARM gem5 Developers MISCREG_MON_NS0_WR, 74910037SARM gem5 Developers // Monitor mode, SCR.NS == 1 75010037SARM gem5 Developers MISCREG_MON_NS1_RD, 75110037SARM gem5 Developers MISCREG_MON_NS1_WR, 75210037SARM gem5 Developers 75310037SARM gem5 Developers NUM_MISCREG_INFOS 75410037SARM gem5 Developers }; 75510037SARM gem5 Developers 75610037SARM gem5 Developers extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; 75710037SARM gem5 Developers 75810037SARM gem5 Developers // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions 7598868SMatt.Horsnell@arm.com MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 7608868SMatt.Horsnell@arm.com unsigned crm, unsigned opc2); 76110037SARM gem5 Developers MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, 76210037SARM gem5 Developers unsigned crn, unsigned crm, 76310037SARM gem5 Developers unsigned op2); 76410037SARM gem5 Developers // Whether a particular AArch64 system register is -always- read only. 76510037SARM gem5 Developers bool aarch64SysRegReadOnly(MiscRegIndex miscReg); 7668868SMatt.Horsnell@arm.com 76710037SARM gem5 Developers // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions 7687259Sgblack@eecs.umich.edu MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 7697259Sgblack@eecs.umich.edu unsigned crm, unsigned opc2); 7707259Sgblack@eecs.umich.edu 77110037SARM gem5 Developers // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions 77210037SARM gem5 Developers MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1); 77310037SARM gem5 Developers 7748868SMatt.Horsnell@arm.com 7759256SAndreas.Sandberg@arm.com const char * const miscRegName[] = { 77610037SARM gem5 Developers "cpsr", 77710037SARM gem5 Developers "spsr", 77810037SARM gem5 Developers "spsr_fiq", 77910037SARM gem5 Developers "spsr_irq", 78010037SARM gem5 Developers "spsr_svc", 78110037SARM gem5 Developers "spsr_mon", 78210037SARM gem5 Developers "spsr_abt", 78310037SARM gem5 Developers "spsr_hyp", 78410037SARM gem5 Developers "spsr_und", 78510037SARM gem5 Developers "elr_hyp", 78610037SARM gem5 Developers "fpsid", 78710037SARM gem5 Developers "fpscr", 78810037SARM gem5 Developers "mvfr1", 78910037SARM gem5 Developers "mvfr0", 79010037SARM gem5 Developers "fpexc", 79110037SARM gem5 Developers 79210037SARM gem5 Developers // Helper registers 79310037SARM gem5 Developers "cpsr_mode", 79410037SARM gem5 Developers "cpsr_q", 79510037SARM gem5 Developers "fpscr_exc", 79610037SARM gem5 Developers "fpscr_qc", 79710037SARM gem5 Developers "lockaddr", 79810037SARM gem5 Developers "lockflag", 79910037SARM gem5 Developers "prrr_mair0", 80010037SARM gem5 Developers "prrr_mair0_ns", 80110037SARM gem5 Developers "prrr_mair0_s", 80210037SARM gem5 Developers "nmrr_mair1", 80310037SARM gem5 Developers "nmrr_mair1_ns", 80410037SARM gem5 Developers "nmrr_mair1_s", 80510037SARM gem5 Developers "pmxevtyper_pmccfiltr", 80610037SARM gem5 Developers "sctlr_rst", 80710037SARM gem5 Developers "sev_mailbox", 80810037SARM gem5 Developers 80910037SARM gem5 Developers // AArch32 CP14 registers 81010037SARM gem5 Developers "dbgdidr", 81110037SARM gem5 Developers "dbgdscrint", 81210037SARM gem5 Developers "dbgdccint", 81310037SARM gem5 Developers "dbgdtrtxint", 81410037SARM gem5 Developers "dbgdtrrxint", 81510037SARM gem5 Developers "dbgwfar", 81610037SARM gem5 Developers "dbgvcr", 81710037SARM gem5 Developers "dbgdtrrxext", 81810037SARM gem5 Developers "dbgdscrext", 81910037SARM gem5 Developers "dbgdtrtxext", 82010037SARM gem5 Developers "dbgoseccr", 82110037SARM gem5 Developers "dbgbvr0", 82210037SARM gem5 Developers "dbgbvr1", 82310037SARM gem5 Developers "dbgbvr2", 82410037SARM gem5 Developers "dbgbvr3", 82510037SARM gem5 Developers "dbgbvr4", 82610037SARM gem5 Developers "dbgbvr5", 82710037SARM gem5 Developers "dbgbcr0", 82810037SARM gem5 Developers "dbgbcr1", 82910037SARM gem5 Developers "dbgbcr2", 83010037SARM gem5 Developers "dbgbcr3", 83110037SARM gem5 Developers "dbgbcr4", 83210037SARM gem5 Developers "dbgbcr5", 83310037SARM gem5 Developers "dbgwvr0", 83410037SARM gem5 Developers "dbgwvr1", 83510037SARM gem5 Developers "dbgwvr2", 83610037SARM gem5 Developers "dbgwvr3", 83710037SARM gem5 Developers "dbgwcr0", 83810037SARM gem5 Developers "dbgwcr1", 83910037SARM gem5 Developers "dbgwcr2", 84010037SARM gem5 Developers "dbgwcr3", 84110037SARM gem5 Developers "dbgdrar", 84210037SARM gem5 Developers "dbgbxvr4", 84310037SARM gem5 Developers "dbgbxvr5", 84410037SARM gem5 Developers "dbgoslar", 84510037SARM gem5 Developers "dbgoslsr", 84610037SARM gem5 Developers "dbgosdlr", 84710037SARM gem5 Developers "dbgprcr", 84810037SARM gem5 Developers "dbgdsar", 84910037SARM gem5 Developers "dbgclaimset", 85010037SARM gem5 Developers "dbgclaimclr", 85110037SARM gem5 Developers "dbgauthstatus", 85210037SARM gem5 Developers "dbgdevid2", 85310037SARM gem5 Developers "dbgdevid1", 85410037SARM gem5 Developers "dbgdevid0", 85510037SARM gem5 Developers "teecr", 85610037SARM gem5 Developers "jidr", 85710037SARM gem5 Developers "teehbr", 85810037SARM gem5 Developers "joscr", 85910037SARM gem5 Developers "jmcr", 86010037SARM gem5 Developers 86110037SARM gem5 Developers // AArch32 CP15 registers 86210037SARM gem5 Developers "midr", 86310037SARM gem5 Developers "ctr", 86410037SARM gem5 Developers "tcmtr", 86510037SARM gem5 Developers "tlbtr", 86610037SARM gem5 Developers "mpidr", 86710037SARM gem5 Developers "revidr", 86810037SARM gem5 Developers "id_pfr0", 86910037SARM gem5 Developers "id_pfr1", 87010037SARM gem5 Developers "id_dfr0", 87110037SARM gem5 Developers "id_afr0", 87210037SARM gem5 Developers "id_mmfr0", 87310037SARM gem5 Developers "id_mmfr1", 87410037SARM gem5 Developers "id_mmfr2", 87510037SARM gem5 Developers "id_mmfr3", 87610037SARM gem5 Developers "id_isar0", 87710037SARM gem5 Developers "id_isar1", 87810037SARM gem5 Developers "id_isar2", 87910037SARM gem5 Developers "id_isar3", 88010037SARM gem5 Developers "id_isar4", 88110037SARM gem5 Developers "id_isar5", 88210037SARM gem5 Developers "ccsidr", 88310037SARM gem5 Developers "clidr", 88410037SARM gem5 Developers "aidr", 88510037SARM gem5 Developers "csselr", 88610037SARM gem5 Developers "csselr_ns", 88710037SARM gem5 Developers "csselr_s", 88810037SARM gem5 Developers "vpidr", 88910037SARM gem5 Developers "vmpidr", 89010037SARM gem5 Developers "sctlr", 89110037SARM gem5 Developers "sctlr_ns", 89210037SARM gem5 Developers "sctlr_s", 89310037SARM gem5 Developers "actlr", 89410037SARM gem5 Developers "actlr_ns", 89510037SARM gem5 Developers "actlr_s", 89610037SARM gem5 Developers "cpacr", 89710037SARM gem5 Developers "scr", 89810037SARM gem5 Developers "sder", 89910037SARM gem5 Developers "nsacr", 90010037SARM gem5 Developers "hsctlr", 90110037SARM gem5 Developers "hactlr", 90210037SARM gem5 Developers "hcr", 90310037SARM gem5 Developers "hdcr", 90410037SARM gem5 Developers "hcptr", 90510037SARM gem5 Developers "hstr", 90610037SARM gem5 Developers "hacr", 90710037SARM gem5 Developers "ttbr0", 90810037SARM gem5 Developers "ttbr0_ns", 90910037SARM gem5 Developers "ttbr0_s", 91010037SARM gem5 Developers "ttbr1", 91110037SARM gem5 Developers "ttbr1_ns", 91210037SARM gem5 Developers "ttbr1_s", 91310037SARM gem5 Developers "ttbcr", 91410037SARM gem5 Developers "ttbcr_ns", 91510037SARM gem5 Developers "ttbcr_s", 91610037SARM gem5 Developers "htcr", 91710037SARM gem5 Developers "vtcr", 91810037SARM gem5 Developers "dacr", 91910037SARM gem5 Developers "dacr_ns", 92010037SARM gem5 Developers "dacr_s", 92110037SARM gem5 Developers "dfsr", 92210037SARM gem5 Developers "dfsr_ns", 92310037SARM gem5 Developers "dfsr_s", 92410037SARM gem5 Developers "ifsr", 92510037SARM gem5 Developers "ifsr_ns", 92610037SARM gem5 Developers "ifsr_s", 92710037SARM gem5 Developers "adfsr", 92810037SARM gem5 Developers "adfsr_ns", 92910037SARM gem5 Developers "adfsr_s", 93010037SARM gem5 Developers "aifsr", 93110037SARM gem5 Developers "aifsr_ns", 93210037SARM gem5 Developers "aifsr_s", 93310037SARM gem5 Developers "hadfsr", 93410037SARM gem5 Developers "haifsr", 93510037SARM gem5 Developers "hsr", 93610037SARM gem5 Developers "dfar", 93710037SARM gem5 Developers "dfar_ns", 93810037SARM gem5 Developers "dfar_s", 93910037SARM gem5 Developers "ifar", 94010037SARM gem5 Developers "ifar_ns", 94110037SARM gem5 Developers "ifar_s", 94210037SARM gem5 Developers "hdfar", 94310037SARM gem5 Developers "hifar", 94410037SARM gem5 Developers "hpfar", 94510037SARM gem5 Developers "icialluis", 94610037SARM gem5 Developers "bpiallis", 94710037SARM gem5 Developers "par", 94810037SARM gem5 Developers "par_ns", 94910037SARM gem5 Developers "par_s", 95010037SARM gem5 Developers "iciallu", 95110037SARM gem5 Developers "icimvau", 95210037SARM gem5 Developers "cp15isb", 95310037SARM gem5 Developers "bpiall", 95410037SARM gem5 Developers "bpimva", 95510037SARM gem5 Developers "dcimvac", 95610037SARM gem5 Developers "dcisw", 95710037SARM gem5 Developers "ats1cpr", 95810037SARM gem5 Developers "ats1cpw", 95910037SARM gem5 Developers "ats1cur", 96010037SARM gem5 Developers "ats1cuw", 96110037SARM gem5 Developers "ats12nsopr", 96210037SARM gem5 Developers "ats12nsopw", 96310037SARM gem5 Developers "ats12nsour", 96410037SARM gem5 Developers "ats12nsouw", 96510037SARM gem5 Developers "dccmvac", 96610037SARM gem5 Developers "dccsw", 96710037SARM gem5 Developers "cp15dsb", 96810037SARM gem5 Developers "cp15dmb", 96910037SARM gem5 Developers "dccmvau", 97010037SARM gem5 Developers "dccimvac", 97110037SARM gem5 Developers "dccisw", 97210037SARM gem5 Developers "ats1hr", 97310037SARM gem5 Developers "ats1hw", 97410037SARM gem5 Developers "tlbiallis", 97510037SARM gem5 Developers "tlbimvais", 97610037SARM gem5 Developers "tlbiasidis", 97710037SARM gem5 Developers "tlbimvaais", 97810037SARM gem5 Developers "tlbimvalis", 97910037SARM gem5 Developers "tlbimvaalis", 98010037SARM gem5 Developers "itlbiall", 98110037SARM gem5 Developers "itlbimva", 98210037SARM gem5 Developers "itlbiasid", 98310037SARM gem5 Developers "dtlbiall", 98410037SARM gem5 Developers "dtlbimva", 98510037SARM gem5 Developers "dtlbiasid", 98610037SARM gem5 Developers "tlbiall", 98710037SARM gem5 Developers "tlbimva", 98810037SARM gem5 Developers "tlbiasid", 98910037SARM gem5 Developers "tlbimvaa", 99010037SARM gem5 Developers "tlbimval", 99110037SARM gem5 Developers "tlbimvaal", 99210037SARM gem5 Developers "tlbiipas2is", 99310037SARM gem5 Developers "tlbiipas2lis", 99410037SARM gem5 Developers "tlbiallhis", 99510037SARM gem5 Developers "tlbimvahis", 99610037SARM gem5 Developers "tlbiallnsnhis", 99710037SARM gem5 Developers "tlbimvalhis", 99810037SARM gem5 Developers "tlbiipas2", 99910037SARM gem5 Developers "tlbiipas2l", 100010037SARM gem5 Developers "tlbiallh", 100110037SARM gem5 Developers "tlbimvah", 100210037SARM gem5 Developers "tlbiallnsnh", 100310037SARM gem5 Developers "tlbimvalh", 100410037SARM gem5 Developers "pmcr", 100510037SARM gem5 Developers "pmcntenset", 100610037SARM gem5 Developers "pmcntenclr", 100710037SARM gem5 Developers "pmovsr", 100810037SARM gem5 Developers "pmswinc", 100910037SARM gem5 Developers "pmselr", 101010037SARM gem5 Developers "pmceid0", 101110037SARM gem5 Developers "pmceid1", 101210037SARM gem5 Developers "pmccntr", 101310037SARM gem5 Developers "pmxevtyper", 101410037SARM gem5 Developers "pmccfiltr", 101510037SARM gem5 Developers "pmxevcntr", 101610037SARM gem5 Developers "pmuserenr", 101710037SARM gem5 Developers "pmintenset", 101810037SARM gem5 Developers "pmintenclr", 101910037SARM gem5 Developers "pmovsset", 10208549Sdaniel.johnson@arm.com "l2ctlr", 102110037SARM gem5 Developers "l2ectlr", 102210037SARM gem5 Developers "prrr", 102310037SARM gem5 Developers "prrr_ns", 102410037SARM gem5 Developers "prrr_s", 102510037SARM gem5 Developers "mair0", 102610037SARM gem5 Developers "mair0_ns", 102710037SARM gem5 Developers "mair0_s", 102810037SARM gem5 Developers "nmrr", 102910037SARM gem5 Developers "nmrr_ns", 103010037SARM gem5 Developers "nmrr_s", 103110037SARM gem5 Developers "mair1", 103210037SARM gem5 Developers "mair1_ns", 103310037SARM gem5 Developers "mair1_s", 103410037SARM gem5 Developers "amair0", 103510037SARM gem5 Developers "amair0_ns", 103610037SARM gem5 Developers "amair0_s", 103710037SARM gem5 Developers "amair1", 103810037SARM gem5 Developers "amair1_ns", 103910037SARM gem5 Developers "amair1_s", 104010037SARM gem5 Developers "hmair0", 104110037SARM gem5 Developers "hmair1", 104210037SARM gem5 Developers "hamair0", 104310037SARM gem5 Developers "hamair1", 104410037SARM gem5 Developers "vbar", 104510037SARM gem5 Developers "vbar_ns", 104610037SARM gem5 Developers "vbar_s", 104710037SARM gem5 Developers "mvbar", 104810037SARM gem5 Developers "rmr", 104910037SARM gem5 Developers "isr", 105010037SARM gem5 Developers "hvbar", 105110037SARM gem5 Developers "fcseidr", 105210037SARM gem5 Developers "contextidr", 105310037SARM gem5 Developers "contextidr_ns", 105410037SARM gem5 Developers "contextidr_s", 105510037SARM gem5 Developers "tpidrurw", 105610037SARM gem5 Developers "tpidrurw_ns", 105710037SARM gem5 Developers "tpidrurw_s", 105810037SARM gem5 Developers "tpidruro", 105910037SARM gem5 Developers "tpidruro_ns", 106010037SARM gem5 Developers "tpidruro_s", 106110037SARM gem5 Developers "tpidrprw", 106210037SARM gem5 Developers "tpidrprw_ns", 106310037SARM gem5 Developers "tpidrprw_s", 106410037SARM gem5 Developers "htpidr", 106510037SARM gem5 Developers "cntfrq", 106610037SARM gem5 Developers "cntkctl", 106710037SARM gem5 Developers "cntp_tval", 106810037SARM gem5 Developers "cntp_tval_ns", 106910037SARM gem5 Developers "cntp_tval_s", 107010037SARM gem5 Developers "cntp_ctl", 107110037SARM gem5 Developers "cntp_ctl_ns", 107210037SARM gem5 Developers "cntp_ctl_s", 107310037SARM gem5 Developers "cntv_tval", 107410037SARM gem5 Developers "cntv_ctl", 107510037SARM gem5 Developers "cnthctl", 107610037SARM gem5 Developers "cnthp_tval", 107710037SARM gem5 Developers "cnthp_ctl", 107810037SARM gem5 Developers "il1data0", 107910037SARM gem5 Developers "il1data1", 108010037SARM gem5 Developers "il1data2", 108110037SARM gem5 Developers "il1data3", 108210037SARM gem5 Developers "dl1data0", 108310037SARM gem5 Developers "dl1data1", 108410037SARM gem5 Developers "dl1data2", 108510037SARM gem5 Developers "dl1data3", 108610037SARM gem5 Developers "dl1data4", 108710037SARM gem5 Developers "ramindex", 108810037SARM gem5 Developers "l2actlr", 108910037SARM gem5 Developers "cbar", 109010037SARM gem5 Developers "httbr", 109110037SARM gem5 Developers "vttbr", 109210037SARM gem5 Developers "cntpct", 109310037SARM gem5 Developers "cntvct", 109410037SARM gem5 Developers "cntp_cval", 109510037SARM gem5 Developers "cntp_cval_ns", 109610037SARM gem5 Developers "cntp_cval_s", 109710037SARM gem5 Developers "cntv_cval", 109810037SARM gem5 Developers "cntvoff", 109910037SARM gem5 Developers "cnthp_cval", 110010037SARM gem5 Developers "cpumerrsr", 110110037SARM gem5 Developers "l2merrsr", 110210037SARM gem5 Developers 110310037SARM gem5 Developers // AArch64 registers (Op0=2) 110410037SARM gem5 Developers "mdccint_el1", 110510037SARM gem5 Developers "osdtrrx_el1", 110610037SARM gem5 Developers "mdscr_el1", 110710037SARM gem5 Developers "osdtrtx_el1", 110810037SARM gem5 Developers "oseccr_el1", 110910037SARM gem5 Developers "dbgbvr0_el1", 111010037SARM gem5 Developers "dbgbvr1_el1", 111110037SARM gem5 Developers "dbgbvr2_el1", 111210037SARM gem5 Developers "dbgbvr3_el1", 111310037SARM gem5 Developers "dbgbvr4_el1", 111410037SARM gem5 Developers "dbgbvr5_el1", 111510037SARM gem5 Developers "dbgbcr0_el1", 111610037SARM gem5 Developers "dbgbcr1_el1", 111710037SARM gem5 Developers "dbgbcr2_el1", 111810037SARM gem5 Developers "dbgbcr3_el1", 111910037SARM gem5 Developers "dbgbcr4_el1", 112010037SARM gem5 Developers "dbgbcr5_el1", 112110037SARM gem5 Developers "dbgwvr0_el1", 112210037SARM gem5 Developers "dbgwvr1_el1", 112310037SARM gem5 Developers "dbgwvr2_el1", 112410037SARM gem5 Developers "dbgwvr3_el1", 112510037SARM gem5 Developers "dbgwcr0_el1", 112610037SARM gem5 Developers "dbgwcr1_el1", 112710037SARM gem5 Developers "dbgwcr2_el1", 112810037SARM gem5 Developers "dbgwcr3_el1", 112910037SARM gem5 Developers "mdccsr_el0", 113010037SARM gem5 Developers "mddtr_el0", 113110037SARM gem5 Developers "mddtrtx_el0", 113210037SARM gem5 Developers "mddtrrx_el0", 113310037SARM gem5 Developers "dbgvcr32_el2", 113410037SARM gem5 Developers "mdrar_el1", 113510037SARM gem5 Developers "oslar_el1", 113610037SARM gem5 Developers "oslsr_el1", 113710037SARM gem5 Developers "osdlr_el1", 113810037SARM gem5 Developers "dbgprcr_el1", 113910037SARM gem5 Developers "dbgclaimset_el1", 114010037SARM gem5 Developers "dbgclaimclr_el1", 114110037SARM gem5 Developers "dbgauthstatus_el1", 114210037SARM gem5 Developers "teecr32_el1", 114310037SARM gem5 Developers "teehbr32_el1", 114410037SARM gem5 Developers 114510037SARM gem5 Developers // AArch64 registers (Op0=1,3) 114610037SARM gem5 Developers "midr_el1", 114710037SARM gem5 Developers "mpidr_el1", 114810037SARM gem5 Developers "revidr_el1", 114910037SARM gem5 Developers "id_pfr0_el1", 115010037SARM gem5 Developers "id_pfr1_el1", 115110037SARM gem5 Developers "id_dfr0_el1", 115210037SARM gem5 Developers "id_afr0_el1", 115310037SARM gem5 Developers "id_mmfr0_el1", 115410037SARM gem5 Developers "id_mmfr1_el1", 115510037SARM gem5 Developers "id_mmfr2_el1", 115610037SARM gem5 Developers "id_mmfr3_el1", 115710037SARM gem5 Developers "id_isar0_el1", 115810037SARM gem5 Developers "id_isar1_el1", 115910037SARM gem5 Developers "id_isar2_el1", 116010037SARM gem5 Developers "id_isar3_el1", 116110037SARM gem5 Developers "id_isar4_el1", 116210037SARM gem5 Developers "id_isar5_el1", 116310037SARM gem5 Developers "mvfr0_el1", 116410037SARM gem5 Developers "mvfr1_el1", 116510037SARM gem5 Developers "mvfr2_el1", 116610037SARM gem5 Developers "id_aa64pfr0_el1", 116710037SARM gem5 Developers "id_aa64pfr1_el1", 116810037SARM gem5 Developers "id_aa64dfr0_el1", 116910037SARM gem5 Developers "id_aa64dfr1_el1", 117010037SARM gem5 Developers "id_aa64afr0_el1", 117110037SARM gem5 Developers "id_aa64afr1_el1", 117210037SARM gem5 Developers "id_aa64isar0_el1", 117310037SARM gem5 Developers "id_aa64isar1_el1", 117410037SARM gem5 Developers "id_aa64mmfr0_el1", 117510037SARM gem5 Developers "id_aa64mmfr1_el1", 117610037SARM gem5 Developers "ccsidr_el1", 117710037SARM gem5 Developers "clidr_el1", 117810037SARM gem5 Developers "aidr_el1", 117910037SARM gem5 Developers "csselr_el1", 118010037SARM gem5 Developers "ctr_el0", 118110037SARM gem5 Developers "dczid_el0", 118210037SARM gem5 Developers "vpidr_el2", 118310037SARM gem5 Developers "vmpidr_el2", 118410037SARM gem5 Developers "sctlr_el1", 118510037SARM gem5 Developers "actlr_el1", 118610037SARM gem5 Developers "cpacr_el1", 118710037SARM gem5 Developers "sctlr_el2", 118810037SARM gem5 Developers "actlr_el2", 118910037SARM gem5 Developers "hcr_el2", 119010037SARM gem5 Developers "mdcr_el2", 119110037SARM gem5 Developers "cptr_el2", 119210037SARM gem5 Developers "hstr_el2", 119310037SARM gem5 Developers "hacr_el2", 119410037SARM gem5 Developers "sctlr_el3", 119510037SARM gem5 Developers "actlr_el3", 119610037SARM gem5 Developers "scr_el3", 119710037SARM gem5 Developers "sder32_el3", 119810037SARM gem5 Developers "cptr_el3", 119910037SARM gem5 Developers "mdcr_el3", 120010037SARM gem5 Developers "ttbr0_el1", 120110037SARM gem5 Developers "ttbr1_el1", 120210037SARM gem5 Developers "tcr_el1", 120310037SARM gem5 Developers "ttbr0_el2", 120410037SARM gem5 Developers "tcr_el2", 120510037SARM gem5 Developers "vttbr_el2", 120610037SARM gem5 Developers "vtcr_el2", 120710037SARM gem5 Developers "ttbr0_el3", 120810037SARM gem5 Developers "tcr_el3", 120910037SARM gem5 Developers "dacr32_el2", 121010037SARM gem5 Developers "spsr_el1", 121110037SARM gem5 Developers "elr_el1", 121210037SARM gem5 Developers "sp_el0", 121310037SARM gem5 Developers "spsel", 121410037SARM gem5 Developers "currentel", 121510037SARM gem5 Developers "nzcv", 121610037SARM gem5 Developers "daif", 121710037SARM gem5 Developers "fpcr", 121810037SARM gem5 Developers "fpsr", 121910037SARM gem5 Developers "dspsr_el0", 122010037SARM gem5 Developers "dlr_el0", 122110037SARM gem5 Developers "spsr_el2", 122210037SARM gem5 Developers "elr_el2", 122310037SARM gem5 Developers "sp_el1", 122410037SARM gem5 Developers "spsr_irq_aa64", 122510037SARM gem5 Developers "spsr_abt_aa64", 122610037SARM gem5 Developers "spsr_und_aa64", 122710037SARM gem5 Developers "spsr_fiq_aa64", 122810037SARM gem5 Developers "spsr_el3", 122910037SARM gem5 Developers "elr_el3", 123010037SARM gem5 Developers "sp_el2", 123110037SARM gem5 Developers "afsr0_el1", 123210037SARM gem5 Developers "afsr1_el1", 123310037SARM gem5 Developers "esr_el1", 123410037SARM gem5 Developers "ifsr32_el2", 123510037SARM gem5 Developers "afsr0_el2", 123610037SARM gem5 Developers "afsr1_el2", 123710037SARM gem5 Developers "esr_el2", 123810037SARM gem5 Developers "fpexc32_el2", 123910037SARM gem5 Developers "afsr0_el3", 124010037SARM gem5 Developers "afsr1_el3", 124110037SARM gem5 Developers "esr_el3", 124210037SARM gem5 Developers "far_el1", 124310037SARM gem5 Developers "far_el2", 124410037SARM gem5 Developers "hpfar_el2", 124510037SARM gem5 Developers "far_el3", 124610037SARM gem5 Developers "ic_ialluis", 124710037SARM gem5 Developers "par_el1", 124810037SARM gem5 Developers "ic_iallu", 124910037SARM gem5 Developers "dc_ivac_xt", 125010037SARM gem5 Developers "dc_isw_xt", 125110037SARM gem5 Developers "at_s1e1r_xt", 125210037SARM gem5 Developers "at_s1e1w_xt", 125310037SARM gem5 Developers "at_s1e0r_xt", 125410037SARM gem5 Developers "at_s1e0w_xt", 125510037SARM gem5 Developers "dc_csw_xt", 125610037SARM gem5 Developers "dc_cisw_xt", 125710037SARM gem5 Developers "dc_zva_xt", 125810037SARM gem5 Developers "ic_ivau_xt", 125910037SARM gem5 Developers "dc_cvac_xt", 126010037SARM gem5 Developers "dc_cvau_xt", 126110037SARM gem5 Developers "dc_civac_xt", 126210037SARM gem5 Developers "at_s1e2r_xt", 126310037SARM gem5 Developers "at_s1e2w_xt", 126410037SARM gem5 Developers "at_s12e1r_xt", 126510037SARM gem5 Developers "at_s12e1w_xt", 126610037SARM gem5 Developers "at_s12e0r_xt", 126710037SARM gem5 Developers "at_s12e0w_xt", 126810037SARM gem5 Developers "at_s1e3r_xt", 126910037SARM gem5 Developers "at_s1e3w_xt", 127010037SARM gem5 Developers "tlbi_vmalle1is", 127110037SARM gem5 Developers "tlbi_vae1is_xt", 127210037SARM gem5 Developers "tlbi_aside1is_xt", 127310037SARM gem5 Developers "tlbi_vaae1is_xt", 127410037SARM gem5 Developers "tlbi_vale1is_xt", 127510037SARM gem5 Developers "tlbi_vaale1is_xt", 127610037SARM gem5 Developers "tlbi_vmalle1", 127710037SARM gem5 Developers "tlbi_vae1_xt", 127810037SARM gem5 Developers "tlbi_aside1_xt", 127910037SARM gem5 Developers "tlbi_vaae1_xt", 128010037SARM gem5 Developers "tlbi_vale1_xt", 128110037SARM gem5 Developers "tlbi_vaale1_xt", 128210037SARM gem5 Developers "tlbi_ipas2e1is_xt", 128310037SARM gem5 Developers "tlbi_ipas2le1is_xt", 128410037SARM gem5 Developers "tlbi_alle2is", 128510037SARM gem5 Developers "tlbi_vae2is_xt", 128610037SARM gem5 Developers "tlbi_alle1is", 128710037SARM gem5 Developers "tlbi_vale2is_xt", 128810037SARM gem5 Developers "tlbi_vmalls12e1is", 128910037SARM gem5 Developers "tlbi_ipas2e1_xt", 129010037SARM gem5 Developers "tlbi_ipas2le1_xt", 129110037SARM gem5 Developers "tlbi_alle2", 129210037SARM gem5 Developers "tlbi_vae2_xt", 129310037SARM gem5 Developers "tlbi_alle1", 129410037SARM gem5 Developers "tlbi_vale2_xt", 129510037SARM gem5 Developers "tlbi_vmalls12e1", 129610037SARM gem5 Developers "tlbi_alle3is", 129710037SARM gem5 Developers "tlbi_vae3is_xt", 129810037SARM gem5 Developers "tlbi_vale3is_xt", 129910037SARM gem5 Developers "tlbi_alle3", 130010037SARM gem5 Developers "tlbi_vae3_xt", 130110037SARM gem5 Developers "tlbi_vale3_xt", 130210037SARM gem5 Developers "pmintenset_el1", 130310037SARM gem5 Developers "pmintenclr_el1", 130410037SARM gem5 Developers "pmcr_el0", 130510037SARM gem5 Developers "pmcntenset_el0", 130610037SARM gem5 Developers "pmcntenclr_el0", 130710037SARM gem5 Developers "pmovsclr_el0", 130810037SARM gem5 Developers "pmswinc_el0", 130910037SARM gem5 Developers "pmselr_el0", 131010037SARM gem5 Developers "pmceid0_el0", 131110037SARM gem5 Developers "pmceid1_el0", 131210037SARM gem5 Developers "pmccntr_el0", 131310037SARM gem5 Developers "pmxevtyper_el0", 131410037SARM gem5 Developers "pmccfiltr_el0", 131510037SARM gem5 Developers "pmxevcntr_el0", 131610037SARM gem5 Developers "pmuserenr_el0", 131710037SARM gem5 Developers "pmovsset_el0", 131810037SARM gem5 Developers "mair_el1", 131910037SARM gem5 Developers "amair_el1", 132010037SARM gem5 Developers "mair_el2", 132110037SARM gem5 Developers "amair_el2", 132210037SARM gem5 Developers "mair_el3", 132310037SARM gem5 Developers "amair_el3", 132410037SARM gem5 Developers "l2ctlr_el1", 132510037SARM gem5 Developers "l2ectlr_el1", 132610037SARM gem5 Developers "vbar_el1", 132710037SARM gem5 Developers "rvbar_el1", 132810037SARM gem5 Developers "isr_el1", 132910037SARM gem5 Developers "vbar_el2", 133010037SARM gem5 Developers "rvbar_el2", 133110037SARM gem5 Developers "vbar_el3", 133210037SARM gem5 Developers "rvbar_el3", 133310037SARM gem5 Developers "rmr_el3", 133410037SARM gem5 Developers "contextidr_el1", 133510037SARM gem5 Developers "tpidr_el1", 133610037SARM gem5 Developers "tpidr_el0", 133710037SARM gem5 Developers "tpidrro_el0", 133810037SARM gem5 Developers "tpidr_el2", 133910037SARM gem5 Developers "tpidr_el3", 134010037SARM gem5 Developers "cntkctl_el1", 134110037SARM gem5 Developers "cntfrq_el0", 134210037SARM gem5 Developers "cntpct_el0", 134310037SARM gem5 Developers "cntvct_el0", 134410037SARM gem5 Developers "cntp_tval_el0", 134510037SARM gem5 Developers "cntp_ctl_el0", 134610037SARM gem5 Developers "cntp_cval_el0", 134710037SARM gem5 Developers "cntv_tval_el0", 134810037SARM gem5 Developers "cntv_ctl_el0", 134910037SARM gem5 Developers "cntv_cval_el0", 135010037SARM gem5 Developers "pmevcntr0_el0", 135110037SARM gem5 Developers "pmevcntr1_el0", 135210037SARM gem5 Developers "pmevcntr2_el0", 135310037SARM gem5 Developers "pmevcntr3_el0", 135410037SARM gem5 Developers "pmevcntr4_el0", 135510037SARM gem5 Developers "pmevcntr5_el0", 135610037SARM gem5 Developers "pmevtyper0_el0", 135710037SARM gem5 Developers "pmevtyper1_el0", 135810037SARM gem5 Developers "pmevtyper2_el0", 135910037SARM gem5 Developers "pmevtyper3_el0", 136010037SARM gem5 Developers "pmevtyper4_el0", 136110037SARM gem5 Developers "pmevtyper5_el0", 136210037SARM gem5 Developers "cntvoff_el2", 136310037SARM gem5 Developers "cnthctl_el2", 136410037SARM gem5 Developers "cnthp_tval_el2", 136510037SARM gem5 Developers "cnthp_ctl_el2", 136610037SARM gem5 Developers "cnthp_cval_el2", 136710037SARM gem5 Developers "cntps_tval_el1", 136810037SARM gem5 Developers "cntps_ctl_el1", 136910037SARM gem5 Developers "cntps_cval_el1", 137010037SARM gem5 Developers "il1data0_el1", 137110037SARM gem5 Developers "il1data1_el1", 137210037SARM gem5 Developers "il1data2_el1", 137310037SARM gem5 Developers "il1data3_el1", 137410037SARM gem5 Developers "dl1data0_el1", 137510037SARM gem5 Developers "dl1data1_el1", 137610037SARM gem5 Developers "dl1data2_el1", 137710037SARM gem5 Developers "dl1data3_el1", 137810037SARM gem5 Developers "dl1data4_el1", 137910037SARM gem5 Developers "l2actlr_el1", 138010037SARM gem5 Developers "cpuactlr_el1", 138110037SARM gem5 Developers "cpuectlr_el1", 138210037SARM gem5 Developers "cpumerrsr_el1", 138310037SARM gem5 Developers "l2merrsr_el1", 138410037SARM gem5 Developers "cbar_el1", 138510856SCurtis.Dunham@arm.com "contextidr_el2", 138610037SARM gem5 Developers 138712675Sgiacomo.travaglini@arm.com "ttbr1_el2", 138812816Sgiacomo.travaglini@arm.com "cnthv_ctl_el2", 138912816Sgiacomo.travaglini@arm.com "cnthv_cval_el2", 139012816Sgiacomo.travaglini@arm.com "cnthv_tval_el2", 139113116Sgiacomo.travaglini@arm.com "id_aa64mmfr2_el1", 139212529Sgiacomo.travaglini@arm.com "freeslot2", 139312529Sgiacomo.travaglini@arm.com 139412529Sgiacomo.travaglini@arm.com "num_phys_regs", 139512529Sgiacomo.travaglini@arm.com 139610037SARM gem5 Developers // Dummy registers 139710037SARM gem5 Developers "nop", 139810037SARM gem5 Developers "raz", 139910037SARM gem5 Developers "cp14_unimpl", 140010037SARM gem5 Developers "cp15_unimpl", 140112530Sgiacomo.travaglini@arm.com "unknown", 140212815Sgiacomo.travaglini@arm.com "impl_defined", 140312815Sgiacomo.travaglini@arm.com "erridr_el1", 140412815Sgiacomo.travaglini@arm.com "errselr_el1", 140512815Sgiacomo.travaglini@arm.com "erxfr_el1", 140612815Sgiacomo.travaglini@arm.com "erxctlr_el1", 140712815Sgiacomo.travaglini@arm.com "erxstatus_el1", 140812815Sgiacomo.travaglini@arm.com "erxaddr_el1", 140912815Sgiacomo.travaglini@arm.com "erxmisc0_el1", 141012815Sgiacomo.travaglini@arm.com "erxmisc1_el1", 141112815Sgiacomo.travaglini@arm.com "disr_el1", 141212815Sgiacomo.travaglini@arm.com "vsesr_el2", 141312815Sgiacomo.travaglini@arm.com "vdisr_el2", 14146242Sgblack@eecs.umich.edu }; 14156242Sgblack@eecs.umich.edu 14169256SAndreas.Sandberg@arm.com static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 14179256SAndreas.Sandberg@arm.com "The miscRegName array and NUM_MISCREGS are inconsistent."); 14189256SAndreas.Sandberg@arm.com 14196750Sgblack@eecs.umich.edu // This mask selects bits of the CPSR that actually go in the CondCodes 14206750Sgblack@eecs.umich.edu // integer register to allow renaming. 14218302SAli.Saidi@ARM.com static const uint32_t CondCodesMask = 0xF00F0000; 14228302SAli.Saidi@ARM.com static const uint32_t CpsrMaskQ = 0x08000000; 14236750Sgblack@eecs.umich.edu 142412762Sgiacomo.travaglini@arm.com // APSR (Application Program Status Register Mask). It is the user level 142512762Sgiacomo.travaglini@arm.com // alias for the CPSR. The APSR is a subset of the CPSR. Although 142612762Sgiacomo.travaglini@arm.com // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of 142712762Sgiacomo.travaglini@arm.com // APSR: 142812762Sgiacomo.travaglini@arm.com // Bit[9] returns the value of CPSR.E. 142912762Sgiacomo.travaglini@arm.com // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits. 143012762Sgiacomo.travaglini@arm.com static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0; 143112762Sgiacomo.travaglini@arm.com 143212762Sgiacomo.travaglini@arm.com // CPSR (Current Program Status Register Mask). 143312762Sgiacomo.travaglini@arm.com static const uint32_t CpsrMask = ApsrMask | 0x00F003DF; 143412762Sgiacomo.travaglini@arm.com 14357643Sgblack@eecs.umich.edu // This mask selects bits of the FPSCR that actually go in the FpCondCodes 14367643Sgblack@eecs.umich.edu // integer register to allow renaming. 14377783SGiacomo.Gabrielli@arm.com static const uint32_t FpCondCodesMask = 0xF0000000; 14387783SGiacomo.Gabrielli@arm.com // This mask selects the cumulative FP exception flags of the FPSCR. 14397783SGiacomo.Gabrielli@arm.com static const uint32_t FpscrExcMask = 0x0000009F; 14407783SGiacomo.Gabrielli@arm.com // This mask selects the cumulative saturation flag of the FPSCR. 14417783SGiacomo.Gabrielli@arm.com static const uint32_t FpscrQcMask = 0x08000000; 14427643Sgblack@eecs.umich.edu 144311939Snikos.nikoleris@arm.com /** 144411939Snikos.nikoleris@arm.com * Check for permission to read coprocessor registers. 144511939Snikos.nikoleris@arm.com * 144611939Snikos.nikoleris@arm.com * Checks whether an instruction at the current program mode has 144711939Snikos.nikoleris@arm.com * permissions to read the coprocessor registers. This function 144811939Snikos.nikoleris@arm.com * returns whether the check is undefined and if not whether the 144911939Snikos.nikoleris@arm.com * read access is permitted. 145011939Snikos.nikoleris@arm.com * 145111939Snikos.nikoleris@arm.com * @param the misc reg indicating the coprocessor 145211939Snikos.nikoleris@arm.com * @param the SCR 145311939Snikos.nikoleris@arm.com * @param the CPSR 145411939Snikos.nikoleris@arm.com * @return a tuple of booleans: can_read, undefined 145511939Snikos.nikoleris@arm.com */ 145611939Snikos.nikoleris@arm.com std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr, 145711939Snikos.nikoleris@arm.com CPSR cpsr); 145810037SARM gem5 Developers 145911939Snikos.nikoleris@arm.com /** 146011939Snikos.nikoleris@arm.com * Check for permission to write coprocessor registers. 146111939Snikos.nikoleris@arm.com * 146211939Snikos.nikoleris@arm.com * Checks whether an instruction at the current program mode has 146311939Snikos.nikoleris@arm.com * permissions to write the coprocessor registers. This function 146411939Snikos.nikoleris@arm.com * returns whether the check is undefined and if not whether the 146511939Snikos.nikoleris@arm.com * write access is permitted. 146611939Snikos.nikoleris@arm.com * 146711939Snikos.nikoleris@arm.com * @param the misc reg indicating the coprocessor 146811939Snikos.nikoleris@arm.com * @param the SCR 146911939Snikos.nikoleris@arm.com * @param the CPSR 147011939Snikos.nikoleris@arm.com * @return a tuple of booleans: can_write, undefined 147111939Snikos.nikoleris@arm.com */ 147211939Snikos.nikoleris@arm.com std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr, 147311939Snikos.nikoleris@arm.com CPSR cpsr); 147410037SARM gem5 Developers 147510037SARM gem5 Developers // Checks read access permissions to AArch64 system registers 147610037SARM gem5 Developers bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 147710037SARM gem5 Developers ThreadContext *tc); 147810037SARM gem5 Developers 147910037SARM gem5 Developers // Checks write access permissions to AArch64 system registers 148010037SARM gem5 Developers bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 148110037SARM gem5 Developers ThreadContext *tc); 148210037SARM gem5 Developers 148310037SARM gem5 Developers // Uses just the scr.ns bit to pre flatten the misc regs. This is useful 148410037SARM gem5 Developers // for MCR/MRC instructions 148510037SARM gem5 Developers int 148612499Sgiacomo.travaglini@arm.com snsBankedIndex(MiscRegIndex reg, ThreadContext *tc); 148710037SARM gem5 Developers 148810037SARM gem5 Developers // Flattens a misc reg index using the specified security state. This is 148910037SARM gem5 Developers // used for opperations (eg address translations) where the security 149010037SARM gem5 Developers // state of the register access may differ from the current state of the 149110037SARM gem5 Developers // processor 149210037SARM gem5 Developers int 149312499Sgiacomo.travaglini@arm.com snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns); 149410037SARM gem5 Developers 149510037SARM gem5 Developers // Takes a misc reg index and returns the root reg if its one of a set of 149610037SARM gem5 Developers // banked registers 149710037SARM gem5 Developers void 149810037SARM gem5 Developers preUnflattenMiscReg(); 149910037SARM gem5 Developers 150010037SARM gem5 Developers int 150110037SARM gem5 Developers unflattenMiscReg(int reg); 150210037SARM gem5 Developers 15038902Sandreas.hansson@arm.com} 15046242Sgblack@eecs.umich.edu 15056242Sgblack@eecs.umich.edu#endif // __ARCH_ARM_MISCREGS_HH__ 1506