miscregs.hh revision 12708
16242Sgblack@eecs.umich.edu/* 212529Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2018 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146242Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156242Sgblack@eecs.umich.edu * All rights reserved. 166242Sgblack@eecs.umich.edu * 176242Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186242Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196242Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216242Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236242Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246242Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256242Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266242Sgblack@eecs.umich.edu * this software without specific prior written permission. 276242Sgblack@eecs.umich.edu * 286242Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296242Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306242Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316242Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326242Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336242Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346242Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356242Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366242Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376242Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386242Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396242Sgblack@eecs.umich.edu * 406242Sgblack@eecs.umich.edu * Authors: Gabe Black 4110037SARM gem5 Developers * Giacomo Gabrielli 426242Sgblack@eecs.umich.edu */ 436242Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MISCREGS_HH__ 446242Sgblack@eecs.umich.edu#define __ARCH_ARM_MISCREGS_HH__ 456242Sgblack@eecs.umich.edu 4610037SARM gem5 Developers#include <bitset> 4711939Snikos.nikoleris@arm.com#include <tuple> 4810037SARM gem5 Developers 496242Sgblack@eecs.umich.edu#include "base/bitunion.hh" 509256SAndreas.Sandberg@arm.com#include "base/compiler.hh" 516242Sgblack@eecs.umich.edu 5210037SARM gem5 Developersclass ThreadContext; 5310037SARM gem5 Developers 5410037SARM gem5 Developers 556242Sgblack@eecs.umich.edunamespace ArmISA 566242Sgblack@eecs.umich.edu{ 576242Sgblack@eecs.umich.edu enum MiscRegIndex { 5810037SARM gem5 Developers MISCREG_CPSR = 0, // 0 5910037SARM gem5 Developers MISCREG_SPSR, // 1 6010037SARM gem5 Developers MISCREG_SPSR_FIQ, // 2 6110037SARM gem5 Developers MISCREG_SPSR_IRQ, // 3 6210037SARM gem5 Developers MISCREG_SPSR_SVC, // 4 6310037SARM gem5 Developers MISCREG_SPSR_MON, // 5 6410037SARM gem5 Developers MISCREG_SPSR_ABT, // 6 6510037SARM gem5 Developers MISCREG_SPSR_HYP, // 7 6610037SARM gem5 Developers MISCREG_SPSR_UND, // 8 6710037SARM gem5 Developers MISCREG_ELR_HYP, // 9 6810037SARM gem5 Developers MISCREG_FPSID, // 10 6910037SARM gem5 Developers MISCREG_FPSCR, // 11 7010037SARM gem5 Developers MISCREG_MVFR1, // 12 7110037SARM gem5 Developers MISCREG_MVFR0, // 13 7210037SARM gem5 Developers MISCREG_FPEXC, // 14 737259Sgblack@eecs.umich.edu 7410037SARM gem5 Developers // Helper registers 7510037SARM gem5 Developers MISCREG_CPSR_MODE, // 15 7610037SARM gem5 Developers MISCREG_CPSR_Q, // 16 7710037SARM gem5 Developers MISCREG_FPSCR_EXC, // 17 7810037SARM gem5 Developers MISCREG_FPSCR_QC, // 18 7910037SARM gem5 Developers MISCREG_LOCKADDR, // 19 8010037SARM gem5 Developers MISCREG_LOCKFLAG, // 20 8110037SARM gem5 Developers MISCREG_PRRR_MAIR0, // 21 8210037SARM gem5 Developers MISCREG_PRRR_MAIR0_NS, // 22 8310037SARM gem5 Developers MISCREG_PRRR_MAIR0_S, // 23 8410037SARM gem5 Developers MISCREG_NMRR_MAIR1, // 24 8510037SARM gem5 Developers MISCREG_NMRR_MAIR1_NS, // 25 8610037SARM gem5 Developers MISCREG_NMRR_MAIR1_S, // 26 8710037SARM gem5 Developers MISCREG_PMXEVTYPER_PMCCFILTR, // 27 8810037SARM gem5 Developers MISCREG_SCTLR_RST, // 28 8910037SARM gem5 Developers MISCREG_SEV_MAILBOX, // 29 908868SMatt.Horsnell@arm.com 9110037SARM gem5 Developers // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) 9210037SARM gem5 Developers MISCREG_DBGDIDR, // 30 9310037SARM gem5 Developers MISCREG_DBGDSCRint, // 31 9410037SARM gem5 Developers MISCREG_DBGDCCINT, // 32 9510037SARM gem5 Developers MISCREG_DBGDTRTXint, // 33 9610037SARM gem5 Developers MISCREG_DBGDTRRXint, // 34 9710037SARM gem5 Developers MISCREG_DBGWFAR, // 35 9810037SARM gem5 Developers MISCREG_DBGVCR, // 36 9910037SARM gem5 Developers MISCREG_DBGDTRRXext, // 37 10010037SARM gem5 Developers MISCREG_DBGDSCRext, // 38 10110037SARM gem5 Developers MISCREG_DBGDTRTXext, // 39 10210037SARM gem5 Developers MISCREG_DBGOSECCR, // 40 10310037SARM gem5 Developers MISCREG_DBGBVR0, // 41 10410037SARM gem5 Developers MISCREG_DBGBVR1, // 42 10510037SARM gem5 Developers MISCREG_DBGBVR2, // 43 10610037SARM gem5 Developers MISCREG_DBGBVR3, // 44 10710037SARM gem5 Developers MISCREG_DBGBVR4, // 45 10810037SARM gem5 Developers MISCREG_DBGBVR5, // 46 10910037SARM gem5 Developers MISCREG_DBGBCR0, // 47 11010037SARM gem5 Developers MISCREG_DBGBCR1, // 48 11110037SARM gem5 Developers MISCREG_DBGBCR2, // 49 11210037SARM gem5 Developers MISCREG_DBGBCR3, // 50 11310037SARM gem5 Developers MISCREG_DBGBCR4, // 51 11410037SARM gem5 Developers MISCREG_DBGBCR5, // 52 11510037SARM gem5 Developers MISCREG_DBGWVR0, // 53 11610037SARM gem5 Developers MISCREG_DBGWVR1, // 54 11710037SARM gem5 Developers MISCREG_DBGWVR2, // 55 11810037SARM gem5 Developers MISCREG_DBGWVR3, // 56 11910037SARM gem5 Developers MISCREG_DBGWCR0, // 57 12010037SARM gem5 Developers MISCREG_DBGWCR1, // 58 12110037SARM gem5 Developers MISCREG_DBGWCR2, // 59 12210037SARM gem5 Developers MISCREG_DBGWCR3, // 60 12310037SARM gem5 Developers MISCREG_DBGDRAR, // 61 12410037SARM gem5 Developers MISCREG_DBGBXVR4, // 62 12510037SARM gem5 Developers MISCREG_DBGBXVR5, // 63 12610037SARM gem5 Developers MISCREG_DBGOSLAR, // 64 12710037SARM gem5 Developers MISCREG_DBGOSLSR, // 65 12810037SARM gem5 Developers MISCREG_DBGOSDLR, // 66 12910037SARM gem5 Developers MISCREG_DBGPRCR, // 67 13010037SARM gem5 Developers MISCREG_DBGDSAR, // 68 13110037SARM gem5 Developers MISCREG_DBGCLAIMSET, // 69 13210037SARM gem5 Developers MISCREG_DBGCLAIMCLR, // 70 13310037SARM gem5 Developers MISCREG_DBGAUTHSTATUS, // 71 13410037SARM gem5 Developers MISCREG_DBGDEVID2, // 72 13510037SARM gem5 Developers MISCREG_DBGDEVID1, // 73 13610037SARM gem5 Developers MISCREG_DBGDEVID0, // 74 13711768SCurtis.Dunham@arm.com MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+ 13810037SARM gem5 Developers MISCREG_JIDR, // 76 13911768SCurtis.Dunham@arm.com MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+ 14010037SARM gem5 Developers MISCREG_JOSCR, // 78 14110037SARM gem5 Developers MISCREG_JMCR, // 79 1427351Sgblack@eecs.umich.edu 14310037SARM gem5 Developers // AArch32 CP15 registers (system control) 14410037SARM gem5 Developers MISCREG_MIDR, // 80 14510037SARM gem5 Developers MISCREG_CTR, // 81 14610037SARM gem5 Developers MISCREG_TCMTR, // 82 14710037SARM gem5 Developers MISCREG_TLBTR, // 83 14810037SARM gem5 Developers MISCREG_MPIDR, // 84 14910037SARM gem5 Developers MISCREG_REVIDR, // 85 15010037SARM gem5 Developers MISCREG_ID_PFR0, // 86 15110037SARM gem5 Developers MISCREG_ID_PFR1, // 87 15210037SARM gem5 Developers MISCREG_ID_DFR0, // 88 15310037SARM gem5 Developers MISCREG_ID_AFR0, // 89 15410037SARM gem5 Developers MISCREG_ID_MMFR0, // 90 15510037SARM gem5 Developers MISCREG_ID_MMFR1, // 91 15610037SARM gem5 Developers MISCREG_ID_MMFR2, // 92 15710037SARM gem5 Developers MISCREG_ID_MMFR3, // 93 15810037SARM gem5 Developers MISCREG_ID_ISAR0, // 94 15910037SARM gem5 Developers MISCREG_ID_ISAR1, // 95 16010037SARM gem5 Developers MISCREG_ID_ISAR2, // 96 16110037SARM gem5 Developers MISCREG_ID_ISAR3, // 97 16210037SARM gem5 Developers MISCREG_ID_ISAR4, // 98 16310037SARM gem5 Developers MISCREG_ID_ISAR5, // 99 16410037SARM gem5 Developers MISCREG_CCSIDR, // 100 16510037SARM gem5 Developers MISCREG_CLIDR, // 101 16610037SARM gem5 Developers MISCREG_AIDR, // 102 16710037SARM gem5 Developers MISCREG_CSSELR, // 103 16810037SARM gem5 Developers MISCREG_CSSELR_NS, // 104 16910037SARM gem5 Developers MISCREG_CSSELR_S, // 105 17010037SARM gem5 Developers MISCREG_VPIDR, // 106 17110037SARM gem5 Developers MISCREG_VMPIDR, // 107 17210037SARM gem5 Developers MISCREG_SCTLR, // 108 17310037SARM gem5 Developers MISCREG_SCTLR_NS, // 109 17410037SARM gem5 Developers MISCREG_SCTLR_S, // 110 17510037SARM gem5 Developers MISCREG_ACTLR, // 111 17610037SARM gem5 Developers MISCREG_ACTLR_NS, // 112 17710037SARM gem5 Developers MISCREG_ACTLR_S, // 113 17810037SARM gem5 Developers MISCREG_CPACR, // 114 17910037SARM gem5 Developers MISCREG_SCR, // 115 18010037SARM gem5 Developers MISCREG_SDER, // 116 18110037SARM gem5 Developers MISCREG_NSACR, // 117 18210037SARM gem5 Developers MISCREG_HSCTLR, // 118 18310037SARM gem5 Developers MISCREG_HACTLR, // 119 18410037SARM gem5 Developers MISCREG_HCR, // 120 18510037SARM gem5 Developers MISCREG_HDCR, // 121 18610037SARM gem5 Developers MISCREG_HCPTR, // 122 18710037SARM gem5 Developers MISCREG_HSTR, // 123 18810037SARM gem5 Developers MISCREG_HACR, // 124 18910037SARM gem5 Developers MISCREG_TTBR0, // 125 19010037SARM gem5 Developers MISCREG_TTBR0_NS, // 126 19110037SARM gem5 Developers MISCREG_TTBR0_S, // 127 19210037SARM gem5 Developers MISCREG_TTBR1, // 128 19310037SARM gem5 Developers MISCREG_TTBR1_NS, // 129 19410037SARM gem5 Developers MISCREG_TTBR1_S, // 130 19510037SARM gem5 Developers MISCREG_TTBCR, // 131 19610037SARM gem5 Developers MISCREG_TTBCR_NS, // 132 19710037SARM gem5 Developers MISCREG_TTBCR_S, // 133 19810037SARM gem5 Developers MISCREG_HTCR, // 134 19910037SARM gem5 Developers MISCREG_VTCR, // 135 20010037SARM gem5 Developers MISCREG_DACR, // 136 20110037SARM gem5 Developers MISCREG_DACR_NS, // 137 20210037SARM gem5 Developers MISCREG_DACR_S, // 138 20310037SARM gem5 Developers MISCREG_DFSR, // 139 20410037SARM gem5 Developers MISCREG_DFSR_NS, // 140 20510037SARM gem5 Developers MISCREG_DFSR_S, // 141 20610037SARM gem5 Developers MISCREG_IFSR, // 142 20710037SARM gem5 Developers MISCREG_IFSR_NS, // 143 20810037SARM gem5 Developers MISCREG_IFSR_S, // 144 20910037SARM gem5 Developers MISCREG_ADFSR, // 145 21010037SARM gem5 Developers MISCREG_ADFSR_NS, // 146 21110037SARM gem5 Developers MISCREG_ADFSR_S, // 147 21210037SARM gem5 Developers MISCREG_AIFSR, // 148 21310037SARM gem5 Developers MISCREG_AIFSR_NS, // 149 21410037SARM gem5 Developers MISCREG_AIFSR_S, // 150 21510037SARM gem5 Developers MISCREG_HADFSR, // 151 21610037SARM gem5 Developers MISCREG_HAIFSR, // 152 21710037SARM gem5 Developers MISCREG_HSR, // 153 21810037SARM gem5 Developers MISCREG_DFAR, // 154 21910037SARM gem5 Developers MISCREG_DFAR_NS, // 155 22010037SARM gem5 Developers MISCREG_DFAR_S, // 156 22110037SARM gem5 Developers MISCREG_IFAR, // 157 22210037SARM gem5 Developers MISCREG_IFAR_NS, // 158 22310037SARM gem5 Developers MISCREG_IFAR_S, // 159 22410037SARM gem5 Developers MISCREG_HDFAR, // 160 22510037SARM gem5 Developers MISCREG_HIFAR, // 161 22610037SARM gem5 Developers MISCREG_HPFAR, // 162 22710037SARM gem5 Developers MISCREG_ICIALLUIS, // 163 22810037SARM gem5 Developers MISCREG_BPIALLIS, // 164 22910037SARM gem5 Developers MISCREG_PAR, // 165 23010037SARM gem5 Developers MISCREG_PAR_NS, // 166 23110037SARM gem5 Developers MISCREG_PAR_S, // 167 23210037SARM gem5 Developers MISCREG_ICIALLU, // 168 23310037SARM gem5 Developers MISCREG_ICIMVAU, // 169 23410037SARM gem5 Developers MISCREG_CP15ISB, // 170 23510037SARM gem5 Developers MISCREG_BPIALL, // 171 23610037SARM gem5 Developers MISCREG_BPIMVA, // 172 23710037SARM gem5 Developers MISCREG_DCIMVAC, // 173 23810037SARM gem5 Developers MISCREG_DCISW, // 174 23910037SARM gem5 Developers MISCREG_ATS1CPR, // 175 24010037SARM gem5 Developers MISCREG_ATS1CPW, // 176 24110037SARM gem5 Developers MISCREG_ATS1CUR, // 177 24210037SARM gem5 Developers MISCREG_ATS1CUW, // 178 24310037SARM gem5 Developers MISCREG_ATS12NSOPR, // 179 24410037SARM gem5 Developers MISCREG_ATS12NSOPW, // 180 24510037SARM gem5 Developers MISCREG_ATS12NSOUR, // 181 24610037SARM gem5 Developers MISCREG_ATS12NSOUW, // 182 24710037SARM gem5 Developers MISCREG_DCCMVAC, // 183 24810037SARM gem5 Developers MISCREG_DCCSW, // 184 24910037SARM gem5 Developers MISCREG_CP15DSB, // 185 25010037SARM gem5 Developers MISCREG_CP15DMB, // 186 25110037SARM gem5 Developers MISCREG_DCCMVAU, // 187 25210037SARM gem5 Developers MISCREG_DCCIMVAC, // 188 25310037SARM gem5 Developers MISCREG_DCCISW, // 189 25410037SARM gem5 Developers MISCREG_ATS1HR, // 190 25510037SARM gem5 Developers MISCREG_ATS1HW, // 191 25610037SARM gem5 Developers MISCREG_TLBIALLIS, // 192 25710037SARM gem5 Developers MISCREG_TLBIMVAIS, // 193 25810037SARM gem5 Developers MISCREG_TLBIASIDIS, // 194 25910037SARM gem5 Developers MISCREG_TLBIMVAAIS, // 195 26010037SARM gem5 Developers MISCREG_TLBIMVALIS, // 196 26110037SARM gem5 Developers MISCREG_TLBIMVAALIS, // 197 26210037SARM gem5 Developers MISCREG_ITLBIALL, // 198 26310037SARM gem5 Developers MISCREG_ITLBIMVA, // 199 26410037SARM gem5 Developers MISCREG_ITLBIASID, // 200 26510037SARM gem5 Developers MISCREG_DTLBIALL, // 201 26610037SARM gem5 Developers MISCREG_DTLBIMVA, // 202 26710037SARM gem5 Developers MISCREG_DTLBIASID, // 203 26810037SARM gem5 Developers MISCREG_TLBIALL, // 204 26910037SARM gem5 Developers MISCREG_TLBIMVA, // 205 27010037SARM gem5 Developers MISCREG_TLBIASID, // 206 27110037SARM gem5 Developers MISCREG_TLBIMVAA, // 207 27210037SARM gem5 Developers MISCREG_TLBIMVAL, // 208 27310037SARM gem5 Developers MISCREG_TLBIMVAAL, // 209 27410037SARM gem5 Developers MISCREG_TLBIIPAS2IS, // 210 27510037SARM gem5 Developers MISCREG_TLBIIPAS2LIS, // 211 27610037SARM gem5 Developers MISCREG_TLBIALLHIS, // 212 27710037SARM gem5 Developers MISCREG_TLBIMVAHIS, // 213 27810037SARM gem5 Developers MISCREG_TLBIALLNSNHIS, // 214 27910037SARM gem5 Developers MISCREG_TLBIMVALHIS, // 215 28010037SARM gem5 Developers MISCREG_TLBIIPAS2, // 216 28110037SARM gem5 Developers MISCREG_TLBIIPAS2L, // 217 28210037SARM gem5 Developers MISCREG_TLBIALLH, // 218 28310037SARM gem5 Developers MISCREG_TLBIMVAH, // 219 28410037SARM gem5 Developers MISCREG_TLBIALLNSNH, // 220 28510037SARM gem5 Developers MISCREG_TLBIMVALH, // 221 28610037SARM gem5 Developers MISCREG_PMCR, // 222 28710037SARM gem5 Developers MISCREG_PMCNTENSET, // 223 28810037SARM gem5 Developers MISCREG_PMCNTENCLR, // 224 28910037SARM gem5 Developers MISCREG_PMOVSR, // 225 29010037SARM gem5 Developers MISCREG_PMSWINC, // 226 29110037SARM gem5 Developers MISCREG_PMSELR, // 227 29210037SARM gem5 Developers MISCREG_PMCEID0, // 228 29310037SARM gem5 Developers MISCREG_PMCEID1, // 229 29410037SARM gem5 Developers MISCREG_PMCCNTR, // 230 29510037SARM gem5 Developers MISCREG_PMXEVTYPER, // 231 29610037SARM gem5 Developers MISCREG_PMCCFILTR, // 232 29710037SARM gem5 Developers MISCREG_PMXEVCNTR, // 233 29810037SARM gem5 Developers MISCREG_PMUSERENR, // 234 29910037SARM gem5 Developers MISCREG_PMINTENSET, // 235 30010037SARM gem5 Developers MISCREG_PMINTENCLR, // 236 30110037SARM gem5 Developers MISCREG_PMOVSSET, // 237 30210037SARM gem5 Developers MISCREG_L2CTLR, // 238 30310037SARM gem5 Developers MISCREG_L2ECTLR, // 239 30410037SARM gem5 Developers MISCREG_PRRR, // 240 30510037SARM gem5 Developers MISCREG_PRRR_NS, // 241 30610037SARM gem5 Developers MISCREG_PRRR_S, // 242 30710037SARM gem5 Developers MISCREG_MAIR0, // 243 30810037SARM gem5 Developers MISCREG_MAIR0_NS, // 244 30910037SARM gem5 Developers MISCREG_MAIR0_S, // 245 31010037SARM gem5 Developers MISCREG_NMRR, // 246 31110037SARM gem5 Developers MISCREG_NMRR_NS, // 247 31210037SARM gem5 Developers MISCREG_NMRR_S, // 248 31310037SARM gem5 Developers MISCREG_MAIR1, // 249 31410037SARM gem5 Developers MISCREG_MAIR1_NS, // 250 31510037SARM gem5 Developers MISCREG_MAIR1_S, // 251 31610037SARM gem5 Developers MISCREG_AMAIR0, // 252 31710037SARM gem5 Developers MISCREG_AMAIR0_NS, // 253 31810037SARM gem5 Developers MISCREG_AMAIR0_S, // 254 31910037SARM gem5 Developers MISCREG_AMAIR1, // 255 32010037SARM gem5 Developers MISCREG_AMAIR1_NS, // 256 32110037SARM gem5 Developers MISCREG_AMAIR1_S, // 257 32210037SARM gem5 Developers MISCREG_HMAIR0, // 258 32310037SARM gem5 Developers MISCREG_HMAIR1, // 259 32410037SARM gem5 Developers MISCREG_HAMAIR0, // 260 32510037SARM gem5 Developers MISCREG_HAMAIR1, // 261 32610037SARM gem5 Developers MISCREG_VBAR, // 262 32710037SARM gem5 Developers MISCREG_VBAR_NS, // 263 32810037SARM gem5 Developers MISCREG_VBAR_S, // 264 32910037SARM gem5 Developers MISCREG_MVBAR, // 265 33010037SARM gem5 Developers MISCREG_RMR, // 266 33110037SARM gem5 Developers MISCREG_ISR, // 267 33210037SARM gem5 Developers MISCREG_HVBAR, // 268 33310037SARM gem5 Developers MISCREG_FCSEIDR, // 269 33410037SARM gem5 Developers MISCREG_CONTEXTIDR, // 270 33510037SARM gem5 Developers MISCREG_CONTEXTIDR_NS, // 271 33610037SARM gem5 Developers MISCREG_CONTEXTIDR_S, // 272 33710037SARM gem5 Developers MISCREG_TPIDRURW, // 273 33810037SARM gem5 Developers MISCREG_TPIDRURW_NS, // 274 33910037SARM gem5 Developers MISCREG_TPIDRURW_S, // 275 34010037SARM gem5 Developers MISCREG_TPIDRURO, // 276 34110037SARM gem5 Developers MISCREG_TPIDRURO_NS, // 277 34210037SARM gem5 Developers MISCREG_TPIDRURO_S, // 278 34310037SARM gem5 Developers MISCREG_TPIDRPRW, // 279 34410037SARM gem5 Developers MISCREG_TPIDRPRW_NS, // 280 34510037SARM gem5 Developers MISCREG_TPIDRPRW_S, // 281 34610037SARM gem5 Developers MISCREG_HTPIDR, // 282 34710037SARM gem5 Developers MISCREG_CNTFRQ, // 283 34810037SARM gem5 Developers MISCREG_CNTKCTL, // 284 34910037SARM gem5 Developers MISCREG_CNTP_TVAL, // 285 35010037SARM gem5 Developers MISCREG_CNTP_TVAL_NS, // 286 35110037SARM gem5 Developers MISCREG_CNTP_TVAL_S, // 287 35210037SARM gem5 Developers MISCREG_CNTP_CTL, // 288 35310037SARM gem5 Developers MISCREG_CNTP_CTL_NS, // 289 35410037SARM gem5 Developers MISCREG_CNTP_CTL_S, // 290 35510037SARM gem5 Developers MISCREG_CNTV_TVAL, // 291 35610037SARM gem5 Developers MISCREG_CNTV_CTL, // 292 35710037SARM gem5 Developers MISCREG_CNTHCTL, // 293 35810037SARM gem5 Developers MISCREG_CNTHP_TVAL, // 294 35910037SARM gem5 Developers MISCREG_CNTHP_CTL, // 295 36010037SARM gem5 Developers MISCREG_IL1DATA0, // 296 36110037SARM gem5 Developers MISCREG_IL1DATA1, // 297 36210037SARM gem5 Developers MISCREG_IL1DATA2, // 298 36310037SARM gem5 Developers MISCREG_IL1DATA3, // 299 36410037SARM gem5 Developers MISCREG_DL1DATA0, // 300 36510037SARM gem5 Developers MISCREG_DL1DATA1, // 301 36610037SARM gem5 Developers MISCREG_DL1DATA2, // 302 36710037SARM gem5 Developers MISCREG_DL1DATA3, // 303 36810037SARM gem5 Developers MISCREG_DL1DATA4, // 304 36910037SARM gem5 Developers MISCREG_RAMINDEX, // 305 37010037SARM gem5 Developers MISCREG_L2ACTLR, // 306 37110037SARM gem5 Developers MISCREG_CBAR, // 307 37210037SARM gem5 Developers MISCREG_HTTBR, // 308 37310037SARM gem5 Developers MISCREG_VTTBR, // 309 37410037SARM gem5 Developers MISCREG_CNTPCT, // 310 37510037SARM gem5 Developers MISCREG_CNTVCT, // 311 37610037SARM gem5 Developers MISCREG_CNTP_CVAL, // 312 37710037SARM gem5 Developers MISCREG_CNTP_CVAL_NS, // 313 37810037SARM gem5 Developers MISCREG_CNTP_CVAL_S, // 314 37910037SARM gem5 Developers MISCREG_CNTV_CVAL, // 315 38010037SARM gem5 Developers MISCREG_CNTVOFF, // 316 38110037SARM gem5 Developers MISCREG_CNTHP_CVAL, // 317 38210037SARM gem5 Developers MISCREG_CPUMERRSR, // 318 38310037SARM gem5 Developers MISCREG_L2MERRSR, // 319 3847259Sgblack@eecs.umich.edu 38510037SARM gem5 Developers // AArch64 registers (Op0=2) 38610037SARM gem5 Developers MISCREG_MDCCINT_EL1, // 320 38710037SARM gem5 Developers MISCREG_OSDTRRX_EL1, // 321 38810037SARM gem5 Developers MISCREG_MDSCR_EL1, // 322 38910037SARM gem5 Developers MISCREG_OSDTRTX_EL1, // 323 39010037SARM gem5 Developers MISCREG_OSECCR_EL1, // 324 39110037SARM gem5 Developers MISCREG_DBGBVR0_EL1, // 325 39210037SARM gem5 Developers MISCREG_DBGBVR1_EL1, // 326 39310037SARM gem5 Developers MISCREG_DBGBVR2_EL1, // 327 39410037SARM gem5 Developers MISCREG_DBGBVR3_EL1, // 328 39510037SARM gem5 Developers MISCREG_DBGBVR4_EL1, // 329 39610037SARM gem5 Developers MISCREG_DBGBVR5_EL1, // 330 39710037SARM gem5 Developers MISCREG_DBGBCR0_EL1, // 331 39810037SARM gem5 Developers MISCREG_DBGBCR1_EL1, // 332 39910037SARM gem5 Developers MISCREG_DBGBCR2_EL1, // 333 40010037SARM gem5 Developers MISCREG_DBGBCR3_EL1, // 334 40110037SARM gem5 Developers MISCREG_DBGBCR4_EL1, // 335 40210037SARM gem5 Developers MISCREG_DBGBCR5_EL1, // 336 40310037SARM gem5 Developers MISCREG_DBGWVR0_EL1, // 337 40410037SARM gem5 Developers MISCREG_DBGWVR1_EL1, // 338 40510037SARM gem5 Developers MISCREG_DBGWVR2_EL1, // 339 40610037SARM gem5 Developers MISCREG_DBGWVR3_EL1, // 340 40710037SARM gem5 Developers MISCREG_DBGWCR0_EL1, // 341 40810037SARM gem5 Developers MISCREG_DBGWCR1_EL1, // 342 40910037SARM gem5 Developers MISCREG_DBGWCR2_EL1, // 343 41010037SARM gem5 Developers MISCREG_DBGWCR3_EL1, // 344 41110037SARM gem5 Developers MISCREG_MDCCSR_EL0, // 345 41210037SARM gem5 Developers MISCREG_MDDTR_EL0, // 346 41310037SARM gem5 Developers MISCREG_MDDTRTX_EL0, // 347 41410037SARM gem5 Developers MISCREG_MDDTRRX_EL0, // 348 41510037SARM gem5 Developers MISCREG_DBGVCR32_EL2, // 349 41610037SARM gem5 Developers MISCREG_MDRAR_EL1, // 350 41710037SARM gem5 Developers MISCREG_OSLAR_EL1, // 351 41810037SARM gem5 Developers MISCREG_OSLSR_EL1, // 352 41910037SARM gem5 Developers MISCREG_OSDLR_EL1, // 353 42010037SARM gem5 Developers MISCREG_DBGPRCR_EL1, // 354 42110037SARM gem5 Developers MISCREG_DBGCLAIMSET_EL1, // 355 42210037SARM gem5 Developers MISCREG_DBGCLAIMCLR_EL1, // 356 42310037SARM gem5 Developers MISCREG_DBGAUTHSTATUS_EL1, // 357 42411768SCurtis.Dunham@arm.com MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+ 42511768SCurtis.Dunham@arm.com MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+ 4267259Sgblack@eecs.umich.edu 42710037SARM gem5 Developers // AArch64 registers (Op0=1,3) 42810037SARM gem5 Developers MISCREG_MIDR_EL1, // 360 42910037SARM gem5 Developers MISCREG_MPIDR_EL1, // 361 43010037SARM gem5 Developers MISCREG_REVIDR_EL1, // 362 43110037SARM gem5 Developers MISCREG_ID_PFR0_EL1, // 363 43210037SARM gem5 Developers MISCREG_ID_PFR1_EL1, // 364 43310037SARM gem5 Developers MISCREG_ID_DFR0_EL1, // 365 43410037SARM gem5 Developers MISCREG_ID_AFR0_EL1, // 366 43510037SARM gem5 Developers MISCREG_ID_MMFR0_EL1, // 367 43610037SARM gem5 Developers MISCREG_ID_MMFR1_EL1, // 368 43710037SARM gem5 Developers MISCREG_ID_MMFR2_EL1, // 369 43810037SARM gem5 Developers MISCREG_ID_MMFR3_EL1, // 370 43910037SARM gem5 Developers MISCREG_ID_ISAR0_EL1, // 371 44010037SARM gem5 Developers MISCREG_ID_ISAR1_EL1, // 372 44110037SARM gem5 Developers MISCREG_ID_ISAR2_EL1, // 373 44210037SARM gem5 Developers MISCREG_ID_ISAR3_EL1, // 374 44310037SARM gem5 Developers MISCREG_ID_ISAR4_EL1, // 375 44410037SARM gem5 Developers MISCREG_ID_ISAR5_EL1, // 376 44510037SARM gem5 Developers MISCREG_MVFR0_EL1, // 377 44610037SARM gem5 Developers MISCREG_MVFR1_EL1, // 378 44710037SARM gem5 Developers MISCREG_MVFR2_EL1, // 379 44810037SARM gem5 Developers MISCREG_ID_AA64PFR0_EL1, // 380 44910037SARM gem5 Developers MISCREG_ID_AA64PFR1_EL1, // 381 45010037SARM gem5 Developers MISCREG_ID_AA64DFR0_EL1, // 382 45110037SARM gem5 Developers MISCREG_ID_AA64DFR1_EL1, // 383 45210037SARM gem5 Developers MISCREG_ID_AA64AFR0_EL1, // 384 45310037SARM gem5 Developers MISCREG_ID_AA64AFR1_EL1, // 385 45410037SARM gem5 Developers MISCREG_ID_AA64ISAR0_EL1, // 386 45510037SARM gem5 Developers MISCREG_ID_AA64ISAR1_EL1, // 387 45610037SARM gem5 Developers MISCREG_ID_AA64MMFR0_EL1, // 388 45710037SARM gem5 Developers MISCREG_ID_AA64MMFR1_EL1, // 389 45810037SARM gem5 Developers MISCREG_CCSIDR_EL1, // 390 45910037SARM gem5 Developers MISCREG_CLIDR_EL1, // 391 46010037SARM gem5 Developers MISCREG_AIDR_EL1, // 392 46110037SARM gem5 Developers MISCREG_CSSELR_EL1, // 393 46210037SARM gem5 Developers MISCREG_CTR_EL0, // 394 46310037SARM gem5 Developers MISCREG_DCZID_EL0, // 395 46410037SARM gem5 Developers MISCREG_VPIDR_EL2, // 396 46510037SARM gem5 Developers MISCREG_VMPIDR_EL2, // 397 46610037SARM gem5 Developers MISCREG_SCTLR_EL1, // 398 46710037SARM gem5 Developers MISCREG_ACTLR_EL1, // 399 46810037SARM gem5 Developers MISCREG_CPACR_EL1, // 400 46910037SARM gem5 Developers MISCREG_SCTLR_EL2, // 401 47010037SARM gem5 Developers MISCREG_ACTLR_EL2, // 402 47110037SARM gem5 Developers MISCREG_HCR_EL2, // 403 47210037SARM gem5 Developers MISCREG_MDCR_EL2, // 404 47310037SARM gem5 Developers MISCREG_CPTR_EL2, // 405 47410037SARM gem5 Developers MISCREG_HSTR_EL2, // 406 47510037SARM gem5 Developers MISCREG_HACR_EL2, // 407 47610037SARM gem5 Developers MISCREG_SCTLR_EL3, // 408 47710037SARM gem5 Developers MISCREG_ACTLR_EL3, // 409 47810037SARM gem5 Developers MISCREG_SCR_EL3, // 410 47910037SARM gem5 Developers MISCREG_SDER32_EL3, // 411 48010037SARM gem5 Developers MISCREG_CPTR_EL3, // 412 48110037SARM gem5 Developers MISCREG_MDCR_EL3, // 413 48210037SARM gem5 Developers MISCREG_TTBR0_EL1, // 414 48310037SARM gem5 Developers MISCREG_TTBR1_EL1, // 415 48410037SARM gem5 Developers MISCREG_TCR_EL1, // 416 48510037SARM gem5 Developers MISCREG_TTBR0_EL2, // 417 48610037SARM gem5 Developers MISCREG_TCR_EL2, // 418 48710037SARM gem5 Developers MISCREG_VTTBR_EL2, // 419 48810037SARM gem5 Developers MISCREG_VTCR_EL2, // 420 48910037SARM gem5 Developers MISCREG_TTBR0_EL3, // 421 49010037SARM gem5 Developers MISCREG_TCR_EL3, // 422 49110037SARM gem5 Developers MISCREG_DACR32_EL2, // 423 49210037SARM gem5 Developers MISCREG_SPSR_EL1, // 424 49310037SARM gem5 Developers MISCREG_ELR_EL1, // 425 49410037SARM gem5 Developers MISCREG_SP_EL0, // 426 49510037SARM gem5 Developers MISCREG_SPSEL, // 427 49610037SARM gem5 Developers MISCREG_CURRENTEL, // 428 49710037SARM gem5 Developers MISCREG_NZCV, // 429 49810037SARM gem5 Developers MISCREG_DAIF, // 430 49910037SARM gem5 Developers MISCREG_FPCR, // 431 50010037SARM gem5 Developers MISCREG_FPSR, // 432 50110037SARM gem5 Developers MISCREG_DSPSR_EL0, // 433 50210037SARM gem5 Developers MISCREG_DLR_EL0, // 434 50310037SARM gem5 Developers MISCREG_SPSR_EL2, // 435 50410037SARM gem5 Developers MISCREG_ELR_EL2, // 436 50510037SARM gem5 Developers MISCREG_SP_EL1, // 437 50610037SARM gem5 Developers MISCREG_SPSR_IRQ_AA64, // 438 50710037SARM gem5 Developers MISCREG_SPSR_ABT_AA64, // 439 50810037SARM gem5 Developers MISCREG_SPSR_UND_AA64, // 440 50910037SARM gem5 Developers MISCREG_SPSR_FIQ_AA64, // 441 51010037SARM gem5 Developers MISCREG_SPSR_EL3, // 442 51110037SARM gem5 Developers MISCREG_ELR_EL3, // 443 51210037SARM gem5 Developers MISCREG_SP_EL2, // 444 51310037SARM gem5 Developers MISCREG_AFSR0_EL1, // 445 51410037SARM gem5 Developers MISCREG_AFSR1_EL1, // 446 51510037SARM gem5 Developers MISCREG_ESR_EL1, // 447 51610037SARM gem5 Developers MISCREG_IFSR32_EL2, // 448 51710037SARM gem5 Developers MISCREG_AFSR0_EL2, // 449 51810037SARM gem5 Developers MISCREG_AFSR1_EL2, // 450 51910037SARM gem5 Developers MISCREG_ESR_EL2, // 451 52010037SARM gem5 Developers MISCREG_FPEXC32_EL2, // 452 52110037SARM gem5 Developers MISCREG_AFSR0_EL3, // 453 52210037SARM gem5 Developers MISCREG_AFSR1_EL3, // 454 52310037SARM gem5 Developers MISCREG_ESR_EL3, // 455 52410037SARM gem5 Developers MISCREG_FAR_EL1, // 456 52510037SARM gem5 Developers MISCREG_FAR_EL2, // 457 52610037SARM gem5 Developers MISCREG_HPFAR_EL2, // 458 52710037SARM gem5 Developers MISCREG_FAR_EL3, // 459 52810037SARM gem5 Developers MISCREG_IC_IALLUIS, // 460 52910037SARM gem5 Developers MISCREG_PAR_EL1, // 461 53010037SARM gem5 Developers MISCREG_IC_IALLU, // 462 53110037SARM gem5 Developers MISCREG_DC_IVAC_Xt, // 463 53210037SARM gem5 Developers MISCREG_DC_ISW_Xt, // 464 53310037SARM gem5 Developers MISCREG_AT_S1E1R_Xt, // 465 53410037SARM gem5 Developers MISCREG_AT_S1E1W_Xt, // 466 53510037SARM gem5 Developers MISCREG_AT_S1E0R_Xt, // 467 53610037SARM gem5 Developers MISCREG_AT_S1E0W_Xt, // 468 53710037SARM gem5 Developers MISCREG_DC_CSW_Xt, // 469 53810037SARM gem5 Developers MISCREG_DC_CISW_Xt, // 470 53910037SARM gem5 Developers MISCREG_DC_ZVA_Xt, // 471 54010037SARM gem5 Developers MISCREG_IC_IVAU_Xt, // 472 54110037SARM gem5 Developers MISCREG_DC_CVAC_Xt, // 473 54210037SARM gem5 Developers MISCREG_DC_CVAU_Xt, // 474 54310037SARM gem5 Developers MISCREG_DC_CIVAC_Xt, // 475 54410037SARM gem5 Developers MISCREG_AT_S1E2R_Xt, // 476 54510037SARM gem5 Developers MISCREG_AT_S1E2W_Xt, // 477 54610037SARM gem5 Developers MISCREG_AT_S12E1R_Xt, // 478 54710037SARM gem5 Developers MISCREG_AT_S12E1W_Xt, // 479 54810037SARM gem5 Developers MISCREG_AT_S12E0R_Xt, // 480 54910037SARM gem5 Developers MISCREG_AT_S12E0W_Xt, // 481 55010037SARM gem5 Developers MISCREG_AT_S1E3R_Xt, // 482 55110037SARM gem5 Developers MISCREG_AT_S1E3W_Xt, // 483 55210037SARM gem5 Developers MISCREG_TLBI_VMALLE1IS, // 484 55310037SARM gem5 Developers MISCREG_TLBI_VAE1IS_Xt, // 485 55410037SARM gem5 Developers MISCREG_TLBI_ASIDE1IS_Xt, // 486 55510037SARM gem5 Developers MISCREG_TLBI_VAAE1IS_Xt, // 487 55610037SARM gem5 Developers MISCREG_TLBI_VALE1IS_Xt, // 488 55710037SARM gem5 Developers MISCREG_TLBI_VAALE1IS_Xt, // 489 55810037SARM gem5 Developers MISCREG_TLBI_VMALLE1, // 490 55910037SARM gem5 Developers MISCREG_TLBI_VAE1_Xt, // 491 56010037SARM gem5 Developers MISCREG_TLBI_ASIDE1_Xt, // 492 56110037SARM gem5 Developers MISCREG_TLBI_VAAE1_Xt, // 493 56210037SARM gem5 Developers MISCREG_TLBI_VALE1_Xt, // 494 56310037SARM gem5 Developers MISCREG_TLBI_VAALE1_Xt, // 495 56410037SARM gem5 Developers MISCREG_TLBI_IPAS2E1IS_Xt, // 496 56510037SARM gem5 Developers MISCREG_TLBI_IPAS2LE1IS_Xt, // 497 56610037SARM gem5 Developers MISCREG_TLBI_ALLE2IS, // 498 56710037SARM gem5 Developers MISCREG_TLBI_VAE2IS_Xt, // 499 56810037SARM gem5 Developers MISCREG_TLBI_ALLE1IS, // 500 56910037SARM gem5 Developers MISCREG_TLBI_VALE2IS_Xt, // 501 57010037SARM gem5 Developers MISCREG_TLBI_VMALLS12E1IS, // 502 57110037SARM gem5 Developers MISCREG_TLBI_IPAS2E1_Xt, // 503 57210037SARM gem5 Developers MISCREG_TLBI_IPAS2LE1_Xt, // 504 57310037SARM gem5 Developers MISCREG_TLBI_ALLE2, // 505 57410037SARM gem5 Developers MISCREG_TLBI_VAE2_Xt, // 506 57510037SARM gem5 Developers MISCREG_TLBI_ALLE1, // 507 57610037SARM gem5 Developers MISCREG_TLBI_VALE2_Xt, // 508 57710037SARM gem5 Developers MISCREG_TLBI_VMALLS12E1, // 509 57810037SARM gem5 Developers MISCREG_TLBI_ALLE3IS, // 510 57910037SARM gem5 Developers MISCREG_TLBI_VAE3IS_Xt, // 511 58010037SARM gem5 Developers MISCREG_TLBI_VALE3IS_Xt, // 512 58110037SARM gem5 Developers MISCREG_TLBI_ALLE3, // 513 58210037SARM gem5 Developers MISCREG_TLBI_VAE3_Xt, // 514 58310037SARM gem5 Developers MISCREG_TLBI_VALE3_Xt, // 515 58410037SARM gem5 Developers MISCREG_PMINTENSET_EL1, // 516 58510037SARM gem5 Developers MISCREG_PMINTENCLR_EL1, // 517 58610037SARM gem5 Developers MISCREG_PMCR_EL0, // 518 58710037SARM gem5 Developers MISCREG_PMCNTENSET_EL0, // 519 58810037SARM gem5 Developers MISCREG_PMCNTENCLR_EL0, // 520 58910037SARM gem5 Developers MISCREG_PMOVSCLR_EL0, // 521 59010037SARM gem5 Developers MISCREG_PMSWINC_EL0, // 522 59110037SARM gem5 Developers MISCREG_PMSELR_EL0, // 523 59210037SARM gem5 Developers MISCREG_PMCEID0_EL0, // 524 59310037SARM gem5 Developers MISCREG_PMCEID1_EL0, // 525 59410037SARM gem5 Developers MISCREG_PMCCNTR_EL0, // 526 59510037SARM gem5 Developers MISCREG_PMXEVTYPER_EL0, // 527 59610037SARM gem5 Developers MISCREG_PMCCFILTR_EL0, // 528 59710037SARM gem5 Developers MISCREG_PMXEVCNTR_EL0, // 529 59810037SARM gem5 Developers MISCREG_PMUSERENR_EL0, // 530 59910037SARM gem5 Developers MISCREG_PMOVSSET_EL0, // 531 60010037SARM gem5 Developers MISCREG_MAIR_EL1, // 532 60110037SARM gem5 Developers MISCREG_AMAIR_EL1, // 533 60210037SARM gem5 Developers MISCREG_MAIR_EL2, // 534 60310037SARM gem5 Developers MISCREG_AMAIR_EL2, // 535 60410037SARM gem5 Developers MISCREG_MAIR_EL3, // 536 60510037SARM gem5 Developers MISCREG_AMAIR_EL3, // 537 60610037SARM gem5 Developers MISCREG_L2CTLR_EL1, // 538 60710037SARM gem5 Developers MISCREG_L2ECTLR_EL1, // 539 60810037SARM gem5 Developers MISCREG_VBAR_EL1, // 540 60910037SARM gem5 Developers MISCREG_RVBAR_EL1, // 541 61010037SARM gem5 Developers MISCREG_ISR_EL1, // 542 61110037SARM gem5 Developers MISCREG_VBAR_EL2, // 543 61210037SARM gem5 Developers MISCREG_RVBAR_EL2, // 544 61310037SARM gem5 Developers MISCREG_VBAR_EL3, // 545 61410037SARM gem5 Developers MISCREG_RVBAR_EL3, // 546 61510037SARM gem5 Developers MISCREG_RMR_EL3, // 547 61610037SARM gem5 Developers MISCREG_CONTEXTIDR_EL1, // 548 61710037SARM gem5 Developers MISCREG_TPIDR_EL1, // 549 61810037SARM gem5 Developers MISCREG_TPIDR_EL0, // 550 61910037SARM gem5 Developers MISCREG_TPIDRRO_EL0, // 551 62010037SARM gem5 Developers MISCREG_TPIDR_EL2, // 552 62110037SARM gem5 Developers MISCREG_TPIDR_EL3, // 553 62210037SARM gem5 Developers MISCREG_CNTKCTL_EL1, // 554 62310037SARM gem5 Developers MISCREG_CNTFRQ_EL0, // 555 62410037SARM gem5 Developers MISCREG_CNTPCT_EL0, // 556 62510037SARM gem5 Developers MISCREG_CNTVCT_EL0, // 557 62610037SARM gem5 Developers MISCREG_CNTP_TVAL_EL0, // 558 62710037SARM gem5 Developers MISCREG_CNTP_CTL_EL0, // 559 62810037SARM gem5 Developers MISCREG_CNTP_CVAL_EL0, // 560 62910037SARM gem5 Developers MISCREG_CNTV_TVAL_EL0, // 561 63010037SARM gem5 Developers MISCREG_CNTV_CTL_EL0, // 562 63110037SARM gem5 Developers MISCREG_CNTV_CVAL_EL0, // 563 63210037SARM gem5 Developers MISCREG_PMEVCNTR0_EL0, // 564 63310037SARM gem5 Developers MISCREG_PMEVCNTR1_EL0, // 565 63410037SARM gem5 Developers MISCREG_PMEVCNTR2_EL0, // 566 63510037SARM gem5 Developers MISCREG_PMEVCNTR3_EL0, // 567 63610037SARM gem5 Developers MISCREG_PMEVCNTR4_EL0, // 568 63710037SARM gem5 Developers MISCREG_PMEVCNTR5_EL0, // 569 63810037SARM gem5 Developers MISCREG_PMEVTYPER0_EL0, // 570 63910037SARM gem5 Developers MISCREG_PMEVTYPER1_EL0, // 571 64010037SARM gem5 Developers MISCREG_PMEVTYPER2_EL0, // 572 64110037SARM gem5 Developers MISCREG_PMEVTYPER3_EL0, // 573 64210037SARM gem5 Developers MISCREG_PMEVTYPER4_EL0, // 574 64310037SARM gem5 Developers MISCREG_PMEVTYPER5_EL0, // 575 64410037SARM gem5 Developers MISCREG_CNTVOFF_EL2, // 576 64510037SARM gem5 Developers MISCREG_CNTHCTL_EL2, // 577 64610037SARM gem5 Developers MISCREG_CNTHP_TVAL_EL2, // 578 64710037SARM gem5 Developers MISCREG_CNTHP_CTL_EL2, // 579 64810037SARM gem5 Developers MISCREG_CNTHP_CVAL_EL2, // 580 64910037SARM gem5 Developers MISCREG_CNTPS_TVAL_EL1, // 581 65010037SARM gem5 Developers MISCREG_CNTPS_CTL_EL1, // 582 65110037SARM gem5 Developers MISCREG_CNTPS_CVAL_EL1, // 583 65210037SARM gem5 Developers MISCREG_IL1DATA0_EL1, // 584 65310037SARM gem5 Developers MISCREG_IL1DATA1_EL1, // 585 65410037SARM gem5 Developers MISCREG_IL1DATA2_EL1, // 586 65510037SARM gem5 Developers MISCREG_IL1DATA3_EL1, // 587 65610037SARM gem5 Developers MISCREG_DL1DATA0_EL1, // 588 65710037SARM gem5 Developers MISCREG_DL1DATA1_EL1, // 589 65810037SARM gem5 Developers MISCREG_DL1DATA2_EL1, // 590 65910037SARM gem5 Developers MISCREG_DL1DATA3_EL1, // 591 66010037SARM gem5 Developers MISCREG_DL1DATA4_EL1, // 592 66110037SARM gem5 Developers MISCREG_L2ACTLR_EL1, // 593 66210037SARM gem5 Developers MISCREG_CPUACTLR_EL1, // 594 66310037SARM gem5 Developers MISCREG_CPUECTLR_EL1, // 595 66410037SARM gem5 Developers MISCREG_CPUMERRSR_EL1, // 596 66510037SARM gem5 Developers MISCREG_L2MERRSR_EL1, // 597 66610037SARM gem5 Developers MISCREG_CBAR_EL1, // 598 66710856SCurtis.Dunham@arm.com MISCREG_CONTEXTIDR_EL2, // 599 6687259Sgblack@eecs.umich.edu 66912675Sgiacomo.travaglini@arm.com // Introduced in ARMv8.1 67012675Sgiacomo.travaglini@arm.com MISCREG_TTBR1_EL2, // 600 67112675Sgiacomo.travaglini@arm.com 67212529Sgiacomo.travaglini@arm.com // These MISCREG_FREESLOT are available Misc Register 67312529Sgiacomo.travaglini@arm.com // slots for future registers to be implemented. 67412675Sgiacomo.travaglini@arm.com MISCREG_FREESLOT_1, // 601 67512675Sgiacomo.travaglini@arm.com MISCREG_FREESLOT_2, // 602 67612675Sgiacomo.travaglini@arm.com MISCREG_FREESLOT_3, // 603 67712675Sgiacomo.travaglini@arm.com MISCREG_FREESLOT_4, // 604 67812675Sgiacomo.travaglini@arm.com MISCREG_FREESLOT_5, // 605 67912529Sgiacomo.travaglini@arm.com 68012529Sgiacomo.travaglini@arm.com // NUM_PHYS_MISCREGS specifies the number of actual physical 68112529Sgiacomo.travaglini@arm.com // registers, not considering the following pseudo-registers 68212530Sgiacomo.travaglini@arm.com // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. 68312529Sgiacomo.travaglini@arm.com // Checkpointing should use this physical index when 68412529Sgiacomo.travaglini@arm.com // saving/restoring register values. 68512529Sgiacomo.travaglini@arm.com NUM_PHYS_MISCREGS = 606, // 606 68612529Sgiacomo.travaglini@arm.com 68710037SARM gem5 Developers // Dummy registers 68812529Sgiacomo.travaglini@arm.com MISCREG_NOP, 68912529Sgiacomo.travaglini@arm.com MISCREG_RAZ, 69012529Sgiacomo.travaglini@arm.com MISCREG_CP14_UNIMPL, 69112529Sgiacomo.travaglini@arm.com MISCREG_CP15_UNIMPL, 69212529Sgiacomo.travaglini@arm.com MISCREG_A64_UNIMPL, 69312529Sgiacomo.travaglini@arm.com MISCREG_UNKNOWN, 69410037SARM gem5 Developers 69512530Sgiacomo.travaglini@arm.com // Implementation defined register: this represent 69612530Sgiacomo.travaglini@arm.com // a pool of unimplemented registers whose access can throw 69712530Sgiacomo.travaglini@arm.com // either UNDEFINED or hypervisor trap exception. 69812530Sgiacomo.travaglini@arm.com MISCREG_IMPDEF_UNIMPL, 69912530Sgiacomo.travaglini@arm.com 70012529Sgiacomo.travaglini@arm.com // Total number of Misc Registers: Physical + Dummy 70112529Sgiacomo.travaglini@arm.com NUM_MISCREGS 7026261Sgblack@eecs.umich.edu }; 7036261Sgblack@eecs.umich.edu 70410037SARM gem5 Developers enum MiscRegInfo { 70510037SARM gem5 Developers MISCREG_IMPLEMENTED, 70610506SAli.Saidi@ARM.com MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a 70710506SAli.Saidi@ARM.com // arch generic counter) 70810037SARM gem5 Developers MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it 70910037SARM gem5 Developers // tells whether the instruction should raise a 71010037SARM gem5 Developers // warning or fail 71110037SARM gem5 Developers MISCREG_MUTEX, // True if the register corresponds to a pair of 71210037SARM gem5 Developers // mutually exclusive registers 71310037SARM gem5 Developers MISCREG_BANKED, // True if the register is banked between the two 71410037SARM gem5 Developers // security states, and this is the parent node of the 71510037SARM gem5 Developers // two banked registers 71610037SARM gem5 Developers MISCREG_BANKED_CHILD, // The entry is one of the child registers that 71710037SARM gem5 Developers // forms a banked set of regs (along with the 71810037SARM gem5 Developers // other child regs) 71910037SARM gem5 Developers 72010037SARM gem5 Developers // Access permissions 72110037SARM gem5 Developers // User mode 72210037SARM gem5 Developers MISCREG_USR_NS_RD, 72310037SARM gem5 Developers MISCREG_USR_NS_WR, 72410037SARM gem5 Developers MISCREG_USR_S_RD, 72510037SARM gem5 Developers MISCREG_USR_S_WR, 72610037SARM gem5 Developers // Privileged modes other than hypervisor or monitor 72710037SARM gem5 Developers MISCREG_PRI_NS_RD, 72810037SARM gem5 Developers MISCREG_PRI_NS_WR, 72910037SARM gem5 Developers MISCREG_PRI_S_RD, 73010037SARM gem5 Developers MISCREG_PRI_S_WR, 73110037SARM gem5 Developers // Hypervisor mode 73210037SARM gem5 Developers MISCREG_HYP_RD, 73310037SARM gem5 Developers MISCREG_HYP_WR, 73410037SARM gem5 Developers // Monitor mode, SCR.NS == 0 73510037SARM gem5 Developers MISCREG_MON_NS0_RD, 73610037SARM gem5 Developers MISCREG_MON_NS0_WR, 73710037SARM gem5 Developers // Monitor mode, SCR.NS == 1 73810037SARM gem5 Developers MISCREG_MON_NS1_RD, 73910037SARM gem5 Developers MISCREG_MON_NS1_WR, 74010037SARM gem5 Developers 74110037SARM gem5 Developers NUM_MISCREG_INFOS 74210037SARM gem5 Developers }; 74310037SARM gem5 Developers 74410037SARM gem5 Developers extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; 74510037SARM gem5 Developers 74610037SARM gem5 Developers // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions 7478868SMatt.Horsnell@arm.com MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 7488868SMatt.Horsnell@arm.com unsigned crm, unsigned opc2); 74910037SARM gem5 Developers MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, 75010037SARM gem5 Developers unsigned crn, unsigned crm, 75110037SARM gem5 Developers unsigned op2); 75210037SARM gem5 Developers // Whether a particular AArch64 system register is -always- read only. 75310037SARM gem5 Developers bool aarch64SysRegReadOnly(MiscRegIndex miscReg); 7548868SMatt.Horsnell@arm.com 75510037SARM gem5 Developers // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions 7567259Sgblack@eecs.umich.edu MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 7577259Sgblack@eecs.umich.edu unsigned crm, unsigned opc2); 7587259Sgblack@eecs.umich.edu 75910037SARM gem5 Developers // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions 76010037SARM gem5 Developers MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1); 76110037SARM gem5 Developers 7628868SMatt.Horsnell@arm.com 7639256SAndreas.Sandberg@arm.com const char * const miscRegName[] = { 76410037SARM gem5 Developers "cpsr", 76510037SARM gem5 Developers "spsr", 76610037SARM gem5 Developers "spsr_fiq", 76710037SARM gem5 Developers "spsr_irq", 76810037SARM gem5 Developers "spsr_svc", 76910037SARM gem5 Developers "spsr_mon", 77010037SARM gem5 Developers "spsr_abt", 77110037SARM gem5 Developers "spsr_hyp", 77210037SARM gem5 Developers "spsr_und", 77310037SARM gem5 Developers "elr_hyp", 77410037SARM gem5 Developers "fpsid", 77510037SARM gem5 Developers "fpscr", 77610037SARM gem5 Developers "mvfr1", 77710037SARM gem5 Developers "mvfr0", 77810037SARM gem5 Developers "fpexc", 77910037SARM gem5 Developers 78010037SARM gem5 Developers // Helper registers 78110037SARM gem5 Developers "cpsr_mode", 78210037SARM gem5 Developers "cpsr_q", 78310037SARM gem5 Developers "fpscr_exc", 78410037SARM gem5 Developers "fpscr_qc", 78510037SARM gem5 Developers "lockaddr", 78610037SARM gem5 Developers "lockflag", 78710037SARM gem5 Developers "prrr_mair0", 78810037SARM gem5 Developers "prrr_mair0_ns", 78910037SARM gem5 Developers "prrr_mair0_s", 79010037SARM gem5 Developers "nmrr_mair1", 79110037SARM gem5 Developers "nmrr_mair1_ns", 79210037SARM gem5 Developers "nmrr_mair1_s", 79310037SARM gem5 Developers "pmxevtyper_pmccfiltr", 79410037SARM gem5 Developers "sctlr_rst", 79510037SARM gem5 Developers "sev_mailbox", 79610037SARM gem5 Developers 79710037SARM gem5 Developers // AArch32 CP14 registers 79810037SARM gem5 Developers "dbgdidr", 79910037SARM gem5 Developers "dbgdscrint", 80010037SARM gem5 Developers "dbgdccint", 80110037SARM gem5 Developers "dbgdtrtxint", 80210037SARM gem5 Developers "dbgdtrrxint", 80310037SARM gem5 Developers "dbgwfar", 80410037SARM gem5 Developers "dbgvcr", 80510037SARM gem5 Developers "dbgdtrrxext", 80610037SARM gem5 Developers "dbgdscrext", 80710037SARM gem5 Developers "dbgdtrtxext", 80810037SARM gem5 Developers "dbgoseccr", 80910037SARM gem5 Developers "dbgbvr0", 81010037SARM gem5 Developers "dbgbvr1", 81110037SARM gem5 Developers "dbgbvr2", 81210037SARM gem5 Developers "dbgbvr3", 81310037SARM gem5 Developers "dbgbvr4", 81410037SARM gem5 Developers "dbgbvr5", 81510037SARM gem5 Developers "dbgbcr0", 81610037SARM gem5 Developers "dbgbcr1", 81710037SARM gem5 Developers "dbgbcr2", 81810037SARM gem5 Developers "dbgbcr3", 81910037SARM gem5 Developers "dbgbcr4", 82010037SARM gem5 Developers "dbgbcr5", 82110037SARM gem5 Developers "dbgwvr0", 82210037SARM gem5 Developers "dbgwvr1", 82310037SARM gem5 Developers "dbgwvr2", 82410037SARM gem5 Developers "dbgwvr3", 82510037SARM gem5 Developers "dbgwcr0", 82610037SARM gem5 Developers "dbgwcr1", 82710037SARM gem5 Developers "dbgwcr2", 82810037SARM gem5 Developers "dbgwcr3", 82910037SARM gem5 Developers "dbgdrar", 83010037SARM gem5 Developers "dbgbxvr4", 83110037SARM gem5 Developers "dbgbxvr5", 83210037SARM gem5 Developers "dbgoslar", 83310037SARM gem5 Developers "dbgoslsr", 83410037SARM gem5 Developers "dbgosdlr", 83510037SARM gem5 Developers "dbgprcr", 83610037SARM gem5 Developers "dbgdsar", 83710037SARM gem5 Developers "dbgclaimset", 83810037SARM gem5 Developers "dbgclaimclr", 83910037SARM gem5 Developers "dbgauthstatus", 84010037SARM gem5 Developers "dbgdevid2", 84110037SARM gem5 Developers "dbgdevid1", 84210037SARM gem5 Developers "dbgdevid0", 84310037SARM gem5 Developers "teecr", 84410037SARM gem5 Developers "jidr", 84510037SARM gem5 Developers "teehbr", 84610037SARM gem5 Developers "joscr", 84710037SARM gem5 Developers "jmcr", 84810037SARM gem5 Developers 84910037SARM gem5 Developers // AArch32 CP15 registers 85010037SARM gem5 Developers "midr", 85110037SARM gem5 Developers "ctr", 85210037SARM gem5 Developers "tcmtr", 85310037SARM gem5 Developers "tlbtr", 85410037SARM gem5 Developers "mpidr", 85510037SARM gem5 Developers "revidr", 85610037SARM gem5 Developers "id_pfr0", 85710037SARM gem5 Developers "id_pfr1", 85810037SARM gem5 Developers "id_dfr0", 85910037SARM gem5 Developers "id_afr0", 86010037SARM gem5 Developers "id_mmfr0", 86110037SARM gem5 Developers "id_mmfr1", 86210037SARM gem5 Developers "id_mmfr2", 86310037SARM gem5 Developers "id_mmfr3", 86410037SARM gem5 Developers "id_isar0", 86510037SARM gem5 Developers "id_isar1", 86610037SARM gem5 Developers "id_isar2", 86710037SARM gem5 Developers "id_isar3", 86810037SARM gem5 Developers "id_isar4", 86910037SARM gem5 Developers "id_isar5", 87010037SARM gem5 Developers "ccsidr", 87110037SARM gem5 Developers "clidr", 87210037SARM gem5 Developers "aidr", 87310037SARM gem5 Developers "csselr", 87410037SARM gem5 Developers "csselr_ns", 87510037SARM gem5 Developers "csselr_s", 87610037SARM gem5 Developers "vpidr", 87710037SARM gem5 Developers "vmpidr", 87810037SARM gem5 Developers "sctlr", 87910037SARM gem5 Developers "sctlr_ns", 88010037SARM gem5 Developers "sctlr_s", 88110037SARM gem5 Developers "actlr", 88210037SARM gem5 Developers "actlr_ns", 88310037SARM gem5 Developers "actlr_s", 88410037SARM gem5 Developers "cpacr", 88510037SARM gem5 Developers "scr", 88610037SARM gem5 Developers "sder", 88710037SARM gem5 Developers "nsacr", 88810037SARM gem5 Developers "hsctlr", 88910037SARM gem5 Developers "hactlr", 89010037SARM gem5 Developers "hcr", 89110037SARM gem5 Developers "hdcr", 89210037SARM gem5 Developers "hcptr", 89310037SARM gem5 Developers "hstr", 89410037SARM gem5 Developers "hacr", 89510037SARM gem5 Developers "ttbr0", 89610037SARM gem5 Developers "ttbr0_ns", 89710037SARM gem5 Developers "ttbr0_s", 89810037SARM gem5 Developers "ttbr1", 89910037SARM gem5 Developers "ttbr1_ns", 90010037SARM gem5 Developers "ttbr1_s", 90110037SARM gem5 Developers "ttbcr", 90210037SARM gem5 Developers "ttbcr_ns", 90310037SARM gem5 Developers "ttbcr_s", 90410037SARM gem5 Developers "htcr", 90510037SARM gem5 Developers "vtcr", 90610037SARM gem5 Developers "dacr", 90710037SARM gem5 Developers "dacr_ns", 90810037SARM gem5 Developers "dacr_s", 90910037SARM gem5 Developers "dfsr", 91010037SARM gem5 Developers "dfsr_ns", 91110037SARM gem5 Developers "dfsr_s", 91210037SARM gem5 Developers "ifsr", 91310037SARM gem5 Developers "ifsr_ns", 91410037SARM gem5 Developers "ifsr_s", 91510037SARM gem5 Developers "adfsr", 91610037SARM gem5 Developers "adfsr_ns", 91710037SARM gem5 Developers "adfsr_s", 91810037SARM gem5 Developers "aifsr", 91910037SARM gem5 Developers "aifsr_ns", 92010037SARM gem5 Developers "aifsr_s", 92110037SARM gem5 Developers "hadfsr", 92210037SARM gem5 Developers "haifsr", 92310037SARM gem5 Developers "hsr", 92410037SARM gem5 Developers "dfar", 92510037SARM gem5 Developers "dfar_ns", 92610037SARM gem5 Developers "dfar_s", 92710037SARM gem5 Developers "ifar", 92810037SARM gem5 Developers "ifar_ns", 92910037SARM gem5 Developers "ifar_s", 93010037SARM gem5 Developers "hdfar", 93110037SARM gem5 Developers "hifar", 93210037SARM gem5 Developers "hpfar", 93310037SARM gem5 Developers "icialluis", 93410037SARM gem5 Developers "bpiallis", 93510037SARM gem5 Developers "par", 93610037SARM gem5 Developers "par_ns", 93710037SARM gem5 Developers "par_s", 93810037SARM gem5 Developers "iciallu", 93910037SARM gem5 Developers "icimvau", 94010037SARM gem5 Developers "cp15isb", 94110037SARM gem5 Developers "bpiall", 94210037SARM gem5 Developers "bpimva", 94310037SARM gem5 Developers "dcimvac", 94410037SARM gem5 Developers "dcisw", 94510037SARM gem5 Developers "ats1cpr", 94610037SARM gem5 Developers "ats1cpw", 94710037SARM gem5 Developers "ats1cur", 94810037SARM gem5 Developers "ats1cuw", 94910037SARM gem5 Developers "ats12nsopr", 95010037SARM gem5 Developers "ats12nsopw", 95110037SARM gem5 Developers "ats12nsour", 95210037SARM gem5 Developers "ats12nsouw", 95310037SARM gem5 Developers "dccmvac", 95410037SARM gem5 Developers "dccsw", 95510037SARM gem5 Developers "cp15dsb", 95610037SARM gem5 Developers "cp15dmb", 95710037SARM gem5 Developers "dccmvau", 95810037SARM gem5 Developers "dccimvac", 95910037SARM gem5 Developers "dccisw", 96010037SARM gem5 Developers "ats1hr", 96110037SARM gem5 Developers "ats1hw", 96210037SARM gem5 Developers "tlbiallis", 96310037SARM gem5 Developers "tlbimvais", 96410037SARM gem5 Developers "tlbiasidis", 96510037SARM gem5 Developers "tlbimvaais", 96610037SARM gem5 Developers "tlbimvalis", 96710037SARM gem5 Developers "tlbimvaalis", 96810037SARM gem5 Developers "itlbiall", 96910037SARM gem5 Developers "itlbimva", 97010037SARM gem5 Developers "itlbiasid", 97110037SARM gem5 Developers "dtlbiall", 97210037SARM gem5 Developers "dtlbimva", 97310037SARM gem5 Developers "dtlbiasid", 97410037SARM gem5 Developers "tlbiall", 97510037SARM gem5 Developers "tlbimva", 97610037SARM gem5 Developers "tlbiasid", 97710037SARM gem5 Developers "tlbimvaa", 97810037SARM gem5 Developers "tlbimval", 97910037SARM gem5 Developers "tlbimvaal", 98010037SARM gem5 Developers "tlbiipas2is", 98110037SARM gem5 Developers "tlbiipas2lis", 98210037SARM gem5 Developers "tlbiallhis", 98310037SARM gem5 Developers "tlbimvahis", 98410037SARM gem5 Developers "tlbiallnsnhis", 98510037SARM gem5 Developers "tlbimvalhis", 98610037SARM gem5 Developers "tlbiipas2", 98710037SARM gem5 Developers "tlbiipas2l", 98810037SARM gem5 Developers "tlbiallh", 98910037SARM gem5 Developers "tlbimvah", 99010037SARM gem5 Developers "tlbiallnsnh", 99110037SARM gem5 Developers "tlbimvalh", 99210037SARM gem5 Developers "pmcr", 99310037SARM gem5 Developers "pmcntenset", 99410037SARM gem5 Developers "pmcntenclr", 99510037SARM gem5 Developers "pmovsr", 99610037SARM gem5 Developers "pmswinc", 99710037SARM gem5 Developers "pmselr", 99810037SARM gem5 Developers "pmceid0", 99910037SARM gem5 Developers "pmceid1", 100010037SARM gem5 Developers "pmccntr", 100110037SARM gem5 Developers "pmxevtyper", 100210037SARM gem5 Developers "pmccfiltr", 100310037SARM gem5 Developers "pmxevcntr", 100410037SARM gem5 Developers "pmuserenr", 100510037SARM gem5 Developers "pmintenset", 100610037SARM gem5 Developers "pmintenclr", 100710037SARM gem5 Developers "pmovsset", 10088549Sdaniel.johnson@arm.com "l2ctlr", 100910037SARM gem5 Developers "l2ectlr", 101010037SARM gem5 Developers "prrr", 101110037SARM gem5 Developers "prrr_ns", 101210037SARM gem5 Developers "prrr_s", 101310037SARM gem5 Developers "mair0", 101410037SARM gem5 Developers "mair0_ns", 101510037SARM gem5 Developers "mair0_s", 101610037SARM gem5 Developers "nmrr", 101710037SARM gem5 Developers "nmrr_ns", 101810037SARM gem5 Developers "nmrr_s", 101910037SARM gem5 Developers "mair1", 102010037SARM gem5 Developers "mair1_ns", 102110037SARM gem5 Developers "mair1_s", 102210037SARM gem5 Developers "amair0", 102310037SARM gem5 Developers "amair0_ns", 102410037SARM gem5 Developers "amair0_s", 102510037SARM gem5 Developers "amair1", 102610037SARM gem5 Developers "amair1_ns", 102710037SARM gem5 Developers "amair1_s", 102810037SARM gem5 Developers "hmair0", 102910037SARM gem5 Developers "hmair1", 103010037SARM gem5 Developers "hamair0", 103110037SARM gem5 Developers "hamair1", 103210037SARM gem5 Developers "vbar", 103310037SARM gem5 Developers "vbar_ns", 103410037SARM gem5 Developers "vbar_s", 103510037SARM gem5 Developers "mvbar", 103610037SARM gem5 Developers "rmr", 103710037SARM gem5 Developers "isr", 103810037SARM gem5 Developers "hvbar", 103910037SARM gem5 Developers "fcseidr", 104010037SARM gem5 Developers "contextidr", 104110037SARM gem5 Developers "contextidr_ns", 104210037SARM gem5 Developers "contextidr_s", 104310037SARM gem5 Developers "tpidrurw", 104410037SARM gem5 Developers "tpidrurw_ns", 104510037SARM gem5 Developers "tpidrurw_s", 104610037SARM gem5 Developers "tpidruro", 104710037SARM gem5 Developers "tpidruro_ns", 104810037SARM gem5 Developers "tpidruro_s", 104910037SARM gem5 Developers "tpidrprw", 105010037SARM gem5 Developers "tpidrprw_ns", 105110037SARM gem5 Developers "tpidrprw_s", 105210037SARM gem5 Developers "htpidr", 105310037SARM gem5 Developers "cntfrq", 105410037SARM gem5 Developers "cntkctl", 105510037SARM gem5 Developers "cntp_tval", 105610037SARM gem5 Developers "cntp_tval_ns", 105710037SARM gem5 Developers "cntp_tval_s", 105810037SARM gem5 Developers "cntp_ctl", 105910037SARM gem5 Developers "cntp_ctl_ns", 106010037SARM gem5 Developers "cntp_ctl_s", 106110037SARM gem5 Developers "cntv_tval", 106210037SARM gem5 Developers "cntv_ctl", 106310037SARM gem5 Developers "cnthctl", 106410037SARM gem5 Developers "cnthp_tval", 106510037SARM gem5 Developers "cnthp_ctl", 106610037SARM gem5 Developers "il1data0", 106710037SARM gem5 Developers "il1data1", 106810037SARM gem5 Developers "il1data2", 106910037SARM gem5 Developers "il1data3", 107010037SARM gem5 Developers "dl1data0", 107110037SARM gem5 Developers "dl1data1", 107210037SARM gem5 Developers "dl1data2", 107310037SARM gem5 Developers "dl1data3", 107410037SARM gem5 Developers "dl1data4", 107510037SARM gem5 Developers "ramindex", 107610037SARM gem5 Developers "l2actlr", 107710037SARM gem5 Developers "cbar", 107810037SARM gem5 Developers "httbr", 107910037SARM gem5 Developers "vttbr", 108010037SARM gem5 Developers "cntpct", 108110037SARM gem5 Developers "cntvct", 108210037SARM gem5 Developers "cntp_cval", 108310037SARM gem5 Developers "cntp_cval_ns", 108410037SARM gem5 Developers "cntp_cval_s", 108510037SARM gem5 Developers "cntv_cval", 108610037SARM gem5 Developers "cntvoff", 108710037SARM gem5 Developers "cnthp_cval", 108810037SARM gem5 Developers "cpumerrsr", 108910037SARM gem5 Developers "l2merrsr", 109010037SARM gem5 Developers 109110037SARM gem5 Developers // AArch64 registers (Op0=2) 109210037SARM gem5 Developers "mdccint_el1", 109310037SARM gem5 Developers "osdtrrx_el1", 109410037SARM gem5 Developers "mdscr_el1", 109510037SARM gem5 Developers "osdtrtx_el1", 109610037SARM gem5 Developers "oseccr_el1", 109710037SARM gem5 Developers "dbgbvr0_el1", 109810037SARM gem5 Developers "dbgbvr1_el1", 109910037SARM gem5 Developers "dbgbvr2_el1", 110010037SARM gem5 Developers "dbgbvr3_el1", 110110037SARM gem5 Developers "dbgbvr4_el1", 110210037SARM gem5 Developers "dbgbvr5_el1", 110310037SARM gem5 Developers "dbgbcr0_el1", 110410037SARM gem5 Developers "dbgbcr1_el1", 110510037SARM gem5 Developers "dbgbcr2_el1", 110610037SARM gem5 Developers "dbgbcr3_el1", 110710037SARM gem5 Developers "dbgbcr4_el1", 110810037SARM gem5 Developers "dbgbcr5_el1", 110910037SARM gem5 Developers "dbgwvr0_el1", 111010037SARM gem5 Developers "dbgwvr1_el1", 111110037SARM gem5 Developers "dbgwvr2_el1", 111210037SARM gem5 Developers "dbgwvr3_el1", 111310037SARM gem5 Developers "dbgwcr0_el1", 111410037SARM gem5 Developers "dbgwcr1_el1", 111510037SARM gem5 Developers "dbgwcr2_el1", 111610037SARM gem5 Developers "dbgwcr3_el1", 111710037SARM gem5 Developers "mdccsr_el0", 111810037SARM gem5 Developers "mddtr_el0", 111910037SARM gem5 Developers "mddtrtx_el0", 112010037SARM gem5 Developers "mddtrrx_el0", 112110037SARM gem5 Developers "dbgvcr32_el2", 112210037SARM gem5 Developers "mdrar_el1", 112310037SARM gem5 Developers "oslar_el1", 112410037SARM gem5 Developers "oslsr_el1", 112510037SARM gem5 Developers "osdlr_el1", 112610037SARM gem5 Developers "dbgprcr_el1", 112710037SARM gem5 Developers "dbgclaimset_el1", 112810037SARM gem5 Developers "dbgclaimclr_el1", 112910037SARM gem5 Developers "dbgauthstatus_el1", 113010037SARM gem5 Developers "teecr32_el1", 113110037SARM gem5 Developers "teehbr32_el1", 113210037SARM gem5 Developers 113310037SARM gem5 Developers // AArch64 registers (Op0=1,3) 113410037SARM gem5 Developers "midr_el1", 113510037SARM gem5 Developers "mpidr_el1", 113610037SARM gem5 Developers "revidr_el1", 113710037SARM gem5 Developers "id_pfr0_el1", 113810037SARM gem5 Developers "id_pfr1_el1", 113910037SARM gem5 Developers "id_dfr0_el1", 114010037SARM gem5 Developers "id_afr0_el1", 114110037SARM gem5 Developers "id_mmfr0_el1", 114210037SARM gem5 Developers "id_mmfr1_el1", 114310037SARM gem5 Developers "id_mmfr2_el1", 114410037SARM gem5 Developers "id_mmfr3_el1", 114510037SARM gem5 Developers "id_isar0_el1", 114610037SARM gem5 Developers "id_isar1_el1", 114710037SARM gem5 Developers "id_isar2_el1", 114810037SARM gem5 Developers "id_isar3_el1", 114910037SARM gem5 Developers "id_isar4_el1", 115010037SARM gem5 Developers "id_isar5_el1", 115110037SARM gem5 Developers "mvfr0_el1", 115210037SARM gem5 Developers "mvfr1_el1", 115310037SARM gem5 Developers "mvfr2_el1", 115410037SARM gem5 Developers "id_aa64pfr0_el1", 115510037SARM gem5 Developers "id_aa64pfr1_el1", 115610037SARM gem5 Developers "id_aa64dfr0_el1", 115710037SARM gem5 Developers "id_aa64dfr1_el1", 115810037SARM gem5 Developers "id_aa64afr0_el1", 115910037SARM gem5 Developers "id_aa64afr1_el1", 116010037SARM gem5 Developers "id_aa64isar0_el1", 116110037SARM gem5 Developers "id_aa64isar1_el1", 116210037SARM gem5 Developers "id_aa64mmfr0_el1", 116310037SARM gem5 Developers "id_aa64mmfr1_el1", 116410037SARM gem5 Developers "ccsidr_el1", 116510037SARM gem5 Developers "clidr_el1", 116610037SARM gem5 Developers "aidr_el1", 116710037SARM gem5 Developers "csselr_el1", 116810037SARM gem5 Developers "ctr_el0", 116910037SARM gem5 Developers "dczid_el0", 117010037SARM gem5 Developers "vpidr_el2", 117110037SARM gem5 Developers "vmpidr_el2", 117210037SARM gem5 Developers "sctlr_el1", 117310037SARM gem5 Developers "actlr_el1", 117410037SARM gem5 Developers "cpacr_el1", 117510037SARM gem5 Developers "sctlr_el2", 117610037SARM gem5 Developers "actlr_el2", 117710037SARM gem5 Developers "hcr_el2", 117810037SARM gem5 Developers "mdcr_el2", 117910037SARM gem5 Developers "cptr_el2", 118010037SARM gem5 Developers "hstr_el2", 118110037SARM gem5 Developers "hacr_el2", 118210037SARM gem5 Developers "sctlr_el3", 118310037SARM gem5 Developers "actlr_el3", 118410037SARM gem5 Developers "scr_el3", 118510037SARM gem5 Developers "sder32_el3", 118610037SARM gem5 Developers "cptr_el3", 118710037SARM gem5 Developers "mdcr_el3", 118810037SARM gem5 Developers "ttbr0_el1", 118910037SARM gem5 Developers "ttbr1_el1", 119010037SARM gem5 Developers "tcr_el1", 119110037SARM gem5 Developers "ttbr0_el2", 119210037SARM gem5 Developers "tcr_el2", 119310037SARM gem5 Developers "vttbr_el2", 119410037SARM gem5 Developers "vtcr_el2", 119510037SARM gem5 Developers "ttbr0_el3", 119610037SARM gem5 Developers "tcr_el3", 119710037SARM gem5 Developers "dacr32_el2", 119810037SARM gem5 Developers "spsr_el1", 119910037SARM gem5 Developers "elr_el1", 120010037SARM gem5 Developers "sp_el0", 120110037SARM gem5 Developers "spsel", 120210037SARM gem5 Developers "currentel", 120310037SARM gem5 Developers "nzcv", 120410037SARM gem5 Developers "daif", 120510037SARM gem5 Developers "fpcr", 120610037SARM gem5 Developers "fpsr", 120710037SARM gem5 Developers "dspsr_el0", 120810037SARM gem5 Developers "dlr_el0", 120910037SARM gem5 Developers "spsr_el2", 121010037SARM gem5 Developers "elr_el2", 121110037SARM gem5 Developers "sp_el1", 121210037SARM gem5 Developers "spsr_irq_aa64", 121310037SARM gem5 Developers "spsr_abt_aa64", 121410037SARM gem5 Developers "spsr_und_aa64", 121510037SARM gem5 Developers "spsr_fiq_aa64", 121610037SARM gem5 Developers "spsr_el3", 121710037SARM gem5 Developers "elr_el3", 121810037SARM gem5 Developers "sp_el2", 121910037SARM gem5 Developers "afsr0_el1", 122010037SARM gem5 Developers "afsr1_el1", 122110037SARM gem5 Developers "esr_el1", 122210037SARM gem5 Developers "ifsr32_el2", 122310037SARM gem5 Developers "afsr0_el2", 122410037SARM gem5 Developers "afsr1_el2", 122510037SARM gem5 Developers "esr_el2", 122610037SARM gem5 Developers "fpexc32_el2", 122710037SARM gem5 Developers "afsr0_el3", 122810037SARM gem5 Developers "afsr1_el3", 122910037SARM gem5 Developers "esr_el3", 123010037SARM gem5 Developers "far_el1", 123110037SARM gem5 Developers "far_el2", 123210037SARM gem5 Developers "hpfar_el2", 123310037SARM gem5 Developers "far_el3", 123410037SARM gem5 Developers "ic_ialluis", 123510037SARM gem5 Developers "par_el1", 123610037SARM gem5 Developers "ic_iallu", 123710037SARM gem5 Developers "dc_ivac_xt", 123810037SARM gem5 Developers "dc_isw_xt", 123910037SARM gem5 Developers "at_s1e1r_xt", 124010037SARM gem5 Developers "at_s1e1w_xt", 124110037SARM gem5 Developers "at_s1e0r_xt", 124210037SARM gem5 Developers "at_s1e0w_xt", 124310037SARM gem5 Developers "dc_csw_xt", 124410037SARM gem5 Developers "dc_cisw_xt", 124510037SARM gem5 Developers "dc_zva_xt", 124610037SARM gem5 Developers "ic_ivau_xt", 124710037SARM gem5 Developers "dc_cvac_xt", 124810037SARM gem5 Developers "dc_cvau_xt", 124910037SARM gem5 Developers "dc_civac_xt", 125010037SARM gem5 Developers "at_s1e2r_xt", 125110037SARM gem5 Developers "at_s1e2w_xt", 125210037SARM gem5 Developers "at_s12e1r_xt", 125310037SARM gem5 Developers "at_s12e1w_xt", 125410037SARM gem5 Developers "at_s12e0r_xt", 125510037SARM gem5 Developers "at_s12e0w_xt", 125610037SARM gem5 Developers "at_s1e3r_xt", 125710037SARM gem5 Developers "at_s1e3w_xt", 125810037SARM gem5 Developers "tlbi_vmalle1is", 125910037SARM gem5 Developers "tlbi_vae1is_xt", 126010037SARM gem5 Developers "tlbi_aside1is_xt", 126110037SARM gem5 Developers "tlbi_vaae1is_xt", 126210037SARM gem5 Developers "tlbi_vale1is_xt", 126310037SARM gem5 Developers "tlbi_vaale1is_xt", 126410037SARM gem5 Developers "tlbi_vmalle1", 126510037SARM gem5 Developers "tlbi_vae1_xt", 126610037SARM gem5 Developers "tlbi_aside1_xt", 126710037SARM gem5 Developers "tlbi_vaae1_xt", 126810037SARM gem5 Developers "tlbi_vale1_xt", 126910037SARM gem5 Developers "tlbi_vaale1_xt", 127010037SARM gem5 Developers "tlbi_ipas2e1is_xt", 127110037SARM gem5 Developers "tlbi_ipas2le1is_xt", 127210037SARM gem5 Developers "tlbi_alle2is", 127310037SARM gem5 Developers "tlbi_vae2is_xt", 127410037SARM gem5 Developers "tlbi_alle1is", 127510037SARM gem5 Developers "tlbi_vale2is_xt", 127610037SARM gem5 Developers "tlbi_vmalls12e1is", 127710037SARM gem5 Developers "tlbi_ipas2e1_xt", 127810037SARM gem5 Developers "tlbi_ipas2le1_xt", 127910037SARM gem5 Developers "tlbi_alle2", 128010037SARM gem5 Developers "tlbi_vae2_xt", 128110037SARM gem5 Developers "tlbi_alle1", 128210037SARM gem5 Developers "tlbi_vale2_xt", 128310037SARM gem5 Developers "tlbi_vmalls12e1", 128410037SARM gem5 Developers "tlbi_alle3is", 128510037SARM gem5 Developers "tlbi_vae3is_xt", 128610037SARM gem5 Developers "tlbi_vale3is_xt", 128710037SARM gem5 Developers "tlbi_alle3", 128810037SARM gem5 Developers "tlbi_vae3_xt", 128910037SARM gem5 Developers "tlbi_vale3_xt", 129010037SARM gem5 Developers "pmintenset_el1", 129110037SARM gem5 Developers "pmintenclr_el1", 129210037SARM gem5 Developers "pmcr_el0", 129310037SARM gem5 Developers "pmcntenset_el0", 129410037SARM gem5 Developers "pmcntenclr_el0", 129510037SARM gem5 Developers "pmovsclr_el0", 129610037SARM gem5 Developers "pmswinc_el0", 129710037SARM gem5 Developers "pmselr_el0", 129810037SARM gem5 Developers "pmceid0_el0", 129910037SARM gem5 Developers "pmceid1_el0", 130010037SARM gem5 Developers "pmccntr_el0", 130110037SARM gem5 Developers "pmxevtyper_el0", 130210037SARM gem5 Developers "pmccfiltr_el0", 130310037SARM gem5 Developers "pmxevcntr_el0", 130410037SARM gem5 Developers "pmuserenr_el0", 130510037SARM gem5 Developers "pmovsset_el0", 130610037SARM gem5 Developers "mair_el1", 130710037SARM gem5 Developers "amair_el1", 130810037SARM gem5 Developers "mair_el2", 130910037SARM gem5 Developers "amair_el2", 131010037SARM gem5 Developers "mair_el3", 131110037SARM gem5 Developers "amair_el3", 131210037SARM gem5 Developers "l2ctlr_el1", 131310037SARM gem5 Developers "l2ectlr_el1", 131410037SARM gem5 Developers "vbar_el1", 131510037SARM gem5 Developers "rvbar_el1", 131610037SARM gem5 Developers "isr_el1", 131710037SARM gem5 Developers "vbar_el2", 131810037SARM gem5 Developers "rvbar_el2", 131910037SARM gem5 Developers "vbar_el3", 132010037SARM gem5 Developers "rvbar_el3", 132110037SARM gem5 Developers "rmr_el3", 132210037SARM gem5 Developers "contextidr_el1", 132310037SARM gem5 Developers "tpidr_el1", 132410037SARM gem5 Developers "tpidr_el0", 132510037SARM gem5 Developers "tpidrro_el0", 132610037SARM gem5 Developers "tpidr_el2", 132710037SARM gem5 Developers "tpidr_el3", 132810037SARM gem5 Developers "cntkctl_el1", 132910037SARM gem5 Developers "cntfrq_el0", 133010037SARM gem5 Developers "cntpct_el0", 133110037SARM gem5 Developers "cntvct_el0", 133210037SARM gem5 Developers "cntp_tval_el0", 133310037SARM gem5 Developers "cntp_ctl_el0", 133410037SARM gem5 Developers "cntp_cval_el0", 133510037SARM gem5 Developers "cntv_tval_el0", 133610037SARM gem5 Developers "cntv_ctl_el0", 133710037SARM gem5 Developers "cntv_cval_el0", 133810037SARM gem5 Developers "pmevcntr0_el0", 133910037SARM gem5 Developers "pmevcntr1_el0", 134010037SARM gem5 Developers "pmevcntr2_el0", 134110037SARM gem5 Developers "pmevcntr3_el0", 134210037SARM gem5 Developers "pmevcntr4_el0", 134310037SARM gem5 Developers "pmevcntr5_el0", 134410037SARM gem5 Developers "pmevtyper0_el0", 134510037SARM gem5 Developers "pmevtyper1_el0", 134610037SARM gem5 Developers "pmevtyper2_el0", 134710037SARM gem5 Developers "pmevtyper3_el0", 134810037SARM gem5 Developers "pmevtyper4_el0", 134910037SARM gem5 Developers "pmevtyper5_el0", 135010037SARM gem5 Developers "cntvoff_el2", 135110037SARM gem5 Developers "cnthctl_el2", 135210037SARM gem5 Developers "cnthp_tval_el2", 135310037SARM gem5 Developers "cnthp_ctl_el2", 135410037SARM gem5 Developers "cnthp_cval_el2", 135510037SARM gem5 Developers "cntps_tval_el1", 135610037SARM gem5 Developers "cntps_ctl_el1", 135710037SARM gem5 Developers "cntps_cval_el1", 135810037SARM gem5 Developers "il1data0_el1", 135910037SARM gem5 Developers "il1data1_el1", 136010037SARM gem5 Developers "il1data2_el1", 136110037SARM gem5 Developers "il1data3_el1", 136210037SARM gem5 Developers "dl1data0_el1", 136310037SARM gem5 Developers "dl1data1_el1", 136410037SARM gem5 Developers "dl1data2_el1", 136510037SARM gem5 Developers "dl1data3_el1", 136610037SARM gem5 Developers "dl1data4_el1", 136710037SARM gem5 Developers "l2actlr_el1", 136810037SARM gem5 Developers "cpuactlr_el1", 136910037SARM gem5 Developers "cpuectlr_el1", 137010037SARM gem5 Developers "cpumerrsr_el1", 137110037SARM gem5 Developers "l2merrsr_el1", 137210037SARM gem5 Developers "cbar_el1", 137310856SCurtis.Dunham@arm.com "contextidr_el2", 137410037SARM gem5 Developers 137512675Sgiacomo.travaglini@arm.com "ttbr1_el2", 137612529Sgiacomo.travaglini@arm.com "freeslot1", 137712529Sgiacomo.travaglini@arm.com "freeslot2", 137812529Sgiacomo.travaglini@arm.com "freeslot3", 137912529Sgiacomo.travaglini@arm.com "freeslot4", 138012529Sgiacomo.travaglini@arm.com "freeslot5", 138112529Sgiacomo.travaglini@arm.com 138212529Sgiacomo.travaglini@arm.com "num_phys_regs", 138312529Sgiacomo.travaglini@arm.com 138410037SARM gem5 Developers // Dummy registers 138510037SARM gem5 Developers "nop", 138610037SARM gem5 Developers "raz", 138710037SARM gem5 Developers "cp14_unimpl", 138810037SARM gem5 Developers "cp15_unimpl", 138910037SARM gem5 Developers "a64_unimpl", 139012530Sgiacomo.travaglini@arm.com "unknown", 139112530Sgiacomo.travaglini@arm.com "impl_defined" 13926242Sgblack@eecs.umich.edu }; 13936242Sgblack@eecs.umich.edu 13949256SAndreas.Sandberg@arm.com static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 13959256SAndreas.Sandberg@arm.com "The miscRegName array and NUM_MISCREGS are inconsistent."); 13969256SAndreas.Sandberg@arm.com 13976242Sgblack@eecs.umich.edu BitUnion32(CPSR) 139810037SARM gem5 Developers Bitfield<31, 30> nz; 13996242Sgblack@eecs.umich.edu Bitfield<29> c; 14006242Sgblack@eecs.umich.edu Bitfield<28> v; 14016242Sgblack@eecs.umich.edu Bitfield<27> q; 140210037SARM gem5 Developers Bitfield<26, 25> it1; 14036242Sgblack@eecs.umich.edu Bitfield<24> j; 140410037SARM gem5 Developers Bitfield<23, 22> res0_23_22; 140510037SARM gem5 Developers Bitfield<21> ss; // AArch64 140610037SARM gem5 Developers Bitfield<20> il; // AArch64 14076242Sgblack@eecs.umich.edu Bitfield<19, 16> ge; 140810037SARM gem5 Developers Bitfield<15, 10> it2; 140910037SARM gem5 Developers Bitfield<9> d; // AArch64 14106242Sgblack@eecs.umich.edu Bitfield<9> e; 14116242Sgblack@eecs.umich.edu Bitfield<8> a; 14126242Sgblack@eecs.umich.edu Bitfield<7> i; 14136242Sgblack@eecs.umich.edu Bitfield<6> f; 141411514Sandreas.sandberg@arm.com Bitfield<8, 6> aif; 141510037SARM gem5 Developers Bitfield<9, 6> daif; // AArch64 14166242Sgblack@eecs.umich.edu Bitfield<5> t; 141710037SARM gem5 Developers Bitfield<4> width; // AArch64 141810037SARM gem5 Developers Bitfield<3, 2> el; // AArch64 14196242Sgblack@eecs.umich.edu Bitfield<4, 0> mode; 142010037SARM gem5 Developers Bitfield<0> sp; // AArch64 14216242Sgblack@eecs.umich.edu EndBitUnion(CPSR) 14226735Sgblack@eecs.umich.edu 14236750Sgblack@eecs.umich.edu // This mask selects bits of the CPSR that actually go in the CondCodes 14246750Sgblack@eecs.umich.edu // integer register to allow renaming. 14258302SAli.Saidi@ARM.com static const uint32_t CondCodesMask = 0xF00F0000; 14268302SAli.Saidi@ARM.com static const uint32_t CpsrMaskQ = 0x08000000; 14276750Sgblack@eecs.umich.edu 142810037SARM gem5 Developers BitUnion32(HDCR) 142910037SARM gem5 Developers Bitfield<11> tdra; 143010037SARM gem5 Developers Bitfield<10> tdosa; 143110037SARM gem5 Developers Bitfield<9> tda; 143210037SARM gem5 Developers Bitfield<8> tde; 143310037SARM gem5 Developers Bitfield<7> hpme; 143410037SARM gem5 Developers Bitfield<6> tpm; 143510037SARM gem5 Developers Bitfield<5> tpmcr; 143610037SARM gem5 Developers Bitfield<4, 0> hpmn; 143710037SARM gem5 Developers EndBitUnion(HDCR) 143810037SARM gem5 Developers 143910037SARM gem5 Developers BitUnion32(HCPTR) 144010037SARM gem5 Developers Bitfield<31> tcpac; 144110037SARM gem5 Developers Bitfield<20> tta; 144210037SARM gem5 Developers Bitfield<15> tase; 144310037SARM gem5 Developers Bitfield<13> tcp13; 144410037SARM gem5 Developers Bitfield<12> tcp12; 144510037SARM gem5 Developers Bitfield<11> tcp11; 144610037SARM gem5 Developers Bitfield<10> tcp10; 144710037SARM gem5 Developers Bitfield<10> tfp; // AArch64 144810037SARM gem5 Developers Bitfield<9> tcp9; 144910037SARM gem5 Developers Bitfield<8> tcp8; 145010037SARM gem5 Developers Bitfield<7> tcp7; 145110037SARM gem5 Developers Bitfield<6> tcp6; 145210037SARM gem5 Developers Bitfield<5> tcp5; 145310037SARM gem5 Developers Bitfield<4> tcp4; 145410037SARM gem5 Developers Bitfield<3> tcp3; 145510037SARM gem5 Developers Bitfield<2> tcp2; 145610037SARM gem5 Developers Bitfield<1> tcp1; 145710037SARM gem5 Developers Bitfield<0> tcp0; 145810037SARM gem5 Developers EndBitUnion(HCPTR) 145910037SARM gem5 Developers 146010037SARM gem5 Developers BitUnion32(HSTR) 146110037SARM gem5 Developers Bitfield<17> tjdbx; 146210037SARM gem5 Developers Bitfield<16> ttee; 146310037SARM gem5 Developers Bitfield<15> t15; 146410037SARM gem5 Developers Bitfield<13> t13; 146510037SARM gem5 Developers Bitfield<12> t12; 146610037SARM gem5 Developers Bitfield<11> t11; 146710037SARM gem5 Developers Bitfield<10> t10; 146810037SARM gem5 Developers Bitfield<9> t9; 146910037SARM gem5 Developers Bitfield<8> t8; 147010037SARM gem5 Developers Bitfield<7> t7; 147110037SARM gem5 Developers Bitfield<6> t6; 147210037SARM gem5 Developers Bitfield<5> t5; 147310037SARM gem5 Developers Bitfield<4> t4; 147410037SARM gem5 Developers Bitfield<3> t3; 147510037SARM gem5 Developers Bitfield<2> t2; 147610037SARM gem5 Developers Bitfield<1> t1; 147710037SARM gem5 Developers Bitfield<0> t0; 147810037SARM gem5 Developers EndBitUnion(HSTR) 147910037SARM gem5 Developers 148010037SARM gem5 Developers BitUnion64(HCR) 148112708Sgiacomo.travaglini@arm.com Bitfield<34> e2h; // AArch64 148210037SARM gem5 Developers Bitfield<33> id; // AArch64 148310037SARM gem5 Developers Bitfield<32> cd; // AArch64 148410037SARM gem5 Developers Bitfield<31> rw; // AArch64 148510037SARM gem5 Developers Bitfield<30> trvm; // AArch64 148610037SARM gem5 Developers Bitfield<29> hcd; // AArch64 148710037SARM gem5 Developers Bitfield<28> tdz; // AArch64 148810037SARM gem5 Developers 148910037SARM gem5 Developers Bitfield<27> tge; 149010037SARM gem5 Developers Bitfield<26> tvm; 149110037SARM gem5 Developers Bitfield<25> ttlb; 149210037SARM gem5 Developers Bitfield<24> tpu; 149310037SARM gem5 Developers Bitfield<23> tpc; 149410037SARM gem5 Developers Bitfield<22> tsw; 149510037SARM gem5 Developers Bitfield<21> tac; 149610037SARM gem5 Developers Bitfield<21> tacr; // AArch64 149710037SARM gem5 Developers Bitfield<20> tidcp; 149810037SARM gem5 Developers Bitfield<19> tsc; 149910037SARM gem5 Developers Bitfield<18> tid3; 150010037SARM gem5 Developers Bitfield<17> tid2; 150110037SARM gem5 Developers Bitfield<16> tid1; 150210037SARM gem5 Developers Bitfield<15> tid0; 150310037SARM gem5 Developers Bitfield<14> twe; 150410037SARM gem5 Developers Bitfield<13> twi; 150510037SARM gem5 Developers Bitfield<12> dc; 150610037SARM gem5 Developers Bitfield<11, 10> bsu; 150710037SARM gem5 Developers Bitfield<9> fb; 150810037SARM gem5 Developers Bitfield<8> va; 150910037SARM gem5 Developers Bitfield<8> vse; // AArch64 151010037SARM gem5 Developers Bitfield<7> vi; 151110037SARM gem5 Developers Bitfield<6> vf; 151210037SARM gem5 Developers Bitfield<5> amo; 151310037SARM gem5 Developers Bitfield<4> imo; 151410037SARM gem5 Developers Bitfield<3> fmo; 151510037SARM gem5 Developers Bitfield<2> ptw; 151610037SARM gem5 Developers Bitfield<1> swio; 151710037SARM gem5 Developers Bitfield<0> vm; 151810037SARM gem5 Developers EndBitUnion(HCR) 151910037SARM gem5 Developers 152010037SARM gem5 Developers BitUnion32(NSACR) 152110037SARM gem5 Developers Bitfield<20> nstrcdis; 152210037SARM gem5 Developers Bitfield<19> rfr; 152310037SARM gem5 Developers Bitfield<15> nsasedis; 152410037SARM gem5 Developers Bitfield<14> nsd32dis; 152510037SARM gem5 Developers Bitfield<13> cp13; 152610037SARM gem5 Developers Bitfield<12> cp12; 152710037SARM gem5 Developers Bitfield<11> cp11; 152810037SARM gem5 Developers Bitfield<10> cp10; 152910037SARM gem5 Developers Bitfield<9> cp9; 153010037SARM gem5 Developers Bitfield<8> cp8; 153110037SARM gem5 Developers Bitfield<7> cp7; 153210037SARM gem5 Developers Bitfield<6> cp6; 153310037SARM gem5 Developers Bitfield<5> cp5; 153410037SARM gem5 Developers Bitfield<4> cp4; 153510037SARM gem5 Developers Bitfield<3> cp3; 153610037SARM gem5 Developers Bitfield<2> cp2; 153710037SARM gem5 Developers Bitfield<1> cp1; 153810037SARM gem5 Developers Bitfield<0> cp0; 153910037SARM gem5 Developers EndBitUnion(NSACR) 154010037SARM gem5 Developers 154110037SARM gem5 Developers BitUnion32(SCR) 154210037SARM gem5 Developers Bitfield<13> twe; 154310037SARM gem5 Developers Bitfield<12> twi; 154410037SARM gem5 Developers Bitfield<11> st; // AArch64 154510037SARM gem5 Developers Bitfield<10> rw; // AArch64 154610037SARM gem5 Developers Bitfield<9> sif; 154710037SARM gem5 Developers Bitfield<8> hce; 154810037SARM gem5 Developers Bitfield<7> scd; 154910037SARM gem5 Developers Bitfield<7> smd; // AArch64 155010037SARM gem5 Developers Bitfield<6> nEt; 155110037SARM gem5 Developers Bitfield<5> aw; 155210037SARM gem5 Developers Bitfield<4> fw; 155310037SARM gem5 Developers Bitfield<3> ea; 155410037SARM gem5 Developers Bitfield<2> fiq; 155510037SARM gem5 Developers Bitfield<1> irq; 155610037SARM gem5 Developers Bitfield<0> ns; 155710037SARM gem5 Developers EndBitUnion(SCR) 155810037SARM gem5 Developers 15596735Sgblack@eecs.umich.edu BitUnion32(SCTLR) 156010037SARM gem5 Developers Bitfield<30> te; // Thumb Exception Enable (AArch32 only) 156110037SARM gem5 Developers Bitfield<29> afe; // Access flag enable (AArch32 only) 156210037SARM gem5 Developers Bitfield<28> tre; // TEX remap enable (AArch32 only) 156310037SARM gem5 Developers Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only) 156410037SARM gem5 Developers Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC, 156510037SARM gem5 Developers // DC CVAC and IC IVAU instructions 156610037SARM gem5 Developers // (AArch64 SCTLR_EL1 only) 156710037SARM gem5 Developers Bitfield<25> ee; // Exception Endianness 156810037SARM gem5 Developers Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only) 156910037SARM gem5 Developers Bitfield<24> e0e; // Endianness of explicit data accesses at EL0 157010037SARM gem5 Developers // (AArch64 SCTLR_EL1 only) 157110037SARM gem5 Developers Bitfield<23> xp; // Extended page table enable (dropped in ARMv7) 157210037SARM gem5 Developers Bitfield<22> u; // Alignment (dropped in ARMv7) 157310037SARM gem5 Developers Bitfield<21> fi; // Fast interrupts configuration enable 157410037SARM gem5 Developers // (ARMv7 only) 157510037SARM gem5 Developers Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN 157610037SARM gem5 Developers // (AArch32 only) 157710037SARM gem5 Developers Bitfield<19> dz; // Divide by Zero fault enable 157810037SARM gem5 Developers // (dropped in ARMv7) 157910037SARM gem5 Developers Bitfield<19> wxn; // Write permission implies XN 158010037SARM gem5 Developers Bitfield<18> ntwe; // Not trap WFE 158110037SARM gem5 Developers // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 158210037SARM gem5 Developers Bitfield<18> rao2; // Read as one 158310037SARM gem5 Developers Bitfield<16> ntwi; // Not trap WFI 158410037SARM gem5 Developers // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 158510037SARM gem5 Developers Bitfield<16> rao3; // Read as one 158610037SARM gem5 Developers Bitfield<15> uct; // Enable EL0 access to CTR_EL0 158710037SARM gem5 Developers // (AArch64 SCTLR_EL1 only) 158810037SARM gem5 Developers Bitfield<14> rr; // Round Robin select (ARMv7 only) 158910037SARM gem5 Developers Bitfield<14> dze; // Enable EL0 access to DC ZVA 159010037SARM gem5 Developers // (AArch64 SCTLR_EL1 only) 159110037SARM gem5 Developers Bitfield<13> v; // Vectors bit (AArch32 only) 159210037SARM gem5 Developers Bitfield<12> i; // Instruction cache enable 159310037SARM gem5 Developers Bitfield<11> z; // Branch prediction enable (ARMv7 only) 159410037SARM gem5 Developers Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only) 159510037SARM gem5 Developers Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7) 159610037SARM gem5 Developers Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only) 159710037SARM gem5 Developers Bitfield<8> sed; // SETEND disable 159810037SARM gem5 Developers // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 159910037SARM gem5 Developers Bitfield<7> b; // Endianness support (dropped in ARMv7) 160010037SARM gem5 Developers Bitfield<7> itd; // IT disable 160110037SARM gem5 Developers // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 160210037SARM gem5 Developers Bitfield<6, 3> rao4; // Read as one 160310037SARM gem5 Developers Bitfield<6> thee; // ThumbEE enable 160410037SARM gem5 Developers // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 160510037SARM gem5 Developers Bitfield<5> cp15ben; // CP15 barrier enable 160610037SARM gem5 Developers // (AArch32 and AArch64 SCTLR_EL1 only) 160710037SARM gem5 Developers Bitfield<4> sa0; // Stack Alignment Check Enable for EL0 160810037SARM gem5 Developers // (AArch64 SCTLR_EL1 only) 160910037SARM gem5 Developers Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only) 161010037SARM gem5 Developers Bitfield<2> c; // Cache enable 161110037SARM gem5 Developers Bitfield<1> a; // Alignment check enable 161210037SARM gem5 Developers Bitfield<0> m; // MMU enable 16136735Sgblack@eecs.umich.edu EndBitUnion(SCTLR) 16147320Sgblack@eecs.umich.edu 16157320Sgblack@eecs.umich.edu BitUnion32(CPACR) 16167320Sgblack@eecs.umich.edu Bitfield<1, 0> cp0; 16177320Sgblack@eecs.umich.edu Bitfield<3, 2> cp1; 16187320Sgblack@eecs.umich.edu Bitfield<5, 4> cp2; 16197320Sgblack@eecs.umich.edu Bitfield<7, 6> cp3; 16207320Sgblack@eecs.umich.edu Bitfield<9, 8> cp4; 16217320Sgblack@eecs.umich.edu Bitfield<11, 10> cp5; 16227320Sgblack@eecs.umich.edu Bitfield<13, 12> cp6; 16237320Sgblack@eecs.umich.edu Bitfield<15, 14> cp7; 16247320Sgblack@eecs.umich.edu Bitfield<17, 16> cp8; 16257320Sgblack@eecs.umich.edu Bitfield<19, 18> cp9; 16267320Sgblack@eecs.umich.edu Bitfield<21, 20> cp10; 162710037SARM gem5 Developers Bitfield<21, 20> fpen; // AArch64 16287320Sgblack@eecs.umich.edu Bitfield<23, 22> cp11; 16297320Sgblack@eecs.umich.edu Bitfield<25, 24> cp12; 16307320Sgblack@eecs.umich.edu Bitfield<27, 26> cp13; 16318206SWilliam.Wang@arm.com Bitfield<29, 28> rsvd; 163210037SARM gem5 Developers Bitfield<28> tta; // AArch64 16337320Sgblack@eecs.umich.edu Bitfield<30> d32dis; 16347320Sgblack@eecs.umich.edu Bitfield<31> asedis; 16357320Sgblack@eecs.umich.edu EndBitUnion(CPACR) 16367362Sgblack@eecs.umich.edu 16377362Sgblack@eecs.umich.edu BitUnion32(FSR) 16387362Sgblack@eecs.umich.edu Bitfield<3, 0> fsLow; 163910037SARM gem5 Developers Bitfield<5, 0> status; // LPAE 16407362Sgblack@eecs.umich.edu Bitfield<7, 4> domain; 164110037SARM gem5 Developers Bitfield<9> lpae; 16427362Sgblack@eecs.umich.edu Bitfield<10> fsHigh; 16437362Sgblack@eecs.umich.edu Bitfield<11> wnr; 16447362Sgblack@eecs.umich.edu Bitfield<12> ext; 164510037SARM gem5 Developers Bitfield<13> cm; // LPAE 16467362Sgblack@eecs.umich.edu EndBitUnion(FSR) 16477376Sgblack@eecs.umich.edu 16487376Sgblack@eecs.umich.edu BitUnion32(FPSCR) 16497376Sgblack@eecs.umich.edu Bitfield<0> ioc; 16507376Sgblack@eecs.umich.edu Bitfield<1> dzc; 16517376Sgblack@eecs.umich.edu Bitfield<2> ofc; 16527376Sgblack@eecs.umich.edu Bitfield<3> ufc; 16537376Sgblack@eecs.umich.edu Bitfield<4> ixc; 16547376Sgblack@eecs.umich.edu Bitfield<7> idc; 16557376Sgblack@eecs.umich.edu Bitfield<8> ioe; 16567376Sgblack@eecs.umich.edu Bitfield<9> dze; 16577376Sgblack@eecs.umich.edu Bitfield<10> ofe; 16587376Sgblack@eecs.umich.edu Bitfield<11> ufe; 16597376Sgblack@eecs.umich.edu Bitfield<12> ixe; 16607376Sgblack@eecs.umich.edu Bitfield<15> ide; 16617376Sgblack@eecs.umich.edu Bitfield<18, 16> len; 16627376Sgblack@eecs.umich.edu Bitfield<21, 20> stride; 16637376Sgblack@eecs.umich.edu Bitfield<23, 22> rMode; 16647376Sgblack@eecs.umich.edu Bitfield<24> fz; 16657376Sgblack@eecs.umich.edu Bitfield<25> dn; 16667376Sgblack@eecs.umich.edu Bitfield<26> ahp; 16677376Sgblack@eecs.umich.edu Bitfield<27> qc; 16687376Sgblack@eecs.umich.edu Bitfield<28> v; 16697376Sgblack@eecs.umich.edu Bitfield<29> c; 16707376Sgblack@eecs.umich.edu Bitfield<30> z; 16717376Sgblack@eecs.umich.edu Bitfield<31> n; 16727376Sgblack@eecs.umich.edu EndBitUnion(FPSCR) 16737383Sgblack@eecs.umich.edu 16747643Sgblack@eecs.umich.edu // This mask selects bits of the FPSCR that actually go in the FpCondCodes 16757643Sgblack@eecs.umich.edu // integer register to allow renaming. 16767783SGiacomo.Gabrielli@arm.com static const uint32_t FpCondCodesMask = 0xF0000000; 16777783SGiacomo.Gabrielli@arm.com // This mask selects the cumulative FP exception flags of the FPSCR. 16787783SGiacomo.Gabrielli@arm.com static const uint32_t FpscrExcMask = 0x0000009F; 16797783SGiacomo.Gabrielli@arm.com // This mask selects the cumulative saturation flag of the FPSCR. 16807783SGiacomo.Gabrielli@arm.com static const uint32_t FpscrQcMask = 0x08000000; 16817643Sgblack@eecs.umich.edu 16827640Sgblack@eecs.umich.edu BitUnion32(FPEXC) 16837640Sgblack@eecs.umich.edu Bitfield<31> ex; 16847640Sgblack@eecs.umich.edu Bitfield<30> en; 16857640Sgblack@eecs.umich.edu Bitfield<29, 0> subArchDefined; 16867640Sgblack@eecs.umich.edu EndBitUnion(FPEXC) 16877640Sgblack@eecs.umich.edu 16887383Sgblack@eecs.umich.edu BitUnion32(MVFR0) 16897383Sgblack@eecs.umich.edu Bitfield<3, 0> advSimdRegisters; 16907383Sgblack@eecs.umich.edu Bitfield<7, 4> singlePrecision; 16917383Sgblack@eecs.umich.edu Bitfield<11, 8> doublePrecision; 16927383Sgblack@eecs.umich.edu Bitfield<15, 12> vfpExceptionTrapping; 16937383Sgblack@eecs.umich.edu Bitfield<19, 16> divide; 16947383Sgblack@eecs.umich.edu Bitfield<23, 20> squareRoot; 16957383Sgblack@eecs.umich.edu Bitfield<27, 24> shortVectors; 16967383Sgblack@eecs.umich.edu Bitfield<31, 28> roundingModes; 16977383Sgblack@eecs.umich.edu EndBitUnion(MVFR0) 16987383Sgblack@eecs.umich.edu 16997383Sgblack@eecs.umich.edu BitUnion32(MVFR1) 17007383Sgblack@eecs.umich.edu Bitfield<3, 0> flushToZero; 17017383Sgblack@eecs.umich.edu Bitfield<7, 4> defaultNaN; 17027383Sgblack@eecs.umich.edu Bitfield<11, 8> advSimdLoadStore; 17037383Sgblack@eecs.umich.edu Bitfield<15, 12> advSimdInteger; 17047383Sgblack@eecs.umich.edu Bitfield<19, 16> advSimdSinglePrecision; 17057383Sgblack@eecs.umich.edu Bitfield<23, 20> advSimdHalfPrecision; 17067383Sgblack@eecs.umich.edu Bitfield<27, 24> vfpHalfPrecision; 17077383Sgblack@eecs.umich.edu Bitfield<31, 28> raz; 17087383Sgblack@eecs.umich.edu EndBitUnion(MVFR1) 17097404SAli.Saidi@ARM.com 171010037SARM gem5 Developers BitUnion64(TTBCR) 171110037SARM gem5 Developers // Short-descriptor translation table format 171210037SARM gem5 Developers Bitfield<2, 0> n; 171310037SARM gem5 Developers Bitfield<4> pd0; 171410037SARM gem5 Developers Bitfield<5> pd1; 171510037SARM gem5 Developers // Long-descriptor translation table format 171610037SARM gem5 Developers Bitfield<5, 0> t0sz; 171710037SARM gem5 Developers Bitfield<7> epd0; 171810037SARM gem5 Developers Bitfield<9, 8> irgn0; 171910037SARM gem5 Developers Bitfield<11, 10> orgn0; 172010037SARM gem5 Developers Bitfield<13, 12> sh0; 172110037SARM gem5 Developers Bitfield<14> tg0; 172210037SARM gem5 Developers Bitfield<21, 16> t1sz; 172310037SARM gem5 Developers Bitfield<22> a1; 172410037SARM gem5 Developers Bitfield<23> epd1; 172510037SARM gem5 Developers Bitfield<25, 24> irgn1; 172610037SARM gem5 Developers Bitfield<27, 26> orgn1; 172710037SARM gem5 Developers Bitfield<29, 28> sh1; 172810037SARM gem5 Developers Bitfield<30> tg1; 172910037SARM gem5 Developers Bitfield<34, 32> ips; 173010037SARM gem5 Developers Bitfield<36> as; 173110037SARM gem5 Developers Bitfield<37> tbi0; 173210037SARM gem5 Developers Bitfield<38> tbi1; 173310037SARM gem5 Developers // Common 173410037SARM gem5 Developers Bitfield<31> eae; 173510037SARM gem5 Developers // TCR_EL2/3 (AArch64) 173610037SARM gem5 Developers Bitfield<18, 16> ps; 173710037SARM gem5 Developers Bitfield<20> tbi; 173810037SARM gem5 Developers EndBitUnion(TTBCR) 173910037SARM gem5 Developers 174010324SCurtis.Dunham@arm.com // Fields of TCR_EL{1,2,3} (mostly overlapping) 174110324SCurtis.Dunham@arm.com // TCR_EL1 is natively 64 bits, the others are 32 bits 174210324SCurtis.Dunham@arm.com BitUnion64(TCR) 174310324SCurtis.Dunham@arm.com Bitfield<5, 0> t0sz; 174410324SCurtis.Dunham@arm.com Bitfield<7> epd0; // EL1 174510324SCurtis.Dunham@arm.com Bitfield<9, 8> irgn0; 174610324SCurtis.Dunham@arm.com Bitfield<11, 10> orgn0; 174710324SCurtis.Dunham@arm.com Bitfield<13, 12> sh0; 174810324SCurtis.Dunham@arm.com Bitfield<15, 14> tg0; 174910324SCurtis.Dunham@arm.com Bitfield<18, 16> ps; 175010324SCurtis.Dunham@arm.com Bitfield<20> tbi; // EL2/EL3 175110324SCurtis.Dunham@arm.com Bitfield<21, 16> t1sz; // EL1 175210324SCurtis.Dunham@arm.com Bitfield<22> a1; // EL1 175310324SCurtis.Dunham@arm.com Bitfield<23> epd1; // EL1 175410324SCurtis.Dunham@arm.com Bitfield<25, 24> irgn1; // EL1 175510324SCurtis.Dunham@arm.com Bitfield<27, 26> orgn1; // EL1 175610324SCurtis.Dunham@arm.com Bitfield<29, 28> sh1; // EL1 175710324SCurtis.Dunham@arm.com Bitfield<31, 30> tg1; // EL1 175810324SCurtis.Dunham@arm.com Bitfield<34, 32> ips; // EL1 175910324SCurtis.Dunham@arm.com Bitfield<36> as; // EL1 176010324SCurtis.Dunham@arm.com Bitfield<37> tbi0; // EL1 176110324SCurtis.Dunham@arm.com Bitfield<38> tbi1; // EL1 176210324SCurtis.Dunham@arm.com EndBitUnion(TCR) 176310324SCurtis.Dunham@arm.com 176410037SARM gem5 Developers BitUnion32(HTCR) 176510037SARM gem5 Developers Bitfield<2, 0> t0sz; 176610037SARM gem5 Developers Bitfield<9, 8> irgn0; 176710037SARM gem5 Developers Bitfield<11, 10> orgn0; 176810037SARM gem5 Developers Bitfield<13, 12> sh0; 176910037SARM gem5 Developers EndBitUnion(HTCR) 177010037SARM gem5 Developers 177110037SARM gem5 Developers BitUnion32(VTCR_t) 177210037SARM gem5 Developers Bitfield<3, 0> t0sz; 177310037SARM gem5 Developers Bitfield<4> s; 177411575SDylan.Johnson@ARM.com Bitfield<5, 0> t0sz64; 177510037SARM gem5 Developers Bitfield<7, 6> sl0; 177610037SARM gem5 Developers Bitfield<9, 8> irgn0; 177710037SARM gem5 Developers Bitfield<11, 10> orgn0; 177810037SARM gem5 Developers Bitfield<13, 12> sh0; 177911575SDylan.Johnson@ARM.com Bitfield<15, 14> tg0; 178010037SARM gem5 Developers EndBitUnion(VTCR_t) 178110037SARM gem5 Developers 17827404SAli.Saidi@ARM.com BitUnion32(PRRR) 17837404SAli.Saidi@ARM.com Bitfield<1,0> tr0; 17847404SAli.Saidi@ARM.com Bitfield<3,2> tr1; 17857404SAli.Saidi@ARM.com Bitfield<5,4> tr2; 17867404SAli.Saidi@ARM.com Bitfield<7,6> tr3; 17877404SAli.Saidi@ARM.com Bitfield<9,8> tr4; 17887404SAli.Saidi@ARM.com Bitfield<11,10> tr5; 17897404SAli.Saidi@ARM.com Bitfield<13,12> tr6; 17907404SAli.Saidi@ARM.com Bitfield<15,14> tr7; 17917404SAli.Saidi@ARM.com Bitfield<16> ds0; 17927404SAli.Saidi@ARM.com Bitfield<17> ds1; 17937404SAli.Saidi@ARM.com Bitfield<18> ns0; 17947404SAli.Saidi@ARM.com Bitfield<19> ns1; 17957404SAli.Saidi@ARM.com Bitfield<24> nos0; 17967404SAli.Saidi@ARM.com Bitfield<25> nos1; 17977404SAli.Saidi@ARM.com Bitfield<26> nos2; 17987404SAli.Saidi@ARM.com Bitfield<27> nos3; 17997404SAli.Saidi@ARM.com Bitfield<28> nos4; 18007404SAli.Saidi@ARM.com Bitfield<29> nos5; 18017404SAli.Saidi@ARM.com Bitfield<30> nos6; 18027404SAli.Saidi@ARM.com Bitfield<31> nos7; 18037404SAli.Saidi@ARM.com EndBitUnion(PRRR) 18047404SAli.Saidi@ARM.com 18057404SAli.Saidi@ARM.com BitUnion32(NMRR) 18067404SAli.Saidi@ARM.com Bitfield<1,0> ir0; 18077404SAli.Saidi@ARM.com Bitfield<3,2> ir1; 18087404SAli.Saidi@ARM.com Bitfield<5,4> ir2; 18097404SAli.Saidi@ARM.com Bitfield<7,6> ir3; 18107404SAli.Saidi@ARM.com Bitfield<9,8> ir4; 18117404SAli.Saidi@ARM.com Bitfield<11,10> ir5; 18127404SAli.Saidi@ARM.com Bitfield<13,12> ir6; 18137404SAli.Saidi@ARM.com Bitfield<15,14> ir7; 18147404SAli.Saidi@ARM.com Bitfield<17,16> or0; 18157404SAli.Saidi@ARM.com Bitfield<19,18> or1; 18167404SAli.Saidi@ARM.com Bitfield<21,20> or2; 18177404SAli.Saidi@ARM.com Bitfield<23,22> or3; 18187404SAli.Saidi@ARM.com Bitfield<25,24> or4; 18197404SAli.Saidi@ARM.com Bitfield<27,26> or5; 18207404SAli.Saidi@ARM.com Bitfield<29,28> or6; 18217404SAli.Saidi@ARM.com Bitfield<31,30> or7; 18227404SAli.Saidi@ARM.com EndBitUnion(NMRR) 18237404SAli.Saidi@ARM.com 18248552Sdaniel.johnson@arm.com BitUnion32(CONTEXTIDR) 18258552Sdaniel.johnson@arm.com Bitfield<7,0> asid; 18268552Sdaniel.johnson@arm.com Bitfield<31,8> procid; 18278552Sdaniel.johnson@arm.com EndBitUnion(CONTEXTIDR) 18288552Sdaniel.johnson@arm.com 18298549Sdaniel.johnson@arm.com BitUnion32(L2CTLR) 18308549Sdaniel.johnson@arm.com Bitfield<2,0> sataRAMLatency; 18318549Sdaniel.johnson@arm.com Bitfield<4,3> reserved_4_3; 18328549Sdaniel.johnson@arm.com Bitfield<5> dataRAMSetup; 18338549Sdaniel.johnson@arm.com Bitfield<8,6> tagRAMLatency; 18348549Sdaniel.johnson@arm.com Bitfield<9> tagRAMSetup; 18358549Sdaniel.johnson@arm.com Bitfield<11,10> dataRAMSlice; 18368549Sdaniel.johnson@arm.com Bitfield<12> tagRAMSlice; 18378549Sdaniel.johnson@arm.com Bitfield<20,13> reserved_20_13; 18388549Sdaniel.johnson@arm.com Bitfield<21> eccandParityEnable; 18398549Sdaniel.johnson@arm.com Bitfield<22> reserved_22; 18408549Sdaniel.johnson@arm.com Bitfield<23> interptCtrlPresent; 18418549Sdaniel.johnson@arm.com Bitfield<25,24> numCPUs; 18428549Sdaniel.johnson@arm.com Bitfield<30,26> reserved_30_26; 18438549Sdaniel.johnson@arm.com Bitfield<31> l2rstDISABLE_monitor; 18448549Sdaniel.johnson@arm.com EndBitUnion(L2CTLR) 18458549Sdaniel.johnson@arm.com 18469130Satgutier@umich.edu BitUnion32(CTR) 18479130Satgutier@umich.edu Bitfield<3,0> iCacheLineSize; 18489130Satgutier@umich.edu Bitfield<13,4> raz_13_4; 18499130Satgutier@umich.edu Bitfield<15,14> l1IndexPolicy; 18509130Satgutier@umich.edu Bitfield<19,16> dCacheLineSize; 18519130Satgutier@umich.edu Bitfield<23,20> erg; 18529130Satgutier@umich.edu Bitfield<27,24> cwg; 18539130Satgutier@umich.edu Bitfield<28> raz_28; 18549130Satgutier@umich.edu Bitfield<31,29> format; 18559130Satgutier@umich.edu EndBitUnion(CTR) 185610037SARM gem5 Developers 185710037SARM gem5 Developers BitUnion32(PMSELR) 185810037SARM gem5 Developers Bitfield<4, 0> sel; 185910037SARM gem5 Developers EndBitUnion(PMSELR) 186010037SARM gem5 Developers 186110037SARM gem5 Developers BitUnion64(PAR) 186210037SARM gem5 Developers // 64-bit format 186310037SARM gem5 Developers Bitfield<63, 56> attr; 186410037SARM gem5 Developers Bitfield<39, 12> pa; 186510037SARM gem5 Developers Bitfield<11> lpae; 186610037SARM gem5 Developers Bitfield<9> ns; 186710037SARM gem5 Developers Bitfield<8, 7> sh; 186810037SARM gem5 Developers Bitfield<0> f; 186910037SARM gem5 Developers EndBitUnion(PAR) 187010037SARM gem5 Developers 187110037SARM gem5 Developers BitUnion32(ESR) 187210037SARM gem5 Developers Bitfield<31, 26> ec; 187310037SARM gem5 Developers Bitfield<25> il; 187410037SARM gem5 Developers Bitfield<15, 0> imm16; 187510037SARM gem5 Developers EndBitUnion(ESR) 187610037SARM gem5 Developers 187710037SARM gem5 Developers BitUnion32(CPTR) 187810037SARM gem5 Developers Bitfield<31> tcpac; 187910037SARM gem5 Developers Bitfield<20> tta; 188010037SARM gem5 Developers Bitfield<13, 12> res1_13_12_el2; 188110037SARM gem5 Developers Bitfield<10> tfp; 188210037SARM gem5 Developers Bitfield<9, 0> res1_9_0_el2; 188310037SARM gem5 Developers EndBitUnion(CPTR) 188410037SARM gem5 Developers 188510037SARM gem5 Developers 188611939Snikos.nikoleris@arm.com /** 188711939Snikos.nikoleris@arm.com * Check for permission to read coprocessor registers. 188811939Snikos.nikoleris@arm.com * 188911939Snikos.nikoleris@arm.com * Checks whether an instruction at the current program mode has 189011939Snikos.nikoleris@arm.com * permissions to read the coprocessor registers. This function 189111939Snikos.nikoleris@arm.com * returns whether the check is undefined and if not whether the 189211939Snikos.nikoleris@arm.com * read access is permitted. 189311939Snikos.nikoleris@arm.com * 189411939Snikos.nikoleris@arm.com * @param the misc reg indicating the coprocessor 189511939Snikos.nikoleris@arm.com * @param the SCR 189611939Snikos.nikoleris@arm.com * @param the CPSR 189711939Snikos.nikoleris@arm.com * @return a tuple of booleans: can_read, undefined 189811939Snikos.nikoleris@arm.com */ 189911939Snikos.nikoleris@arm.com std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr, 190011939Snikos.nikoleris@arm.com CPSR cpsr); 190110037SARM gem5 Developers 190211939Snikos.nikoleris@arm.com /** 190311939Snikos.nikoleris@arm.com * Check for permission to write coprocessor registers. 190411939Snikos.nikoleris@arm.com * 190511939Snikos.nikoleris@arm.com * Checks whether an instruction at the current program mode has 190611939Snikos.nikoleris@arm.com * permissions to write the coprocessor registers. This function 190711939Snikos.nikoleris@arm.com * returns whether the check is undefined and if not whether the 190811939Snikos.nikoleris@arm.com * write access is permitted. 190911939Snikos.nikoleris@arm.com * 191011939Snikos.nikoleris@arm.com * @param the misc reg indicating the coprocessor 191111939Snikos.nikoleris@arm.com * @param the SCR 191211939Snikos.nikoleris@arm.com * @param the CPSR 191311939Snikos.nikoleris@arm.com * @return a tuple of booleans: can_write, undefined 191411939Snikos.nikoleris@arm.com */ 191511939Snikos.nikoleris@arm.com std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr, 191611939Snikos.nikoleris@arm.com CPSR cpsr); 191710037SARM gem5 Developers 191810037SARM gem5 Developers // Checks read access permissions to AArch64 system registers 191910037SARM gem5 Developers bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 192010037SARM gem5 Developers ThreadContext *tc); 192110037SARM gem5 Developers 192210037SARM gem5 Developers // Checks write access permissions to AArch64 system registers 192310037SARM gem5 Developers bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 192410037SARM gem5 Developers ThreadContext *tc); 192510037SARM gem5 Developers 192610037SARM gem5 Developers // Uses just the scr.ns bit to pre flatten the misc regs. This is useful 192710037SARM gem5 Developers // for MCR/MRC instructions 192810037SARM gem5 Developers int 192912499Sgiacomo.travaglini@arm.com snsBankedIndex(MiscRegIndex reg, ThreadContext *tc); 193010037SARM gem5 Developers 193110037SARM gem5 Developers // Flattens a misc reg index using the specified security state. This is 193210037SARM gem5 Developers // used for opperations (eg address translations) where the security 193310037SARM gem5 Developers // state of the register access may differ from the current state of the 193410037SARM gem5 Developers // processor 193510037SARM gem5 Developers int 193612499Sgiacomo.travaglini@arm.com snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns); 193710037SARM gem5 Developers 193810037SARM gem5 Developers // Takes a misc reg index and returns the root reg if its one of a set of 193910037SARM gem5 Developers // banked registers 194010037SARM gem5 Developers void 194110037SARM gem5 Developers preUnflattenMiscReg(); 194210037SARM gem5 Developers 194310037SARM gem5 Developers int 194410037SARM gem5 Developers unflattenMiscReg(int reg); 194510037SARM gem5 Developers 19468902Sandreas.hansson@arm.com} 19476242Sgblack@eecs.umich.edu 19486242Sgblack@eecs.umich.edu#endif // __ARCH_ARM_MISCREGS_HH__ 1949