miscregs.cc revision 7351:d90afcb8724e 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/miscregs.hh"
41
42namespace ArmISA
43{
44
45MiscRegIndex
46decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
47{
48    switch (crn) {
49      case 0:
50        switch (opc1) {
51          case 0:
52            switch (crm) {
53              case 0:
54                switch (opc2) {
55                  case 1:
56                    return MISCREG_CTR;
57                  case 2:
58                    return MISCREG_TCMTR;
59                  case 3:
60                    return MISCREG_TLBTR;
61                  case 5:
62                    return MISCREG_MPIDR;
63                  default:
64                    return MISCREG_MIDR;
65                }
66                break;
67              case 1:
68                switch (opc2) {
69                  case 0:
70                    return MISCREG_ID_PFR0;
71                  case 1:
72                    return MISCREG_ID_PFR1;
73                  case 2:
74                    return MISCREG_ID_DFR0;
75                  case 3:
76                    return MISCREG_ID_AFR0;
77                  case 4:
78                    return MISCREG_ID_MMFR0;
79                  case 5:
80                    return MISCREG_ID_MMFR1;
81                  case 6:
82                    return MISCREG_ID_MMFR2;
83                  case 7:
84                    return MISCREG_ID_MMFR3;
85                }
86                break;
87              case 2:
88                switch (opc2) {
89                  case 0:
90                    return MISCREG_ID_ISAR0;
91                  case 1:
92                    return MISCREG_ID_ISAR1;
93                  case 2:
94                    return MISCREG_ID_ISAR2;
95                  case 3:
96                    return MISCREG_ID_ISAR3;
97                  case 4:
98                    return MISCREG_ID_ISAR4;
99                  case 5:
100                    return MISCREG_ID_ISAR5;
101                  case 6:
102                  case 7:
103                    return MISCREG_RAZ; // read as zero
104                }
105                break;
106              default:
107                return MISCREG_RAZ; // read as zero
108            }
109            break;
110          case 1:
111            if (crm == 0) {
112                switch (opc2) {
113                  case 0:
114                    return MISCREG_CCSIDR;
115                  case 1:
116                    return MISCREG_CLIDR;
117                  case 7:
118                    return MISCREG_AIDR;
119                }
120            }
121            break;
122          case 2:
123            if (crm == 0 && opc2 == 0) {
124                return MISCREG_CSSELR;
125            }
126            break;
127        }
128        break;
129      case 1:
130        if (opc1 == 0) {
131            if (crm == 0) {
132                switch (opc2) {
133                  case 0:
134                    return MISCREG_SCTLR;
135                  case 1:
136                    return MISCREG_ACTLR;
137                  case 0x2:
138                    return MISCREG_CPACR;
139                }
140            } else if (crm == 1) {
141                switch (opc2) {
142                  case 0:
143                    return MISCREG_SCR;
144                  case 1:
145                    return MISCREG_SDER;
146                  case 2:
147                    return MISCREG_NSACR;
148                }
149            }
150        }
151        break;
152      case 2:
153        if (opc2 == 0 && crm == 0) {
154            switch (opc2) {
155              case 0:
156                return MISCREG_TTBR0;
157              case 1:
158                return MISCREG_TTBR1;
159              case 2:
160                return MISCREG_TTBCR;
161            }
162        }
163        break;
164      case 3:
165        if (opc1 == 0 && crm == 0 && opc2 == 0) {
166            return MISCREG_DACR;
167        }
168        break;
169      case 5:
170        if (opc1 == 0) {
171            if (crm == 0) {
172                if (opc2 == 0) {
173                    return MISCREG_DFSR;
174                } else if (opc2 == 1) {
175                    return MISCREG_IFSR;
176                }
177            } else if (crm == 1) {
178                if (opc2 == 0) {
179                    return MISCREG_ADFSR;
180                } else if (opc2 == 1) {
181                    return MISCREG_AIFSR;
182                }
183            }
184        }
185        break;
186      case 6:
187        if (opc1 == 0 && crm == 0) {
188            switch (opc2) {
189              case 0:
190                return MISCREG_DFAR;
191              case 2:
192                return MISCREG_IFAR;
193            }
194        }
195        break;
196      case 7:
197        if (opc1 == 0) {
198            switch (crm) {
199              case 0:
200                if (opc2 == 4) {
201                    return MISCREG_NOP;
202                }
203                break;
204              case 1:
205                switch (opc2) {
206                  case 0:
207                    return MISCREG_ICIALLUIS;
208                  case 6:
209                    return MISCREG_BPIALLIS;
210                }
211                break;
212              case 4:
213                if (opc2 == 0) {
214                    return MISCREG_PAR;
215                }
216                break;
217              case 5:
218                switch (opc2) {
219                  case 0:
220                    return MISCREG_ICIALLU;
221                  case 1:
222                    return MISCREG_ICIMVAU;
223                  case 4:
224                    return MISCREG_CP15ISB;
225                  case 6:
226                    return MISCREG_BPIALL;
227                  case 7:
228                    return MISCREG_BPIMVA;
229                }
230                break;
231              case 6:
232                if (opc2 == 1) {
233                    return MISCREG_DCIMVAC;
234                } else if (opc2 == 2) {
235                    return MISCREG_DCISW;
236                }
237                break;
238              case 8:
239                switch (opc2) {
240                  case 0:
241                    return MISCREG_V2PCWPR;
242                  case 1:
243                    return MISCREG_V2PCWPW;
244                  case 2:
245                    return MISCREG_V2PCWUR;
246                  case 3:
247                    return MISCREG_V2PCWUW;
248                  case 4:
249                    return MISCREG_V2POWPR;
250                  case 5:
251                    return MISCREG_V2POWPW;
252                  case 6:
253                    return MISCREG_V2POWUR;
254                  case 7:
255                    return MISCREG_V2POWUW;
256                }
257                break;
258              case 10:
259                switch (opc2) {
260                  case 1:
261                    return MISCREG_DCCMVAC;
262                  case 2:
263                    return MISCREG_MCCSW;
264                  case 4:
265                    return MISCREG_CP15DSB;
266                  case 5:
267                    return MISCREG_CP15DMB;
268                }
269                break;
270              case 11:
271                if (opc2 == 1) {
272                    return MISCREG_DCCMVAU;
273                }
274                break;
275              case 13:
276                if (opc2 == 1) {
277                    return MISCREG_NOP;
278                }
279                break;
280              case 14:
281                if (opc2 == 1) {
282                    return MISCREG_DCCIMVAC;
283                } else if (opc2 == 2) {
284                    return MISCREG_DCCISW;
285                }
286                break;
287            }
288        }
289        break;
290      case 8:
291        if (opc1 == 0) {
292            switch (crm) {
293              case 3:
294                switch (opc2) {
295                  case 0:
296                    return MISCREG_TLBIALLIS;
297                  case 1:
298                    return MISCREG_TLBIMVAIS;
299                  case 2:
300                    return MISCREG_TLBIASIDIS;
301                  case 3:
302                    return MISCREG_TLBIMVAAIS;
303                }
304                break;
305              case 5:
306                switch (opc2) {
307                  case 0:
308                    return MISCREG_ITLBIALL;
309                  case 1:
310                    return MISCREG_ITLBIMVA;
311                  case 2:
312                    return MISCREG_ITLBIASID;
313                }
314                break;
315              case 6:
316                switch (opc2) {
317                  case 0:
318                    return MISCREG_DTLBIALL;
319                  case 1:
320                    return MISCREG_DTLBIMVA;
321                  case 2:
322                    return MISCREG_DTLBIASID;
323                }
324                break;
325              case 7:
326                switch (opc2) {
327                  case 0:
328                    return MISCREG_TLBIALL;
329                  case 1:
330                    return MISCREG_TLBIMVA;
331                  case 2:
332                    return MISCREG_TLBIASID;
333                  case 3:
334                    return MISCREG_TLBIMVAA;
335                }
336                break;
337            }
338        }
339        break;
340      case 9:
341        if (opc1 >= 0 && opc1 <= 7) {
342            switch (crm) {
343              case 0:
344              case 1:
345              case 2:
346              case 5:
347              case 6:
348              case 7:
349              case 8:
350                //Reserved for Branch Predictor, Cache and TCM operations
351              case 12:
352              case 13:
353              case 14:
354              case 15:
355                // Reserved for Performance monitors
356                break;
357            }
358        }
359        break;
360      case 10:
361        if (opc1 == 0) {
362            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
363            if (crm == 2) { // TEX Remap Registers
364                if (opc2 == 0) {
365                    return MISCREG_PRRR;
366                } else if (opc2 == 1) {
367                    return MISCREG_NMRR;
368                }
369            }
370        }
371        break;
372      case 11:
373        if (opc1 >= 0 && opc1 <=7) {
374            switch (crm) {
375              case 0:
376              case 1:
377              case 2:
378              case 3:
379              case 4:
380              case 5:
381              case 6:
382              case 7:
383              case 8:
384              case 15:
385                // Reserved for DMA operations for TCM access
386                break;
387            }
388        }
389        break;
390      case 12:
391        if (opc1 == 0) {
392            if (crm == 0) {
393                if (opc2 == 0) {
394                    return MISCREG_VBAR;
395                } else if (opc2 == 1) {
396                    return MISCREG_MVBAR;
397                }
398            } else if (crm == 1) {
399                if (opc2 == 0) {
400                    return MISCREG_ISR;
401                }
402            }
403        }
404        break;
405      case 13:
406        if (opc1 == 0) {
407            if (crm == 0) {
408                switch (crm) {
409                  case 0:
410                    return MISCREG_FCEIDR;
411                  case 1:
412                    return MISCREG_CONTEXTIDR;
413                  case 2:
414                    return MISCREG_TPIDRURW;
415                  case 3:
416                    return MISCREG_TPIDRURO;
417                  case 4:
418                    return MISCREG_TPIDRPRW;
419                }
420            }
421        }
422        break;
423      case 15:
424        // Implementation defined
425        break;
426    }
427    // Unrecognized register
428    return NUM_MISCREGS;
429}
430
431};
432