miscregs.cc revision 7259:200840489735
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include "arch/arm/miscregs.hh" 41 42namespace ArmISA 43{ 44 45MiscRegIndex 46decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 47{ 48 switch (crn) { 49 case 0: 50 switch (opc1) { 51 case 0: 52 switch (crm) { 53 case 0: 54 switch (opc2) { 55 case 1: 56 return MISCREG_CTR; 57 case 2: 58 return MISCREG_TCMTR; 59 case 4: 60 return MISCREG_MPUIR; 61 case 5: 62 return MISCREG_MPIDR; 63 default: 64 return MISCREG_MIDR; 65 } 66 break; 67 case 1: 68 switch (opc2) { 69 case 0: 70 return MISCREG_ID_PFR0; 71 case 1: 72 return MISCREG_ID_PFR1; 73 case 2: 74 return MISCREG_ID_DFR0; 75 case 3: 76 return MISCREG_ID_AFR0; 77 case 4: 78 return MISCREG_ID_MMFR0; 79 case 5: 80 return MISCREG_ID_MMFR1; 81 case 6: 82 return MISCREG_ID_MMFR2; 83 case 7: 84 return MISCREG_ID_MMFR3; 85 } 86 break; 87 case 2: 88 switch (opc2) { 89 case 0: 90 return MISCREG_ID_ISAR0; 91 case 1: 92 return MISCREG_ID_ISAR1; 93 case 2: 94 return MISCREG_ID_ISAR2; 95 case 3: 96 return MISCREG_ID_ISAR3; 97 case 4: 98 return MISCREG_ID_ISAR4; 99 case 5: 100 return MISCREG_ID_ISAR5; 101 case 6: 102 case 7: 103 return MISCREG_RAZ; // read as zero 104 } 105 break; 106 default: 107 return MISCREG_RAZ; // read as zero 108 } 109 break; 110 case 1: 111 if (crm == 0) { 112 switch (opc2) { 113 case 0: 114 return MISCREG_CCSIDR; 115 case 1: 116 return MISCREG_CLIDR; 117 case 7: 118 return MISCREG_AIDR; 119 } 120 } 121 break; 122 case 2: 123 if (crm == 0 && opc2 == 0) { 124 return MISCREG_CSSELR; 125 } 126 break; 127 } 128 break; 129 case 1: 130 if (opc1 == 0 && crm == 0) { 131 switch (opc2) { 132 case 0: 133 return MISCREG_SCTLR; 134 case 1: 135 return MISCREG_ACTLR; 136 case 0x2: 137 return MISCREG_CPACR; 138 } 139 } 140 break; 141 case 5: 142 if (opc1 == 0) { 143 if (crm == 0) { 144 if (opc2 == 0) { 145 return MISCREG_DFSR; 146 } else if (opc2 == 1) { 147 return MISCREG_IFSR; 148 } 149 } else if (crm == 1) { 150 if (opc2 == 0) { 151 return MISCREG_ADFSR; 152 } else if (opc2 == 1) { 153 return MISCREG_AIFSR; 154 } 155 } 156 } 157 break; 158 case 6: 159 if (opc1 == 0) { 160 switch (crm) { 161 case 0: 162 switch (opc2) { 163 case 0: 164 return MISCREG_DFAR; 165 case 2: 166 return MISCREG_IFAR; 167 } 168 break; 169 case 1: 170 switch (opc2) { 171 case 0: 172 return MISCREG_DRBAR; 173 case 1: 174 return MISCREG_IRBAR; 175 case 2: 176 return MISCREG_DRSR; 177 case 3: 178 return MISCREG_IRSR; 179 case 4: 180 return MISCREG_DRACR; 181 case 5: 182 return MISCREG_IRACR; 183 } 184 break; 185 case 2: 186 if (opc2 == 0) { 187 return MISCREG_RGNR; 188 } 189 } 190 } 191 break; 192 case 7: 193 if (opc1 == 0) { 194 switch (crm) { 195 case 0: 196 if (opc2 == 4) { 197 return MISCREG_NOP; 198 } 199 break; 200 case 1: 201 switch (opc2) { 202 case 0: 203 return MISCREG_ICIALLUIS; 204 case 6: 205 return MISCREG_BPIALLIS; 206 } 207 break; 208 case 5: 209 switch (opc2) { 210 case 0: 211 return MISCREG_ICIALLU; 212 case 1: 213 return MISCREG_ICIMVAU; 214 case 4: 215 return MISCREG_CP15ISB; 216 case 6: 217 return MISCREG_BPIALL; 218 case 7: 219 return MISCREG_BPIMVA; 220 } 221 break; 222 case 6: 223 if (opc2 == 1) { 224 return MISCREG_DCIMVAC; 225 } else if (opc2 == 2) { 226 return MISCREG_DCISW; 227 } 228 break; 229 case 10: 230 switch (opc2) { 231 case 1: 232 return MISCREG_DCCMVAC; 233 case 2: 234 return MISCREG_MCCSW; 235 case 4: 236 return MISCREG_CP15DSB; 237 case 5: 238 return MISCREG_CP15DMB; 239 } 240 break; 241 case 11: 242 if (opc2 == 1) { 243 return MISCREG_DCCMVAU; 244 } 245 break; 246 case 13: 247 if (opc2 == 1) { 248 return MISCREG_NOP; 249 } 250 break; 251 case 14: 252 if (opc2 == 1) { 253 return MISCREG_DCCIMVAC; 254 } else if (opc2 == 2) { 255 return MISCREG_DCCISW; 256 } 257 break; 258 } 259 } 260 break; 261 case 9: 262 if (opc1 >= 0 && opc1 <= 7) { 263 switch (crm) { 264 case 0: 265 case 1: 266 case 2: 267 case 5: 268 case 6: 269 case 7: 270 case 8: 271 //Reserved for Branch Predictor, Cache and TCM operations 272 case 12: 273 case 13: 274 case 14: 275 case 15: 276 // Reserved for Performance monitors 277 break; 278 } 279 } 280 break; 281 case 11: 282 if (opc1 >= 0 && opc1 <=7) { 283 switch (crm) { 284 case 0: 285 case 1: 286 case 2: 287 case 3: 288 case 4: 289 case 5: 290 case 6: 291 case 7: 292 case 8: 293 case 15: 294 // Reserved for DMA operations for TCM access 295 break; 296 } 297 } 298 break; 299 case 13: 300 if (opc1 == 0) { 301 if (crm == 0) { 302 switch (crm) { 303 case 1: 304 return MISCREG_CONTEXTIDR; 305 case 2: 306 return MISCREG_TPIDRURW; 307 case 3: 308 return MISCREG_TPIDRURO; 309 case 4: 310 return MISCREG_TPIDRPRW; 311 } 312 } 313 } 314 break; 315 case 15: 316 // Implementation defined 317 break; 318 } 319 // Unrecognized register 320 return NUM_MISCREGS; 321} 322 323}; 324