miscregs.cc revision 14229 
1/*
2 * Copyright (c) 2010-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 *          Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57    switch(crn) {
58      case 0:
59        switch (opc1) {
60          case 0:
61            switch (opc2) {
62              case 0:
63                switch (crm) {
64                  case 0:
65                    return MISCREG_DBGDIDR;
66                  case 1:
67                    return MISCREG_DBGDSCRint;
68                }
69                break;
70            }
71            break;
72          case 7:
73            switch (opc2) {
74              case 0:
75                switch (crm) {
76                  case 0:
77                    return MISCREG_JIDR;
78                }
79              break;
80            }
81            break;
82        }
83        break;
84      case 1:
85        switch (opc1) {
86          case 6:
87            switch (crm) {
88              case 0:
89                switch (opc2) {
90                  case 0:
91                    return MISCREG_TEEHBR;
92                }
93                break;
94            }
95            break;
96          case 7:
97            switch (crm) {
98              case 0:
99                switch (opc2) {
100                  case 0:
101                    return MISCREG_JOSCR;
102                }
103                break;
104            }
105            break;
106        }
107        break;
108      case 2:
109        switch (opc1) {
110          case 7:
111            switch (crm) {
112              case 0:
113                switch (opc2) {
114                  case 0:
115                    return MISCREG_JMCR;
116                }
117                break;
118            }
119            break;
120        }
121        break;
122    }
123    // If we get here then it must be a register that we haven't implemented
124    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125         crn, opc1, crm, opc2);
126    return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134    switch (crn) {
135      case 0:
136        switch (opc1) {
137          case 0:
138            switch (crm) {
139              case 0:
140                switch (opc2) {
141                  case 1:
142                    return MISCREG_CTR;
143                  case 2:
144                    return MISCREG_TCMTR;
145                  case 3:
146                    return MISCREG_TLBTR;
147                  case 5:
148                    return MISCREG_MPIDR;
149                  case 6:
150                    return MISCREG_REVIDR;
151                  default:
152                    return MISCREG_MIDR;
153                }
154                break;
155              case 1:
156                switch (opc2) {
157                  case 0:
158                    return MISCREG_ID_PFR0;
159                  case 1:
160                    return MISCREG_ID_PFR1;
161                  case 2:
162                    return MISCREG_ID_DFR0;
163                  case 3:
164                    return MISCREG_ID_AFR0;
165                  case 4:
166                    return MISCREG_ID_MMFR0;
167                  case 5:
168                    return MISCREG_ID_MMFR1;
169                  case 6:
170                    return MISCREG_ID_MMFR2;
171                  case 7:
172                    return MISCREG_ID_MMFR3;
173                }
174                break;
175              case 2:
176                switch (opc2) {
177                  case 0:
178                    return MISCREG_ID_ISAR0;
179                  case 1:
180                    return MISCREG_ID_ISAR1;
181                  case 2:
182                    return MISCREG_ID_ISAR2;
183                  case 3:
184                    return MISCREG_ID_ISAR3;
185                  case 4:
186                    return MISCREG_ID_ISAR4;
187                  case 5:
188                    return MISCREG_ID_ISAR5;
189                  case 6:
190                  case 7:
191                    return MISCREG_RAZ; // read as zero
192                }
193                break;
194              default:
195                return MISCREG_RAZ; // read as zero
196            }
197            break;
198          case 1:
199            if (crm == 0) {
200                switch (opc2) {
201                  case 0:
202                    return MISCREG_CCSIDR;
203                  case 1:
204                    return MISCREG_CLIDR;
205                  case 7:
206                    return MISCREG_AIDR;
207                }
208            }
209            break;
210          case 2:
211            if (crm == 0 && opc2 == 0) {
212                return MISCREG_CSSELR;
213            }
214            break;
215          case 4:
216            if (crm == 0) {
217                if (opc2 == 0)
218                    return MISCREG_VPIDR;
219                else if (opc2 == 5)
220                    return MISCREG_VMPIDR;
221            }
222            break;
223        }
224        break;
225      case 1:
226        if (opc1 == 0) {
227            if (crm == 0) {
228                switch (opc2) {
229                  case 0:
230                    return MISCREG_SCTLR;
231                  case 1:
232                    return MISCREG_ACTLR;
233                  case 0x2:
234                    return MISCREG_CPACR;
235                }
236            } else if (crm == 1) {
237                switch (opc2) {
238                  case 0:
239                    return MISCREG_SCR;
240                  case 1:
241                    return MISCREG_SDER;
242                  case 2:
243                    return MISCREG_NSACR;
244                }
245            }
246        } else if (opc1 == 4) {
247            if (crm == 0) {
248                if (opc2 == 0)
249                    return MISCREG_HSCTLR;
250                else if (opc2 == 1)
251                    return MISCREG_HACTLR;
252            } else if (crm == 1) {
253                switch (opc2) {
254                  case 0:
255                    return MISCREG_HCR;
256                  case 1:
257                    return MISCREG_HDCR;
258                  case 2:
259                    return MISCREG_HCPTR;
260                  case 3:
261                    return MISCREG_HSTR;
262                  case 7:
263                    return MISCREG_HACR;
264                }
265            }
266        }
267        break;
268      case 2:
269        if (opc1 == 0 && crm == 0) {
270            switch (opc2) {
271              case 0:
272                return MISCREG_TTBR0;
273              case 1:
274                return MISCREG_TTBR1;
275              case 2:
276                return MISCREG_TTBCR;
277            }
278        } else if (opc1 == 4) {
279            if (crm == 0 && opc2 == 2)
280                return MISCREG_HTCR;
281            else if (crm == 1 && opc2 == 2)
282                return MISCREG_VTCR;
283        }
284        break;
285      case 3:
286        if (opc1 == 0 && crm == 0 && opc2 == 0) {
287            return MISCREG_DACR;
288        }
289        break;
290      case 4:
291        if (opc1 == 0 && crm == 6 && opc2 == 0) {
292            return MISCREG_ICC_PMR;
293        }
294        break;
295      case 5:
296        if (opc1 == 0) {
297            if (crm == 0) {
298                if (opc2 == 0) {
299                    return MISCREG_DFSR;
300                } else if (opc2 == 1) {
301                    return MISCREG_IFSR;
302                }
303            } else if (crm == 1) {
304                if (opc2 == 0) {
305                    return MISCREG_ADFSR;
306                } else if (opc2 == 1) {
307                    return MISCREG_AIFSR;
308                }
309            }
310        } else if (opc1 == 4) {
311            if (crm == 1) {
312                if (opc2 == 0)
313                    return MISCREG_HADFSR;
314                else if (opc2 == 1)
315                    return MISCREG_HAIFSR;
316            } else if (crm == 2 && opc2 == 0) {
317                return MISCREG_HSR;
318            }
319        }
320        break;
321      case 6:
322        if (opc1 == 0 && crm == 0) {
323            switch (opc2) {
324              case 0:
325                return MISCREG_DFAR;
326              case 2:
327                return MISCREG_IFAR;
328            }
329        } else if (opc1 == 4 && crm == 0) {
330            switch (opc2) {
331              case 0:
332                return MISCREG_HDFAR;
333              case 2:
334                return MISCREG_HIFAR;
335              case 4:
336                return MISCREG_HPFAR;
337            }
338        }
339        break;
340      case 7:
341        if (opc1 == 0) {
342            switch (crm) {
343              case 0:
344                if (opc2 == 4) {
345                    return MISCREG_NOP;
346                }
347                break;
348              case 1:
349                switch (opc2) {
350                  case 0:
351                    return MISCREG_ICIALLUIS;
352                  case 6:
353                    return MISCREG_BPIALLIS;
354                }
355                break;
356              case 4:
357                if (opc2 == 0) {
358                    return MISCREG_PAR;
359                }
360                break;
361              case 5:
362                switch (opc2) {
363                  case 0:
364                    return MISCREG_ICIALLU;
365                  case 1:
366                    return MISCREG_ICIMVAU;
367                  case 4:
368                    return MISCREG_CP15ISB;
369                  case 6:
370                    return MISCREG_BPIALL;
371                  case 7:
372                    return MISCREG_BPIMVA;
373                }
374                break;
375              case 6:
376                if (opc2 == 1) {
377                    return MISCREG_DCIMVAC;
378                } else if (opc2 == 2) {
379                    return MISCREG_DCISW;
380                }
381                break;
382              case 8:
383                switch (opc2) {
384                  case 0:
385                    return MISCREG_ATS1CPR;
386                  case 1:
387                    return MISCREG_ATS1CPW;
388                  case 2:
389                    return MISCREG_ATS1CUR;
390                  case 3:
391                    return MISCREG_ATS1CUW;
392                  case 4:
393                    return MISCREG_ATS12NSOPR;
394                  case 5:
395                    return MISCREG_ATS12NSOPW;
396                  case 6:
397                    return MISCREG_ATS12NSOUR;
398                  case 7:
399                    return MISCREG_ATS12NSOUW;
400                }
401                break;
402              case 10:
403                switch (opc2) {
404                  case 1:
405                    return MISCREG_DCCMVAC;
406                  case 2:
407                    return MISCREG_DCCSW;
408                  case 4:
409                    return MISCREG_CP15DSB;
410                  case 5:
411                    return MISCREG_CP15DMB;
412                }
413                break;
414              case 11:
415                if (opc2 == 1) {
416                    return MISCREG_DCCMVAU;
417                }
418                break;
419              case 13:
420                if (opc2 == 1) {
421                    return MISCREG_NOP;
422                }
423                break;
424              case 14:
425                if (opc2 == 1) {
426                    return MISCREG_DCCIMVAC;
427                } else if (opc2 == 2) {
428                    return MISCREG_DCCISW;
429                }
430                break;
431            }
432        } else if (opc1 == 4 && crm == 8) {
433            if (opc2 == 0)
434                return MISCREG_ATS1HR;
435            else if (opc2 == 1)
436                return MISCREG_ATS1HW;
437        }
438        break;
439      case 8:
440        if (opc1 == 0) {
441            switch (crm) {
442              case 3:
443                switch (opc2) {
444                  case 0:
445                    return MISCREG_TLBIALLIS;
446                  case 1:
447                    return MISCREG_TLBIMVAIS;
448                  case 2:
449                    return MISCREG_TLBIASIDIS;
450                  case 3:
451                    return MISCREG_TLBIMVAAIS;
452                  case 5:
453                    return MISCREG_TLBIMVALIS;
454                  case 7:
455                    return MISCREG_TLBIMVAALIS;
456                }
457                break;
458              case 5:
459                switch (opc2) {
460                  case 0:
461                    return MISCREG_ITLBIALL;
462                  case 1:
463                    return MISCREG_ITLBIMVA;
464                  case 2:
465                    return MISCREG_ITLBIASID;
466                }
467                break;
468              case 6:
469                switch (opc2) {
470                  case 0:
471                    return MISCREG_DTLBIALL;
472                  case 1:
473                    return MISCREG_DTLBIMVA;
474                  case 2:
475                    return MISCREG_DTLBIASID;
476                }
477                break;
478              case 7:
479                switch (opc2) {
480                  case 0:
481                    return MISCREG_TLBIALL;
482                  case 1:
483                    return MISCREG_TLBIMVA;
484                  case 2:
485                    return MISCREG_TLBIASID;
486                  case 3:
487                    return MISCREG_TLBIMVAA;
488                  case 5:
489                    return MISCREG_TLBIMVAL;
490                  case 7:
491                    return MISCREG_TLBIMVAAL;
492                }
493                break;
494            }
495        } else if (opc1 == 4) {
496            if (crm == 0) {
497                switch (opc2) {
498                  case 1:
499                    return MISCREG_TLBIIPAS2IS;
500                  case 5:
501                    return MISCREG_TLBIIPAS2LIS;
502                }
503            } else if (crm == 3) {
504                switch (opc2) {
505                  case 0:
506                    return MISCREG_TLBIALLHIS;
507                  case 1:
508                    return MISCREG_TLBIMVAHIS;
509                  case 4:
510                    return MISCREG_TLBIALLNSNHIS;
511                  case 5:
512                    return MISCREG_TLBIMVALHIS;
513                }
514            } else if (crm == 4) {
515                switch (opc2) {
516                  case 1:
517                    return MISCREG_TLBIIPAS2;
518                  case 5:
519                    return MISCREG_TLBIIPAS2L;
520                }
521            } else if (crm == 7) {
522                switch (opc2) {
523                  case 0:
524                    return MISCREG_TLBIALLH;
525                  case 1:
526                    return MISCREG_TLBIMVAH;
527                  case 4:
528                    return MISCREG_TLBIALLNSNH;
529                  case 5:
530                    return MISCREG_TLBIMVALH;
531                }
532            }
533        }
534        break;
535      case 9:
536        // Every cop register with CRn = 9 and CRm in
537        // {0-2}, {5-8} is implementation defined regardless
538        // of opc1 and opc2.
539        switch (crm) {
540          case 0:
541          case 1:
542          case 2:
543          case 5:
544          case 6:
545          case 7:
546          case 8:
547            return MISCREG_IMPDEF_UNIMPL;
548        }
549        if (opc1 == 0) {
550            switch (crm) {
551              case 12:
552                switch (opc2) {
553                  case 0:
554                    return MISCREG_PMCR;
555                  case 1:
556                    return MISCREG_PMCNTENSET;
557                  case 2:
558                    return MISCREG_PMCNTENCLR;
559                  case 3:
560                    return MISCREG_PMOVSR;
561                  case 4:
562                    return MISCREG_PMSWINC;
563                  case 5:
564                    return MISCREG_PMSELR;
565                  case 6:
566                    return MISCREG_PMCEID0;
567                  case 7:
568                    return MISCREG_PMCEID1;
569                }
570                break;
571              case 13:
572                switch (opc2) {
573                  case 0:
574                    return MISCREG_PMCCNTR;
575                  case 1:
576                    // Selector is PMSELR.SEL
577                    return MISCREG_PMXEVTYPER_PMCCFILTR;
578                  case 2:
579                    return MISCREG_PMXEVCNTR;
580                }
581                break;
582              case 14:
583                switch (opc2) {
584                  case 0:
585                    return MISCREG_PMUSERENR;
586                  case 1:
587                    return MISCREG_PMINTENSET;
588                  case 2:
589                    return MISCREG_PMINTENCLR;
590                  case 3:
591                    return MISCREG_PMOVSSET;
592                }
593                break;
594            }
595        } else if (opc1 == 1) {
596            switch (crm) {
597              case 0:
598                switch (opc2) {
599                  case 2: // L2CTLR, L2 Control Register
600                    return MISCREG_L2CTLR;
601                  case 3:
602                    return MISCREG_L2ECTLR;
603                }
604                break;
605                break;
606            }
607        }
608        break;
609      case 10:
610        if (opc1 == 0) {
611            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
612            if (crm < 2) {
613                return MISCREG_IMPDEF_UNIMPL;
614            } else if (crm == 2) { // TEX Remap Registers
615                if (opc2 == 0) {
616                    // Selector is TTBCR.EAE
617                    return MISCREG_PRRR_MAIR0;
618                } else if (opc2 == 1) {
619                    // Selector is TTBCR.EAE
620                    return MISCREG_NMRR_MAIR1;
621                }
622            } else if (crm == 3) {
623                if (opc2 == 0) {
624                    return MISCREG_AMAIR0;
625                } else if (opc2 == 1) {
626                    return MISCREG_AMAIR1;
627                }
628            }
629        } else if (opc1 == 4) {
630            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
631            if (crm == 2) {
632                if (opc2 == 0)
633                    return MISCREG_HMAIR0;
634                else if (opc2 == 1)
635                    return MISCREG_HMAIR1;
636            } else if (crm == 3) {
637                if (opc2 == 0)
638                    return MISCREG_HAMAIR0;
639                else if (opc2 == 1)
640                    return MISCREG_HAMAIR1;
641            }
642        }
643        break;
644      case 11:
645        if (opc1 <=7) {
646            switch (crm) {
647              case 0:
648              case 1:
649              case 2:
650              case 3:
651              case 4:
652              case 5:
653              case 6:
654              case 7:
655              case 8:
656              case 15:
657                // Reserved for DMA operations for TCM access
658                return MISCREG_IMPDEF_UNIMPL;
659              default:
660                break;
661            }
662        }
663        break;
664      case 12:
665        if (opc1 == 0) {
666            if (crm == 0) {
667                if (opc2 == 0) {
668                    return MISCREG_VBAR;
669                } else if (opc2 == 1) {
670                    return MISCREG_MVBAR;
671                }
672            } else if (crm == 1) {
673                if (opc2 == 0) {
674                    return MISCREG_ISR;
675                }
676            } else if (crm == 8) {
677                switch (opc2) {
678                    case 0:
679                        return MISCREG_ICC_IAR0;
680                    case 1:
681                        return MISCREG_ICC_EOIR0;
682                    case 2:
683                        return MISCREG_ICC_HPPIR0;
684                    case 3:
685                        return MISCREG_ICC_BPR0;
686                    case 4:
687                        return MISCREG_ICC_AP0R0;
688                    case 5:
689                        return MISCREG_ICC_AP0R1;
690                    case 6:
691                        return MISCREG_ICC_AP0R2;
692                    case 7:
693                        return MISCREG_ICC_AP0R3;
694                }
695            } else if (crm == 9) {
696                switch (opc2) {
697                    case 0:
698                        return MISCREG_ICC_AP1R0;
699                    case 1:
700                        return MISCREG_ICC_AP1R1;
701                    case 2:
702                        return MISCREG_ICC_AP1R2;
703                    case 3:
704                        return MISCREG_ICC_AP1R3;
705                }
706            } else if (crm == 11) {
707                switch (opc2) {
708                    case 1:
709                        return MISCREG_ICC_DIR;
710                    case 3:
711                        return MISCREG_ICC_RPR;
712                }
713            } else if (crm == 12) {
714                switch (opc2) {
715                    case 0:
716                        return MISCREG_ICC_IAR1;
717                    case 1:
718                        return MISCREG_ICC_EOIR1;
719                    case 2:
720                        return MISCREG_ICC_HPPIR1;
721                    case 3:
722                        return MISCREG_ICC_BPR1;
723                    case 4:
724                        return MISCREG_ICC_CTLR;
725                    case 5:
726                        return MISCREG_ICC_SRE;
727                    case 6:
728                        return MISCREG_ICC_IGRPEN0;
729                    case 7:
730                        return MISCREG_ICC_IGRPEN1;
731                }
732            }
733        } else if (opc1 == 4) {
734            if (crm == 0 && opc2 == 0) {
735                return MISCREG_HVBAR;
736            } else if (crm == 8) {
737                switch (opc2) {
738                    case 0:
739                        return MISCREG_ICH_AP0R0;
740                    case 1:
741                        return MISCREG_ICH_AP0R1;
742                    case 2:
743                        return MISCREG_ICH_AP0R2;
744                    case 3:
745                        return MISCREG_ICH_AP0R3;
746                }
747            } else if (crm == 9) {
748                switch (opc2) {
749                    case 0:
750                        return MISCREG_ICH_AP1R0;
751                    case 1:
752                        return MISCREG_ICH_AP1R1;
753                    case 2:
754                        return MISCREG_ICH_AP1R2;
755                    case 3:
756                        return MISCREG_ICH_AP1R3;
757                    case 5:
758                        return MISCREG_ICC_HSRE;
759                }
760            } else if (crm == 11) {
761                switch (opc2) {
762                    case 0:
763                        return MISCREG_ICH_HCR;
764                    case 1:
765                        return MISCREG_ICH_VTR;
766                    case 2:
767                        return MISCREG_ICH_MISR;
768                    case 3:
769                        return MISCREG_ICH_EISR;
770                    case 5:
771                        return MISCREG_ICH_ELRSR;
772                    case 7:
773                        return MISCREG_ICH_VMCR;
774                }
775            } else if (crm == 12) {
776                switch (opc2) {
777                    case 0:
778                        return MISCREG_ICH_LR0;
779                    case 1:
780                        return MISCREG_ICH_LR1;
781                    case 2:
782                        return MISCREG_ICH_LR2;
783                    case 3:
784                        return MISCREG_ICH_LR3;
785                    case 4:
786                        return MISCREG_ICH_LR4;
787                    case 5:
788                        return MISCREG_ICH_LR5;
789                    case 6:
790                        return MISCREG_ICH_LR6;
791                    case 7:
792                        return MISCREG_ICH_LR7;
793                }
794            } else if (crm == 13) {
795                switch (opc2) {
796                    case 0:
797                        return MISCREG_ICH_LR8;
798                    case 1:
799                        return MISCREG_ICH_LR9;
800                    case 2:
801                        return MISCREG_ICH_LR10;
802                    case 3:
803                        return MISCREG_ICH_LR11;
804                    case 4:
805                        return MISCREG_ICH_LR12;
806                    case 5:
807                        return MISCREG_ICH_LR13;
808                    case 6:
809                        return MISCREG_ICH_LR14;
810                    case 7:
811                        return MISCREG_ICH_LR15;
812                }
813            } else if (crm == 14) {
814                switch (opc2) {
815                    case 0:
816                        return MISCREG_ICH_LRC0;
817                    case 1:
818                        return MISCREG_ICH_LRC1;
819                    case 2:
820                        return MISCREG_ICH_LRC2;
821                    case 3:
822                        return MISCREG_ICH_LRC3;
823                    case 4:
824                        return MISCREG_ICH_LRC4;
825                    case 5:
826                        return MISCREG_ICH_LRC5;
827                    case 6:
828                        return MISCREG_ICH_LRC6;
829                    case 7:
830                        return MISCREG_ICH_LRC7;
831                }
832            } else if (crm == 15) {
833                switch (opc2) {
834                    case 0:
835                        return MISCREG_ICH_LRC8;
836                    case 1:
837                        return MISCREG_ICH_LRC9;
838                    case 2:
839                        return MISCREG_ICH_LRC10;
840                    case 3:
841                        return MISCREG_ICH_LRC11;
842                    case 4:
843                        return MISCREG_ICH_LRC12;
844                    case 5:
845                        return MISCREG_ICH_LRC13;
846                    case 6:
847                        return MISCREG_ICH_LRC14;
848                    case 7:
849                        return MISCREG_ICH_LRC15;
850                }
851            }
852        } else if (opc1 == 6) {
853            if (crm == 12) {
854                switch (opc2) {
855                    case 4:
856                        return MISCREG_ICC_MCTLR;
857                    case 5:
858                        return MISCREG_ICC_MSRE;
859                    case 7:
860                        return MISCREG_ICC_MGRPEN1;
861                }
862            }
863        }
864        break;
865      case 13:
866        if (opc1 == 0) {
867            if (crm == 0) {
868                switch (opc2) {
869                  case 0:
870                    return MISCREG_FCSEIDR;
871                  case 1:
872                    return MISCREG_CONTEXTIDR;
873                  case 2:
874                    return MISCREG_TPIDRURW;
875                  case 3:
876                    return MISCREG_TPIDRURO;
877                  case 4:
878                    return MISCREG_TPIDRPRW;
879                }
880            }
881        } else if (opc1 == 4) {
882            if (crm == 0 && opc2 == 2)
883                return MISCREG_HTPIDR;
884        }
885        break;
886      case 14:
887        if (opc1 == 0) {
888            switch (crm) {
889              case 0:
890                if (opc2 == 0)
891                    return MISCREG_CNTFRQ;
892                break;
893              case 1:
894                if (opc2 == 0)
895                    return MISCREG_CNTKCTL;
896                break;
897              case 2:
898                if (opc2 == 0)
899                    return MISCREG_CNTP_TVAL;
900                else if (opc2 == 1)
901                    return MISCREG_CNTP_CTL;
902                break;
903              case 3:
904                if (opc2 == 0)
905                    return MISCREG_CNTV_TVAL;
906                else if (opc2 == 1)
907                    return MISCREG_CNTV_CTL;
908                break;
909            }
910        } else if (opc1 == 4) {
911            if (crm == 1 && opc2 == 0) {
912                return MISCREG_CNTHCTL;
913            } else if (crm == 2) {
914                if (opc2 == 0)
915                    return MISCREG_CNTHP_TVAL;
916                else if (opc2 == 1)
917                    return MISCREG_CNTHP_CTL;
918            }
919        }
920        break;
921      case 15:
922        // Implementation defined
923        return MISCREG_IMPDEF_UNIMPL;
924    }
925    // Unrecognized register
926    return MISCREG_CP15_UNIMPL;
927}
928
929MiscRegIndex
930decodeCP15Reg64(unsigned crm, unsigned opc1)
931{
932    switch (crm) {
933      case 2:
934        switch (opc1) {
935          case 0:
936            return MISCREG_TTBR0;
937          case 1:
938            return MISCREG_TTBR1;
939          case 4:
940            return MISCREG_HTTBR;
941          case 6:
942            return MISCREG_VTTBR;
943        }
944        break;
945      case 7:
946        if (opc1 == 0)
947            return MISCREG_PAR;
948        break;
949      case 14:
950        switch (opc1) {
951          case 0:
952            return MISCREG_CNTPCT;
953          case 1:
954            return MISCREG_CNTVCT;
955          case 2:
956            return MISCREG_CNTP_CVAL;
957          case 3:
958            return MISCREG_CNTV_CVAL;
959          case 4:
960            return MISCREG_CNTVOFF;
961          case 6:
962            return MISCREG_CNTHP_CVAL;
963        }
964        break;
965      case 12:
966        switch (opc1) {
967          case 0:
968            return MISCREG_ICC_SGI1R;
969          case 1:
970            return MISCREG_ICC_ASGI1R;
971          case 2:
972            return MISCREG_ICC_SGI0R;
973          default:
974            break;
975        }
976        break;
977      case 15:
978        if (opc1 == 0)
979            return MISCREG_CPUMERRSR;
980        else if (opc1 == 1)
981            return MISCREG_L2MERRSR;
982        break;
983    }
984    // Unrecognized register
985    return MISCREG_CP15_UNIMPL;
986}
987
988std::tuple<bool, bool>
989canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
990{
991    bool secure = !scr.ns;
992    bool canRead = false;
993    bool undefined = false;
994
995    switch (cpsr.mode) {
996      case MODE_USER:
997        canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
998                           miscRegInfo[reg][MISCREG_USR_NS_RD];
999        break;
1000      case MODE_FIQ:
1001      case MODE_IRQ:
1002      case MODE_SVC:
1003      case MODE_ABORT:
1004      case MODE_UNDEFINED:
1005      case MODE_SYSTEM:
1006        canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1007                           miscRegInfo[reg][MISCREG_PRI_NS_RD];
1008        break;
1009      case MODE_MON:
1010        canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1011                           miscRegInfo[reg][MISCREG_MON_NS1_RD];
1012        break;
1013      case MODE_HYP:
1014        canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1015        break;
1016      default:
1017        undefined = true;
1018    }
1019    // can't do permissions checkes on the root of a banked pair of regs
1020    assert(!miscRegInfo[reg][MISCREG_BANKED]);
1021    return std::make_tuple(canRead, undefined);
1022}
1023
1024std::tuple<bool, bool>
1025canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1026{
1027    bool secure = !scr.ns;
1028    bool canWrite = false;
1029    bool undefined = false;
1030
1031    switch (cpsr.mode) {
1032      case MODE_USER:
1033        canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1034                            miscRegInfo[reg][MISCREG_USR_NS_WR];
1035        break;
1036      case MODE_FIQ:
1037      case MODE_IRQ:
1038      case MODE_SVC:
1039      case MODE_ABORT:
1040      case MODE_UNDEFINED:
1041      case MODE_SYSTEM:
1042        canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1043                            miscRegInfo[reg][MISCREG_PRI_NS_WR];
1044        break;
1045      case MODE_MON:
1046        canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1047                            miscRegInfo[reg][MISCREG_MON_NS1_WR];
1048        break;
1049      case MODE_HYP:
1050        canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
1051        break;
1052      default:
1053        undefined = true;
1054    }
1055    // can't do permissions checkes on the root of a banked pair of regs
1056    assert(!miscRegInfo[reg][MISCREG_BANKED]);
1057    return std::make_tuple(canWrite, undefined);
1058}
1059
1060int
1061snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1062{
1063    SCR scr = tc->readMiscReg(MISCREG_SCR);
1064    return snsBankedIndex(reg, tc, scr.ns);
1065}
1066
1067int
1068snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1069{
1070    int reg_as_int = static_cast<int>(reg);
1071    if (miscRegInfo[reg][MISCREG_BANKED]) {
1072        reg_as_int += (ArmSystem::haveSecurity(tc) &&
1073                      !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1074    }
1075    return reg_as_int;
1076}
1077
1078
1079/**
1080 * If the reg is a child reg of a banked set, then the parent is the last
1081 * banked one in the list. This is messy, and the wish is to eventually have
1082 * the bitmap replaced with a better data structure. the preUnflatten function
1083 * initializes a lookup table to speed up the search for these banked
1084 * registers.
1085 */
1086
1087int unflattenResultMiscReg[NUM_MISCREGS];
1088
1089void
1090preUnflattenMiscReg()
1091{
1092    int reg = -1;
1093    for (int i = 0 ; i < NUM_MISCREGS; i++){
1094        if (miscRegInfo[i][MISCREG_BANKED])
1095            reg = i;
1096        if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1097            unflattenResultMiscReg[i] = reg;
1098        else
1099            unflattenResultMiscReg[i] = i;
1100        // if this assert fails, no parent was found, and something is broken
1101        assert(unflattenResultMiscReg[i] > -1);
1102    }
1103}
1104
1105int
1106unflattenMiscReg(int reg)
1107{
1108    return unflattenResultMiscReg[reg];
1109}
1110
1111bool
1112canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1113{
1114    // Check for SP_EL0 access while SPSEL == 0
1115    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1116        return false;
1117
1118    // Check for RVBAR access
1119    if (reg == MISCREG_RVBAR_EL1) {
1120        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1121        if (highest_el == EL2 || highest_el == EL3)
1122            return false;
1123    }
1124    if (reg == MISCREG_RVBAR_EL2) {
1125        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1126        if (highest_el == EL3)
1127            return false;
1128    }
1129
1130    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1131
1132    switch (currEL(cpsr)) {
1133      case EL0:
1134        return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1135            miscRegInfo[reg][MISCREG_USR_NS_RD];
1136      case EL1:
1137        return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1138            miscRegInfo[reg][MISCREG_PRI_NS_RD];
1139      case EL2:
1140        return miscRegInfo[reg][MISCREG_HYP_RD];
1141      case EL3:
1142        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1143            miscRegInfo[reg][MISCREG_MON_NS1_RD];
1144      default:
1145        panic("Invalid exception level");
1146    }
1147}
1148
1149bool
1150canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1151{
1152    // Check for SP_EL0 access while SPSEL == 0
1153    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1154        return false;
1155    ExceptionLevel el = currEL(cpsr);
1156    if (reg == MISCREG_DAIF) {
1157        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1158        if (el == EL0 && !sctlr.uma)
1159            return false;
1160    }
1161    if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1162        // In syscall-emulation mode, this test is skipped and DCZVA is always
1163        // allowed at EL0
1164        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1165        if (el == EL0 && !sctlr.dze)
1166            return false;
1167    }
1168    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1169        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1170        if (el == EL0 && !sctlr.uci)
1171            return false;
1172    }
1173
1174    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1175
1176    switch (el) {
1177      case EL0:
1178        return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1179            miscRegInfo[reg][MISCREG_USR_NS_WR];
1180      case EL1:
1181        return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1182            miscRegInfo[reg][MISCREG_PRI_NS_WR];
1183      case EL2:
1184        return miscRegInfo[reg][MISCREG_HYP_WR];
1185      case EL3:
1186        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1187            miscRegInfo[reg][MISCREG_MON_NS1_WR];
1188      default:
1189        panic("Invalid exception level");
1190    }
1191}
1192
1193MiscRegIndex
1194decodeAArch64SysReg(unsigned op0, unsigned op1,
1195                    unsigned crn, unsigned crm,
1196                    unsigned op2)
1197{
1198    switch (op0) {
1199      case 1:
1200        switch (crn) {
1201          case 7:
1202            switch (op1) {
1203              case 0:
1204                switch (crm) {
1205                  case 1:
1206                    switch (op2) {
1207                      case 0:
1208                        return MISCREG_IC_IALLUIS;
1209                    }
1210                    break;
1211                  case 5:
1212                    switch (op2) {
1213                      case 0:
1214                        return MISCREG_IC_IALLU;
1215                    }
1216                    break;
1217                  case 6:
1218                    switch (op2) {
1219                      case 1:
1220                        return MISCREG_DC_IVAC_Xt;
1221                      case 2:
1222                        return MISCREG_DC_ISW_Xt;
1223                    }
1224                    break;
1225                  case 8:
1226                    switch (op2) {
1227                      case 0:
1228                        return MISCREG_AT_S1E1R_Xt;
1229                      case 1:
1230                        return MISCREG_AT_S1E1W_Xt;
1231                      case 2:
1232                        return MISCREG_AT_S1E0R_Xt;
1233                      case 3:
1234                        return MISCREG_AT_S1E0W_Xt;
1235                    }
1236                    break;
1237                  case 10:
1238                    switch (op2) {
1239                      case 2:
1240                        return MISCREG_DC_CSW_Xt;
1241                    }
1242                    break;
1243                  case 14:
1244                    switch (op2) {
1245                      case 2:
1246                        return MISCREG_DC_CISW_Xt;
1247                    }
1248                    break;
1249                }
1250                break;
1251              case 3:
1252                switch (crm) {
1253                  case 4:
1254                    switch (op2) {
1255                      case 1:
1256                        return MISCREG_DC_ZVA_Xt;
1257                    }
1258                    break;
1259                  case 5:
1260                    switch (op2) {
1261                      case 1:
1262                        return MISCREG_IC_IVAU_Xt;
1263                    }
1264                    break;
1265                  case 10:
1266                    switch (op2) {
1267                      case 1:
1268                        return MISCREG_DC_CVAC_Xt;
1269                    }
1270                    break;
1271                  case 11:
1272                    switch (op2) {
1273                      case 1:
1274                        return MISCREG_DC_CVAU_Xt;
1275                    }
1276                    break;
1277                  case 14:
1278                    switch (op2) {
1279                      case 1:
1280                        return MISCREG_DC_CIVAC_Xt;
1281                    }
1282                    break;
1283                }
1284                break;
1285              case 4:
1286                switch (crm) {
1287                  case 8:
1288                    switch (op2) {
1289                      case 0:
1290                        return MISCREG_AT_S1E2R_Xt;
1291                      case 1:
1292                        return MISCREG_AT_S1E2W_Xt;
1293                      case 4:
1294                        return MISCREG_AT_S12E1R_Xt;
1295                      case 5:
1296                        return MISCREG_AT_S12E1W_Xt;
1297                      case 6:
1298                        return MISCREG_AT_S12E0R_Xt;
1299                      case 7:
1300                        return MISCREG_AT_S12E0W_Xt;
1301                    }
1302                    break;
1303                }
1304                break;
1305              case 6:
1306                switch (crm) {
1307                  case 8:
1308                    switch (op2) {
1309                      case 0:
1310                        return MISCREG_AT_S1E3R_Xt;
1311                      case 1:
1312                        return MISCREG_AT_S1E3W_Xt;
1313                    }
1314                    break;
1315                }
1316                break;
1317            }
1318            break;
1319          case 8:
1320            switch (op1) {
1321              case 0:
1322                switch (crm) {
1323                  case 3:
1324                    switch (op2) {
1325                      case 0:
1326                        return MISCREG_TLBI_VMALLE1IS;
1327                      case 1:
1328                        return MISCREG_TLBI_VAE1IS_Xt;
1329                      case 2:
1330                        return MISCREG_TLBI_ASIDE1IS_Xt;
1331                      case 3:
1332                        return MISCREG_TLBI_VAAE1IS_Xt;
1333                      case 5:
1334                        return MISCREG_TLBI_VALE1IS_Xt;
1335                      case 7:
1336                        return MISCREG_TLBI_VAALE1IS_Xt;
1337                    }
1338                    break;
1339                  case 7:
1340                    switch (op2) {
1341                      case 0:
1342                        return MISCREG_TLBI_VMALLE1;
1343                      case 1:
1344                        return MISCREG_TLBI_VAE1_Xt;
1345                      case 2:
1346                        return MISCREG_TLBI_ASIDE1_Xt;
1347                      case 3:
1348                        return MISCREG_TLBI_VAAE1_Xt;
1349                      case 5:
1350                        return MISCREG_TLBI_VALE1_Xt;
1351                      case 7:
1352                        return MISCREG_TLBI_VAALE1_Xt;
1353                    }
1354                    break;
1355                }
1356                break;
1357              case 4:
1358                switch (crm) {
1359                  case 0:
1360                    switch (op2) {
1361                      case 1:
1362                        return MISCREG_TLBI_IPAS2E1IS_Xt;
1363                      case 5:
1364                        return MISCREG_TLBI_IPAS2LE1IS_Xt;
1365                    }
1366                    break;
1367                  case 3:
1368                    switch (op2) {
1369                      case 0:
1370                        return MISCREG_TLBI_ALLE2IS;
1371                      case 1:
1372                        return MISCREG_TLBI_VAE2IS_Xt;
1373                      case 4:
1374                        return MISCREG_TLBI_ALLE1IS;
1375                      case 5:
1376                        return MISCREG_TLBI_VALE2IS_Xt;
1377                      case 6:
1378                        return MISCREG_TLBI_VMALLS12E1IS;
1379                    }
1380                    break;
1381                  case 4:
1382                    switch (op2) {
1383                      case 1:
1384                        return MISCREG_TLBI_IPAS2E1_Xt;
1385                      case 5:
1386                        return MISCREG_TLBI_IPAS2LE1_Xt;
1387                    }
1388                    break;
1389                  case 7:
1390                    switch (op2) {
1391                      case 0:
1392                        return MISCREG_TLBI_ALLE2;
1393                      case 1:
1394                        return MISCREG_TLBI_VAE2_Xt;
1395                      case 4:
1396                        return MISCREG_TLBI_ALLE1;
1397                      case 5:
1398                        return MISCREG_TLBI_VALE2_Xt;
1399                      case 6:
1400                        return MISCREG_TLBI_VMALLS12E1;
1401                    }
1402                    break;
1403                }
1404                break;
1405              case 6:
1406                switch (crm) {
1407                  case 3:
1408                    switch (op2) {
1409                      case 0:
1410                        return MISCREG_TLBI_ALLE3IS;
1411                      case 1:
1412                        return MISCREG_TLBI_VAE3IS_Xt;
1413                      case 5:
1414                        return MISCREG_TLBI_VALE3IS_Xt;
1415                    }
1416                    break;
1417                  case 7:
1418                    switch (op2) {
1419                      case 0:
1420                        return MISCREG_TLBI_ALLE3;
1421                      case 1:
1422                        return MISCREG_TLBI_VAE3_Xt;
1423                      case 5:
1424                        return MISCREG_TLBI_VALE3_Xt;
1425                    }
1426                    break;
1427                }
1428                break;
1429            }
1430            break;
1431          case 11:
1432          case 15:
1433            // SYS Instruction with CRn = { 11, 15 }
1434            // (Trappable by HCR_EL2.TIDCP)
1435            return MISCREG_IMPDEF_UNIMPL;
1436        }
1437        break;
1438      case 2:
1439        switch (crn) {
1440          case 0:
1441            switch (op1) {
1442              case 0:
1443                switch (crm) {
1444                  case 0:
1445                    switch (op2) {
1446                      case 2:
1447                        return MISCREG_OSDTRRX_EL1;
1448                      case 4:
1449                        return MISCREG_DBGBVR0_EL1;
1450                      case 5:
1451                        return MISCREG_DBGBCR0_EL1;
1452                      case 6:
1453                        return MISCREG_DBGWVR0_EL1;
1454                      case 7:
1455                        return MISCREG_DBGWCR0_EL1;
1456                    }
1457                    break;
1458                  case 1:
1459                    switch (op2) {
1460                      case 4:
1461                        return MISCREG_DBGBVR1_EL1;
1462                      case 5:
1463                        return MISCREG_DBGBCR1_EL1;
1464                      case 6:
1465                        return MISCREG_DBGWVR1_EL1;
1466                      case 7:
1467                        return MISCREG_DBGWCR1_EL1;
1468                    }
1469                    break;
1470                  case 2:
1471                    switch (op2) {
1472                      case 0:
1473                        return MISCREG_MDCCINT_EL1;
1474                      case 2:
1475                        return MISCREG_MDSCR_EL1;
1476                      case 4:
1477                        return MISCREG_DBGBVR2_EL1;
1478                      case 5:
1479                        return MISCREG_DBGBCR2_EL1;
1480                      case 6:
1481                        return MISCREG_DBGWVR2_EL1;
1482                      case 7:
1483                        return MISCREG_DBGWCR2_EL1;
1484                    }
1485                    break;
1486                  case 3:
1487                    switch (op2) {
1488                      case 2:
1489                        return MISCREG_OSDTRTX_EL1;
1490                      case 4:
1491                        return MISCREG_DBGBVR3_EL1;
1492                      case 5:
1493                        return MISCREG_DBGBCR3_EL1;
1494                      case 6:
1495                        return MISCREG_DBGWVR3_EL1;
1496                      case 7:
1497                        return MISCREG_DBGWCR3_EL1;
1498                    }
1499                    break;
1500                  case 4:
1501                    switch (op2) {
1502                      case 4:
1503                        return MISCREG_DBGBVR4_EL1;
1504                      case 5:
1505                        return MISCREG_DBGBCR4_EL1;
1506                    }
1507                    break;
1508                  case 5:
1509                    switch (op2) {
1510                      case 4:
1511                        return MISCREG_DBGBVR5_EL1;
1512                      case 5:
1513                        return MISCREG_DBGBCR5_EL1;
1514                    }
1515                    break;
1516                  case 6:
1517                    switch (op2) {
1518                      case 2:
1519                        return MISCREG_OSECCR_EL1;
1520                    }
1521                    break;
1522                }
1523                break;
1524              case 2:
1525                switch (crm) {
1526                  case 0:
1527                    switch (op2) {
1528                      case 0:
1529                        return MISCREG_TEECR32_EL1;
1530                    }
1531                    break;
1532                }
1533                break;
1534              case 3:
1535                switch (crm) {
1536                  case 1:
1537                    switch (op2) {
1538                      case 0:
1539                        return MISCREG_MDCCSR_EL0;
1540                    }
1541                    break;
1542                  case 4:
1543                    switch (op2) {
1544                      case 0:
1545                        return MISCREG_MDDTR_EL0;
1546                    }
1547                    break;
1548                  case 5:
1549                    switch (op2) {
1550                      case 0:
1551                        return MISCREG_MDDTRRX_EL0;
1552                    }
1553                    break;
1554                }
1555                break;
1556              case 4:
1557                switch (crm) {
1558                  case 7:
1559                    switch (op2) {
1560                      case 0:
1561                        return MISCREG_DBGVCR32_EL2;
1562                    }
1563                    break;
1564                }
1565                break;
1566            }
1567            break;
1568          case 1:
1569            switch (op1) {
1570              case 0:
1571                switch (crm) {
1572                  case 0:
1573                    switch (op2) {
1574                      case 0:
1575                        return MISCREG_MDRAR_EL1;
1576                      case 4:
1577                        return MISCREG_OSLAR_EL1;
1578                    }
1579                    break;
1580                  case 1:
1581                    switch (op2) {
1582                      case 4:
1583                        return MISCREG_OSLSR_EL1;
1584                    }
1585                    break;
1586                  case 3:
1587                    switch (op2) {
1588                      case 4:
1589                        return MISCREG_OSDLR_EL1;
1590                    }
1591                    break;
1592                  case 4:
1593                    switch (op2) {
1594                      case 4:
1595                        return MISCREG_DBGPRCR_EL1;
1596                    }
1597                    break;
1598                }
1599                break;
1600              case 2:
1601                switch (crm) {
1602                  case 0:
1603                    switch (op2) {
1604                      case 0:
1605                        return MISCREG_TEEHBR32_EL1;
1606                    }
1607                    break;
1608                }
1609                break;
1610            }
1611            break;
1612          case 7:
1613            switch (op1) {
1614              case 0:
1615                switch (crm) {
1616                  case 8:
1617                    switch (op2) {
1618                      case 6:
1619                        return MISCREG_DBGCLAIMSET_EL1;
1620                    }
1621                    break;
1622                  case 9:
1623                    switch (op2) {
1624                      case 6:
1625                        return MISCREG_DBGCLAIMCLR_EL1;
1626                    }
1627                    break;
1628                  case 14:
1629                    switch (op2) {
1630                      case 6:
1631                        return MISCREG_DBGAUTHSTATUS_EL1;
1632                    }
1633                    break;
1634                }
1635                break;
1636            }
1637            break;
1638        }
1639        break;
1640      case 3:
1641        switch (crn) {
1642          case 0:
1643            switch (op1) {
1644              case 0:
1645                switch (crm) {
1646                  case 0:
1647                    switch (op2) {
1648                      case 0:
1649                        return MISCREG_MIDR_EL1;
1650                      case 5:
1651                        return MISCREG_MPIDR_EL1;
1652                      case 6:
1653                        return MISCREG_REVIDR_EL1;
1654                    }
1655                    break;
1656                  case 1:
1657                    switch (op2) {
1658                      case 0:
1659                        return MISCREG_ID_PFR0_EL1;
1660                      case 1:
1661                        return MISCREG_ID_PFR1_EL1;
1662                      case 2:
1663                        return MISCREG_ID_DFR0_EL1;
1664                      case 3:
1665                        return MISCREG_ID_AFR0_EL1;
1666                      case 4:
1667                        return MISCREG_ID_MMFR0_EL1;
1668                      case 5:
1669                        return MISCREG_ID_MMFR1_EL1;
1670                      case 6:
1671                        return MISCREG_ID_MMFR2_EL1;
1672                      case 7:
1673                        return MISCREG_ID_MMFR3_EL1;
1674                    }
1675                    break;
1676                  case 2:
1677                    switch (op2) {
1678                      case 0:
1679                        return MISCREG_ID_ISAR0_EL1;
1680                      case 1:
1681                        return MISCREG_ID_ISAR1_EL1;
1682                      case 2:
1683                        return MISCREG_ID_ISAR2_EL1;
1684                      case 3:
1685                        return MISCREG_ID_ISAR3_EL1;
1686                      case 4:
1687                        return MISCREG_ID_ISAR4_EL1;
1688                      case 5:
1689                        return MISCREG_ID_ISAR5_EL1;
1690                    }
1691                    break;
1692                  case 3:
1693                    switch (op2) {
1694                      case 0:
1695                        return MISCREG_MVFR0_EL1;
1696                      case 1:
1697                        return MISCREG_MVFR1_EL1;
1698                      case 2:
1699                        return MISCREG_MVFR2_EL1;
1700                      case 3 ... 7:
1701                        return MISCREG_RAZ;
1702                    }
1703                    break;
1704                  case 4:
1705                    switch (op2) {
1706                      case 0:
1707                        return MISCREG_ID_AA64PFR0_EL1;
1708                      case 1:
1709                        return MISCREG_ID_AA64PFR1_EL1;
1710                      case 2 ... 3:
1711                        return MISCREG_RAZ;
1712                      case 4:
1713                        return MISCREG_ID_AA64ZFR0_EL1;
1714                      case 5 ... 7:
1715                        return MISCREG_RAZ;
1716                    }
1717                    break;
1718                  case 5:
1719                    switch (op2) {
1720                      case 0:
1721                        return MISCREG_ID_AA64DFR0_EL1;
1722                      case 1:
1723                        return MISCREG_ID_AA64DFR1_EL1;
1724                      case 4:
1725                        return MISCREG_ID_AA64AFR0_EL1;
1726                      case 5:
1727                        return MISCREG_ID_AA64AFR1_EL1;
1728                      case 2:
1729                      case 3:
1730                      case 6:
1731                      case 7:
1732                        return MISCREG_RAZ;
1733                    }
1734                    break;
1735                  case 6:
1736                    switch (op2) {
1737                      case 0:
1738                        return MISCREG_ID_AA64ISAR0_EL1;
1739                      case 1:
1740                        return MISCREG_ID_AA64ISAR1_EL1;
1741                      case 2 ... 7:
1742                        return MISCREG_RAZ;
1743                    }
1744                    break;
1745                  case 7:
1746                    switch (op2) {
1747                      case 0:
1748                        return MISCREG_ID_AA64MMFR0_EL1;
1749                      case 1:
1750                        return MISCREG_ID_AA64MMFR1_EL1;
1751                      case 2:
1752                        return MISCREG_ID_AA64MMFR2_EL1;
1753                      case 3 ... 7:
1754                        return MISCREG_RAZ;
1755                    }
1756                    break;
1757                }
1758                break;
1759              case 1:
1760                switch (crm) {
1761                  case 0:
1762                    switch (op2) {
1763                      case 0:
1764                        return MISCREG_CCSIDR_EL1;
1765                      case 1:
1766                        return MISCREG_CLIDR_EL1;
1767                      case 7:
1768                        return MISCREG_AIDR_EL1;
1769                    }
1770                    break;
1771                }
1772                break;
1773              case 2:
1774                switch (crm) {
1775                  case 0:
1776                    switch (op2) {
1777                      case 0:
1778                        return MISCREG_CSSELR_EL1;
1779                    }
1780                    break;
1781                }
1782                break;
1783              case 3:
1784                switch (crm) {
1785                  case 0:
1786                    switch (op2) {
1787                      case 1:
1788                        return MISCREG_CTR_EL0;
1789                      case 7:
1790                        return MISCREG_DCZID_EL0;
1791                    }
1792                    break;
1793                }
1794                break;
1795              case 4:
1796                switch (crm) {
1797                  case 0:
1798                    switch (op2) {
1799                      case 0:
1800                        return MISCREG_VPIDR_EL2;
1801                      case 5:
1802                        return MISCREG_VMPIDR_EL2;
1803                    }
1804                    break;
1805                }
1806                break;
1807            }
1808            break;
1809          case 1:
1810            switch (op1) {
1811              case 0:
1812                switch (crm) {
1813                  case 0:
1814                    switch (op2) {
1815                      case 0:
1816                        return MISCREG_SCTLR_EL1;
1817                      case 1:
1818                        return MISCREG_ACTLR_EL1;
1819                      case 2:
1820                        return MISCREG_CPACR_EL1;
1821                    }
1822                    break;
1823                  case 2:
1824                    switch (op2) {
1825                      case 0:
1826                        return MISCREG_ZCR_EL1;
1827                    }
1828                    break;
1829                }
1830                break;
1831              case 4:
1832                switch (crm) {
1833                  case 0:
1834                    switch (op2) {
1835                      case 0:
1836                        return MISCREG_SCTLR_EL2;
1837                      case 1:
1838                        return MISCREG_ACTLR_EL2;
1839                    }
1840                    break;
1841                  case 1:
1842                    switch (op2) {
1843                      case 0:
1844                        return MISCREG_HCR_EL2;
1845                      case 1:
1846                        return MISCREG_MDCR_EL2;
1847                      case 2:
1848                        return MISCREG_CPTR_EL2;
1849                      case 3:
1850                        return MISCREG_HSTR_EL2;
1851                      case 7:
1852                        return MISCREG_HACR_EL2;
1853                    }
1854                    break;
1855                  case 2:
1856                    switch (op2) {
1857                      case 0:
1858                        return MISCREG_ZCR_EL2;
1859                    }
1860                    break;
1861                }
1862                break;
1863              case 5:
1864                switch (crm) {
1865                  case 2:
1866                    switch (op2) {
1867                      case 0:
1868                        return MISCREG_ZCR_EL12;
1869                    }
1870                    break;
1871                }
1872                break;
1873              case 6:
1874                switch (crm) {
1875                  case 0:
1876                    switch (op2) {
1877                      case 0:
1878                        return MISCREG_SCTLR_EL3;
1879                      case 1:
1880                        return MISCREG_ACTLR_EL3;
1881                    }
1882                    break;
1883                  case 1:
1884                    switch (op2) {
1885                      case 0:
1886                        return MISCREG_SCR_EL3;
1887                      case 1:
1888                        return MISCREG_SDER32_EL3;
1889                      case 2:
1890                        return MISCREG_CPTR_EL3;
1891                    }
1892                    break;
1893                  case 2:
1894                    switch (op2) {
1895                      case 0:
1896                        return MISCREG_ZCR_EL3;
1897                    }
1898                    break;
1899                  case 3:
1900                    switch (op2) {
1901                      case 1:
1902                        return MISCREG_MDCR_EL3;
1903                    }
1904                    break;
1905                }
1906                break;
1907            }
1908            break;
1909          case 2:
1910            switch (op1) {
1911              case 0:
1912                switch (crm) {
1913                  case 0:
1914                    switch (op2) {
1915                      case 0:
1916                        return MISCREG_TTBR0_EL1;
1917                      case 1:
1918                        return MISCREG_TTBR1_EL1;
1919                      case 2:
1920                        return MISCREG_TCR_EL1;
1921                    }
1922                    break;
1923                }
1924                break;
1925              case 4:
1926                switch (crm) {
1927                  case 0:
1928                    switch (op2) {
1929                      case 0:
1930                        return MISCREG_TTBR0_EL2;
1931                      case 1:
1932                        return MISCREG_TTBR1_EL2;
1933                      case 2:
1934                        return MISCREG_TCR_EL2;
1935                    }
1936                    break;
1937                  case 1:
1938                    switch (op2) {
1939                      case 0:
1940                        return MISCREG_VTTBR_EL2;
1941                      case 2:
1942                        return MISCREG_VTCR_EL2;
1943                    }
1944                    break;
1945                }
1946                break;
1947              case 6:
1948                switch (crm) {
1949                  case 0:
1950                    switch (op2) {
1951                      case 0:
1952                        return MISCREG_TTBR0_EL3;
1953                      case 2:
1954                        return MISCREG_TCR_EL3;
1955                    }
1956                    break;
1957                }
1958                break;
1959            }
1960            break;
1961          case 3:
1962            switch (op1) {
1963              case 4:
1964                switch (crm) {
1965                  case 0:
1966                    switch (op2) {
1967                      case 0:
1968                        return MISCREG_DACR32_EL2;
1969                    }
1970                    break;
1971                }
1972                break;
1973            }
1974            break;
1975          case 4:
1976            switch (op1) {
1977              case 0:
1978                switch (crm) {
1979                  case 0:
1980                    switch (op2) {
1981                      case 0:
1982                        return MISCREG_SPSR_EL1;
1983                      case 1:
1984                        return MISCREG_ELR_EL1;
1985                    }
1986                    break;
1987                  case 1:
1988                    switch (op2) {
1989                      case 0:
1990                        return MISCREG_SP_EL0;
1991                    }
1992                    break;
1993                  case 2:
1994                    switch (op2) {
1995                      case 0:
1996                        return MISCREG_SPSEL;
1997                      case 2:
1998                        return MISCREG_CURRENTEL;
1999                      case 3:
2000                        return MISCREG_PAN;
2001                    }
2002                    break;
2003                  case 6:
2004                    switch (op2) {
2005                      case 0:
2006                        return MISCREG_ICC_PMR_EL1;
2007                    }
2008                    break;
2009                }
2010                break;
2011              case 3:
2012                switch (crm) {
2013                  case 2:
2014                    switch (op2) {
2015                      case 0:
2016                        return MISCREG_NZCV;
2017                      case 1:
2018                        return MISCREG_DAIF;
2019                    }
2020                    break;
2021                  case 4:
2022                    switch (op2) {
2023                      case 0:
2024                        return MISCREG_FPCR;
2025                      case 1:
2026                        return MISCREG_FPSR;
2027                    }
2028                    break;
2029                  case 5:
2030                    switch (op2) {
2031                      case 0:
2032                        return MISCREG_DSPSR_EL0;
2033                      case 1:
2034                        return MISCREG_DLR_EL0;
2035                    }
2036                    break;
2037                }
2038                break;
2039              case 4:
2040                switch (crm) {
2041                  case 0:
2042                    switch (op2) {
2043                      case 0:
2044                        return MISCREG_SPSR_EL2;
2045                      case 1:
2046                        return MISCREG_ELR_EL2;
2047                    }
2048                    break;
2049                  case 1:
2050                    switch (op2) {
2051                      case 0:
2052                        return MISCREG_SP_EL1;
2053                    }
2054                    break;
2055                  case 3:
2056                    switch (op2) {
2057                      case 0:
2058                        return MISCREG_SPSR_IRQ_AA64;
2059                      case 1:
2060                        return MISCREG_SPSR_ABT_AA64;
2061                      case 2:
2062                        return MISCREG_SPSR_UND_AA64;
2063                      case 3:
2064                        return MISCREG_SPSR_FIQ_AA64;
2065                    }
2066                    break;
2067                }
2068                break;
2069              case 6:
2070                switch (crm) {
2071                  case 0:
2072                    switch (op2) {
2073                      case 0:
2074                        return MISCREG_SPSR_EL3;
2075                      case 1:
2076                        return MISCREG_ELR_EL3;
2077                    }
2078                    break;
2079                  case 1:
2080                    switch (op2) {
2081                      case 0:
2082                        return MISCREG_SP_EL2;
2083                    }
2084                    break;
2085                }
2086                break;
2087            }
2088            break;
2089          case 5:
2090            switch (op1) {
2091              case 0:
2092                switch (crm) {
2093                  case 1:
2094                    switch (op2) {
2095                      case 0:
2096                        return MISCREG_AFSR0_EL1;
2097                      case 1:
2098                        return MISCREG_AFSR1_EL1;
2099                    }
2100                    break;
2101                  case 2:
2102                    switch (op2) {
2103                      case 0:
2104                        return MISCREG_ESR_EL1;
2105                    }
2106                    break;
2107                  case 3:
2108                    switch (op2) {
2109                      case 0:
2110                        return MISCREG_ERRIDR_EL1;
2111                      case 1:
2112                        return MISCREG_ERRSELR_EL1;
2113                    }
2114                    break;
2115                  case 4:
2116                    switch (op2) {
2117                      case 0:
2118                        return MISCREG_ERXFR_EL1;
2119                      case 1:
2120                        return MISCREG_ERXCTLR_EL1;
2121                      case 2:
2122                        return MISCREG_ERXSTATUS_EL1;
2123                      case 3:
2124                        return MISCREG_ERXADDR_EL1;
2125                    }
2126                    break;
2127                  case 5:
2128                    switch (op2) {
2129                      case 0:
2130                        return MISCREG_ERXMISC0_EL1;
2131                      case 1:
2132                        return MISCREG_ERXMISC1_EL1;
2133                    }
2134                    break;
2135                }
2136                break;
2137              case 4:
2138                switch (crm) {
2139                  case 0:
2140                    switch (op2) {
2141                      case 1:
2142                        return MISCREG_IFSR32_EL2;
2143                    }
2144                    break;
2145                  case 1:
2146                    switch (op2) {
2147                      case 0:
2148                        return MISCREG_AFSR0_EL2;
2149                      case 1:
2150                        return MISCREG_AFSR1_EL2;
2151                    }
2152                    break;
2153                  case 2:
2154                    switch (op2) {
2155                      case 0:
2156                        return MISCREG_ESR_EL2;
2157                      case 3:
2158                        return MISCREG_VSESR_EL2;
2159                    }
2160                    break;
2161                  case 3:
2162                    switch (op2) {
2163                      case 0:
2164                        return MISCREG_FPEXC32_EL2;
2165                    }
2166                    break;
2167                }
2168                break;
2169              case 6:
2170                switch (crm) {
2171                  case 1:
2172                    switch (op2) {
2173                      case 0:
2174                        return MISCREG_AFSR0_EL3;
2175                      case 1:
2176                        return MISCREG_AFSR1_EL3;
2177                    }
2178                    break;
2179                  case 2:
2180                    switch (op2) {
2181                      case 0:
2182                        return MISCREG_ESR_EL3;
2183                    }
2184                    break;
2185                }
2186                break;
2187            }
2188            break;
2189          case 6:
2190            switch (op1) {
2191              case 0:
2192                switch (crm) {
2193                  case 0:
2194                    switch (op2) {
2195                      case 0:
2196                        return MISCREG_FAR_EL1;
2197                    }
2198                    break;
2199                }
2200                break;
2201              case 4:
2202                switch (crm) {
2203                  case 0:
2204                    switch (op2) {
2205                      case 0:
2206                        return MISCREG_FAR_EL2;
2207                      case 4:
2208                        return MISCREG_HPFAR_EL2;
2209                    }
2210                    break;
2211                }
2212                break;
2213              case 6:
2214                switch (crm) {
2215                  case 0:
2216                    switch (op2) {
2217                      case 0:
2218                        return MISCREG_FAR_EL3;
2219                    }
2220                    break;
2221                }
2222                break;
2223            }
2224            break;
2225          case 7:
2226            switch (op1) {
2227              case 0:
2228                switch (crm) {
2229                  case 4:
2230                    switch (op2) {
2231                      case 0:
2232                        return MISCREG_PAR_EL1;
2233                    }
2234                    break;
2235                }
2236                break;
2237            }
2238            break;
2239          case 9:
2240            switch (op1) {
2241              case 0:
2242                switch (crm) {
2243                  case 14:
2244                    switch (op2) {
2245                      case 1:
2246                        return MISCREG_PMINTENSET_EL1;
2247                      case 2:
2248                        return MISCREG_PMINTENCLR_EL1;
2249                    }
2250                    break;
2251                }
2252                break;
2253              case 3:
2254                switch (crm) {
2255                  case 12:
2256                    switch (op2) {
2257                      case 0:
2258                        return MISCREG_PMCR_EL0;
2259                      case 1:
2260                        return MISCREG_PMCNTENSET_EL0;
2261                      case 2:
2262                        return MISCREG_PMCNTENCLR_EL0;
2263                      case 3:
2264                        return MISCREG_PMOVSCLR_EL0;
2265                      case 4:
2266                        return MISCREG_PMSWINC_EL0;
2267                      case 5:
2268                        return MISCREG_PMSELR_EL0;
2269                      case 6:
2270                        return MISCREG_PMCEID0_EL0;
2271                      case 7:
2272                        return MISCREG_PMCEID1_EL0;
2273                    }
2274                    break;
2275                  case 13:
2276                    switch (op2) {
2277                      case 0:
2278                        return MISCREG_PMCCNTR_EL0;
2279                      case 1:
2280                        return MISCREG_PMXEVTYPER_EL0;
2281                      case 2:
2282                        return MISCREG_PMXEVCNTR_EL0;
2283                    }
2284                    break;
2285                  case 14:
2286                    switch (op2) {
2287                      case 0:
2288                        return MISCREG_PMUSERENR_EL0;
2289                      case 3:
2290                        return MISCREG_PMOVSSET_EL0;
2291                    }
2292                    break;
2293                }
2294                break;
2295            }
2296            break;
2297          case 10:
2298            switch (op1) {
2299              case 0:
2300                switch (crm) {
2301                  case 2:
2302                    switch (op2) {
2303                      case 0:
2304                        return MISCREG_MAIR_EL1;
2305                    }
2306                    break;
2307                  case 3:
2308                    switch (op2) {
2309                      case 0:
2310                        return MISCREG_AMAIR_EL1;
2311                    }
2312                    break;
2313                }
2314                break;
2315              case 4:
2316                switch (crm) {
2317                  case 2:
2318                    switch (op2) {
2319                      case 0:
2320                        return MISCREG_MAIR_EL2;
2321                    }
2322                    break;
2323                  case 3:
2324                    switch (op2) {
2325                      case 0:
2326                        return MISCREG_AMAIR_EL2;
2327                    }
2328                    break;
2329                }
2330                break;
2331              case 6:
2332                switch (crm) {
2333                  case 2:
2334                    switch (op2) {
2335                      case 0:
2336                        return MISCREG_MAIR_EL3;
2337                    }
2338                    break;
2339                  case 3:
2340                    switch (op2) {
2341                      case 0:
2342                        return MISCREG_AMAIR_EL3;
2343                    }
2344                    break;
2345                }
2346                break;
2347            }
2348            break;
2349          case 11:
2350            switch (op1) {
2351              case 1:
2352                switch (crm) {
2353                  case 0:
2354                    switch (op2) {
2355                      case 2:
2356                        return MISCREG_L2CTLR_EL1;
2357                      case 3:
2358                        return MISCREG_L2ECTLR_EL1;
2359                    }
2360                    break;
2361                }
2362                M5_FALLTHROUGH;
2363              default:
2364                // S3_<op1>_11_<Cm>_<op2>
2365                return MISCREG_IMPDEF_UNIMPL;
2366            }
2367            M5_UNREACHABLE;
2368          case 12:
2369            switch (op1) {
2370              case 0:
2371                switch (crm) {
2372                  case 0:
2373                    switch (op2) {
2374                      case 0:
2375                        return MISCREG_VBAR_EL1;
2376                      case 1:
2377                        return MISCREG_RVBAR_EL1;
2378                    }
2379                    break;
2380                  case 1:
2381                    switch (op2) {
2382                      case 0:
2383                        return MISCREG_ISR_EL1;
2384                      case 1:
2385                        return MISCREG_DISR_EL1;
2386                    }
2387                    break;
2388                  case 8:
2389                    switch (op2) {
2390                      case 0:
2391                        return MISCREG_ICC_IAR0_EL1;
2392                      case 1:
2393                        return MISCREG_ICC_EOIR0_EL1;
2394                      case 2:
2395                        return MISCREG_ICC_HPPIR0_EL1;
2396                      case 3:
2397                        return MISCREG_ICC_BPR0_EL1;
2398                      case 4:
2399                        return MISCREG_ICC_AP0R0_EL1;
2400                      case 5:
2401                        return MISCREG_ICC_AP0R1_EL1;
2402                      case 6:
2403                        return MISCREG_ICC_AP0R2_EL1;
2404                      case 7:
2405                        return MISCREG_ICC_AP0R3_EL1;
2406                    }
2407                    break;
2408                  case 9:
2409                    switch (op2) {
2410                      case 0:
2411                        return MISCREG_ICC_AP1R0_EL1;
2412                      case 1:
2413                        return MISCREG_ICC_AP1R1_EL1;
2414                      case 2:
2415                        return MISCREG_ICC_AP1R2_EL1;
2416                      case 3:
2417                        return MISCREG_ICC_AP1R3_EL1;
2418                    }
2419                    break;
2420                  case 11:
2421                    switch (op2) {
2422                      case 1:
2423                        return MISCREG_ICC_DIR_EL1;
2424                      case 3:
2425                        return MISCREG_ICC_RPR_EL1;
2426                      case 5:
2427                        return MISCREG_ICC_SGI1R_EL1;
2428                      case 6:
2429                        return MISCREG_ICC_ASGI1R_EL1;
2430                      case 7:
2431                        return MISCREG_ICC_SGI0R_EL1;
2432                    }
2433                    break;
2434                  case 12:
2435                    switch (op2) {
2436                      case 0:
2437                        return MISCREG_ICC_IAR1_EL1;
2438                      case 1:
2439                        return MISCREG_ICC_EOIR1_EL1;
2440                      case 2:
2441                        return MISCREG_ICC_HPPIR1_EL1;
2442                      case 3:
2443                        return MISCREG_ICC_BPR1_EL1;
2444                      case 4:
2445                        return MISCREG_ICC_CTLR_EL1;
2446                      case 5:
2447                        return MISCREG_ICC_SRE_EL1;
2448                      case 6:
2449                        return MISCREG_ICC_IGRPEN0_EL1;
2450                      case 7:
2451                        return MISCREG_ICC_IGRPEN1_EL1;
2452                    }
2453                    break;
2454                }
2455                break;
2456              case 4:
2457                switch (crm) {
2458                  case 0:
2459                    switch (op2) {
2460                      case 0:
2461                        return MISCREG_VBAR_EL2;
2462                      case 1:
2463                        return MISCREG_RVBAR_EL2;
2464                    }
2465                    break;
2466                  case 1:
2467                    switch (op2) {
2468                      case 1:
2469                        return MISCREG_VDISR_EL2;
2470                    }
2471                    break;
2472                  case 8:
2473                    switch (op2) {
2474                      case 0:
2475                        return MISCREG_ICH_AP0R0_EL2;
2476                      case 1:
2477                        return MISCREG_ICH_AP0R1_EL2;
2478                      case 2:
2479                        return MISCREG_ICH_AP0R2_EL2;
2480                      case 3:
2481                        return MISCREG_ICH_AP0R3_EL2;
2482                    }
2483                    break;
2484                  case 9:
2485                    switch (op2) {
2486                      case 0:
2487                        return MISCREG_ICH_AP1R0_EL2;
2488                      case 1:
2489                        return MISCREG_ICH_AP1R1_EL2;
2490                      case 2:
2491                        return MISCREG_ICH_AP1R2_EL2;
2492                      case 3:
2493                        return MISCREG_ICH_AP1R3_EL2;
2494                      case 5:
2495                        return MISCREG_ICC_SRE_EL2;
2496                    }
2497                    break;
2498                  case 11:
2499                    switch (op2) {
2500                      case 0:
2501                        return MISCREG_ICH_HCR_EL2;
2502                      case 1:
2503                        return MISCREG_ICH_VTR_EL2;
2504                      case 2:
2505                        return MISCREG_ICH_MISR_EL2;
2506                      case 3:
2507                        return MISCREG_ICH_EISR_EL2;
2508                      case 5:
2509                        return MISCREG_ICH_ELRSR_EL2;
2510                      case 7:
2511                        return MISCREG_ICH_VMCR_EL2;
2512                    }
2513                    break;
2514                  case 12:
2515                    switch (op2) {
2516                      case 0:
2517                        return MISCREG_ICH_LR0_EL2;
2518                      case 1:
2519                        return MISCREG_ICH_LR1_EL2;
2520                      case 2:
2521                        return MISCREG_ICH_LR2_EL2;
2522                      case 3:
2523                        return MISCREG_ICH_LR3_EL2;
2524                      case 4:
2525                        return MISCREG_ICH_LR4_EL2;
2526                      case 5:
2527                        return MISCREG_ICH_LR5_EL2;
2528                      case 6:
2529                        return MISCREG_ICH_LR6_EL2;
2530                      case 7:
2531                        return MISCREG_ICH_LR7_EL2;
2532                    }
2533                    break;
2534                  case 13:
2535                    switch (op2) {
2536                      case 0:
2537                        return MISCREG_ICH_LR8_EL2;
2538                      case 1:
2539                        return MISCREG_ICH_LR9_EL2;
2540                      case 2:
2541                        return MISCREG_ICH_LR10_EL2;
2542                      case 3:
2543                        return MISCREG_ICH_LR11_EL2;
2544                      case 4:
2545                        return MISCREG_ICH_LR12_EL2;
2546                      case 5:
2547                        return MISCREG_ICH_LR13_EL2;
2548                      case 6:
2549                        return MISCREG_ICH_LR14_EL2;
2550                      case 7:
2551                        return MISCREG_ICH_LR15_EL2;
2552                    }
2553                    break;
2554                }
2555                break;
2556              case 6:
2557                switch (crm) {
2558                  case 0:
2559                    switch (op2) {
2560                      case 0:
2561                        return MISCREG_VBAR_EL3;
2562                      case 1:
2563                        return MISCREG_RVBAR_EL3;
2564                      case 2:
2565                        return MISCREG_RMR_EL3;
2566                    }
2567                    break;
2568                  case 12:
2569                    switch (op2) {
2570                      case 4:
2571                        return MISCREG_ICC_CTLR_EL3;
2572                      case 5:
2573                        return MISCREG_ICC_SRE_EL3;
2574                      case 7:
2575                        return MISCREG_ICC_IGRPEN1_EL3;
2576                    }
2577                    break;
2578                }
2579                break;
2580            }
2581            break;
2582          case 13:
2583            switch (op1) {
2584              case 0:
2585                switch (crm) {
2586                  case 0:
2587                    switch (op2) {
2588                      case 1:
2589                        return MISCREG_CONTEXTIDR_EL1;
2590                      case 4:
2591                        return MISCREG_TPIDR_EL1;
2592                    }
2593                    break;
2594                }
2595                break;
2596              case 3:
2597                switch (crm) {
2598                  case 0:
2599                    switch (op2) {
2600                      case 2:
2601                        return MISCREG_TPIDR_EL0;
2602                      case 3:
2603                        return MISCREG_TPIDRRO_EL0;
2604                    }
2605                    break;
2606                }
2607                break;
2608              case 4:
2609                switch (crm) {
2610                  case 0:
2611                    switch (op2) {
2612                      case 1:
2613                        return MISCREG_CONTEXTIDR_EL2;
2614                      case 2:
2615                        return MISCREG_TPIDR_EL2;
2616                    }
2617                    break;
2618                }
2619                break;
2620              case 6:
2621                switch (crm) {
2622                  case 0:
2623                    switch (op2) {
2624                      case 2:
2625                        return MISCREG_TPIDR_EL3;
2626                    }
2627                    break;
2628                }
2629                break;
2630            }
2631            break;
2632          case 14:
2633            switch (op1) {
2634              case 0:
2635                switch (crm) {
2636                  case 1:
2637                    switch (op2) {
2638                      case 0:
2639                        return MISCREG_CNTKCTL_EL1;
2640                    }
2641                    break;
2642                }
2643                break;
2644              case 3:
2645                switch (crm) {
2646                  case 0:
2647                    switch (op2) {
2648                      case 0:
2649                        return MISCREG_CNTFRQ_EL0;
2650                      case 1:
2651                        return MISCREG_CNTPCT_EL0;
2652                      case 2:
2653                        return MISCREG_CNTVCT_EL0;
2654                    }
2655                    break;
2656                  case 2:
2657                    switch (op2) {
2658                      case 0:
2659                        return MISCREG_CNTP_TVAL_EL0;
2660                      case 1:
2661                        return MISCREG_CNTP_CTL_EL0;
2662                      case 2:
2663                        return MISCREG_CNTP_CVAL_EL0;
2664                    }
2665                    break;
2666                  case 3:
2667                    switch (op2) {
2668                      case 0:
2669                        return MISCREG_CNTV_TVAL_EL0;
2670                      case 1:
2671                        return MISCREG_CNTV_CTL_EL0;
2672                      case 2:
2673                        return MISCREG_CNTV_CVAL_EL0;
2674                    }
2675                    break;
2676                  case 8:
2677                    switch (op2) {
2678                      case 0:
2679                        return MISCREG_PMEVCNTR0_EL0;
2680                      case 1:
2681                        return MISCREG_PMEVCNTR1_EL0;
2682                      case 2:
2683                        return MISCREG_PMEVCNTR2_EL0;
2684                      case 3:
2685                        return MISCREG_PMEVCNTR3_EL0;
2686                      case 4:
2687                        return MISCREG_PMEVCNTR4_EL0;
2688                      case 5:
2689                        return MISCREG_PMEVCNTR5_EL0;
2690                    }
2691                    break;
2692                  case 12:
2693                    switch (op2) {
2694                      case 0:
2695                        return MISCREG_PMEVTYPER0_EL0;
2696                      case 1:
2697                        return MISCREG_PMEVTYPER1_EL0;
2698                      case 2:
2699                        return MISCREG_PMEVTYPER2_EL0;
2700                      case 3:
2701                        return MISCREG_PMEVTYPER3_EL0;
2702                      case 4:
2703                        return MISCREG_PMEVTYPER4_EL0;
2704                      case 5:
2705                        return MISCREG_PMEVTYPER5_EL0;
2706                    }
2707                    break;
2708                  case 15:
2709                    switch (op2) {
2710                      case 7:
2711                        return MISCREG_PMCCFILTR_EL0;
2712                    }
2713                }
2714                break;
2715              case 4:
2716                switch (crm) {
2717                  case 0:
2718                    switch (op2) {
2719                      case 3:
2720                        return MISCREG_CNTVOFF_EL2;
2721                    }
2722                    break;
2723                  case 1:
2724                    switch (op2) {
2725                      case 0:
2726                        return MISCREG_CNTHCTL_EL2;
2727                    }
2728                    break;
2729                  case 2:
2730                    switch (op2) {
2731                      case 0:
2732                        return MISCREG_CNTHP_TVAL_EL2;
2733                      case 1:
2734                        return MISCREG_CNTHP_CTL_EL2;
2735                      case 2:
2736                        return MISCREG_CNTHP_CVAL_EL2;
2737                    }
2738                    break;
2739                  case 3:
2740                    switch (op2) {
2741                      case 0:
2742                        return MISCREG_CNTHV_TVAL_EL2;
2743                      case 1:
2744                        return MISCREG_CNTHV_CTL_EL2;
2745                      case 2:
2746                        return MISCREG_CNTHV_CVAL_EL2;
2747                    }
2748                    break;
2749                }
2750                break;
2751              case 7:
2752                switch (crm) {
2753                  case 2:
2754                    switch (op2) {
2755                      case 0:
2756                        return MISCREG_CNTPS_TVAL_EL1;
2757                      case 1:
2758                        return MISCREG_CNTPS_CTL_EL1;
2759                      case 2:
2760                        return MISCREG_CNTPS_CVAL_EL1;
2761                    }
2762                    break;
2763                }
2764                break;
2765            }
2766            break;
2767          case 15:
2768            switch (op1) {
2769              case 0:
2770                switch (crm) {
2771                  case 0:
2772                    switch (op2) {
2773                      case 0:
2774                        return MISCREG_IL1DATA0_EL1;
2775                      case 1:
2776                        return MISCREG_IL1DATA1_EL1;
2777                      case 2:
2778                        return MISCREG_IL1DATA2_EL1;
2779                      case 3:
2780                        return MISCREG_IL1DATA3_EL1;
2781                    }
2782                    break;
2783                  case 1:
2784                    switch (op2) {
2785                      case 0:
2786                        return MISCREG_DL1DATA0_EL1;
2787                      case 1:
2788                        return MISCREG_DL1DATA1_EL1;
2789                      case 2:
2790                        return MISCREG_DL1DATA2_EL1;
2791                      case 3:
2792                        return MISCREG_DL1DATA3_EL1;
2793                      case 4:
2794                        return MISCREG_DL1DATA4_EL1;
2795                    }
2796                    break;
2797                }
2798                break;
2799              case 1:
2800                switch (crm) {
2801                  case 0:
2802                    switch (op2) {
2803                      case 0:
2804                        return MISCREG_L2ACTLR_EL1;
2805                    }
2806                    break;
2807                  case 2:
2808                    switch (op2) {
2809                      case 0:
2810                        return MISCREG_CPUACTLR_EL1;
2811                      case 1:
2812                        return MISCREG_CPUECTLR_EL1;
2813                      case 2:
2814                        return MISCREG_CPUMERRSR_EL1;
2815                      case 3:
2816                        return MISCREG_L2MERRSR_EL1;
2817                    }
2818                    break;
2819                  case 3:
2820                    switch (op2) {
2821                      case 0:
2822                        return MISCREG_CBAR_EL1;
2823
2824                    }
2825                    break;
2826                }
2827                break;
2828            }
2829            // S3_<op1>_15_<Cm>_<op2>
2830            return MISCREG_IMPDEF_UNIMPL;
2831        }
2832        break;
2833    }
2834
2835    return MISCREG_UNKNOWN;
2836}
2837
2838bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2839
2840void
2841ISA::initializeMiscRegMetadata()
2842{
2843    // the MiscReg metadata tables are shared across all instances of the
2844    // ISA object, so there's no need to initialize them multiple times.
2845    static bool completed = false;
2846    if (completed)
2847        return;
2848
2849    // This boolean variable specifies if the system is running in aarch32 at
2850    // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2851    // is running in aarch64 (aarch32EL3 = false)
2852    bool aarch32EL3 = haveSecurity && !highestELIs64;
2853
2854    // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2855    // unsupported
2856    bool SPAN = false;
2857
2858    // Implicit error synchronization event enable (Arm 8.2+), unsupported
2859    bool IESB = false;
2860
2861    // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2862    // unsupported
2863    bool LSMAOE = false;
2864
2865    // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2866    bool nTLSMD = false;
2867
2868    // Pointer authentication (Arm 8.3+), unsupported
2869    bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2870    bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2871    bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2872    bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2873
2874    /**
2875     * Some registers alias with others, and therefore need to be translated.
2876     * When two mapping registers are given, they are the 32b lower and
2877     * upper halves, respectively, of the 64b register being mapped.
2878     * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2879     *
2880     * NAM = "not architecturally mandated",
2881     * from ARM DDI 0487A.i, template text
2882     * "AArch64 System register ___ can be mapped to
2883     *  AArch32 System register ___, but this is not
2884     *  architecturally mandated."
2885     */
2886
2887    InitReg(MISCREG_CPSR)
2888      .allPrivileges();
2889    InitReg(MISCREG_SPSR)
2890      .allPrivileges();
2891    InitReg(MISCREG_SPSR_FIQ)
2892      .allPrivileges();
2893    InitReg(MISCREG_SPSR_IRQ)
2894      .allPrivileges();
2895    InitReg(MISCREG_SPSR_SVC)
2896      .allPrivileges();
2897    InitReg(MISCREG_SPSR_MON)
2898      .allPrivileges();
2899    InitReg(MISCREG_SPSR_ABT)
2900      .allPrivileges();
2901    InitReg(MISCREG_SPSR_HYP)
2902      .allPrivileges();
2903    InitReg(MISCREG_SPSR_UND)
2904      .allPrivileges();
2905    InitReg(MISCREG_ELR_HYP)
2906      .allPrivileges();
2907    InitReg(MISCREG_FPSID)
2908      .allPrivileges();
2909    InitReg(MISCREG_FPSCR)
2910      .allPrivileges();
2911    InitReg(MISCREG_MVFR1)
2912      .allPrivileges();
2913    InitReg(MISCREG_MVFR0)
2914      .allPrivileges();
2915    InitReg(MISCREG_FPEXC)
2916      .allPrivileges();
2917
2918    // Helper registers
2919    InitReg(MISCREG_CPSR_MODE)
2920      .allPrivileges();
2921    InitReg(MISCREG_CPSR_Q)
2922      .allPrivileges();
2923    InitReg(MISCREG_FPSCR_EXC)
2924      .allPrivileges();
2925    InitReg(MISCREG_FPSCR_QC)
2926      .allPrivileges();
2927    InitReg(MISCREG_LOCKADDR)
2928      .allPrivileges();
2929    InitReg(MISCREG_LOCKFLAG)
2930      .allPrivileges();
2931    InitReg(MISCREG_PRRR_MAIR0)
2932      .mutex()
2933      .banked();
2934    InitReg(MISCREG_PRRR_MAIR0_NS)
2935      .mutex()
2936      .privSecure(!aarch32EL3)
2937      .bankedChild();
2938    InitReg(MISCREG_PRRR_MAIR0_S)
2939      .mutex()
2940      .bankedChild();
2941    InitReg(MISCREG_NMRR_MAIR1)
2942      .mutex()
2943      .banked();
2944    InitReg(MISCREG_NMRR_MAIR1_NS)
2945      .mutex()
2946      .privSecure(!aarch32EL3)
2947      .bankedChild();
2948    InitReg(MISCREG_NMRR_MAIR1_S)
2949      .mutex()
2950      .bankedChild();
2951    InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2952      .mutex();
2953    InitReg(MISCREG_SCTLR_RST)
2954      .allPrivileges();
2955    InitReg(MISCREG_SEV_MAILBOX)
2956      .allPrivileges();
2957
2958    // AArch32 CP14 registers
2959    InitReg(MISCREG_DBGDIDR)
2960      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2961    InitReg(MISCREG_DBGDSCRint)
2962      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2963    InitReg(MISCREG_DBGDCCINT)
2964      .unimplemented()
2965      .allPrivileges();
2966    InitReg(MISCREG_DBGDTRTXint)
2967      .unimplemented()
2968      .allPrivileges();
2969    InitReg(MISCREG_DBGDTRRXint)
2970      .unimplemented()
2971      .allPrivileges();
2972    InitReg(MISCREG_DBGWFAR)
2973      .unimplemented()
2974      .allPrivileges();
2975    InitReg(MISCREG_DBGVCR)
2976      .unimplemented()
2977      .allPrivileges();
2978    InitReg(MISCREG_DBGDTRRXext)
2979      .unimplemented()
2980      .allPrivileges();
2981    InitReg(MISCREG_DBGDSCRext)
2982      .unimplemented()
2983      .warnNotFail()
2984      .allPrivileges();
2985    InitReg(MISCREG_DBGDTRTXext)
2986      .unimplemented()
2987      .allPrivileges();
2988    InitReg(MISCREG_DBGOSECCR)
2989      .unimplemented()
2990      .allPrivileges();
2991    InitReg(MISCREG_DBGBVR0)
2992      .unimplemented()
2993      .allPrivileges();
2994    InitReg(MISCREG_DBGBVR1)
2995      .unimplemented()
2996      .allPrivileges();
2997    InitReg(MISCREG_DBGBVR2)
2998      .unimplemented()
2999      .allPrivileges();
3000    InitReg(MISCREG_DBGBVR3)
3001      .unimplemented()
3002      .allPrivileges();
3003    InitReg(MISCREG_DBGBVR4)
3004      .unimplemented()
3005      .allPrivileges();
3006    InitReg(MISCREG_DBGBVR5)
3007      .unimplemented()
3008      .allPrivileges();
3009    InitReg(MISCREG_DBGBCR0)
3010      .unimplemented()
3011      .allPrivileges();
3012    InitReg(MISCREG_DBGBCR1)
3013      .unimplemented()
3014      .allPrivileges();
3015    InitReg(MISCREG_DBGBCR2)
3016      .unimplemented()
3017      .allPrivileges();
3018    InitReg(MISCREG_DBGBCR3)
3019      .unimplemented()
3020      .allPrivileges();
3021    InitReg(MISCREG_DBGBCR4)
3022      .unimplemented()
3023      .allPrivileges();
3024    InitReg(MISCREG_DBGBCR5)
3025      .unimplemented()
3026      .allPrivileges();
3027    InitReg(MISCREG_DBGWVR0)
3028      .unimplemented()
3029      .allPrivileges();
3030    InitReg(MISCREG_DBGWVR1)
3031      .unimplemented()
3032      .allPrivileges();
3033    InitReg(MISCREG_DBGWVR2)
3034      .unimplemented()
3035      .allPrivileges();
3036    InitReg(MISCREG_DBGWVR3)
3037      .unimplemented()
3038      .allPrivileges();
3039    InitReg(MISCREG_DBGWCR0)
3040      .unimplemented()
3041      .allPrivileges();
3042    InitReg(MISCREG_DBGWCR1)
3043      .unimplemented()
3044      .allPrivileges();
3045    InitReg(MISCREG_DBGWCR2)
3046      .unimplemented()
3047      .allPrivileges();
3048    InitReg(MISCREG_DBGWCR3)
3049      .unimplemented()
3050      .allPrivileges();
3051    InitReg(MISCREG_DBGDRAR)
3052      .unimplemented()
3053      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3054    InitReg(MISCREG_DBGBXVR4)
3055      .unimplemented()
3056      .allPrivileges();
3057    InitReg(MISCREG_DBGBXVR5)
3058      .unimplemented()
3059      .allPrivileges();
3060    InitReg(MISCREG_DBGOSLAR)
3061      .unimplemented()
3062      .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3063    InitReg(MISCREG_DBGOSLSR)
3064      .unimplemented()
3065      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3066    InitReg(MISCREG_DBGOSDLR)
3067      .unimplemented()
3068      .allPrivileges();
3069    InitReg(MISCREG_DBGPRCR)
3070      .unimplemented()
3071      .allPrivileges();
3072    InitReg(MISCREG_DBGDSAR)
3073      .unimplemented()
3074      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3075    InitReg(MISCREG_DBGCLAIMSET)
3076      .unimplemented()
3077      .allPrivileges();
3078    InitReg(MISCREG_DBGCLAIMCLR)
3079      .unimplemented()
3080      .allPrivileges();
3081    InitReg(MISCREG_DBGAUTHSTATUS)
3082      .unimplemented()
3083      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3084    InitReg(MISCREG_DBGDEVID2)
3085      .unimplemented()
3086      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3087    InitReg(MISCREG_DBGDEVID1)
3088      .unimplemented()
3089      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3090    InitReg(MISCREG_DBGDEVID0)
3091      .unimplemented()
3092      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3093    InitReg(MISCREG_TEECR)
3094      .unimplemented()
3095      .allPrivileges();
3096    InitReg(MISCREG_JIDR)
3097      .allPrivileges();
3098    InitReg(MISCREG_TEEHBR)
3099      .allPrivileges();
3100    InitReg(MISCREG_JOSCR)
3101      .allPrivileges();
3102    InitReg(MISCREG_JMCR)
3103      .allPrivileges();
3104
3105    // AArch32 CP15 registers
3106    InitReg(MISCREG_MIDR)
3107      .allPrivileges().exceptUserMode().writes(0);
3108    InitReg(MISCREG_CTR)
3109      .allPrivileges().exceptUserMode().writes(0);
3110    InitReg(MISCREG_TCMTR)
3111      .allPrivileges().exceptUserMode().writes(0);
3112    InitReg(MISCREG_TLBTR)
3113      .allPrivileges().exceptUserMode().writes(0);
3114    InitReg(MISCREG_MPIDR)
3115      .allPrivileges().exceptUserMode().writes(0);
3116    InitReg(MISCREG_REVIDR)
3117      .unimplemented()
3118      .warnNotFail()
3119      .allPrivileges().exceptUserMode().writes(0);
3120    InitReg(MISCREG_ID_PFR0)
3121      .allPrivileges().exceptUserMode().writes(0);
3122    InitReg(MISCREG_ID_PFR1)
3123      .allPrivileges().exceptUserMode().writes(0);
3124    InitReg(MISCREG_ID_DFR0)
3125      .allPrivileges().exceptUserMode().writes(0);
3126    InitReg(MISCREG_ID_AFR0)
3127      .allPrivileges().exceptUserMode().writes(0);
3128    InitReg(MISCREG_ID_MMFR0)
3129      .allPrivileges().exceptUserMode().writes(0);
3130    InitReg(MISCREG_ID_MMFR1)
3131      .allPrivileges().exceptUserMode().writes(0);
3132    InitReg(MISCREG_ID_MMFR2)
3133      .allPrivileges().exceptUserMode().writes(0);
3134    InitReg(MISCREG_ID_MMFR3)
3135      .allPrivileges().exceptUserMode().writes(0);
3136    InitReg(MISCREG_ID_ISAR0)
3137      .allPrivileges().exceptUserMode().writes(0);
3138    InitReg(MISCREG_ID_ISAR1)
3139      .allPrivileges().exceptUserMode().writes(0);
3140    InitReg(MISCREG_ID_ISAR2)
3141      .allPrivileges().exceptUserMode().writes(0);
3142    InitReg(MISCREG_ID_ISAR3)
3143      .allPrivileges().exceptUserMode().writes(0);
3144    InitReg(MISCREG_ID_ISAR4)
3145      .allPrivileges().exceptUserMode().writes(0);
3146    InitReg(MISCREG_ID_ISAR5)
3147      .allPrivileges().exceptUserMode().writes(0);
3148    InitReg(MISCREG_CCSIDR)
3149      .allPrivileges().exceptUserMode().writes(0);
3150    InitReg(MISCREG_CLIDR)
3151      .allPrivileges().exceptUserMode().writes(0);
3152    InitReg(MISCREG_AIDR)
3153      .allPrivileges().exceptUserMode().writes(0);
3154    InitReg(MISCREG_CSSELR)
3155      .banked();
3156    InitReg(MISCREG_CSSELR_NS)
3157      .bankedChild()
3158      .privSecure(!aarch32EL3)
3159      .nonSecure().exceptUserMode();
3160    InitReg(MISCREG_CSSELR_S)
3161      .bankedChild()
3162      .secure().exceptUserMode();
3163    InitReg(MISCREG_VPIDR)
3164      .hyp().monNonSecure();
3165    InitReg(MISCREG_VMPIDR)
3166      .hyp().monNonSecure();
3167    InitReg(MISCREG_SCTLR)
3168      .banked()
3169      // readMiscRegNoEffect() uses this metadata
3170      // despite using children (below) as backing store
3171      .res0(0x8d22c600)
3172      .res1(0x00400800 | (SPAN   ? 0 : 0x800000)
3173                       | (LSMAOE ? 0 :     0x10)
3174                       | (nTLSMD ? 0 :      0x8));
3175    InitReg(MISCREG_SCTLR_NS)
3176      .bankedChild()
3177      .privSecure(!aarch32EL3)
3178      .nonSecure().exceptUserMode();
3179    InitReg(MISCREG_SCTLR_S)
3180      .bankedChild()
3181      .secure().exceptUserMode();
3182    InitReg(MISCREG_ACTLR)
3183      .banked();
3184    InitReg(MISCREG_ACTLR_NS)
3185      .bankedChild()
3186      .privSecure(!aarch32EL3)
3187      .nonSecure().exceptUserMode();
3188    InitReg(MISCREG_ACTLR_S)
3189      .bankedChild()
3190      .secure().exceptUserMode();
3191    InitReg(MISCREG_CPACR)
3192      .allPrivileges().exceptUserMode();
3193    InitReg(MISCREG_SCR)
3194      .mon().secure().exceptUserMode()
3195      .res0(0xff40)  // [31:16], [6]
3196      .res1(0x0030); // [5:4]
3197    InitReg(MISCREG_SDER)
3198      .mon();
3199    InitReg(MISCREG_NSACR)
3200      .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3201    InitReg(MISCREG_HSCTLR)
3202      .hyp().monNonSecure()
3203      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
3204                       | (IESB   ? 0 :   0x200000)
3205                       | (EnDA   ? 0 :  0x8000000)
3206                       | (EnIB   ? 0 : 0x40000000)
3207                       | (EnIA   ? 0 : 0x80000000))
3208      .res1(0x30c50830);
3209    InitReg(MISCREG_HACTLR)
3210      .hyp().monNonSecure();
3211    InitReg(MISCREG_HCR)
3212      .hyp().monNonSecure();
3213    InitReg(MISCREG_HDCR)
3214      .hyp().monNonSecure();
3215    InitReg(MISCREG_HCPTR)
3216      .hyp().monNonSecure();
3217    InitReg(MISCREG_HSTR)
3218      .hyp().monNonSecure();
3219    InitReg(MISCREG_HACR)
3220      .unimplemented()
3221      .warnNotFail()
3222      .hyp().monNonSecure();
3223    InitReg(MISCREG_TTBR0)
3224      .banked();
3225    InitReg(MISCREG_TTBR0_NS)
3226      .bankedChild()
3227      .privSecure(!aarch32EL3)
3228      .nonSecure().exceptUserMode();
3229    InitReg(MISCREG_TTBR0_S)
3230      .bankedChild()
3231      .secure().exceptUserMode();
3232    InitReg(MISCREG_TTBR1)
3233      .banked();
3234    InitReg(MISCREG_TTBR1_NS)
3235      .bankedChild()
3236      .privSecure(!aarch32EL3)
3237      .nonSecure().exceptUserMode();
3238    InitReg(MISCREG_TTBR1_S)
3239      .bankedChild()
3240      .secure().exceptUserMode();
3241    InitReg(MISCREG_TTBCR)
3242      .banked();
3243    InitReg(MISCREG_TTBCR_NS)
3244      .bankedChild()
3245      .privSecure(!aarch32EL3)
3246      .nonSecure().exceptUserMode();
3247    InitReg(MISCREG_TTBCR_S)
3248      .bankedChild()
3249      .secure().exceptUserMode();
3250    InitReg(MISCREG_HTCR)
3251      .hyp().monNonSecure();
3252    InitReg(MISCREG_VTCR)
3253      .hyp().monNonSecure();
3254    InitReg(MISCREG_DACR)
3255      .banked();
3256    InitReg(MISCREG_DACR_NS)
3257      .bankedChild()
3258      .privSecure(!aarch32EL3)
3259      .nonSecure().exceptUserMode();
3260    InitReg(MISCREG_DACR_S)
3261      .bankedChild()
3262      .secure().exceptUserMode();
3263    InitReg(MISCREG_DFSR)
3264      .banked();
3265    InitReg(MISCREG_DFSR_NS)
3266      .bankedChild()
3267      .privSecure(!aarch32EL3)
3268      .nonSecure().exceptUserMode();
3269    InitReg(MISCREG_DFSR_S)
3270      .bankedChild()
3271      .secure().exceptUserMode();
3272    InitReg(MISCREG_IFSR)
3273      .banked();
3274    InitReg(MISCREG_IFSR_NS)
3275      .bankedChild()
3276      .privSecure(!aarch32EL3)
3277      .nonSecure().exceptUserMode();
3278    InitReg(MISCREG_IFSR_S)
3279      .bankedChild()
3280      .secure().exceptUserMode();
3281    InitReg(MISCREG_ADFSR)
3282      .unimplemented()
3283      .warnNotFail()
3284      .banked();
3285    InitReg(MISCREG_ADFSR_NS)
3286      .unimplemented()
3287      .warnNotFail()
3288      .bankedChild()
3289      .privSecure(!aarch32EL3)
3290      .nonSecure().exceptUserMode();
3291    InitReg(MISCREG_ADFSR_S)
3292      .unimplemented()
3293      .warnNotFail()
3294      .bankedChild()
3295      .secure().exceptUserMode();
3296    InitReg(MISCREG_AIFSR)
3297      .unimplemented()
3298      .warnNotFail()
3299      .banked();
3300    InitReg(MISCREG_AIFSR_NS)
3301      .unimplemented()
3302      .warnNotFail()
3303      .bankedChild()
3304      .privSecure(!aarch32EL3)
3305      .nonSecure().exceptUserMode();
3306    InitReg(MISCREG_AIFSR_S)
3307      .unimplemented()
3308      .warnNotFail()
3309      .bankedChild()
3310      .secure().exceptUserMode();
3311    InitReg(MISCREG_HADFSR)
3312      .hyp().monNonSecure();
3313    InitReg(MISCREG_HAIFSR)
3314      .hyp().monNonSecure();
3315    InitReg(MISCREG_HSR)
3316      .hyp().monNonSecure();
3317    InitReg(MISCREG_DFAR)
3318      .banked();
3319    InitReg(MISCREG_DFAR_NS)
3320      .bankedChild()
3321      .privSecure(!aarch32EL3)
3322      .nonSecure().exceptUserMode();
3323    InitReg(MISCREG_DFAR_S)
3324      .bankedChild()
3325      .secure().exceptUserMode();
3326    InitReg(MISCREG_IFAR)
3327      .banked();
3328    InitReg(MISCREG_IFAR_NS)
3329      .bankedChild()
3330      .privSecure(!aarch32EL3)
3331      .nonSecure().exceptUserMode();
3332    InitReg(MISCREG_IFAR_S)
3333      .bankedChild()
3334      .secure().exceptUserMode();
3335    InitReg(MISCREG_HDFAR)
3336      .hyp().monNonSecure();
3337    InitReg(MISCREG_HIFAR)
3338      .hyp().monNonSecure();
3339    InitReg(MISCREG_HPFAR)
3340      .hyp().monNonSecure();
3341    InitReg(MISCREG_ICIALLUIS)
3342      .unimplemented()
3343      .warnNotFail()
3344      .writes(1).exceptUserMode();
3345    InitReg(MISCREG_BPIALLIS)
3346      .unimplemented()
3347      .warnNotFail()
3348      .writes(1).exceptUserMode();
3349    InitReg(MISCREG_PAR)
3350      .banked();
3351    InitReg(MISCREG_PAR_NS)
3352      .bankedChild()
3353      .privSecure(!aarch32EL3)
3354      .nonSecure().exceptUserMode();
3355    InitReg(MISCREG_PAR_S)
3356      .bankedChild()
3357      .secure().exceptUserMode();
3358    InitReg(MISCREG_ICIALLU)
3359      .writes(1).exceptUserMode();
3360    InitReg(MISCREG_ICIMVAU)
3361      .unimplemented()
3362      .warnNotFail()
3363      .writes(1).exceptUserMode();
3364    InitReg(MISCREG_CP15ISB)
3365      .writes(1);
3366    InitReg(MISCREG_BPIALL)
3367      .unimplemented()
3368      .warnNotFail()
3369      .writes(1).exceptUserMode();
3370    InitReg(MISCREG_BPIMVA)
3371      .unimplemented()
3372      .warnNotFail()
3373      .writes(1).exceptUserMode();
3374    InitReg(MISCREG_DCIMVAC)
3375      .unimplemented()
3376      .warnNotFail()
3377      .writes(1).exceptUserMode();
3378    InitReg(MISCREG_DCISW)
3379      .unimplemented()
3380      .warnNotFail()
3381      .writes(1).exceptUserMode();
3382    InitReg(MISCREG_ATS1CPR)
3383      .writes(1).exceptUserMode();
3384    InitReg(MISCREG_ATS1CPW)
3385      .writes(1).exceptUserMode();
3386    InitReg(MISCREG_ATS1CUR)
3387      .writes(1).exceptUserMode();
3388    InitReg(MISCREG_ATS1CUW)
3389      .writes(1).exceptUserMode();
3390    InitReg(MISCREG_ATS12NSOPR)
3391      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3392    InitReg(MISCREG_ATS12NSOPW)
3393      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3394    InitReg(MISCREG_ATS12NSOUR)
3395      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3396    InitReg(MISCREG_ATS12NSOUW)
3397      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3398    InitReg(MISCREG_DCCMVAC)
3399      .writes(1).exceptUserMode();
3400    InitReg(MISCREG_DCCSW)
3401      .unimplemented()
3402      .warnNotFail()
3403      .writes(1).exceptUserMode();
3404    InitReg(MISCREG_CP15DSB)
3405      .writes(1);
3406    InitReg(MISCREG_CP15DMB)
3407      .writes(1);
3408    InitReg(MISCREG_DCCMVAU)
3409      .unimplemented()
3410      .warnNotFail()
3411      .writes(1).exceptUserMode();
3412    InitReg(MISCREG_DCCIMVAC)
3413      .unimplemented()
3414      .warnNotFail()
3415      .writes(1).exceptUserMode();
3416    InitReg(MISCREG_DCCISW)
3417      .unimplemented()
3418      .warnNotFail()
3419      .writes(1).exceptUserMode();
3420    InitReg(MISCREG_ATS1HR)
3421      .monNonSecureWrite().hypWrite();
3422    InitReg(MISCREG_ATS1HW)
3423      .monNonSecureWrite().hypWrite();
3424    InitReg(MISCREG_TLBIALLIS)
3425      .writes(1).exceptUserMode();
3426    InitReg(MISCREG_TLBIMVAIS)
3427      .writes(1).exceptUserMode();
3428    InitReg(MISCREG_TLBIASIDIS)
3429      .writes(1).exceptUserMode();
3430    InitReg(MISCREG_TLBIMVAAIS)
3431      .writes(1).exceptUserMode();
3432    InitReg(MISCREG_TLBIMVALIS)
3433      .writes(1).exceptUserMode();
3434    InitReg(MISCREG_TLBIMVAALIS)
3435      .writes(1).exceptUserMode();
3436    InitReg(MISCREG_ITLBIALL)
3437      .writes(1).exceptUserMode();
3438    InitReg(MISCREG_ITLBIMVA)
3439      .writes(1).exceptUserMode();
3440    InitReg(MISCREG_ITLBIASID)
3441      .writes(1).exceptUserMode();
3442    InitReg(MISCREG_DTLBIALL)
3443      .writes(1).exceptUserMode();
3444    InitReg(MISCREG_DTLBIMVA)
3445      .writes(1).exceptUserMode();
3446    InitReg(MISCREG_DTLBIASID)
3447      .writes(1).exceptUserMode();
3448    InitReg(MISCREG_TLBIALL)
3449      .writes(1).exceptUserMode();
3450    InitReg(MISCREG_TLBIMVA)
3451      .writes(1).exceptUserMode();
3452    InitReg(MISCREG_TLBIASID)
3453      .writes(1).exceptUserMode();
3454    InitReg(MISCREG_TLBIMVAA)
3455      .writes(1).exceptUserMode();
3456    InitReg(MISCREG_TLBIMVAL)
3457      .writes(1).exceptUserMode();
3458    InitReg(MISCREG_TLBIMVAAL)
3459      .writes(1).exceptUserMode();
3460    InitReg(MISCREG_TLBIIPAS2IS)
3461      .monNonSecureWrite().hypWrite();
3462    InitReg(MISCREG_TLBIIPAS2LIS)
3463      .monNonSecureWrite().hypWrite();
3464    InitReg(MISCREG_TLBIALLHIS)
3465      .monNonSecureWrite().hypWrite();
3466    InitReg(MISCREG_TLBIMVAHIS)
3467      .monNonSecureWrite().hypWrite();
3468    InitReg(MISCREG_TLBIALLNSNHIS)
3469      .monNonSecureWrite().hypWrite();
3470    InitReg(MISCREG_TLBIMVALHIS)
3471      .monNonSecureWrite().hypWrite();
3472    InitReg(MISCREG_TLBIIPAS2)
3473      .monNonSecureWrite().hypWrite();
3474    InitReg(MISCREG_TLBIIPAS2L)
3475      .monNonSecureWrite().hypWrite();
3476    InitReg(MISCREG_TLBIALLH)
3477      .monNonSecureWrite().hypWrite();
3478    InitReg(MISCREG_TLBIMVAH)
3479      .monNonSecureWrite().hypWrite();
3480    InitReg(MISCREG_TLBIALLNSNH)
3481      .monNonSecureWrite().hypWrite();
3482    InitReg(MISCREG_TLBIMVALH)
3483      .monNonSecureWrite().hypWrite();
3484    InitReg(MISCREG_PMCR)
3485      .allPrivileges();
3486    InitReg(MISCREG_PMCNTENSET)
3487      .allPrivileges();
3488    InitReg(MISCREG_PMCNTENCLR)
3489      .allPrivileges();
3490    InitReg(MISCREG_PMOVSR)
3491      .allPrivileges();
3492    InitReg(MISCREG_PMSWINC)
3493      .allPrivileges();
3494    InitReg(MISCREG_PMSELR)
3495      .allPrivileges();
3496    InitReg(MISCREG_PMCEID0)
3497      .allPrivileges();
3498    InitReg(MISCREG_PMCEID1)
3499      .allPrivileges();
3500    InitReg(MISCREG_PMCCNTR)
3501      .allPrivileges();
3502    InitReg(MISCREG_PMXEVTYPER)
3503      .allPrivileges();
3504    InitReg(MISCREG_PMCCFILTR)
3505      .allPrivileges();
3506    InitReg(MISCREG_PMXEVCNTR)
3507      .allPrivileges();
3508    InitReg(MISCREG_PMUSERENR)
3509      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3510    InitReg(MISCREG_PMINTENSET)
3511      .allPrivileges().exceptUserMode();
3512    InitReg(MISCREG_PMINTENCLR)
3513      .allPrivileges().exceptUserMode();
3514    InitReg(MISCREG_PMOVSSET)
3515      .unimplemented()
3516      .allPrivileges();
3517    InitReg(MISCREG_L2CTLR)
3518      .allPrivileges().exceptUserMode();
3519    InitReg(MISCREG_L2ECTLR)
3520      .unimplemented()
3521      .allPrivileges().exceptUserMode();
3522    InitReg(MISCREG_PRRR)
3523      .banked();
3524    InitReg(MISCREG_PRRR_NS)
3525      .bankedChild()
3526      .privSecure(!aarch32EL3)
3527      .nonSecure().exceptUserMode();
3528    InitReg(MISCREG_PRRR_S)
3529      .bankedChild()
3530      .secure().exceptUserMode();
3531    InitReg(MISCREG_MAIR0)
3532      .banked();
3533    InitReg(MISCREG_MAIR0_NS)
3534      .bankedChild()
3535      .privSecure(!aarch32EL3)
3536      .nonSecure().exceptUserMode();
3537    InitReg(MISCREG_MAIR0_S)
3538      .bankedChild()
3539      .secure().exceptUserMode();
3540    InitReg(MISCREG_NMRR)
3541      .banked();
3542    InitReg(MISCREG_NMRR_NS)
3543      .bankedChild()
3544      .privSecure(!aarch32EL3)
3545      .nonSecure().exceptUserMode();
3546    InitReg(MISCREG_NMRR_S)
3547      .bankedChild()
3548      .secure().exceptUserMode();
3549    InitReg(MISCREG_MAIR1)
3550      .banked();
3551    InitReg(MISCREG_MAIR1_NS)
3552      .bankedChild()
3553      .privSecure(!aarch32EL3)
3554      .nonSecure().exceptUserMode();
3555    InitReg(MISCREG_MAIR1_S)
3556      .bankedChild()
3557      .secure().exceptUserMode();
3558    InitReg(MISCREG_AMAIR0)
3559      .banked();
3560    InitReg(MISCREG_AMAIR0_NS)
3561      .bankedChild()
3562      .privSecure(!aarch32EL3)
3563      .nonSecure().exceptUserMode();
3564    InitReg(MISCREG_AMAIR0_S)
3565      .bankedChild()
3566      .secure().exceptUserMode();
3567    InitReg(MISCREG_AMAIR1)
3568      .banked();
3569    InitReg(MISCREG_AMAIR1_NS)
3570      .bankedChild()
3571      .privSecure(!aarch32EL3)
3572      .nonSecure().exceptUserMode();
3573    InitReg(MISCREG_AMAIR1_S)
3574      .bankedChild()
3575      .secure().exceptUserMode();
3576    InitReg(MISCREG_HMAIR0)
3577      .hyp().monNonSecure();
3578    InitReg(MISCREG_HMAIR1)
3579      .hyp().monNonSecure();
3580    InitReg(MISCREG_HAMAIR0)
3581      .unimplemented()
3582      .warnNotFail()
3583      .hyp().monNonSecure();
3584    InitReg(MISCREG_HAMAIR1)
3585      .unimplemented()
3586      .warnNotFail()
3587      .hyp().monNonSecure();
3588    InitReg(MISCREG_VBAR)
3589      .banked();
3590    InitReg(MISCREG_VBAR_NS)
3591      .bankedChild()
3592      .privSecure(!aarch32EL3)
3593      .nonSecure().exceptUserMode();
3594    InitReg(MISCREG_VBAR_S)
3595      .bankedChild()
3596      .secure().exceptUserMode();
3597    InitReg(MISCREG_MVBAR)
3598      .mon().secure()
3599      .hypRead(FullSystem && system->highestEL() == EL2)
3600      .privRead(FullSystem && system->highestEL() == EL1)
3601      .exceptUserMode();
3602    InitReg(MISCREG_RMR)
3603      .unimplemented()
3604      .mon().secure().exceptUserMode();
3605    InitReg(MISCREG_ISR)
3606      .allPrivileges().exceptUserMode().writes(0);
3607    InitReg(MISCREG_HVBAR)
3608      .hyp().monNonSecure()
3609      .res0(0x1f);
3610    InitReg(MISCREG_FCSEIDR)
3611      .unimplemented()
3612      .warnNotFail()
3613      .allPrivileges().exceptUserMode();
3614    InitReg(MISCREG_CONTEXTIDR)
3615      .banked();
3616    InitReg(MISCREG_CONTEXTIDR_NS)
3617      .bankedChild()
3618      .privSecure(!aarch32EL3)
3619      .nonSecure().exceptUserMode();
3620    InitReg(MISCREG_CONTEXTIDR_S)
3621      .bankedChild()
3622      .secure().exceptUserMode();
3623    InitReg(MISCREG_TPIDRURW)
3624      .banked();
3625    InitReg(MISCREG_TPIDRURW_NS)
3626      .bankedChild()
3627      .allPrivileges()
3628      .privSecure(!aarch32EL3)
3629      .monSecure(0);
3630    InitReg(MISCREG_TPIDRURW_S)
3631      .bankedChild()
3632      .secure();
3633    InitReg(MISCREG_TPIDRURO)
3634      .banked();
3635    InitReg(MISCREG_TPIDRURO_NS)
3636      .bankedChild()
3637      .allPrivileges()
3638      .userNonSecureWrite(0).userSecureRead(1)
3639      .privSecure(!aarch32EL3)
3640      .monSecure(0);
3641    InitReg(MISCREG_TPIDRURO_S)
3642      .bankedChild()
3643      .secure().userSecureWrite(0);
3644    InitReg(MISCREG_TPIDRPRW)
3645      .banked();
3646    InitReg(MISCREG_TPIDRPRW_NS)
3647      .bankedChild()
3648      .nonSecure().exceptUserMode()
3649      .privSecure(!aarch32EL3);
3650    InitReg(MISCREG_TPIDRPRW_S)
3651      .bankedChild()
3652      .secure().exceptUserMode();
3653    InitReg(MISCREG_HTPIDR)
3654      .hyp().monNonSecure();
3655    InitReg(MISCREG_CNTFRQ)
3656      .unverifiable()
3657      .reads(1).mon();
3658    InitReg(MISCREG_CNTKCTL)
3659      .allPrivileges().exceptUserMode();
3660    InitReg(MISCREG_CNTP_TVAL)
3661      .banked();
3662    InitReg(MISCREG_CNTP_TVAL_NS)
3663      .bankedChild()
3664      .allPrivileges()
3665      .privSecure(!aarch32EL3)
3666      .monSecure(0);
3667    InitReg(MISCREG_CNTP_TVAL_S)
3668      .bankedChild()
3669      .secure().user(1);
3670    InitReg(MISCREG_CNTP_CTL)
3671      .banked();
3672    InitReg(MISCREG_CNTP_CTL_NS)
3673      .bankedChild()
3674      .allPrivileges()
3675      .privSecure(!aarch32EL3)
3676      .monSecure(0);
3677    InitReg(MISCREG_CNTP_CTL_S)
3678      .bankedChild()
3679      .secure().user(1);
3680    InitReg(MISCREG_CNTV_TVAL)
3681      .allPrivileges();
3682    InitReg(MISCREG_CNTV_CTL)
3683      .allPrivileges();
3684    InitReg(MISCREG_CNTHCTL)
3685      .hypWrite().monNonSecureRead();
3686    InitReg(MISCREG_CNTHP_TVAL)
3687      .hypWrite().monNonSecureRead();
3688    InitReg(MISCREG_CNTHP_CTL)
3689      .hypWrite().monNonSecureRead();
3690    InitReg(MISCREG_IL1DATA0)
3691      .unimplemented()
3692      .allPrivileges().exceptUserMode();
3693    InitReg(MISCREG_IL1DATA1)
3694      .unimplemented()
3695      .allPrivileges().exceptUserMode();
3696    InitReg(MISCREG_IL1DATA2)
3697      .unimplemented()
3698      .allPrivileges().exceptUserMode();
3699    InitReg(MISCREG_IL1DATA3)
3700      .unimplemented()
3701      .allPrivileges().exceptUserMode();
3702    InitReg(MISCREG_DL1DATA0)
3703      .unimplemented()
3704      .allPrivileges().exceptUserMode();
3705    InitReg(MISCREG_DL1DATA1)
3706      .unimplemented()
3707      .allPrivileges().exceptUserMode();
3708    InitReg(MISCREG_DL1DATA2)
3709      .unimplemented()
3710      .allPrivileges().exceptUserMode();
3711    InitReg(MISCREG_DL1DATA3)
3712      .unimplemented()
3713      .allPrivileges().exceptUserMode();
3714    InitReg(MISCREG_DL1DATA4)
3715      .unimplemented()
3716      .allPrivileges().exceptUserMode();
3717    InitReg(MISCREG_RAMINDEX)
3718      .unimplemented()
3719      .writes(1).exceptUserMode();
3720    InitReg(MISCREG_L2ACTLR)
3721      .unimplemented()
3722      .allPrivileges().exceptUserMode();
3723    InitReg(MISCREG_CBAR)
3724      .unimplemented()
3725      .allPrivileges().exceptUserMode().writes(0);
3726    InitReg(MISCREG_HTTBR)
3727      .hyp().monNonSecure();
3728    InitReg(MISCREG_VTTBR)
3729      .hyp().monNonSecure();
3730    InitReg(MISCREG_CNTPCT)
3731      .reads(1);
3732    InitReg(MISCREG_CNTVCT)
3733      .unverifiable()
3734      .reads(1);
3735    InitReg(MISCREG_CNTP_CVAL)
3736      .banked();
3737    InitReg(MISCREG_CNTP_CVAL_NS)
3738      .bankedChild()
3739      .allPrivileges()
3740      .privSecure(!aarch32EL3)
3741      .monSecure(0);
3742    InitReg(MISCREG_CNTP_CVAL_S)
3743      .bankedChild()
3744      .secure().user(1);
3745    InitReg(MISCREG_CNTV_CVAL)
3746      .allPrivileges();
3747    InitReg(MISCREG_CNTVOFF)
3748      .hyp().monNonSecure();
3749    InitReg(MISCREG_CNTHP_CVAL)
3750      .hypWrite().monNonSecureRead();
3751    InitReg(MISCREG_CPUMERRSR)
3752      .unimplemented()
3753      .allPrivileges().exceptUserMode();
3754    InitReg(MISCREG_L2MERRSR)
3755      .unimplemented()
3756      .warnNotFail()
3757      .allPrivileges().exceptUserMode();
3758
3759    // AArch64 registers (Op0=2);
3760    InitReg(MISCREG_MDCCINT_EL1)
3761      .allPrivileges();
3762    InitReg(MISCREG_OSDTRRX_EL1)
3763      .allPrivileges()
3764      .mapsTo(MISCREG_DBGDTRRXext);
3765    InitReg(MISCREG_MDSCR_EL1)
3766      .allPrivileges()
3767      .mapsTo(MISCREG_DBGDSCRext);
3768    InitReg(MISCREG_OSDTRTX_EL1)
3769      .allPrivileges()
3770      .mapsTo(MISCREG_DBGDTRTXext);
3771    InitReg(MISCREG_OSECCR_EL1)
3772      .allPrivileges()
3773      .mapsTo(MISCREG_DBGOSECCR);
3774    InitReg(MISCREG_DBGBVR0_EL1)
3775      .allPrivileges()
3776      .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3777    InitReg(MISCREG_DBGBVR1_EL1)
3778      .allPrivileges()
3779      .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3780    InitReg(MISCREG_DBGBVR2_EL1)
3781      .allPrivileges()
3782      .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3783    InitReg(MISCREG_DBGBVR3_EL1)
3784      .allPrivileges()
3785      .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3786    InitReg(MISCREG_DBGBVR4_EL1)
3787      .allPrivileges()
3788      .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3789    InitReg(MISCREG_DBGBVR5_EL1)
3790      .allPrivileges()
3791      .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3792    InitReg(MISCREG_DBGBCR0_EL1)
3793      .allPrivileges()
3794      .mapsTo(MISCREG_DBGBCR0);
3795    InitReg(MISCREG_DBGBCR1_EL1)
3796      .allPrivileges()
3797      .mapsTo(MISCREG_DBGBCR1);
3798    InitReg(MISCREG_DBGBCR2_EL1)
3799      .allPrivileges()
3800      .mapsTo(MISCREG_DBGBCR2);
3801    InitReg(MISCREG_DBGBCR3_EL1)
3802      .allPrivileges()
3803      .mapsTo(MISCREG_DBGBCR3);
3804    InitReg(MISCREG_DBGBCR4_EL1)
3805      .allPrivileges()
3806      .mapsTo(MISCREG_DBGBCR4);
3807    InitReg(MISCREG_DBGBCR5_EL1)
3808      .allPrivileges()
3809      .mapsTo(MISCREG_DBGBCR5);
3810    InitReg(MISCREG_DBGWVR0_EL1)
3811      .allPrivileges()
3812      .mapsTo(MISCREG_DBGWVR0);
3813    InitReg(MISCREG_DBGWVR1_EL1)
3814      .allPrivileges()
3815      .mapsTo(MISCREG_DBGWVR1);
3816    InitReg(MISCREG_DBGWVR2_EL1)
3817      .allPrivileges()
3818      .mapsTo(MISCREG_DBGWVR2);
3819    InitReg(MISCREG_DBGWVR3_EL1)
3820      .allPrivileges()
3821      .mapsTo(MISCREG_DBGWVR3);
3822    InitReg(MISCREG_DBGWCR0_EL1)
3823      .allPrivileges()
3824      .mapsTo(MISCREG_DBGWCR0);
3825    InitReg(MISCREG_DBGWCR1_EL1)
3826      .allPrivileges()
3827      .mapsTo(MISCREG_DBGWCR1);
3828    InitReg(MISCREG_DBGWCR2_EL1)
3829      .allPrivileges()
3830      .mapsTo(MISCREG_DBGWCR2);
3831    InitReg(MISCREG_DBGWCR3_EL1)
3832      .allPrivileges()
3833      .mapsTo(MISCREG_DBGWCR3);
3834    InitReg(MISCREG_MDCCSR_EL0)
3835      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3836      .mapsTo(MISCREG_DBGDSCRint);
3837    InitReg(MISCREG_MDDTR_EL0)
3838      .allPrivileges();
3839    InitReg(MISCREG_MDDTRTX_EL0)
3840      .allPrivileges();
3841    InitReg(MISCREG_MDDTRRX_EL0)
3842      .allPrivileges();
3843    InitReg(MISCREG_DBGVCR32_EL2)
3844      .allPrivileges()
3845      .mapsTo(MISCREG_DBGVCR);
3846    InitReg(MISCREG_MDRAR_EL1)
3847      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3848      .mapsTo(MISCREG_DBGDRAR);
3849    InitReg(MISCREG_OSLAR_EL1)
3850      .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3851      .mapsTo(MISCREG_DBGOSLAR);
3852    InitReg(MISCREG_OSLSR_EL1)
3853      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3854      .mapsTo(MISCREG_DBGOSLSR);
3855    InitReg(MISCREG_OSDLR_EL1)
3856      .allPrivileges()
3857      .mapsTo(MISCREG_DBGOSDLR);
3858    InitReg(MISCREG_DBGPRCR_EL1)
3859      .allPrivileges()
3860      .mapsTo(MISCREG_DBGPRCR);
3861    InitReg(MISCREG_DBGCLAIMSET_EL1)
3862      .allPrivileges()
3863      .mapsTo(MISCREG_DBGCLAIMSET);
3864    InitReg(MISCREG_DBGCLAIMCLR_EL1)
3865      .allPrivileges()
3866      .mapsTo(MISCREG_DBGCLAIMCLR);
3867    InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3868      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3869      .mapsTo(MISCREG_DBGAUTHSTATUS);
3870    InitReg(MISCREG_TEECR32_EL1);
3871    InitReg(MISCREG_TEEHBR32_EL1);
3872
3873    // AArch64 registers (Op0=1,3);
3874    InitReg(MISCREG_MIDR_EL1)
3875      .allPrivileges().exceptUserMode().writes(0);
3876    InitReg(MISCREG_MPIDR_EL1)
3877      .allPrivileges().exceptUserMode().writes(0);
3878    InitReg(MISCREG_REVIDR_EL1)
3879      .allPrivileges().exceptUserMode().writes(0);
3880    InitReg(MISCREG_ID_PFR0_EL1)
3881      .allPrivileges().exceptUserMode().writes(0)
3882      .mapsTo(MISCREG_ID_PFR0);
3883    InitReg(MISCREG_ID_PFR1_EL1)
3884      .allPrivileges().exceptUserMode().writes(0)
3885      .mapsTo(MISCREG_ID_PFR1);
3886    InitReg(MISCREG_ID_DFR0_EL1)
3887      .allPrivileges().exceptUserMode().writes(0)
3888      .mapsTo(MISCREG_ID_DFR0);
3889    InitReg(MISCREG_ID_AFR0_EL1)
3890      .allPrivileges().exceptUserMode().writes(0)
3891      .mapsTo(MISCREG_ID_AFR0);
3892    InitReg(MISCREG_ID_MMFR0_EL1)
3893      .allPrivileges().exceptUserMode().writes(0)
3894      .mapsTo(MISCREG_ID_MMFR0);
3895    InitReg(MISCREG_ID_MMFR1_EL1)
3896      .allPrivileges().exceptUserMode().writes(0)
3897      .mapsTo(MISCREG_ID_MMFR1);
3898    InitReg(MISCREG_ID_MMFR2_EL1)
3899      .allPrivileges().exceptUserMode().writes(0)
3900      .mapsTo(MISCREG_ID_MMFR2);
3901    InitReg(MISCREG_ID_MMFR3_EL1)
3902      .allPrivileges().exceptUserMode().writes(0)
3903      .mapsTo(MISCREG_ID_MMFR3);
3904    InitReg(MISCREG_ID_ISAR0_EL1)
3905      .allPrivileges().exceptUserMode().writes(0)
3906      .mapsTo(MISCREG_ID_ISAR0);
3907    InitReg(MISCREG_ID_ISAR1_EL1)
3908      .allPrivileges().exceptUserMode().writes(0)
3909      .mapsTo(MISCREG_ID_ISAR1);
3910    InitReg(MISCREG_ID_ISAR2_EL1)
3911      .allPrivileges().exceptUserMode().writes(0)
3912      .mapsTo(MISCREG_ID_ISAR2);
3913    InitReg(MISCREG_ID_ISAR3_EL1)
3914      .allPrivileges().exceptUserMode().writes(0)
3915      .mapsTo(MISCREG_ID_ISAR3);
3916    InitReg(MISCREG_ID_ISAR4_EL1)
3917      .allPrivileges().exceptUserMode().writes(0)
3918      .mapsTo(MISCREG_ID_ISAR4);
3919    InitReg(MISCREG_ID_ISAR5_EL1)
3920      .allPrivileges().exceptUserMode().writes(0)
3921      .mapsTo(MISCREG_ID_ISAR5);
3922    InitReg(MISCREG_MVFR0_EL1)
3923      .allPrivileges().exceptUserMode().writes(0);
3924    InitReg(MISCREG_MVFR1_EL1)
3925      .allPrivileges().exceptUserMode().writes(0);
3926    InitReg(MISCREG_MVFR2_EL1)
3927      .allPrivileges().exceptUserMode().writes(0);
3928    InitReg(MISCREG_ID_AA64PFR0_EL1)
3929      .allPrivileges().exceptUserMode().writes(0);
3930    InitReg(MISCREG_ID_AA64PFR1_EL1)
3931      .allPrivileges().exceptUserMode().writes(0);
3932    InitReg(MISCREG_ID_AA64DFR0_EL1)
3933      .allPrivileges().exceptUserMode().writes(0);
3934    InitReg(MISCREG_ID_AA64DFR1_EL1)
3935      .allPrivileges().exceptUserMode().writes(0);
3936    InitReg(MISCREG_ID_AA64AFR0_EL1)
3937      .allPrivileges().exceptUserMode().writes(0);
3938    InitReg(MISCREG_ID_AA64AFR1_EL1)
3939      .allPrivileges().exceptUserMode().writes(0);
3940    InitReg(MISCREG_ID_AA64ISAR0_EL1)
3941      .allPrivileges().exceptUserMode().writes(0);
3942    InitReg(MISCREG_ID_AA64ISAR1_EL1)
3943      .allPrivileges().exceptUserMode().writes(0);
3944    InitReg(MISCREG_ID_AA64MMFR0_EL1)
3945      .allPrivileges().exceptUserMode().writes(0);
3946    InitReg(MISCREG_ID_AA64MMFR1_EL1)
3947      .allPrivileges().exceptUserMode().writes(0);
3948    InitReg(MISCREG_ID_AA64MMFR2_EL1)
3949      .allPrivileges().exceptUserMode().writes(0);
3950    InitReg(MISCREG_CCSIDR_EL1)
3951      .allPrivileges().exceptUserMode().writes(0);
3952    InitReg(MISCREG_CLIDR_EL1)
3953      .allPrivileges().exceptUserMode().writes(0);
3954    InitReg(MISCREG_AIDR_EL1)
3955      .allPrivileges().exceptUserMode().writes(0);
3956    InitReg(MISCREG_CSSELR_EL1)
3957      .allPrivileges().exceptUserMode()
3958      .mapsTo(MISCREG_CSSELR_NS);
3959    InitReg(MISCREG_CTR_EL0)
3960      .reads(1);
3961    InitReg(MISCREG_DCZID_EL0)
3962      .reads(1);
3963    InitReg(MISCREG_VPIDR_EL2)
3964      .hyp().mon()
3965      .mapsTo(MISCREG_VPIDR);
3966    InitReg(MISCREG_VMPIDR_EL2)
3967      .hyp().mon()
3968      .mapsTo(MISCREG_VMPIDR);
3969    InitReg(MISCREG_SCTLR_EL1)
3970      .allPrivileges().exceptUserMode()
3971      .res0( 0x20440 | (EnDB   ? 0 :     0x2000)
3972                     | (IESB   ? 0 :   0x200000)
3973                     | (EnDA   ? 0 :  0x8000000)
3974                     | (EnIB   ? 0 : 0x40000000)
3975                     | (EnIA   ? 0 : 0x80000000))
3976      .res1(0x500800 | (SPAN   ? 0 :   0x800000)
3977                     | (nTLSMD ? 0 :  0x8000000)
3978                     | (LSMAOE ? 0 : 0x10000000))
3979      .mapsTo(MISCREG_SCTLR_NS);
3980    InitReg(MISCREG_ACTLR_EL1)
3981      .allPrivileges().exceptUserMode()
3982      .mapsTo(MISCREG_ACTLR_NS);
3983    InitReg(MISCREG_CPACR_EL1)
3984      .allPrivileges().exceptUserMode()
3985      .mapsTo(MISCREG_CPACR);
3986    InitReg(MISCREG_SCTLR_EL2)
3987      .hyp().mon()
3988      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
3989                       | (IESB   ? 0 :   0x200000)
3990                       | (EnDA   ? 0 :  0x8000000)
3991                       | (EnIB   ? 0 : 0x40000000)
3992                       | (EnIA   ? 0 : 0x80000000))
3993      .res1(0x30c50830)
3994      .mapsTo(MISCREG_HSCTLR);
3995    InitReg(MISCREG_ACTLR_EL2)
3996      .hyp().mon()
3997      .mapsTo(MISCREG_HACTLR);
3998    InitReg(MISCREG_HCR_EL2)
3999      .hyp().mon()
4000      .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
4001    InitReg(MISCREG_MDCR_EL2)
4002      .hyp().mon()
4003      .mapsTo(MISCREG_HDCR);
4004    InitReg(MISCREG_CPTR_EL2)
4005      .hyp().mon()
4006      .mapsTo(MISCREG_HCPTR);
4007    InitReg(MISCREG_HSTR_EL2)
4008      .hyp().mon()
4009      .mapsTo(MISCREG_HSTR);
4010    InitReg(MISCREG_HACR_EL2)
4011      .hyp().mon()
4012      .mapsTo(MISCREG_HACR);
4013    InitReg(MISCREG_SCTLR_EL3)
4014      .mon()
4015      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
4016                       | (IESB   ? 0 :   0x200000)
4017                       | (EnDA   ? 0 :  0x8000000)
4018                       | (EnIB   ? 0 : 0x40000000)
4019                       | (EnIA   ? 0 : 0x80000000))
4020      .res1(0x30c50830);
4021    InitReg(MISCREG_ACTLR_EL3)
4022      .mon();
4023    InitReg(MISCREG_SCR_EL3)
4024      .mon()
4025      .mapsTo(MISCREG_SCR); // NAM D7-2005
4026    InitReg(MISCREG_SDER32_EL3)
4027      .mon()
4028      .mapsTo(MISCREG_SDER);
4029    InitReg(MISCREG_CPTR_EL3)
4030      .mon();
4031    InitReg(MISCREG_MDCR_EL3)
4032      .mon();
4033    InitReg(MISCREG_TTBR0_EL1)
4034      .allPrivileges().exceptUserMode()
4035      .mapsTo(MISCREG_TTBR0_NS);
4036    InitReg(MISCREG_TTBR1_EL1)
4037      .allPrivileges().exceptUserMode()
4038      .mapsTo(MISCREG_TTBR1_NS);
4039    InitReg(MISCREG_TCR_EL1)
4040      .allPrivileges().exceptUserMode()
4041      .mapsTo(MISCREG_TTBCR_NS);
4042    InitReg(MISCREG_TTBR0_EL2)
4043      .hyp().mon()
4044      .mapsTo(MISCREG_HTTBR);
4045    InitReg(MISCREG_TTBR1_EL2)
4046      .hyp().mon();
4047    InitReg(MISCREG_TCR_EL2)
4048      .hyp().mon()
4049      .mapsTo(MISCREG_HTCR);
4050    InitReg(MISCREG_VTTBR_EL2)
4051      .hyp().mon()
4052      .mapsTo(MISCREG_VTTBR);
4053    InitReg(MISCREG_VTCR_EL2)
4054      .hyp().mon()
4055      .mapsTo(MISCREG_VTCR);
4056    InitReg(MISCREG_TTBR0_EL3)
4057      .mon();
4058    InitReg(MISCREG_TCR_EL3)
4059      .mon();
4060    InitReg(MISCREG_DACR32_EL2)
4061      .hyp().mon()
4062      .mapsTo(MISCREG_DACR_NS);
4063    InitReg(MISCREG_SPSR_EL1)
4064      .allPrivileges().exceptUserMode()
4065      .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4066    InitReg(MISCREG_ELR_EL1)
4067      .allPrivileges().exceptUserMode();
4068    InitReg(MISCREG_SP_EL0)
4069      .allPrivileges().exceptUserMode();
4070    InitReg(MISCREG_SPSEL)
4071      .allPrivileges().exceptUserMode();
4072    InitReg(MISCREG_CURRENTEL)
4073      .allPrivileges().exceptUserMode().writes(0);
4074    InitReg(MISCREG_PAN)
4075      .allPrivileges().exceptUserMode()
4076      .implemented(havePAN);
4077    InitReg(MISCREG_NZCV)
4078      .allPrivileges();
4079    InitReg(MISCREG_DAIF)
4080      .allPrivileges();
4081    InitReg(MISCREG_FPCR)
4082      .allPrivileges();
4083    InitReg(MISCREG_FPSR)
4084      .allPrivileges();
4085    InitReg(MISCREG_DSPSR_EL0)
4086      .allPrivileges();
4087    InitReg(MISCREG_DLR_EL0)
4088      .allPrivileges();
4089    InitReg(MISCREG_SPSR_EL2)
4090      .hyp().mon()
4091      .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4092    InitReg(MISCREG_ELR_EL2)
4093      .hyp().mon();
4094    InitReg(MISCREG_SP_EL1)
4095      .hyp().mon();
4096    InitReg(MISCREG_SPSR_IRQ_AA64)
4097      .hyp().mon();
4098    InitReg(MISCREG_SPSR_ABT_AA64)
4099      .hyp().mon();
4100    InitReg(MISCREG_SPSR_UND_AA64)
4101      .hyp().mon();
4102    InitReg(MISCREG_SPSR_FIQ_AA64)
4103      .hyp().mon();
4104    InitReg(MISCREG_SPSR_EL3)
4105      .mon()
4106      .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4107    InitReg(MISCREG_ELR_EL3)
4108      .mon();
4109    InitReg(MISCREG_SP_EL2)
4110      .mon();
4111    InitReg(MISCREG_AFSR0_EL1)
4112      .allPrivileges().exceptUserMode()
4113      .mapsTo(MISCREG_ADFSR_NS);
4114    InitReg(MISCREG_AFSR1_EL1)
4115      .allPrivileges().exceptUserMode()
4116      .mapsTo(MISCREG_AIFSR_NS);
4117    InitReg(MISCREG_ESR_EL1)
4118      .allPrivileges().exceptUserMode();
4119    InitReg(MISCREG_IFSR32_EL2)
4120      .hyp().mon()
4121      .mapsTo(MISCREG_IFSR_NS);
4122    InitReg(MISCREG_AFSR0_EL2)
4123      .hyp().mon()
4124      .mapsTo(MISCREG_HADFSR);
4125    InitReg(MISCREG_AFSR1_EL2)
4126      .hyp().mon()
4127      .mapsTo(MISCREG_HAIFSR);
4128    InitReg(MISCREG_ESR_EL2)
4129      .hyp().mon()
4130      .mapsTo(MISCREG_HSR);
4131    InitReg(MISCREG_FPEXC32_EL2)
4132      .hyp().mon().mapsTo(MISCREG_FPEXC);
4133    InitReg(MISCREG_AFSR0_EL3)
4134      .mon();
4135    InitReg(MISCREG_AFSR1_EL3)
4136      .mon();
4137    InitReg(MISCREG_ESR_EL3)
4138      .mon();
4139    InitReg(MISCREG_FAR_EL1)
4140      .allPrivileges().exceptUserMode()
4141      .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4142    InitReg(MISCREG_FAR_EL2)
4143      .hyp().mon()
4144      .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4145    InitReg(MISCREG_HPFAR_EL2)
4146      .hyp().mon()
4147      .mapsTo(MISCREG_HPFAR);
4148    InitReg(MISCREG_FAR_EL3)
4149      .mon();
4150    InitReg(MISCREG_IC_IALLUIS)
4151      .warnNotFail()
4152      .writes(1).exceptUserMode();
4153    InitReg(MISCREG_PAR_EL1)
4154      .allPrivileges().exceptUserMode()
4155      .mapsTo(MISCREG_PAR_NS);
4156    InitReg(MISCREG_IC_IALLU)
4157      .warnNotFail()
4158      .writes(1).exceptUserMode();
4159    InitReg(MISCREG_DC_IVAC_Xt)
4160      .warnNotFail()
4161      .writes(1).exceptUserMode();
4162    InitReg(MISCREG_DC_ISW_Xt)
4163      .warnNotFail()
4164      .writes(1).exceptUserMode();
4165    InitReg(MISCREG_AT_S1E1R_Xt)
4166      .writes(1).exceptUserMode();
4167    InitReg(MISCREG_AT_S1E1W_Xt)
4168      .writes(1).exceptUserMode();
4169    InitReg(MISCREG_AT_S1E0R_Xt)
4170      .writes(1).exceptUserMode();
4171    InitReg(MISCREG_AT_S1E0W_Xt)
4172      .writes(1).exceptUserMode();
4173    InitReg(MISCREG_DC_CSW_Xt)
4174      .warnNotFail()
4175      .writes(1).exceptUserMode();
4176    InitReg(MISCREG_DC_CISW_Xt)
4177      .warnNotFail()
4178      .writes(1).exceptUserMode();
4179    InitReg(MISCREG_DC_ZVA_Xt)
4180      .warnNotFail()
4181      .writes(1).userSecureWrite(0);
4182    InitReg(MISCREG_IC_IVAU_Xt)
4183      .writes(1);
4184    InitReg(MISCREG_DC_CVAC_Xt)
4185      .warnNotFail()
4186      .writes(1);
4187    InitReg(MISCREG_DC_CVAU_Xt)
4188      .warnNotFail()
4189      .writes(1);
4190    InitReg(MISCREG_DC_CIVAC_Xt)
4191      .warnNotFail()
4192      .writes(1);
4193    InitReg(MISCREG_AT_S1E2R_Xt)
4194      .monNonSecureWrite().hypWrite();
4195    InitReg(MISCREG_AT_S1E2W_Xt)
4196      .monNonSecureWrite().hypWrite();
4197    InitReg(MISCREG_AT_S12E1R_Xt)
4198      .hypWrite().monSecureWrite().monNonSecureWrite();
4199    InitReg(MISCREG_AT_S12E1W_Xt)
4200      .hypWrite().monSecureWrite().monNonSecureWrite();
4201    InitReg(MISCREG_AT_S12E0R_Xt)
4202      .hypWrite().monSecureWrite().monNonSecureWrite();
4203    InitReg(MISCREG_AT_S12E0W_Xt)
4204      .hypWrite().monSecureWrite().monNonSecureWrite();
4205    InitReg(MISCREG_AT_S1E3R_Xt)
4206      .monSecureWrite().monNonSecureWrite();
4207    InitReg(MISCREG_AT_S1E3W_Xt)
4208      .monSecureWrite().monNonSecureWrite();
4209    InitReg(MISCREG_TLBI_VMALLE1IS)
4210      .writes(1).exceptUserMode();
4211    InitReg(MISCREG_TLBI_VAE1IS_Xt)
4212      .writes(1).exceptUserMode();
4213    InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4214      .writes(1).exceptUserMode();
4215    InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4216      .writes(1).exceptUserMode();
4217    InitReg(MISCREG_TLBI_VALE1IS_Xt)
4218      .writes(1).exceptUserMode();
4219    InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4220      .writes(1).exceptUserMode();
4221    InitReg(MISCREG_TLBI_VMALLE1)
4222      .writes(1).exceptUserMode();
4223    InitReg(MISCREG_TLBI_VAE1_Xt)
4224      .writes(1).exceptUserMode();
4225    InitReg(MISCREG_TLBI_ASIDE1_Xt)
4226      .writes(1).exceptUserMode();
4227    InitReg(MISCREG_TLBI_VAAE1_Xt)
4228      .writes(1).exceptUserMode();
4229    InitReg(MISCREG_TLBI_VALE1_Xt)
4230      .writes(1).exceptUserMode();
4231    InitReg(MISCREG_TLBI_VAALE1_Xt)
4232      .writes(1).exceptUserMode();
4233    InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4234      .hypWrite().monSecureWrite().monNonSecureWrite();
4235    InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4236      .hypWrite().monSecureWrite().monNonSecureWrite();
4237    InitReg(MISCREG_TLBI_ALLE2IS)
4238      .monNonSecureWrite().hypWrite();
4239    InitReg(MISCREG_TLBI_VAE2IS_Xt)
4240      .monNonSecureWrite().hypWrite();
4241    InitReg(MISCREG_TLBI_ALLE1IS)
4242      .hypWrite().monSecureWrite().monNonSecureWrite();
4243    InitReg(MISCREG_TLBI_VALE2IS_Xt)
4244      .monNonSecureWrite().hypWrite();
4245    InitReg(MISCREG_TLBI_VMALLS12E1IS)
4246      .hypWrite().monSecureWrite().monNonSecureWrite();
4247    InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4248      .hypWrite().monSecureWrite().monNonSecureWrite();
4249    InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4250      .hypWrite().monSecureWrite().monNonSecureWrite();
4251    InitReg(MISCREG_TLBI_ALLE2)
4252      .monNonSecureWrite().hypWrite();
4253    InitReg(MISCREG_TLBI_VAE2_Xt)
4254      .monNonSecureWrite().hypWrite();
4255    InitReg(MISCREG_TLBI_ALLE1)
4256      .hypWrite().monSecureWrite().monNonSecureWrite();
4257    InitReg(MISCREG_TLBI_VALE2_Xt)
4258      .monNonSecureWrite().hypWrite();
4259    InitReg(MISCREG_TLBI_VMALLS12E1)
4260      .hypWrite().monSecureWrite().monNonSecureWrite();
4261    InitReg(MISCREG_TLBI_ALLE3IS)
4262      .monSecureWrite().monNonSecureWrite();
4263    InitReg(MISCREG_TLBI_VAE3IS_Xt)
4264      .monSecureWrite().monNonSecureWrite();
4265    InitReg(MISCREG_TLBI_VALE3IS_Xt)
4266      .monSecureWrite().monNonSecureWrite();
4267    InitReg(MISCREG_TLBI_ALLE3)
4268      .monSecureWrite().monNonSecureWrite();
4269    InitReg(MISCREG_TLBI_VAE3_Xt)
4270      .monSecureWrite().monNonSecureWrite();
4271    InitReg(MISCREG_TLBI_VALE3_Xt)
4272      .monSecureWrite().monNonSecureWrite();
4273    InitReg(MISCREG_PMINTENSET_EL1)
4274      .allPrivileges().exceptUserMode()
4275      .mapsTo(MISCREG_PMINTENSET);
4276    InitReg(MISCREG_PMINTENCLR_EL1)
4277      .allPrivileges().exceptUserMode()
4278      .mapsTo(MISCREG_PMINTENCLR);
4279    InitReg(MISCREG_PMCR_EL0)
4280      .allPrivileges()
4281      .mapsTo(MISCREG_PMCR);
4282    InitReg(MISCREG_PMCNTENSET_EL0)
4283      .allPrivileges()
4284      .mapsTo(MISCREG_PMCNTENSET);
4285    InitReg(MISCREG_PMCNTENCLR_EL0)
4286      .allPrivileges()
4287      .mapsTo(MISCREG_PMCNTENCLR);
4288    InitReg(MISCREG_PMOVSCLR_EL0)
4289      .allPrivileges();
4290//    .mapsTo(MISCREG_PMOVSCLR);
4291    InitReg(MISCREG_PMSWINC_EL0)
4292      .writes(1).user()
4293      .mapsTo(MISCREG_PMSWINC);
4294    InitReg(MISCREG_PMSELR_EL0)
4295      .allPrivileges()
4296      .mapsTo(MISCREG_PMSELR);
4297    InitReg(MISCREG_PMCEID0_EL0)
4298      .reads(1).user()
4299      .mapsTo(MISCREG_PMCEID0);
4300    InitReg(MISCREG_PMCEID1_EL0)
4301      .reads(1).user()
4302      .mapsTo(MISCREG_PMCEID1);
4303    InitReg(MISCREG_PMCCNTR_EL0)
4304      .allPrivileges()
4305      .mapsTo(MISCREG_PMCCNTR);
4306    InitReg(MISCREG_PMXEVTYPER_EL0)
4307      .allPrivileges()
4308      .mapsTo(MISCREG_PMXEVTYPER);
4309    InitReg(MISCREG_PMCCFILTR_EL0)
4310      .allPrivileges();
4311    InitReg(MISCREG_PMXEVCNTR_EL0)
4312      .allPrivileges()
4313      .mapsTo(MISCREG_PMXEVCNTR);
4314    InitReg(MISCREG_PMUSERENR_EL0)
4315      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4316      .mapsTo(MISCREG_PMUSERENR);
4317    InitReg(MISCREG_PMOVSSET_EL0)
4318      .allPrivileges()
4319      .mapsTo(MISCREG_PMOVSSET);
4320    InitReg(MISCREG_MAIR_EL1)
4321      .allPrivileges().exceptUserMode()
4322      .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4323    InitReg(MISCREG_AMAIR_EL1)
4324      .allPrivileges().exceptUserMode()
4325      .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4326    InitReg(MISCREG_MAIR_EL2)
4327      .hyp().mon()
4328      .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4329    InitReg(MISCREG_AMAIR_EL2)
4330      .hyp().mon()
4331      .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4332    InitReg(MISCREG_MAIR_EL3)
4333      .mon();
4334    InitReg(MISCREG_AMAIR_EL3)
4335      .mon();
4336    InitReg(MISCREG_L2CTLR_EL1)
4337      .allPrivileges().exceptUserMode();
4338    InitReg(MISCREG_L2ECTLR_EL1)
4339      .allPrivileges().exceptUserMode();
4340    InitReg(MISCREG_VBAR_EL1)
4341      .allPrivileges().exceptUserMode()
4342      .mapsTo(MISCREG_VBAR_NS);
4343    InitReg(MISCREG_RVBAR_EL1)
4344      .allPrivileges().exceptUserMode().writes(0);
4345    InitReg(MISCREG_ISR_EL1)
4346      .allPrivileges().exceptUserMode().writes(0);
4347    InitReg(MISCREG_VBAR_EL2)
4348      .hyp().mon()
4349      .res0(0x7ff)
4350      .mapsTo(MISCREG_HVBAR);
4351    InitReg(MISCREG_RVBAR_EL2)
4352      .mon().hyp().writes(0);
4353    InitReg(MISCREG_VBAR_EL3)
4354      .mon();
4355    InitReg(MISCREG_RVBAR_EL3)
4356      .mon().writes(0);
4357    InitReg(MISCREG_RMR_EL3)
4358      .mon();
4359    InitReg(MISCREG_CONTEXTIDR_EL1)
4360      .allPrivileges().exceptUserMode()
4361      .mapsTo(MISCREG_CONTEXTIDR_NS);
4362    InitReg(MISCREG_TPIDR_EL1)
4363      .allPrivileges().exceptUserMode()
4364      .mapsTo(MISCREG_TPIDRPRW_NS);
4365    InitReg(MISCREG_TPIDR_EL0)
4366      .allPrivileges()
4367      .mapsTo(MISCREG_TPIDRURW_NS);
4368    InitReg(MISCREG_TPIDRRO_EL0)
4369      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4370      .mapsTo(MISCREG_TPIDRURO_NS);
4371    InitReg(MISCREG_TPIDR_EL2)
4372      .hyp().mon()
4373      .mapsTo(MISCREG_HTPIDR);
4374    InitReg(MISCREG_TPIDR_EL3)
4375      .mon();
4376    InitReg(MISCREG_CNTKCTL_EL1)
4377      .allPrivileges().exceptUserMode()
4378      .mapsTo(MISCREG_CNTKCTL);
4379    InitReg(MISCREG_CNTFRQ_EL0)
4380      .reads(1).mon()
4381      .mapsTo(MISCREG_CNTFRQ);
4382    InitReg(MISCREG_CNTPCT_EL0)
4383      .reads(1)
4384      .mapsTo(MISCREG_CNTPCT); /* 64b */
4385    InitReg(MISCREG_CNTVCT_EL0)
4386      .unverifiable()
4387      .reads(1)
4388      .mapsTo(MISCREG_CNTVCT); /* 64b */
4389    InitReg(MISCREG_CNTP_TVAL_EL0)
4390      .allPrivileges()
4391      .mapsTo(MISCREG_CNTP_TVAL_NS);
4392    InitReg(MISCREG_CNTP_CTL_EL0)
4393      .allPrivileges()
4394      .mapsTo(MISCREG_CNTP_CTL_NS);
4395    InitReg(MISCREG_CNTP_CVAL_EL0)
4396      .allPrivileges()
4397      .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
4398    InitReg(MISCREG_CNTV_TVAL_EL0)
4399      .allPrivileges()
4400      .mapsTo(MISCREG_CNTV_TVAL);
4401    InitReg(MISCREG_CNTV_CTL_EL0)
4402      .allPrivileges()
4403      .mapsTo(MISCREG_CNTV_CTL);
4404    InitReg(MISCREG_CNTV_CVAL_EL0)
4405      .allPrivileges()
4406      .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4407    InitReg(MISCREG_PMEVCNTR0_EL0)
4408      .allPrivileges();
4409//    .mapsTo(MISCREG_PMEVCNTR0);
4410    InitReg(MISCREG_PMEVCNTR1_EL0)
4411      .allPrivileges();
4412//    .mapsTo(MISCREG_PMEVCNTR1);
4413    InitReg(MISCREG_PMEVCNTR2_EL0)
4414      .allPrivileges();
4415//    .mapsTo(MISCREG_PMEVCNTR2);
4416    InitReg(MISCREG_PMEVCNTR3_EL0)
4417      .allPrivileges();
4418//    .mapsTo(MISCREG_PMEVCNTR3);
4419    InitReg(MISCREG_PMEVCNTR4_EL0)
4420      .allPrivileges();
4421//    .mapsTo(MISCREG_PMEVCNTR4);
4422    InitReg(MISCREG_PMEVCNTR5_EL0)
4423      .allPrivileges();
4424//    .mapsTo(MISCREG_PMEVCNTR5);
4425    InitReg(MISCREG_PMEVTYPER0_EL0)
4426      .allPrivileges();
4427//    .mapsTo(MISCREG_PMEVTYPER0);
4428    InitReg(MISCREG_PMEVTYPER1_EL0)
4429      .allPrivileges();
4430//    .mapsTo(MISCREG_PMEVTYPER1);
4431    InitReg(MISCREG_PMEVTYPER2_EL0)
4432      .allPrivileges();
4433//    .mapsTo(MISCREG_PMEVTYPER2);
4434    InitReg(MISCREG_PMEVTYPER3_EL0)
4435      .allPrivileges();
4436//    .mapsTo(MISCREG_PMEVTYPER3);
4437    InitReg(MISCREG_PMEVTYPER4_EL0)
4438      .allPrivileges();
4439//    .mapsTo(MISCREG_PMEVTYPER4);
4440    InitReg(MISCREG_PMEVTYPER5_EL0)
4441      .allPrivileges();
4442//    .mapsTo(MISCREG_PMEVTYPER5);
4443    InitReg(MISCREG_CNTVOFF_EL2)
4444      .hyp().mon()
4445      .mapsTo(MISCREG_CNTVOFF); /* 64b */
4446    InitReg(MISCREG_CNTHCTL_EL2)
4447      .mon().hyp()
4448      .mapsTo(MISCREG_CNTHCTL);
4449    InitReg(MISCREG_CNTHP_TVAL_EL2)
4450      .mon().hyp()
4451      .mapsTo(MISCREG_CNTHP_TVAL);
4452    InitReg(MISCREG_CNTHP_CTL_EL2)
4453      .mon().hyp()
4454      .mapsTo(MISCREG_CNTHP_CTL);
4455    InitReg(MISCREG_CNTHP_CVAL_EL2)
4456      .mon().hyp()
4457      .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4458    InitReg(MISCREG_CNTPS_TVAL_EL1)
4459      .mon().privSecure();
4460    InitReg(MISCREG_CNTPS_CTL_EL1)
4461      .mon().privSecure();
4462    InitReg(MISCREG_CNTPS_CVAL_EL1)
4463      .mon().privSecure();
4464    InitReg(MISCREG_IL1DATA0_EL1)
4465      .allPrivileges().exceptUserMode();
4466    InitReg(MISCREG_IL1DATA1_EL1)
4467      .allPrivileges().exceptUserMode();
4468    InitReg(MISCREG_IL1DATA2_EL1)
4469      .allPrivileges().exceptUserMode();
4470    InitReg(MISCREG_IL1DATA3_EL1)
4471      .allPrivileges().exceptUserMode();
4472    InitReg(MISCREG_DL1DATA0_EL1)
4473      .allPrivileges().exceptUserMode();
4474    InitReg(MISCREG_DL1DATA1_EL1)
4475      .allPrivileges().exceptUserMode();
4476    InitReg(MISCREG_DL1DATA2_EL1)
4477      .allPrivileges().exceptUserMode();
4478    InitReg(MISCREG_DL1DATA3_EL1)
4479      .allPrivileges().exceptUserMode();
4480    InitReg(MISCREG_DL1DATA4_EL1)
4481      .allPrivileges().exceptUserMode();
4482    InitReg(MISCREG_L2ACTLR_EL1)
4483      .allPrivileges().exceptUserMode();
4484    InitReg(MISCREG_CPUACTLR_EL1)
4485      .allPrivileges().exceptUserMode();
4486    InitReg(MISCREG_CPUECTLR_EL1)
4487      .allPrivileges().exceptUserMode();
4488    InitReg(MISCREG_CPUMERRSR_EL1)
4489      .allPrivileges().exceptUserMode();
4490    InitReg(MISCREG_L2MERRSR_EL1)
4491      .unimplemented()
4492      .warnNotFail()
4493      .allPrivileges().exceptUserMode();
4494    InitReg(MISCREG_CBAR_EL1)
4495      .allPrivileges().exceptUserMode().writes(0);
4496    InitReg(MISCREG_CONTEXTIDR_EL2)
4497      .mon().hyp();
4498
4499    // GICv3 AArch64
4500    InitReg(MISCREG_ICC_PMR_EL1)
4501        .res0(0xffffff00) // [31:8]
4502        .allPrivileges().exceptUserMode()
4503        .mapsTo(MISCREG_ICC_PMR);
4504    InitReg(MISCREG_ICC_IAR0_EL1)
4505        .allPrivileges().exceptUserMode().writes(0)
4506        .mapsTo(MISCREG_ICC_IAR0);
4507    InitReg(MISCREG_ICC_EOIR0_EL1)
4508        .allPrivileges().exceptUserMode().reads(0)
4509        .mapsTo(MISCREG_ICC_EOIR0);
4510    InitReg(MISCREG_ICC_HPPIR0_EL1)
4511        .allPrivileges().exceptUserMode().writes(0)
4512        .mapsTo(MISCREG_ICC_HPPIR0);
4513    InitReg(MISCREG_ICC_BPR0_EL1)
4514        .res0(0xfffffff8) // [31:3]
4515        .allPrivileges().exceptUserMode()
4516        .mapsTo(MISCREG_ICC_BPR0);
4517    InitReg(MISCREG_ICC_AP0R0_EL1)
4518        .allPrivileges().exceptUserMode()
4519        .mapsTo(MISCREG_ICC_AP0R0);
4520    InitReg(MISCREG_ICC_AP0R1_EL1)
4521        .allPrivileges().exceptUserMode()
4522        .mapsTo(MISCREG_ICC_AP0R1);
4523    InitReg(MISCREG_ICC_AP0R2_EL1)
4524        .allPrivileges().exceptUserMode()
4525        .mapsTo(MISCREG_ICC_AP0R2);
4526    InitReg(MISCREG_ICC_AP0R3_EL1)
4527        .allPrivileges().exceptUserMode()
4528        .mapsTo(MISCREG_ICC_AP0R3);
4529    InitReg(MISCREG_ICC_AP1R0_EL1)
4530        .banked()
4531        .mapsTo(MISCREG_ICC_AP1R0);
4532    InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4533        .bankedChild()
4534        .allPrivileges().exceptUserMode()
4535        .mapsTo(MISCREG_ICC_AP1R0_NS);
4536    InitReg(MISCREG_ICC_AP1R0_EL1_S)
4537        .bankedChild()
4538        .allPrivileges().exceptUserMode()
4539        .mapsTo(MISCREG_ICC_AP1R0_S);
4540    InitReg(MISCREG_ICC_AP1R1_EL1)
4541        .banked()
4542        .mapsTo(MISCREG_ICC_AP1R1);
4543    InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4544        .bankedChild()
4545        .allPrivileges().exceptUserMode()
4546        .mapsTo(MISCREG_ICC_AP1R1_NS);
4547    InitReg(MISCREG_ICC_AP1R1_EL1_S)
4548        .bankedChild()
4549        .allPrivileges().exceptUserMode()
4550        .mapsTo(MISCREG_ICC_AP1R1_S);
4551    InitReg(MISCREG_ICC_AP1R2_EL1)
4552        .banked()
4553        .mapsTo(MISCREG_ICC_AP1R2);
4554    InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4555        .bankedChild()
4556        .allPrivileges().exceptUserMode()
4557        .mapsTo(MISCREG_ICC_AP1R2_NS);
4558    InitReg(MISCREG_ICC_AP1R2_EL1_S)
4559        .bankedChild()
4560        .allPrivileges().exceptUserMode()
4561        .mapsTo(MISCREG_ICC_AP1R2_S);
4562    InitReg(MISCREG_ICC_AP1R3_EL1)
4563        .banked()
4564        .mapsTo(MISCREG_ICC_AP1R3);
4565    InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4566        .bankedChild()
4567        .allPrivileges().exceptUserMode()
4568        .mapsTo(MISCREG_ICC_AP1R3_NS);
4569    InitReg(MISCREG_ICC_AP1R3_EL1_S)
4570        .bankedChild()
4571        .allPrivileges().exceptUserMode()
4572        .mapsTo(MISCREG_ICC_AP1R3_S);
4573    InitReg(MISCREG_ICC_DIR_EL1)
4574        .res0(0xFF000000) // [31:24]
4575        .allPrivileges().exceptUserMode().reads(0)
4576        .mapsTo(MISCREG_ICC_DIR);
4577    InitReg(MISCREG_ICC_RPR_EL1)
4578        .allPrivileges().exceptUserMode().writes(0)
4579        .mapsTo(MISCREG_ICC_RPR);
4580    InitReg(MISCREG_ICC_SGI1R_EL1)
4581        .allPrivileges().exceptUserMode().reads(0)
4582        .mapsTo(MISCREG_ICC_SGI1R);
4583    InitReg(MISCREG_ICC_ASGI1R_EL1)
4584        .allPrivileges().exceptUserMode().reads(0)
4585        .mapsTo(MISCREG_ICC_ASGI1R);
4586    InitReg(MISCREG_ICC_SGI0R_EL1)
4587        .allPrivileges().exceptUserMode().reads(0)
4588        .mapsTo(MISCREG_ICC_SGI0R);
4589    InitReg(MISCREG_ICC_IAR1_EL1)
4590        .allPrivileges().exceptUserMode().writes(0)
4591        .mapsTo(MISCREG_ICC_IAR1);
4592    InitReg(MISCREG_ICC_EOIR1_EL1)
4593        .res0(0xFF000000) // [31:24]
4594        .allPrivileges().exceptUserMode().reads(0)
4595        .mapsTo(MISCREG_ICC_EOIR1);
4596    InitReg(MISCREG_ICC_HPPIR1_EL1)
4597        .allPrivileges().exceptUserMode().writes(0)
4598        .mapsTo(MISCREG_ICC_HPPIR1);
4599    InitReg(MISCREG_ICC_BPR1_EL1)
4600        .banked()
4601        .mapsTo(MISCREG_ICC_BPR1);
4602    InitReg(MISCREG_ICC_BPR1_EL1_NS)
4603        .bankedChild()
4604        .res0(0xfffffff8) // [31:3]
4605        .allPrivileges().exceptUserMode()
4606        .mapsTo(MISCREG_ICC_BPR1_NS);
4607    InitReg(MISCREG_ICC_BPR1_EL1_S)
4608        .bankedChild()
4609        .res0(0xfffffff8) // [31:3]
4610        .secure().exceptUserMode()
4611        .mapsTo(MISCREG_ICC_BPR1_S);
4612    InitReg(MISCREG_ICC_CTLR_EL1)
4613        .banked()
4614        .mapsTo(MISCREG_ICC_CTLR);
4615    InitReg(MISCREG_ICC_CTLR_EL1_NS)
4616        .bankedChild()
4617        .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4618        .allPrivileges().exceptUserMode()
4619        .mapsTo(MISCREG_ICC_CTLR_NS);
4620    InitReg(MISCREG_ICC_CTLR_EL1_S)
4621        .bankedChild()
4622        .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4623        .secure().exceptUserMode()
4624        .mapsTo(MISCREG_ICC_CTLR_S);
4625    InitReg(MISCREG_ICC_SRE_EL1)
4626        .banked()
4627        .mapsTo(MISCREG_ICC_SRE);
4628    InitReg(MISCREG_ICC_SRE_EL1_NS)
4629        .bankedChild()
4630        .res0(0xFFFFFFF8) // [31:3]
4631        .allPrivileges().exceptUserMode()
4632        .mapsTo(MISCREG_ICC_SRE_NS);
4633    InitReg(MISCREG_ICC_SRE_EL1_S)
4634        .bankedChild()
4635        .res0(0xFFFFFFF8) // [31:3]
4636        .secure().exceptUserMode()
4637        .mapsTo(MISCREG_ICC_SRE_S);
4638    InitReg(MISCREG_ICC_IGRPEN0_EL1)
4639        .res0(0xFFFFFFFE) // [31:1]
4640        .allPrivileges().exceptUserMode()
4641        .mapsTo(MISCREG_ICC_IGRPEN0);
4642    InitReg(MISCREG_ICC_IGRPEN1_EL1)
4643        .banked()
4644        .mapsTo(MISCREG_ICC_IGRPEN1);
4645    InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4646        .bankedChild()
4647        .res0(0xFFFFFFFE) // [31:1]
4648        .allPrivileges().exceptUserMode()
4649        .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4650    InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4651        .bankedChild()
4652        .res0(0xFFFFFFFE) // [31:1]
4653        .secure().exceptUserMode()
4654        .mapsTo(MISCREG_ICC_IGRPEN1_S);
4655    InitReg(MISCREG_ICC_SRE_EL2)
4656        .hyp().mon()
4657        .mapsTo(MISCREG_ICC_HSRE);
4658    InitReg(MISCREG_ICC_CTLR_EL3)
4659        .allPrivileges().exceptUserMode()
4660        .mapsTo(MISCREG_ICC_MCTLR);
4661    InitReg(MISCREG_ICC_SRE_EL3)
4662        .allPrivileges().exceptUserMode()
4663        .mapsTo(MISCREG_ICC_MSRE);
4664    InitReg(MISCREG_ICC_IGRPEN1_EL3)
4665        .allPrivileges().exceptUserMode()
4666        .mapsTo(MISCREG_ICC_MGRPEN1);
4667
4668    InitReg(MISCREG_ICH_AP0R0_EL2)
4669        .hyp().mon()
4670        .mapsTo(MISCREG_ICH_AP0R0);
4671    InitReg(MISCREG_ICH_AP0R1_EL2)
4672        .hyp().mon()
4673        .unimplemented()
4674        .mapsTo(MISCREG_ICH_AP0R1);
4675    InitReg(MISCREG_ICH_AP0R2_EL2)
4676        .hyp().mon()
4677        .unimplemented()
4678        .mapsTo(MISCREG_ICH_AP0R2);
4679    InitReg(MISCREG_ICH_AP0R3_EL2)
4680        .hyp().mon()
4681        .unimplemented()
4682        .mapsTo(MISCREG_ICH_AP0R3);
4683    InitReg(MISCREG_ICH_AP1R0_EL2)
4684        .hyp().mon()
4685        .mapsTo(MISCREG_ICH_AP1R0);
4686    InitReg(MISCREG_ICH_AP1R1_EL2)
4687        .hyp().mon()
4688        .unimplemented()
4689        .mapsTo(MISCREG_ICH_AP1R1);
4690    InitReg(MISCREG_ICH_AP1R2_EL2)
4691        .hyp().mon()
4692        .unimplemented()
4693        .mapsTo(MISCREG_ICH_AP1R2);
4694    InitReg(MISCREG_ICH_AP1R3_EL2)
4695        .hyp().mon()
4696        .unimplemented()
4697        .mapsTo(MISCREG_ICH_AP1R3);
4698    InitReg(MISCREG_ICH_HCR_EL2)
4699        .hyp().mon()
4700        .mapsTo(MISCREG_ICH_HCR);
4701    InitReg(MISCREG_ICH_VTR_EL2)
4702        .hyp().mon().writes(0)
4703        .mapsTo(MISCREG_ICH_VTR);
4704    InitReg(MISCREG_ICH_MISR_EL2)
4705        .hyp().mon().writes(0)
4706        .mapsTo(MISCREG_ICH_MISR);
4707    InitReg(MISCREG_ICH_EISR_EL2)
4708        .hyp().mon().writes(0)
4709        .mapsTo(MISCREG_ICH_EISR);
4710    InitReg(MISCREG_ICH_ELRSR_EL2)
4711        .hyp().mon().writes(0)
4712        .mapsTo(MISCREG_ICH_ELRSR);
4713    InitReg(MISCREG_ICH_VMCR_EL2)
4714        .hyp().mon()
4715        .mapsTo(MISCREG_ICH_VMCR);
4716    InitReg(MISCREG_ICH_LR0_EL2)
4717        .hyp().mon()
4718        .allPrivileges().exceptUserMode();
4719    InitReg(MISCREG_ICH_LR1_EL2)
4720        .hyp().mon()
4721        .allPrivileges().exceptUserMode();
4722    InitReg(MISCREG_ICH_LR2_EL2)
4723        .hyp().mon()
4724        .allPrivileges().exceptUserMode();
4725    InitReg(MISCREG_ICH_LR3_EL2)
4726        .hyp().mon()
4727        .allPrivileges().exceptUserMode();
4728    InitReg(MISCREG_ICH_LR4_EL2)
4729        .hyp().mon()
4730        .allPrivileges().exceptUserMode();
4731    InitReg(MISCREG_ICH_LR5_EL2)
4732        .hyp().mon()
4733        .allPrivileges().exceptUserMode();
4734    InitReg(MISCREG_ICH_LR6_EL2)
4735        .hyp().mon()
4736        .allPrivileges().exceptUserMode();
4737    InitReg(MISCREG_ICH_LR7_EL2)
4738        .hyp().mon()
4739        .allPrivileges().exceptUserMode();
4740    InitReg(MISCREG_ICH_LR8_EL2)
4741        .hyp().mon()
4742        .allPrivileges().exceptUserMode();
4743    InitReg(MISCREG_ICH_LR9_EL2)
4744        .hyp().mon()
4745        .allPrivileges().exceptUserMode();
4746    InitReg(MISCREG_ICH_LR10_EL2)
4747        .hyp().mon()
4748        .allPrivileges().exceptUserMode();
4749    InitReg(MISCREG_ICH_LR11_EL2)
4750        .hyp().mon()
4751        .allPrivileges().exceptUserMode();
4752    InitReg(MISCREG_ICH_LR12_EL2)
4753        .hyp().mon()
4754        .allPrivileges().exceptUserMode();
4755    InitReg(MISCREG_ICH_LR13_EL2)
4756        .hyp().mon()
4757        .allPrivileges().exceptUserMode();
4758    InitReg(MISCREG_ICH_LR14_EL2)
4759        .hyp().mon()
4760        .allPrivileges().exceptUserMode();
4761    InitReg(MISCREG_ICH_LR15_EL2)
4762        .hyp().mon()
4763        .allPrivileges().exceptUserMode();
4764
4765    // GICv3 AArch32
4766    InitReg(MISCREG_ICC_AP0R0)
4767        .allPrivileges().exceptUserMode();
4768    InitReg(MISCREG_ICC_AP0R1)
4769        .allPrivileges().exceptUserMode();
4770    InitReg(MISCREG_ICC_AP0R2)
4771        .allPrivileges().exceptUserMode();
4772    InitReg(MISCREG_ICC_AP0R3)
4773        .allPrivileges().exceptUserMode();
4774    InitReg(MISCREG_ICC_AP1R0)
4775        .allPrivileges().exceptUserMode();
4776    InitReg(MISCREG_ICC_AP1R0_NS)
4777        .allPrivileges().exceptUserMode();
4778    InitReg(MISCREG_ICC_AP1R0_S)
4779        .allPrivileges().exceptUserMode();
4780    InitReg(MISCREG_ICC_AP1R1)
4781        .allPrivileges().exceptUserMode();
4782    InitReg(MISCREG_ICC_AP1R1_NS)
4783        .allPrivileges().exceptUserMode();
4784    InitReg(MISCREG_ICC_AP1R1_S)
4785        .allPrivileges().exceptUserMode();
4786    InitReg(MISCREG_ICC_AP1R2)
4787        .allPrivileges().exceptUserMode();
4788    InitReg(MISCREG_ICC_AP1R2_NS)
4789        .allPrivileges().exceptUserMode();
4790    InitReg(MISCREG_ICC_AP1R2_S)
4791        .allPrivileges().exceptUserMode();
4792    InitReg(MISCREG_ICC_AP1R3)
4793        .allPrivileges().exceptUserMode();
4794    InitReg(MISCREG_ICC_AP1R3_NS)
4795        .allPrivileges().exceptUserMode();
4796    InitReg(MISCREG_ICC_AP1R3_S)
4797        .allPrivileges().exceptUserMode();
4798    InitReg(MISCREG_ICC_ASGI1R)
4799        .allPrivileges().exceptUserMode().reads(0);
4800    InitReg(MISCREG_ICC_BPR0)
4801        .allPrivileges().exceptUserMode();
4802    InitReg(MISCREG_ICC_BPR1)
4803        .allPrivileges().exceptUserMode();
4804    InitReg(MISCREG_ICC_BPR1_NS)
4805        .allPrivileges().exceptUserMode();
4806    InitReg(MISCREG_ICC_BPR1_S)
4807        .allPrivileges().exceptUserMode();
4808    InitReg(MISCREG_ICC_CTLR)
4809        .allPrivileges().exceptUserMode();
4810    InitReg(MISCREG_ICC_CTLR_NS)
4811        .allPrivileges().exceptUserMode();
4812    InitReg(MISCREG_ICC_CTLR_S)
4813        .allPrivileges().exceptUserMode();
4814    InitReg(MISCREG_ICC_DIR)
4815        .allPrivileges().exceptUserMode().reads(0);
4816    InitReg(MISCREG_ICC_EOIR0)
4817        .allPrivileges().exceptUserMode().reads(0);
4818    InitReg(MISCREG_ICC_EOIR1)
4819        .allPrivileges().exceptUserMode().reads(0);
4820    InitReg(MISCREG_ICC_HPPIR0)
4821        .allPrivileges().exceptUserMode().writes(0);
4822    InitReg(MISCREG_ICC_HPPIR1)
4823        .allPrivileges().exceptUserMode().writes(0);
4824    InitReg(MISCREG_ICC_HSRE)
4825        .allPrivileges().exceptUserMode();
4826    InitReg(MISCREG_ICC_IAR0)
4827        .allPrivileges().exceptUserMode().writes(0);
4828    InitReg(MISCREG_ICC_IAR1)
4829        .allPrivileges().exceptUserMode().writes(0);
4830    InitReg(MISCREG_ICC_IGRPEN0)
4831        .allPrivileges().exceptUserMode();
4832    InitReg(MISCREG_ICC_IGRPEN1)
4833        .allPrivileges().exceptUserMode();
4834    InitReg(MISCREG_ICC_IGRPEN1_NS)
4835        .allPrivileges().exceptUserMode();
4836    InitReg(MISCREG_ICC_IGRPEN1_S)
4837        .allPrivileges().exceptUserMode();
4838    InitReg(MISCREG_ICC_MCTLR)
4839        .allPrivileges().exceptUserMode();
4840    InitReg(MISCREG_ICC_MGRPEN1)
4841        .allPrivileges().exceptUserMode();
4842    InitReg(MISCREG_ICC_MSRE)
4843        .allPrivileges().exceptUserMode();
4844    InitReg(MISCREG_ICC_PMR)
4845        .allPrivileges().exceptUserMode();
4846    InitReg(MISCREG_ICC_RPR)
4847        .allPrivileges().exceptUserMode().writes(0);
4848    InitReg(MISCREG_ICC_SGI0R)
4849        .allPrivileges().exceptUserMode().reads(0);
4850    InitReg(MISCREG_ICC_SGI1R)
4851        .allPrivileges().exceptUserMode().reads(0);
4852    InitReg(MISCREG_ICC_SRE)
4853        .allPrivileges().exceptUserMode();
4854    InitReg(MISCREG_ICC_SRE_NS)
4855        .allPrivileges().exceptUserMode();
4856    InitReg(MISCREG_ICC_SRE_S)
4857        .allPrivileges().exceptUserMode();
4858
4859    InitReg(MISCREG_ICH_AP0R0)
4860        .hyp().mon();
4861    InitReg(MISCREG_ICH_AP0R1)
4862        .hyp().mon();
4863    InitReg(MISCREG_ICH_AP0R2)
4864        .hyp().mon();
4865    InitReg(MISCREG_ICH_AP0R3)
4866        .hyp().mon();
4867    InitReg(MISCREG_ICH_AP1R0)
4868        .hyp().mon();
4869    InitReg(MISCREG_ICH_AP1R1)
4870        .hyp().mon();
4871    InitReg(MISCREG_ICH_AP1R2)
4872        .hyp().mon();
4873    InitReg(MISCREG_ICH_AP1R3)
4874        .hyp().mon();
4875    InitReg(MISCREG_ICH_HCR)
4876        .hyp().mon();
4877    InitReg(MISCREG_ICH_VTR)
4878        .hyp().mon().writes(0);
4879    InitReg(MISCREG_ICH_MISR)
4880        .hyp().mon().writes(0);
4881    InitReg(MISCREG_ICH_EISR)
4882        .hyp().mon().writes(0);
4883    InitReg(MISCREG_ICH_ELRSR)
4884        .hyp().mon().writes(0);
4885    InitReg(MISCREG_ICH_VMCR)
4886        .hyp().mon();
4887    InitReg(MISCREG_ICH_LR0)
4888        .hyp().mon();
4889    InitReg(MISCREG_ICH_LR1)
4890        .hyp().mon();
4891    InitReg(MISCREG_ICH_LR2)
4892        .hyp().mon();
4893    InitReg(MISCREG_ICH_LR3)
4894        .hyp().mon();
4895    InitReg(MISCREG_ICH_LR4)
4896        .hyp().mon();
4897    InitReg(MISCREG_ICH_LR5)
4898        .hyp().mon();
4899    InitReg(MISCREG_ICH_LR6)
4900        .hyp().mon();
4901    InitReg(MISCREG_ICH_LR7)
4902        .hyp().mon();
4903    InitReg(MISCREG_ICH_LR8)
4904        .hyp().mon();
4905    InitReg(MISCREG_ICH_LR9)
4906        .hyp().mon();
4907    InitReg(MISCREG_ICH_LR10)
4908        .hyp().mon();
4909    InitReg(MISCREG_ICH_LR11)
4910        .hyp().mon();
4911    InitReg(MISCREG_ICH_LR12)
4912        .hyp().mon();
4913    InitReg(MISCREG_ICH_LR13)
4914        .hyp().mon();
4915    InitReg(MISCREG_ICH_LR14)
4916        .hyp().mon();
4917    InitReg(MISCREG_ICH_LR15)
4918        .hyp().mon();
4919    InitReg(MISCREG_ICH_LRC0)
4920        .mapsTo(MISCREG_ICH_LR0)
4921        .hyp().mon();
4922    InitReg(MISCREG_ICH_LRC1)
4923        .mapsTo(MISCREG_ICH_LR1)
4924        .hyp().mon();
4925    InitReg(MISCREG_ICH_LRC2)
4926        .mapsTo(MISCREG_ICH_LR2)
4927        .hyp().mon();
4928    InitReg(MISCREG_ICH_LRC3)
4929        .mapsTo(MISCREG_ICH_LR3)
4930        .hyp().mon();
4931    InitReg(MISCREG_ICH_LRC4)
4932        .mapsTo(MISCREG_ICH_LR4)
4933        .hyp().mon();
4934    InitReg(MISCREG_ICH_LRC5)
4935        .mapsTo(MISCREG_ICH_LR5)
4936        .hyp().mon();
4937    InitReg(MISCREG_ICH_LRC6)
4938        .mapsTo(MISCREG_ICH_LR6)
4939        .hyp().mon();
4940    InitReg(MISCREG_ICH_LRC7)
4941        .mapsTo(MISCREG_ICH_LR7)
4942        .hyp().mon();
4943    InitReg(MISCREG_ICH_LRC8)
4944        .mapsTo(MISCREG_ICH_LR8)
4945        .hyp().mon();
4946    InitReg(MISCREG_ICH_LRC9)
4947        .mapsTo(MISCREG_ICH_LR9)
4948        .hyp().mon();
4949    InitReg(MISCREG_ICH_LRC10)
4950        .mapsTo(MISCREG_ICH_LR10)
4951        .hyp().mon();
4952    InitReg(MISCREG_ICH_LRC11)
4953        .mapsTo(MISCREG_ICH_LR11)
4954        .hyp().mon();
4955    InitReg(MISCREG_ICH_LRC12)
4956        .mapsTo(MISCREG_ICH_LR12)
4957        .hyp().mon();
4958    InitReg(MISCREG_ICH_LRC13)
4959        .mapsTo(MISCREG_ICH_LR13)
4960        .hyp().mon();
4961    InitReg(MISCREG_ICH_LRC14)
4962        .mapsTo(MISCREG_ICH_LR14)
4963        .hyp().mon();
4964    InitReg(MISCREG_ICH_LRC15)
4965        .mapsTo(MISCREG_ICH_LR15)
4966        .hyp().mon();
4967
4968    InitReg(MISCREG_CNTHV_CTL_EL2)
4969      .mon().hyp();
4970    InitReg(MISCREG_CNTHV_CVAL_EL2)
4971      .mon().hyp();
4972    InitReg(MISCREG_CNTHV_TVAL_EL2)
4973      .mon().hyp();
4974
4975    // SVE
4976    InitReg(MISCREG_ID_AA64ZFR0_EL1)
4977        .allPrivileges().exceptUserMode().writes(0);
4978    InitReg(MISCREG_ZCR_EL3)
4979        .mon();
4980    InitReg(MISCREG_ZCR_EL2)
4981        .hyp().mon();
4982    InitReg(MISCREG_ZCR_EL12)
4983        .unimplemented().warnNotFail();
4984    InitReg(MISCREG_ZCR_EL1)
4985        .allPrivileges().exceptUserMode();
4986
4987    // Dummy registers
4988    InitReg(MISCREG_NOP)
4989      .allPrivileges();
4990    InitReg(MISCREG_RAZ)
4991      .allPrivileges().exceptUserMode().writes(0);
4992    InitReg(MISCREG_CP14_UNIMPL)
4993      .unimplemented()
4994      .warnNotFail();
4995    InitReg(MISCREG_CP15_UNIMPL)
4996      .unimplemented()
4997      .warnNotFail();
4998    InitReg(MISCREG_UNKNOWN);
4999    InitReg(MISCREG_IMPDEF_UNIMPL)
5000      .unimplemented()
5001      .warnNotFail(impdefAsNop);
5002
5003    // RAS extension (unimplemented)
5004    InitReg(MISCREG_ERRIDR_EL1)
5005      .unimplemented()
5006      .warnNotFail();
5007    InitReg(MISCREG_ERRSELR_EL1)
5008      .unimplemented()
5009      .warnNotFail();
5010    InitReg(MISCREG_ERXFR_EL1)
5011      .unimplemented()
5012      .warnNotFail();
5013    InitReg(MISCREG_ERXCTLR_EL1)
5014      .unimplemented()
5015      .warnNotFail();
5016    InitReg(MISCREG_ERXSTATUS_EL1)
5017      .unimplemented()
5018      .warnNotFail();
5019    InitReg(MISCREG_ERXADDR_EL1)
5020      .unimplemented()
5021      .warnNotFail();
5022    InitReg(MISCREG_ERXMISC0_EL1)
5023      .unimplemented()
5024      .warnNotFail();
5025    InitReg(MISCREG_ERXMISC1_EL1)
5026      .unimplemented()
5027      .warnNotFail();
5028    InitReg(MISCREG_DISR_EL1)
5029      .unimplemented()
5030      .warnNotFail();
5031    InitReg(MISCREG_VSESR_EL2)
5032      .unimplemented()
5033      .warnNotFail();
5034    InitReg(MISCREG_VDISR_EL2)
5035      .unimplemented()
5036      .warnNotFail();
5037
5038    // Register mappings for some unimplemented registers:
5039    // ESR_EL1 -> DFSR
5040    // RMR_EL1 -> RMR
5041    // RMR_EL2 -> HRMR
5042    // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5043    // DBGDTRRX_EL0 -> DBGDTRRXint
5044    // DBGDTRTX_EL0 -> DBGDTRRXint
5045    // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5046
5047    completed = true;
5048}
5049
5050} // namespace ArmISA
5051