miscregs.cc revision 13759 
1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 *          Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57    switch(crn) {
58      case 0:
59        switch (opc1) {
60          case 0:
61            switch (opc2) {
62              case 0:
63                switch (crm) {
64                  case 0:
65                    return MISCREG_DBGDIDR;
66                  case 1:
67                    return MISCREG_DBGDSCRint;
68                }
69                break;
70            }
71            break;
72          case 7:
73            switch (opc2) {
74              case 0:
75                switch (crm) {
76                  case 0:
77                    return MISCREG_JIDR;
78                }
79              break;
80            }
81            break;
82        }
83        break;
84      case 1:
85        switch (opc1) {
86          case 6:
87            switch (crm) {
88              case 0:
89                switch (opc2) {
90                  case 0:
91                    return MISCREG_TEEHBR;
92                }
93                break;
94            }
95            break;
96          case 7:
97            switch (crm) {
98              case 0:
99                switch (opc2) {
100                  case 0:
101                    return MISCREG_JOSCR;
102                }
103                break;
104            }
105            break;
106        }
107        break;
108      case 2:
109        switch (opc1) {
110          case 7:
111            switch (crm) {
112              case 0:
113                switch (opc2) {
114                  case 0:
115                    return MISCREG_JMCR;
116                }
117                break;
118            }
119            break;
120        }
121        break;
122    }
123    // If we get here then it must be a register that we haven't implemented
124    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125         crn, opc1, crm, opc2);
126    return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134    switch (crn) {
135      case 0:
136        switch (opc1) {
137          case 0:
138            switch (crm) {
139              case 0:
140                switch (opc2) {
141                  case 1:
142                    return MISCREG_CTR;
143                  case 2:
144                    return MISCREG_TCMTR;
145                  case 3:
146                    return MISCREG_TLBTR;
147                  case 5:
148                    return MISCREG_MPIDR;
149                  case 6:
150                    return MISCREG_REVIDR;
151                  default:
152                    return MISCREG_MIDR;
153                }
154                break;
155              case 1:
156                switch (opc2) {
157                  case 0:
158                    return MISCREG_ID_PFR0;
159                  case 1:
160                    return MISCREG_ID_PFR1;
161                  case 2:
162                    return MISCREG_ID_DFR0;
163                  case 3:
164                    return MISCREG_ID_AFR0;
165                  case 4:
166                    return MISCREG_ID_MMFR0;
167                  case 5:
168                    return MISCREG_ID_MMFR1;
169                  case 6:
170                    return MISCREG_ID_MMFR2;
171                  case 7:
172                    return MISCREG_ID_MMFR3;
173                }
174                break;
175              case 2:
176                switch (opc2) {
177                  case 0:
178                    return MISCREG_ID_ISAR0;
179                  case 1:
180                    return MISCREG_ID_ISAR1;
181                  case 2:
182                    return MISCREG_ID_ISAR2;
183                  case 3:
184                    return MISCREG_ID_ISAR3;
185                  case 4:
186                    return MISCREG_ID_ISAR4;
187                  case 5:
188                    return MISCREG_ID_ISAR5;
189                  case 6:
190                  case 7:
191                    return MISCREG_RAZ; // read as zero
192                }
193                break;
194              default:
195                return MISCREG_RAZ; // read as zero
196            }
197            break;
198          case 1:
199            if (crm == 0) {
200                switch (opc2) {
201                  case 0:
202                    return MISCREG_CCSIDR;
203                  case 1:
204                    return MISCREG_CLIDR;
205                  case 7:
206                    return MISCREG_AIDR;
207                }
208            }
209            break;
210          case 2:
211            if (crm == 0 && opc2 == 0) {
212                return MISCREG_CSSELR;
213            }
214            break;
215          case 4:
216            if (crm == 0) {
217                if (opc2 == 0)
218                    return MISCREG_VPIDR;
219                else if (opc2 == 5)
220                    return MISCREG_VMPIDR;
221            }
222            break;
223        }
224        break;
225      case 1:
226        if (opc1 == 0) {
227            if (crm == 0) {
228                switch (opc2) {
229                  case 0:
230                    return MISCREG_SCTLR;
231                  case 1:
232                    return MISCREG_ACTLR;
233                  case 0x2:
234                    return MISCREG_CPACR;
235                }
236            } else if (crm == 1) {
237                switch (opc2) {
238                  case 0:
239                    return MISCREG_SCR;
240                  case 1:
241                    return MISCREG_SDER;
242                  case 2:
243                    return MISCREG_NSACR;
244                }
245            }
246        } else if (opc1 == 4) {
247            if (crm == 0) {
248                if (opc2 == 0)
249                    return MISCREG_HSCTLR;
250                else if (opc2 == 1)
251                    return MISCREG_HACTLR;
252            } else if (crm == 1) {
253                switch (opc2) {
254                  case 0:
255                    return MISCREG_HCR;
256                  case 1:
257                    return MISCREG_HDCR;
258                  case 2:
259                    return MISCREG_HCPTR;
260                  case 3:
261                    return MISCREG_HSTR;
262                  case 7:
263                    return MISCREG_HACR;
264                }
265            }
266        }
267        break;
268      case 2:
269        if (opc1 == 0 && crm == 0) {
270            switch (opc2) {
271              case 0:
272                return MISCREG_TTBR0;
273              case 1:
274                return MISCREG_TTBR1;
275              case 2:
276                return MISCREG_TTBCR;
277            }
278        } else if (opc1 == 4) {
279            if (crm == 0 && opc2 == 2)
280                return MISCREG_HTCR;
281            else if (crm == 1 && opc2 == 2)
282                return MISCREG_VTCR;
283        }
284        break;
285      case 3:
286        if (opc1 == 0 && crm == 0 && opc2 == 0) {
287            return MISCREG_DACR;
288        }
289        break;
290      case 4:
291        if (opc1 == 0 && crm == 6 && opc2 == 0) {
292            return MISCREG_ICC_PMR;
293        }
294        break;
295      case 5:
296        if (opc1 == 0) {
297            if (crm == 0) {
298                if (opc2 == 0) {
299                    return MISCREG_DFSR;
300                } else if (opc2 == 1) {
301                    return MISCREG_IFSR;
302                }
303            } else if (crm == 1) {
304                if (opc2 == 0) {
305                    return MISCREG_ADFSR;
306                } else if (opc2 == 1) {
307                    return MISCREG_AIFSR;
308                }
309            }
310        } else if (opc1 == 4) {
311            if (crm == 1) {
312                if (opc2 == 0)
313                    return MISCREG_HADFSR;
314                else if (opc2 == 1)
315                    return MISCREG_HAIFSR;
316            } else if (crm == 2 && opc2 == 0) {
317                return MISCREG_HSR;
318            }
319        }
320        break;
321      case 6:
322        if (opc1 == 0 && crm == 0) {
323            switch (opc2) {
324              case 0:
325                return MISCREG_DFAR;
326              case 2:
327                return MISCREG_IFAR;
328            }
329        } else if (opc1 == 4 && crm == 0) {
330            switch (opc2) {
331              case 0:
332                return MISCREG_HDFAR;
333              case 2:
334                return MISCREG_HIFAR;
335              case 4:
336                return MISCREG_HPFAR;
337            }
338        }
339        break;
340      case 7:
341        if (opc1 == 0) {
342            switch (crm) {
343              case 0:
344                if (opc2 == 4) {
345                    return MISCREG_NOP;
346                }
347                break;
348              case 1:
349                switch (opc2) {
350                  case 0:
351                    return MISCREG_ICIALLUIS;
352                  case 6:
353                    return MISCREG_BPIALLIS;
354                }
355                break;
356              case 4:
357                if (opc2 == 0) {
358                    return MISCREG_PAR;
359                }
360                break;
361              case 5:
362                switch (opc2) {
363                  case 0:
364                    return MISCREG_ICIALLU;
365                  case 1:
366                    return MISCREG_ICIMVAU;
367                  case 4:
368                    return MISCREG_CP15ISB;
369                  case 6:
370                    return MISCREG_BPIALL;
371                  case 7:
372                    return MISCREG_BPIMVA;
373                }
374                break;
375              case 6:
376                if (opc2 == 1) {
377                    return MISCREG_DCIMVAC;
378                } else if (opc2 == 2) {
379                    return MISCREG_DCISW;
380                }
381                break;
382              case 8:
383                switch (opc2) {
384                  case 0:
385                    return MISCREG_ATS1CPR;
386                  case 1:
387                    return MISCREG_ATS1CPW;
388                  case 2:
389                    return MISCREG_ATS1CUR;
390                  case 3:
391                    return MISCREG_ATS1CUW;
392                  case 4:
393                    return MISCREG_ATS12NSOPR;
394                  case 5:
395                    return MISCREG_ATS12NSOPW;
396                  case 6:
397                    return MISCREG_ATS12NSOUR;
398                  case 7:
399                    return MISCREG_ATS12NSOUW;
400                }
401                break;
402              case 10:
403                switch (opc2) {
404                  case 1:
405                    return MISCREG_DCCMVAC;
406                  case 2:
407                    return MISCREG_DCCSW;
408                  case 4:
409                    return MISCREG_CP15DSB;
410                  case 5:
411                    return MISCREG_CP15DMB;
412                }
413                break;
414              case 11:
415                if (opc2 == 1) {
416                    return MISCREG_DCCMVAU;
417                }
418                break;
419              case 13:
420                if (opc2 == 1) {
421                    return MISCREG_NOP;
422                }
423                break;
424              case 14:
425                if (opc2 == 1) {
426                    return MISCREG_DCCIMVAC;
427                } else if (opc2 == 2) {
428                    return MISCREG_DCCISW;
429                }
430                break;
431            }
432        } else if (opc1 == 4 && crm == 8) {
433            if (opc2 == 0)
434                return MISCREG_ATS1HR;
435            else if (opc2 == 1)
436                return MISCREG_ATS1HW;
437        }
438        break;
439      case 8:
440        if (opc1 == 0) {
441            switch (crm) {
442              case 3:
443                switch (opc2) {
444                  case 0:
445                    return MISCREG_TLBIALLIS;
446                  case 1:
447                    return MISCREG_TLBIMVAIS;
448                  case 2:
449                    return MISCREG_TLBIASIDIS;
450                  case 3:
451                    return MISCREG_TLBIMVAAIS;
452                  case 5:
453                    return MISCREG_TLBIMVALIS;
454                  case 7:
455                    return MISCREG_TLBIMVAALIS;
456                }
457                break;
458              case 5:
459                switch (opc2) {
460                  case 0:
461                    return MISCREG_ITLBIALL;
462                  case 1:
463                    return MISCREG_ITLBIMVA;
464                  case 2:
465                    return MISCREG_ITLBIASID;
466                }
467                break;
468              case 6:
469                switch (opc2) {
470                  case 0:
471                    return MISCREG_DTLBIALL;
472                  case 1:
473                    return MISCREG_DTLBIMVA;
474                  case 2:
475                    return MISCREG_DTLBIASID;
476                }
477                break;
478              case 7:
479                switch (opc2) {
480                  case 0:
481                    return MISCREG_TLBIALL;
482                  case 1:
483                    return MISCREG_TLBIMVA;
484                  case 2:
485                    return MISCREG_TLBIASID;
486                  case 3:
487                    return MISCREG_TLBIMVAA;
488                  case 5:
489                    return MISCREG_TLBIMVAL;
490                  case 7:
491                    return MISCREG_TLBIMVAAL;
492                }
493                break;
494            }
495        } else if (opc1 == 4) {
496            if (crm == 0) {
497                switch (opc2) {
498                  case 1:
499                    return MISCREG_TLBIIPAS2IS;
500                  case 5:
501                    return MISCREG_TLBIIPAS2LIS;
502                }
503            } else if (crm == 3) {
504                switch (opc2) {
505                  case 0:
506                    return MISCREG_TLBIALLHIS;
507                  case 1:
508                    return MISCREG_TLBIMVAHIS;
509                  case 4:
510                    return MISCREG_TLBIALLNSNHIS;
511                  case 5:
512                    return MISCREG_TLBIMVALHIS;
513                }
514            } else if (crm == 4) {
515                switch (opc2) {
516                  case 1:
517                    return MISCREG_TLBIIPAS2;
518                  case 5:
519                    return MISCREG_TLBIIPAS2L;
520                }
521            } else if (crm == 7) {
522                switch (opc2) {
523                  case 0:
524                    return MISCREG_TLBIALLH;
525                  case 1:
526                    return MISCREG_TLBIMVAH;
527                  case 4:
528                    return MISCREG_TLBIALLNSNH;
529                  case 5:
530                    return MISCREG_TLBIMVALH;
531                }
532            }
533        }
534        break;
535      case 9:
536        // Every cop register with CRn = 9 and CRm in
537        // {0-2}, {5-8} is implementation defined regardless
538        // of opc1 and opc2.
539        switch (crm) {
540          case 0:
541          case 1:
542          case 2:
543          case 5:
544          case 6:
545          case 7:
546          case 8:
547            return MISCREG_IMPDEF_UNIMPL;
548        }
549        if (opc1 == 0) {
550            switch (crm) {
551              case 12:
552                switch (opc2) {
553                  case 0:
554                    return MISCREG_PMCR;
555                  case 1:
556                    return MISCREG_PMCNTENSET;
557                  case 2:
558                    return MISCREG_PMCNTENCLR;
559                  case 3:
560                    return MISCREG_PMOVSR;
561                  case 4:
562                    return MISCREG_PMSWINC;
563                  case 5:
564                    return MISCREG_PMSELR;
565                  case 6:
566                    return MISCREG_PMCEID0;
567                  case 7:
568                    return MISCREG_PMCEID1;
569                }
570                break;
571              case 13:
572                switch (opc2) {
573                  case 0:
574                    return MISCREG_PMCCNTR;
575                  case 1:
576                    // Selector is PMSELR.SEL
577                    return MISCREG_PMXEVTYPER_PMCCFILTR;
578                  case 2:
579                    return MISCREG_PMXEVCNTR;
580                }
581                break;
582              case 14:
583                switch (opc2) {
584                  case 0:
585                    return MISCREG_PMUSERENR;
586                  case 1:
587                    return MISCREG_PMINTENSET;
588                  case 2:
589                    return MISCREG_PMINTENCLR;
590                  case 3:
591                    return MISCREG_PMOVSSET;
592                }
593                break;
594            }
595        } else if (opc1 == 1) {
596            switch (crm) {
597              case 0:
598                switch (opc2) {
599                  case 2: // L2CTLR, L2 Control Register
600                    return MISCREG_L2CTLR;
601                  case 3:
602                    return MISCREG_L2ECTLR;
603                }
604                break;
605                break;
606            }
607        }
608        break;
609      case 10:
610        if (opc1 == 0) {
611            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
612            if (crm < 2) {
613                return MISCREG_IMPDEF_UNIMPL;
614            } else if (crm == 2) { // TEX Remap Registers
615                if (opc2 == 0) {
616                    // Selector is TTBCR.EAE
617                    return MISCREG_PRRR_MAIR0;
618                } else if (opc2 == 1) {
619                    // Selector is TTBCR.EAE
620                    return MISCREG_NMRR_MAIR1;
621                }
622            } else if (crm == 3) {
623                if (opc2 == 0) {
624                    return MISCREG_AMAIR0;
625                } else if (opc2 == 1) {
626                    return MISCREG_AMAIR1;
627                }
628            }
629        } else if (opc1 == 4) {
630            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
631            if (crm == 2) {
632                if (opc2 == 0)
633                    return MISCREG_HMAIR0;
634                else if (opc2 == 1)
635                    return MISCREG_HMAIR1;
636            } else if (crm == 3) {
637                if (opc2 == 0)
638                    return MISCREG_HAMAIR0;
639                else if (opc2 == 1)
640                    return MISCREG_HAMAIR1;
641            }
642        }
643        break;
644      case 11:
645        if (opc1 <=7) {
646            switch (crm) {
647              case 0:
648              case 1:
649              case 2:
650              case 3:
651              case 4:
652              case 5:
653              case 6:
654              case 7:
655              case 8:
656              case 15:
657                // Reserved for DMA operations for TCM access
658                return MISCREG_IMPDEF_UNIMPL;
659              default:
660                break;
661            }
662        }
663        break;
664      case 12:
665        if (opc1 == 0) {
666            if (crm == 0) {
667                if (opc2 == 0) {
668                    return MISCREG_VBAR;
669                } else if (opc2 == 1) {
670                    return MISCREG_MVBAR;
671                }
672            } else if (crm == 1) {
673                if (opc2 == 0) {
674                    return MISCREG_ISR;
675                }
676            } else if (crm == 8) {
677                switch (opc2) {
678                    case 0:
679                        return MISCREG_ICC_IAR0;
680                    case 1:
681                        return MISCREG_ICC_EOIR0;
682                    case 2:
683                        return MISCREG_ICC_HPPIR0;
684                    case 3:
685                        return MISCREG_ICC_BPR0;
686                    case 4:
687                        return MISCREG_ICC_AP0R0;
688                    case 5:
689                        return MISCREG_ICC_AP0R1;
690                    case 6:
691                        return MISCREG_ICC_AP0R2;
692                    case 7:
693                        return MISCREG_ICC_AP0R3;
694                }
695            } else if (crm == 9) {
696                switch (opc2) {
697                    case 0:
698                        return MISCREG_ICC_AP1R0;
699                    case 1:
700                        return MISCREG_ICC_AP1R1;
701                    case 2:
702                        return MISCREG_ICC_AP1R2;
703                    case 3:
704                        return MISCREG_ICC_AP1R3;
705                }
706            } else if (crm == 11) {
707                switch (opc2) {
708                    case 1:
709                        return MISCREG_ICC_DIR;
710                    case 3:
711                        return MISCREG_ICC_RPR;
712                }
713            } else if (crm == 12) {
714                switch (opc2) {
715                    case 0:
716                        return MISCREG_ICC_IAR1;
717                    case 1:
718                        return MISCREG_ICC_EOIR1;
719                    case 2:
720                        return MISCREG_ICC_HPPIR1;
721                    case 3:
722                        return MISCREG_ICC_BPR1;
723                    case 4:
724                        return MISCREG_ICC_CTLR;
725                    case 5:
726                        return MISCREG_ICC_SRE;
727                    case 6:
728                        return MISCREG_ICC_IGRPEN0;
729                    case 7:
730                        return MISCREG_ICC_IGRPEN1;
731                }
732            }
733        } else if (opc1 == 4) {
734            if (crm == 0 && opc2 == 0) {
735                return MISCREG_HVBAR;
736            } else if (crm == 8) {
737                switch (opc2) {
738                    case 0:
739                        return MISCREG_ICH_AP0R0;
740                    case 1:
741                        return MISCREG_ICH_AP0R1;
742                    case 2:
743                        return MISCREG_ICH_AP0R2;
744                    case 3:
745                        return MISCREG_ICH_AP0R3;
746                }
747            } else if (crm == 9) {
748                switch (opc2) {
749                    case 0:
750                        return MISCREG_ICH_AP1R0;
751                    case 1:
752                        return MISCREG_ICH_AP1R1;
753                    case 2:
754                        return MISCREG_ICH_AP1R2;
755                    case 3:
756                        return MISCREG_ICH_AP1R3;
757                    case 5:
758                        return MISCREG_ICC_HSRE;
759                }
760            } else if (crm == 11) {
761                switch (opc2) {
762                    case 0:
763                        return MISCREG_ICH_HCR;
764                    case 1:
765                        return MISCREG_ICH_VTR;
766                    case 2:
767                        return MISCREG_ICH_MISR;
768                    case 3:
769                        return MISCREG_ICH_EISR;
770                    case 5:
771                        return MISCREG_ICH_ELRSR;
772                    case 7:
773                        return MISCREG_ICH_VMCR;
774                }
775            } else if (crm == 12) {
776                switch (opc2) {
777                    case 0:
778                        return MISCREG_ICH_LR0;
779                    case 1:
780                        return MISCREG_ICH_LR1;
781                    case 2:
782                        return MISCREG_ICH_LR2;
783                    case 3:
784                        return MISCREG_ICH_LR3;
785                    case 4:
786                        return MISCREG_ICH_LR4;
787                    case 5:
788                        return MISCREG_ICH_LR5;
789                    case 6:
790                        return MISCREG_ICH_LR6;
791                    case 7:
792                        return MISCREG_ICH_LR7;
793                }
794            } else if (crm == 13) {
795                switch (opc2) {
796                    case 0:
797                        return MISCREG_ICH_LR8;
798                    case 1:
799                        return MISCREG_ICH_LR9;
800                    case 2:
801                        return MISCREG_ICH_LR10;
802                    case 3:
803                        return MISCREG_ICH_LR11;
804                    case 4:
805                        return MISCREG_ICH_LR12;
806                    case 5:
807                        return MISCREG_ICH_LR13;
808                    case 6:
809                        return MISCREG_ICH_LR14;
810                    case 7:
811                        return MISCREG_ICH_LR15;
812                }
813            } else if (crm == 14) {
814                switch (opc2) {
815                    case 0:
816                        return MISCREG_ICH_LRC0;
817                    case 1:
818                        return MISCREG_ICH_LRC1;
819                    case 2:
820                        return MISCREG_ICH_LRC2;
821                    case 3:
822                        return MISCREG_ICH_LRC3;
823                    case 4:
824                        return MISCREG_ICH_LRC4;
825                    case 5:
826                        return MISCREG_ICH_LRC5;
827                    case 6:
828                        return MISCREG_ICH_LRC6;
829                    case 7:
830                        return MISCREG_ICH_LRC7;
831                }
832            } else if (crm == 15) {
833                switch (opc2) {
834                    case 0:
835                        return MISCREG_ICH_LRC8;
836                    case 1:
837                        return MISCREG_ICH_LRC9;
838                    case 2:
839                        return MISCREG_ICH_LRC10;
840                    case 3:
841                        return MISCREG_ICH_LRC11;
842                    case 4:
843                        return MISCREG_ICH_LRC12;
844                    case 5:
845                        return MISCREG_ICH_LRC13;
846                    case 6:
847                        return MISCREG_ICH_LRC14;
848                    case 7:
849                        return MISCREG_ICH_LRC15;
850                }
851            }
852        } else if (opc1 == 6) {
853            if (crm == 12) {
854                switch (opc2) {
855                    case 4:
856                        return MISCREG_ICC_MCTLR;
857                    case 5:
858                        return MISCREG_ICC_MSRE;
859                    case 7:
860                        return MISCREG_ICC_MGRPEN1;
861                }
862            }
863        }
864        break;
865      case 13:
866        if (opc1 == 0) {
867            if (crm == 0) {
868                switch (opc2) {
869                  case 0:
870                    return MISCREG_FCSEIDR;
871                  case 1:
872                    return MISCREG_CONTEXTIDR;
873                  case 2:
874                    return MISCREG_TPIDRURW;
875                  case 3:
876                    return MISCREG_TPIDRURO;
877                  case 4:
878                    return MISCREG_TPIDRPRW;
879                }
880            }
881        } else if (opc1 == 4) {
882            if (crm == 0 && opc2 == 2)
883                return MISCREG_HTPIDR;
884        }
885        break;
886      case 14:
887        if (opc1 == 0) {
888            switch (crm) {
889              case 0:
890                if (opc2 == 0)
891                    return MISCREG_CNTFRQ;
892                break;
893              case 1:
894                if (opc2 == 0)
895                    return MISCREG_CNTKCTL;
896                break;
897              case 2:
898                if (opc2 == 0)
899                    return MISCREG_CNTP_TVAL;
900                else if (opc2 == 1)
901                    return MISCREG_CNTP_CTL;
902                break;
903              case 3:
904                if (opc2 == 0)
905                    return MISCREG_CNTV_TVAL;
906                else if (opc2 == 1)
907                    return MISCREG_CNTV_CTL;
908                break;
909            }
910        } else if (opc1 == 4) {
911            if (crm == 1 && opc2 == 0) {
912                return MISCREG_CNTHCTL;
913            } else if (crm == 2) {
914                if (opc2 == 0)
915                    return MISCREG_CNTHP_TVAL;
916                else if (opc2 == 1)
917                    return MISCREG_CNTHP_CTL;
918            }
919        }
920        break;
921      case 15:
922        // Implementation defined
923        return MISCREG_IMPDEF_UNIMPL;
924    }
925    // Unrecognized register
926    return MISCREG_CP15_UNIMPL;
927}
928
929MiscRegIndex
930decodeCP15Reg64(unsigned crm, unsigned opc1)
931{
932    switch (crm) {
933      case 2:
934        switch (opc1) {
935          case 0:
936            return MISCREG_TTBR0;
937          case 1:
938            return MISCREG_TTBR1;
939          case 4:
940            return MISCREG_HTTBR;
941          case 6:
942            return MISCREG_VTTBR;
943        }
944        break;
945      case 7:
946        if (opc1 == 0)
947            return MISCREG_PAR;
948        break;
949      case 14:
950        switch (opc1) {
951          case 0:
952            return MISCREG_CNTPCT;
953          case 1:
954            return MISCREG_CNTVCT;
955          case 2:
956            return MISCREG_CNTP_CVAL;
957          case 3:
958            return MISCREG_CNTV_CVAL;
959          case 4:
960            return MISCREG_CNTVOFF;
961          case 6:
962            return MISCREG_CNTHP_CVAL;
963        }
964        break;
965      case 15:
966        if (opc1 == 0)
967            return MISCREG_CPUMERRSR;
968        else if (opc1 == 1)
969            return MISCREG_L2MERRSR;
970        break;
971    }
972    // Unrecognized register
973    return MISCREG_CP15_UNIMPL;
974}
975
976std::tuple<bool, bool>
977canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
978{
979    bool secure = !scr.ns;
980    bool canRead = false;
981    bool undefined = false;
982
983    switch (cpsr.mode) {
984      case MODE_USER:
985        canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
986                           miscRegInfo[reg][MISCREG_USR_NS_RD];
987        break;
988      case MODE_FIQ:
989      case MODE_IRQ:
990      case MODE_SVC:
991      case MODE_ABORT:
992      case MODE_UNDEFINED:
993      case MODE_SYSTEM:
994        canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
995                           miscRegInfo[reg][MISCREG_PRI_NS_RD];
996        break;
997      case MODE_MON:
998        canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
999                           miscRegInfo[reg][MISCREG_MON_NS1_RD];
1000        break;
1001      case MODE_HYP:
1002        canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1003        break;
1004      default:
1005        undefined = true;
1006    }
1007    // can't do permissions checkes on the root of a banked pair of regs
1008    assert(!miscRegInfo[reg][MISCREG_BANKED]);
1009    return std::make_tuple(canRead, undefined);
1010}
1011
1012std::tuple<bool, bool>
1013canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1014{
1015    bool secure = !scr.ns;
1016    bool canWrite = false;
1017    bool undefined = false;
1018
1019    switch (cpsr.mode) {
1020      case MODE_USER:
1021        canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1022                            miscRegInfo[reg][MISCREG_USR_NS_WR];
1023        break;
1024      case MODE_FIQ:
1025      case MODE_IRQ:
1026      case MODE_SVC:
1027      case MODE_ABORT:
1028      case MODE_UNDEFINED:
1029      case MODE_SYSTEM:
1030        canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1031                            miscRegInfo[reg][MISCREG_PRI_NS_WR];
1032        break;
1033      case MODE_MON:
1034        canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1035                            miscRegInfo[reg][MISCREG_MON_NS1_WR];
1036        break;
1037      case MODE_HYP:
1038        canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
1039        break;
1040      default:
1041        undefined = true;
1042    }
1043    // can't do permissions checkes on the root of a banked pair of regs
1044    assert(!miscRegInfo[reg][MISCREG_BANKED]);
1045    return std::make_tuple(canWrite, undefined);
1046}
1047
1048int
1049snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1050{
1051    SCR scr = tc->readMiscReg(MISCREG_SCR);
1052    return snsBankedIndex(reg, tc, scr.ns);
1053}
1054
1055int
1056snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1057{
1058    int reg_as_int = static_cast<int>(reg);
1059    if (miscRegInfo[reg][MISCREG_BANKED]) {
1060        reg_as_int += (ArmSystem::haveSecurity(tc) &&
1061                      !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1062    }
1063    return reg_as_int;
1064}
1065
1066
1067/**
1068 * If the reg is a child reg of a banked set, then the parent is the last
1069 * banked one in the list. This is messy, and the wish is to eventually have
1070 * the bitmap replaced with a better data structure. the preUnflatten function
1071 * initializes a lookup table to speed up the search for these banked
1072 * registers.
1073 */
1074
1075int unflattenResultMiscReg[NUM_MISCREGS];
1076
1077void
1078preUnflattenMiscReg()
1079{
1080    int reg = -1;
1081    for (int i = 0 ; i < NUM_MISCREGS; i++){
1082        if (miscRegInfo[i][MISCREG_BANKED])
1083            reg = i;
1084        if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1085            unflattenResultMiscReg[i] = reg;
1086        else
1087            unflattenResultMiscReg[i] = i;
1088        // if this assert fails, no parent was found, and something is broken
1089        assert(unflattenResultMiscReg[i] > -1);
1090    }
1091}
1092
1093int
1094unflattenMiscReg(int reg)
1095{
1096    return unflattenResultMiscReg[reg];
1097}
1098
1099bool
1100canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1101{
1102    // Check for SP_EL0 access while SPSEL == 0
1103    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1104        return false;
1105
1106    // Check for RVBAR access
1107    if (reg == MISCREG_RVBAR_EL1) {
1108        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1109        if (highest_el == EL2 || highest_el == EL3)
1110            return false;
1111    }
1112    if (reg == MISCREG_RVBAR_EL2) {
1113        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1114        if (highest_el == EL3)
1115            return false;
1116    }
1117
1118    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1119
1120    switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
1121      case EL0:
1122        return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1123            miscRegInfo[reg][MISCREG_USR_NS_RD];
1124      case EL1:
1125        return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1126            miscRegInfo[reg][MISCREG_PRI_NS_RD];
1127      case EL2:
1128        return miscRegInfo[reg][MISCREG_HYP_RD];
1129      case EL3:
1130        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1131            miscRegInfo[reg][MISCREG_MON_NS1_RD];
1132      default:
1133        panic("Invalid exception level");
1134    }
1135}
1136
1137bool
1138canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1139{
1140    // Check for SP_EL0 access while SPSEL == 0
1141    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1142        return false;
1143    ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
1144    if (reg == MISCREG_DAIF) {
1145        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1146        if (el == EL0 && !sctlr.uma)
1147            return false;
1148    }
1149    if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1150        // In syscall-emulation mode, this test is skipped and DCZVA is always
1151        // allowed at EL0
1152        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1153        if (el == EL0 && !sctlr.dze)
1154            return false;
1155    }
1156    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1157        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1158        if (el == EL0 && !sctlr.uci)
1159            return false;
1160    }
1161
1162    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1163
1164    switch (el) {
1165      case EL0:
1166        return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1167            miscRegInfo[reg][MISCREG_USR_NS_WR];
1168      case EL1:
1169        return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1170            miscRegInfo[reg][MISCREG_PRI_NS_WR];
1171      case EL2:
1172        return miscRegInfo[reg][MISCREG_HYP_WR];
1173      case EL3:
1174        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1175            miscRegInfo[reg][MISCREG_MON_NS1_WR];
1176      default:
1177        panic("Invalid exception level");
1178    }
1179}
1180
1181MiscRegIndex
1182decodeAArch64SysReg(unsigned op0, unsigned op1,
1183                    unsigned crn, unsigned crm,
1184                    unsigned op2)
1185{
1186    switch (op0) {
1187      case 1:
1188        switch (crn) {
1189          case 7:
1190            switch (op1) {
1191              case 0:
1192                switch (crm) {
1193                  case 1:
1194                    switch (op2) {
1195                      case 0:
1196                        return MISCREG_IC_IALLUIS;
1197                    }
1198                    break;
1199                  case 5:
1200                    switch (op2) {
1201                      case 0:
1202                        return MISCREG_IC_IALLU;
1203                    }
1204                    break;
1205                  case 6:
1206                    switch (op2) {
1207                      case 1:
1208                        return MISCREG_DC_IVAC_Xt;
1209                      case 2:
1210                        return MISCREG_DC_ISW_Xt;
1211                    }
1212                    break;
1213                  case 8:
1214                    switch (op2) {
1215                      case 0:
1216                        return MISCREG_AT_S1E1R_Xt;
1217                      case 1:
1218                        return MISCREG_AT_S1E1W_Xt;
1219                      case 2:
1220                        return MISCREG_AT_S1E0R_Xt;
1221                      case 3:
1222                        return MISCREG_AT_S1E0W_Xt;
1223                    }
1224                    break;
1225                  case 10:
1226                    switch (op2) {
1227                      case 2:
1228                        return MISCREG_DC_CSW_Xt;
1229                    }
1230                    break;
1231                  case 14:
1232                    switch (op2) {
1233                      case 2:
1234                        return MISCREG_DC_CISW_Xt;
1235                    }
1236                    break;
1237                }
1238                break;
1239              case 3:
1240                switch (crm) {
1241                  case 4:
1242                    switch (op2) {
1243                      case 1:
1244                        return MISCREG_DC_ZVA_Xt;
1245                    }
1246                    break;
1247                  case 5:
1248                    switch (op2) {
1249                      case 1:
1250                        return MISCREG_IC_IVAU_Xt;
1251                    }
1252                    break;
1253                  case 10:
1254                    switch (op2) {
1255                      case 1:
1256                        return MISCREG_DC_CVAC_Xt;
1257                    }
1258                    break;
1259                  case 11:
1260                    switch (op2) {
1261                      case 1:
1262                        return MISCREG_DC_CVAU_Xt;
1263                    }
1264                    break;
1265                  case 14:
1266                    switch (op2) {
1267                      case 1:
1268                        return MISCREG_DC_CIVAC_Xt;
1269                    }
1270                    break;
1271                }
1272                break;
1273              case 4:
1274                switch (crm) {
1275                  case 8:
1276                    switch (op2) {
1277                      case 0:
1278                        return MISCREG_AT_S1E2R_Xt;
1279                      case 1:
1280                        return MISCREG_AT_S1E2W_Xt;
1281                      case 4:
1282                        return MISCREG_AT_S12E1R_Xt;
1283                      case 5:
1284                        return MISCREG_AT_S12E1W_Xt;
1285                      case 6:
1286                        return MISCREG_AT_S12E0R_Xt;
1287                      case 7:
1288                        return MISCREG_AT_S12E0W_Xt;
1289                    }
1290                    break;
1291                }
1292                break;
1293              case 6:
1294                switch (crm) {
1295                  case 8:
1296                    switch (op2) {
1297                      case 0:
1298                        return MISCREG_AT_S1E3R_Xt;
1299                      case 1:
1300                        return MISCREG_AT_S1E3W_Xt;
1301                    }
1302                    break;
1303                }
1304                break;
1305            }
1306            break;
1307          case 8:
1308            switch (op1) {
1309              case 0:
1310                switch (crm) {
1311                  case 3:
1312                    switch (op2) {
1313                      case 0:
1314                        return MISCREG_TLBI_VMALLE1IS;
1315                      case 1:
1316                        return MISCREG_TLBI_VAE1IS_Xt;
1317                      case 2:
1318                        return MISCREG_TLBI_ASIDE1IS_Xt;
1319                      case 3:
1320                        return MISCREG_TLBI_VAAE1IS_Xt;
1321                      case 5:
1322                        return MISCREG_TLBI_VALE1IS_Xt;
1323                      case 7:
1324                        return MISCREG_TLBI_VAALE1IS_Xt;
1325                    }
1326                    break;
1327                  case 7:
1328                    switch (op2) {
1329                      case 0:
1330                        return MISCREG_TLBI_VMALLE1;
1331                      case 1:
1332                        return MISCREG_TLBI_VAE1_Xt;
1333                      case 2:
1334                        return MISCREG_TLBI_ASIDE1_Xt;
1335                      case 3:
1336                        return MISCREG_TLBI_VAAE1_Xt;
1337                      case 5:
1338                        return MISCREG_TLBI_VALE1_Xt;
1339                      case 7:
1340                        return MISCREG_TLBI_VAALE1_Xt;
1341                    }
1342                    break;
1343                }
1344                break;
1345              case 4:
1346                switch (crm) {
1347                  case 0:
1348                    switch (op2) {
1349                      case 1:
1350                        return MISCREG_TLBI_IPAS2E1IS_Xt;
1351                      case 5:
1352                        return MISCREG_TLBI_IPAS2LE1IS_Xt;
1353                    }
1354                    break;
1355                  case 3:
1356                    switch (op2) {
1357                      case 0:
1358                        return MISCREG_TLBI_ALLE2IS;
1359                      case 1:
1360                        return MISCREG_TLBI_VAE2IS_Xt;
1361                      case 4:
1362                        return MISCREG_TLBI_ALLE1IS;
1363                      case 5:
1364                        return MISCREG_TLBI_VALE2IS_Xt;
1365                      case 6:
1366                        return MISCREG_TLBI_VMALLS12E1IS;
1367                    }
1368                    break;
1369                  case 4:
1370                    switch (op2) {
1371                      case 1:
1372                        return MISCREG_TLBI_IPAS2E1_Xt;
1373                      case 5:
1374                        return MISCREG_TLBI_IPAS2LE1_Xt;
1375                    }
1376                    break;
1377                  case 7:
1378                    switch (op2) {
1379                      case 0:
1380                        return MISCREG_TLBI_ALLE2;
1381                      case 1:
1382                        return MISCREG_TLBI_VAE2_Xt;
1383                      case 4:
1384                        return MISCREG_TLBI_ALLE1;
1385                      case 5:
1386                        return MISCREG_TLBI_VALE2_Xt;
1387                      case 6:
1388                        return MISCREG_TLBI_VMALLS12E1;
1389                    }
1390                    break;
1391                }
1392                break;
1393              case 6:
1394                switch (crm) {
1395                  case 3:
1396                    switch (op2) {
1397                      case 0:
1398                        return MISCREG_TLBI_ALLE3IS;
1399                      case 1:
1400                        return MISCREG_TLBI_VAE3IS_Xt;
1401                      case 5:
1402                        return MISCREG_TLBI_VALE3IS_Xt;
1403                    }
1404                    break;
1405                  case 7:
1406                    switch (op2) {
1407                      case 0:
1408                        return MISCREG_TLBI_ALLE3;
1409                      case 1:
1410                        return MISCREG_TLBI_VAE3_Xt;
1411                      case 5:
1412                        return MISCREG_TLBI_VALE3_Xt;
1413                    }
1414                    break;
1415                }
1416                break;
1417            }
1418            break;
1419          case 11:
1420          case 15:
1421            // SYS Instruction with CRn = { 11, 15 }
1422            // (Trappable by HCR_EL2.TIDCP)
1423            return MISCREG_IMPDEF_UNIMPL;
1424        }
1425        break;
1426      case 2:
1427        switch (crn) {
1428          case 0:
1429            switch (op1) {
1430              case 0:
1431                switch (crm) {
1432                  case 0:
1433                    switch (op2) {
1434                      case 2:
1435                        return MISCREG_OSDTRRX_EL1;
1436                      case 4:
1437                        return MISCREG_DBGBVR0_EL1;
1438                      case 5:
1439                        return MISCREG_DBGBCR0_EL1;
1440                      case 6:
1441                        return MISCREG_DBGWVR0_EL1;
1442                      case 7:
1443                        return MISCREG_DBGWCR0_EL1;
1444                    }
1445                    break;
1446                  case 1:
1447                    switch (op2) {
1448                      case 4:
1449                        return MISCREG_DBGBVR1_EL1;
1450                      case 5:
1451                        return MISCREG_DBGBCR1_EL1;
1452                      case 6:
1453                        return MISCREG_DBGWVR1_EL1;
1454                      case 7:
1455                        return MISCREG_DBGWCR1_EL1;
1456                    }
1457                    break;
1458                  case 2:
1459                    switch (op2) {
1460                      case 0:
1461                        return MISCREG_MDCCINT_EL1;
1462                      case 2:
1463                        return MISCREG_MDSCR_EL1;
1464                      case 4:
1465                        return MISCREG_DBGBVR2_EL1;
1466                      case 5:
1467                        return MISCREG_DBGBCR2_EL1;
1468                      case 6:
1469                        return MISCREG_DBGWVR2_EL1;
1470                      case 7:
1471                        return MISCREG_DBGWCR2_EL1;
1472                    }
1473                    break;
1474                  case 3:
1475                    switch (op2) {
1476                      case 2:
1477                        return MISCREG_OSDTRTX_EL1;
1478                      case 4:
1479                        return MISCREG_DBGBVR3_EL1;
1480                      case 5:
1481                        return MISCREG_DBGBCR3_EL1;
1482                      case 6:
1483                        return MISCREG_DBGWVR3_EL1;
1484                      case 7:
1485                        return MISCREG_DBGWCR3_EL1;
1486                    }
1487                    break;
1488                  case 4:
1489                    switch (op2) {
1490                      case 4:
1491                        return MISCREG_DBGBVR4_EL1;
1492                      case 5:
1493                        return MISCREG_DBGBCR4_EL1;
1494                    }
1495                    break;
1496                  case 5:
1497                    switch (op2) {
1498                      case 4:
1499                        return MISCREG_DBGBVR5_EL1;
1500                      case 5:
1501                        return MISCREG_DBGBCR5_EL1;
1502                    }
1503                    break;
1504                  case 6:
1505                    switch (op2) {
1506                      case 2:
1507                        return MISCREG_OSECCR_EL1;
1508                    }
1509                    break;
1510                }
1511                break;
1512              case 2:
1513                switch (crm) {
1514                  case 0:
1515                    switch (op2) {
1516                      case 0:
1517                        return MISCREG_TEECR32_EL1;
1518                    }
1519                    break;
1520                }
1521                break;
1522              case 3:
1523                switch (crm) {
1524                  case 1:
1525                    switch (op2) {
1526                      case 0:
1527                        return MISCREG_MDCCSR_EL0;
1528                    }
1529                    break;
1530                  case 4:
1531                    switch (op2) {
1532                      case 0:
1533                        return MISCREG_MDDTR_EL0;
1534                    }
1535                    break;
1536                  case 5:
1537                    switch (op2) {
1538                      case 0:
1539                        return MISCREG_MDDTRRX_EL0;
1540                    }
1541                    break;
1542                }
1543                break;
1544              case 4:
1545                switch (crm) {
1546                  case 7:
1547                    switch (op2) {
1548                      case 0:
1549                        return MISCREG_DBGVCR32_EL2;
1550                    }
1551                    break;
1552                }
1553                break;
1554            }
1555            break;
1556          case 1:
1557            switch (op1) {
1558              case 0:
1559                switch (crm) {
1560                  case 0:
1561                    switch (op2) {
1562                      case 0:
1563                        return MISCREG_MDRAR_EL1;
1564                      case 4:
1565                        return MISCREG_OSLAR_EL1;
1566                    }
1567                    break;
1568                  case 1:
1569                    switch (op2) {
1570                      case 4:
1571                        return MISCREG_OSLSR_EL1;
1572                    }
1573                    break;
1574                  case 3:
1575                    switch (op2) {
1576                      case 4:
1577                        return MISCREG_OSDLR_EL1;
1578                    }
1579                    break;
1580                  case 4:
1581                    switch (op2) {
1582                      case 4:
1583                        return MISCREG_DBGPRCR_EL1;
1584                    }
1585                    break;
1586                }
1587                break;
1588              case 2:
1589                switch (crm) {
1590                  case 0:
1591                    switch (op2) {
1592                      case 0:
1593                        return MISCREG_TEEHBR32_EL1;
1594                    }
1595                    break;
1596                }
1597                break;
1598            }
1599            break;
1600          case 7:
1601            switch (op1) {
1602              case 0:
1603                switch (crm) {
1604                  case 8:
1605                    switch (op2) {
1606                      case 6:
1607                        return MISCREG_DBGCLAIMSET_EL1;
1608                    }
1609                    break;
1610                  case 9:
1611                    switch (op2) {
1612                      case 6:
1613                        return MISCREG_DBGCLAIMCLR_EL1;
1614                    }
1615                    break;
1616                  case 14:
1617                    switch (op2) {
1618                      case 6:
1619                        return MISCREG_DBGAUTHSTATUS_EL1;
1620                    }
1621                    break;
1622                }
1623                break;
1624            }
1625            break;
1626        }
1627        break;
1628      case 3:
1629        switch (crn) {
1630          case 0:
1631            switch (op1) {
1632              case 0:
1633                switch (crm) {
1634                  case 0:
1635                    switch (op2) {
1636                      case 0:
1637                        return MISCREG_MIDR_EL1;
1638                      case 5:
1639                        return MISCREG_MPIDR_EL1;
1640                      case 6:
1641                        return MISCREG_REVIDR_EL1;
1642                    }
1643                    break;
1644                  case 1:
1645                    switch (op2) {
1646                      case 0:
1647                        return MISCREG_ID_PFR0_EL1;
1648                      case 1:
1649                        return MISCREG_ID_PFR1_EL1;
1650                      case 2:
1651                        return MISCREG_ID_DFR0_EL1;
1652                      case 3:
1653                        return MISCREG_ID_AFR0_EL1;
1654                      case 4:
1655                        return MISCREG_ID_MMFR0_EL1;
1656                      case 5:
1657                        return MISCREG_ID_MMFR1_EL1;
1658                      case 6:
1659                        return MISCREG_ID_MMFR2_EL1;
1660                      case 7:
1661                        return MISCREG_ID_MMFR3_EL1;
1662                    }
1663                    break;
1664                  case 2:
1665                    switch (op2) {
1666                      case 0:
1667                        return MISCREG_ID_ISAR0_EL1;
1668                      case 1:
1669                        return MISCREG_ID_ISAR1_EL1;
1670                      case 2:
1671                        return MISCREG_ID_ISAR2_EL1;
1672                      case 3:
1673                        return MISCREG_ID_ISAR3_EL1;
1674                      case 4:
1675                        return MISCREG_ID_ISAR4_EL1;
1676                      case 5:
1677                        return MISCREG_ID_ISAR5_EL1;
1678                    }
1679                    break;
1680                  case 3:
1681                    switch (op2) {
1682                      case 0:
1683                        return MISCREG_MVFR0_EL1;
1684                      case 1:
1685                        return MISCREG_MVFR1_EL1;
1686                      case 2:
1687                        return MISCREG_MVFR2_EL1;
1688                      case 3 ... 7:
1689                        return MISCREG_RAZ;
1690                    }
1691                    break;
1692                  case 4:
1693                    switch (op2) {
1694                      case 0:
1695                        return MISCREG_ID_AA64PFR0_EL1;
1696                      case 1:
1697                        return MISCREG_ID_AA64PFR1_EL1;
1698                      case 2 ... 3:
1699                        return MISCREG_RAZ;
1700                      case 4:
1701                        return MISCREG_ID_AA64ZFR0_EL1;
1702                      case 5 ... 7:
1703                        return MISCREG_RAZ;
1704                    }
1705                    break;
1706                  case 5:
1707                    switch (op2) {
1708                      case 0:
1709                        return MISCREG_ID_AA64DFR0_EL1;
1710                      case 1:
1711                        return MISCREG_ID_AA64DFR1_EL1;
1712                      case 4:
1713                        return MISCREG_ID_AA64AFR0_EL1;
1714                      case 5:
1715                        return MISCREG_ID_AA64AFR1_EL1;
1716                      case 2:
1717                      case 3:
1718                      case 6:
1719                      case 7:
1720                        return MISCREG_RAZ;
1721                    }
1722                    break;
1723                  case 6:
1724                    switch (op2) {
1725                      case 0:
1726                        return MISCREG_ID_AA64ISAR0_EL1;
1727                      case 1:
1728                        return MISCREG_ID_AA64ISAR1_EL1;
1729                      case 2 ... 7:
1730                        return MISCREG_RAZ;
1731                    }
1732                    break;
1733                  case 7:
1734                    switch (op2) {
1735                      case 0:
1736                        return MISCREG_ID_AA64MMFR0_EL1;
1737                      case 1:
1738                        return MISCREG_ID_AA64MMFR1_EL1;
1739                      case 2:
1740                        return MISCREG_ID_AA64MMFR2_EL1;
1741                      case 3 ... 7:
1742                        return MISCREG_RAZ;
1743                    }
1744                    break;
1745                }
1746                break;
1747              case 1:
1748                switch (crm) {
1749                  case 0:
1750                    switch (op2) {
1751                      case 0:
1752                        return MISCREG_CCSIDR_EL1;
1753                      case 1:
1754                        return MISCREG_CLIDR_EL1;
1755                      case 7:
1756                        return MISCREG_AIDR_EL1;
1757                    }
1758                    break;
1759                }
1760                break;
1761              case 2:
1762                switch (crm) {
1763                  case 0:
1764                    switch (op2) {
1765                      case 0:
1766                        return MISCREG_CSSELR_EL1;
1767                    }
1768                    break;
1769                }
1770                break;
1771              case 3:
1772                switch (crm) {
1773                  case 0:
1774                    switch (op2) {
1775                      case 1:
1776                        return MISCREG_CTR_EL0;
1777                      case 7:
1778                        return MISCREG_DCZID_EL0;
1779                    }
1780                    break;
1781                }
1782                break;
1783              case 4:
1784                switch (crm) {
1785                  case 0:
1786                    switch (op2) {
1787                      case 0:
1788                        return MISCREG_VPIDR_EL2;
1789                      case 5:
1790                        return MISCREG_VMPIDR_EL2;
1791                    }
1792                    break;
1793                }
1794                break;
1795            }
1796            break;
1797          case 1:
1798            switch (op1) {
1799              case 0:
1800                switch (crm) {
1801                  case 0:
1802                    switch (op2) {
1803                      case 0:
1804                        return MISCREG_SCTLR_EL1;
1805                      case 1:
1806                        return MISCREG_ACTLR_EL1;
1807                      case 2:
1808                        return MISCREG_CPACR_EL1;
1809                    }
1810                    break;
1811                  case 2:
1812                    switch (op2) {
1813                      case 0:
1814                        return MISCREG_ZCR_EL1;
1815                    }
1816                    break;
1817                }
1818                break;
1819              case 4:
1820                switch (crm) {
1821                  case 0:
1822                    switch (op2) {
1823                      case 0:
1824                        return MISCREG_SCTLR_EL2;
1825                      case 1:
1826                        return MISCREG_ACTLR_EL2;
1827                    }
1828                    break;
1829                  case 1:
1830                    switch (op2) {
1831                      case 0:
1832                        return MISCREG_HCR_EL2;
1833                      case 1:
1834                        return MISCREG_MDCR_EL2;
1835                      case 2:
1836                        return MISCREG_CPTR_EL2;
1837                      case 3:
1838                        return MISCREG_HSTR_EL2;
1839                      case 7:
1840                        return MISCREG_HACR_EL2;
1841                    }
1842                    break;
1843                  case 2:
1844                    switch (op2) {
1845                      case 0:
1846                        return MISCREG_ZCR_EL2;
1847                    }
1848                    break;
1849                }
1850                break;
1851              case 5:
1852                switch (crm) {
1853                  case 2:
1854                    switch (op2) {
1855                      case 0:
1856                        return MISCREG_ZCR_EL12;
1857                    }
1858                    break;
1859                }
1860                break;
1861              case 6:
1862                switch (crm) {
1863                  case 0:
1864                    switch (op2) {
1865                      case 0:
1866                        return MISCREG_SCTLR_EL3;
1867                      case 1:
1868                        return MISCREG_ACTLR_EL3;
1869                    }
1870                    break;
1871                  case 1:
1872                    switch (op2) {
1873                      case 0:
1874                        return MISCREG_SCR_EL3;
1875                      case 1:
1876                        return MISCREG_SDER32_EL3;
1877                      case 2:
1878                        return MISCREG_CPTR_EL3;
1879                    }
1880                    break;
1881                  case 2:
1882                    switch (op2) {
1883                      case 0:
1884                        return MISCREG_ZCR_EL3;
1885                    }
1886                    break;
1887                  case 3:
1888                    switch (op2) {
1889                      case 1:
1890                        return MISCREG_MDCR_EL3;
1891                    }
1892                    break;
1893                }
1894                break;
1895            }
1896            break;
1897          case 2:
1898            switch (op1) {
1899              case 0:
1900                switch (crm) {
1901                  case 0:
1902                    switch (op2) {
1903                      case 0:
1904                        return MISCREG_TTBR0_EL1;
1905                      case 1:
1906                        return MISCREG_TTBR1_EL1;
1907                      case 2:
1908                        return MISCREG_TCR_EL1;
1909                    }
1910                    break;
1911                }
1912                break;
1913              case 4:
1914                switch (crm) {
1915                  case 0:
1916                    switch (op2) {
1917                      case 0:
1918                        return MISCREG_TTBR0_EL2;
1919                      case 1:
1920                        return MISCREG_TTBR1_EL2;
1921                      case 2:
1922                        return MISCREG_TCR_EL2;
1923                    }
1924                    break;
1925                  case 1:
1926                    switch (op2) {
1927                      case 0:
1928                        return MISCREG_VTTBR_EL2;
1929                      case 2:
1930                        return MISCREG_VTCR_EL2;
1931                    }
1932                    break;
1933                }
1934                break;
1935              case 6:
1936                switch (crm) {
1937                  case 0:
1938                    switch (op2) {
1939                      case 0:
1940                        return MISCREG_TTBR0_EL3;
1941                      case 2:
1942                        return MISCREG_TCR_EL3;
1943                    }
1944                    break;
1945                }
1946                break;
1947            }
1948            break;
1949          case 3:
1950            switch (op1) {
1951              case 4:
1952                switch (crm) {
1953                  case 0:
1954                    switch (op2) {
1955                      case 0:
1956                        return MISCREG_DACR32_EL2;
1957                    }
1958                    break;
1959                }
1960                break;
1961            }
1962            break;
1963          case 4:
1964            switch (op1) {
1965              case 0:
1966                switch (crm) {
1967                  case 0:
1968                    switch (op2) {
1969                      case 0:
1970                        return MISCREG_SPSR_EL1;
1971                      case 1:
1972                        return MISCREG_ELR_EL1;
1973                    }
1974                    break;
1975                  case 1:
1976                    switch (op2) {
1977                      case 0:
1978                        return MISCREG_SP_EL0;
1979                    }
1980                    break;
1981                  case 2:
1982                    switch (op2) {
1983                      case 0:
1984                        return MISCREG_SPSEL;
1985                      case 2:
1986                        return MISCREG_CURRENTEL;
1987                    }
1988                    break;
1989                  case 6:
1990                    switch (op2) {
1991                      case 0:
1992                        return MISCREG_ICC_PMR_EL1;
1993                    }
1994                    break;
1995                }
1996                break;
1997              case 3:
1998                switch (crm) {
1999                  case 2:
2000                    switch (op2) {
2001                      case 0:
2002                        return MISCREG_NZCV;
2003                      case 1:
2004                        return MISCREG_DAIF;
2005                    }
2006                    break;
2007                  case 4:
2008                    switch (op2) {
2009                      case 0:
2010                        return MISCREG_FPCR;
2011                      case 1:
2012                        return MISCREG_FPSR;
2013                    }
2014                    break;
2015                  case 5:
2016                    switch (op2) {
2017                      case 0:
2018                        return MISCREG_DSPSR_EL0;
2019                      case 1:
2020                        return MISCREG_DLR_EL0;
2021                    }
2022                    break;
2023                }
2024                break;
2025              case 4:
2026                switch (crm) {
2027                  case 0:
2028                    switch (op2) {
2029                      case 0:
2030                        return MISCREG_SPSR_EL2;
2031                      case 1:
2032                        return MISCREG_ELR_EL2;
2033                    }
2034                    break;
2035                  case 1:
2036                    switch (op2) {
2037                      case 0:
2038                        return MISCREG_SP_EL1;
2039                    }
2040                    break;
2041                  case 3:
2042                    switch (op2) {
2043                      case 0:
2044                        return MISCREG_SPSR_IRQ_AA64;
2045                      case 1:
2046                        return MISCREG_SPSR_ABT_AA64;
2047                      case 2:
2048                        return MISCREG_SPSR_UND_AA64;
2049                      case 3:
2050                        return MISCREG_SPSR_FIQ_AA64;
2051                    }
2052                    break;
2053                }
2054                break;
2055              case 6:
2056                switch (crm) {
2057                  case 0:
2058                    switch (op2) {
2059                      case 0:
2060                        return MISCREG_SPSR_EL3;
2061                      case 1:
2062                        return MISCREG_ELR_EL3;
2063                    }
2064                    break;
2065                  case 1:
2066                    switch (op2) {
2067                      case 0:
2068                        return MISCREG_SP_EL2;
2069                    }
2070                    break;
2071                }
2072                break;
2073            }
2074            break;
2075          case 5:
2076            switch (op1) {
2077              case 0:
2078                switch (crm) {
2079                  case 1:
2080                    switch (op2) {
2081                      case 0:
2082                        return MISCREG_AFSR0_EL1;
2083                      case 1:
2084                        return MISCREG_AFSR1_EL1;
2085                    }
2086                    break;
2087                  case 2:
2088                    switch (op2) {
2089                      case 0:
2090                        return MISCREG_ESR_EL1;
2091                    }
2092                    break;
2093                  case 3:
2094                    switch (op2) {
2095                      case 0:
2096                        return MISCREG_ERRIDR_EL1;
2097                      case 1:
2098                        return MISCREG_ERRSELR_EL1;
2099                    }
2100                    break;
2101                  case 4:
2102                    switch (op2) {
2103                      case 0:
2104                        return MISCREG_ERXFR_EL1;
2105                      case 1:
2106                        return MISCREG_ERXCTLR_EL1;
2107                      case 2:
2108                        return MISCREG_ERXSTATUS_EL1;
2109                      case 3:
2110                        return MISCREG_ERXADDR_EL1;
2111                    }
2112                    break;
2113                  case 5:
2114                    switch (op2) {
2115                      case 0:
2116                        return MISCREG_ERXMISC0_EL1;
2117                      case 1:
2118                        return MISCREG_ERXMISC1_EL1;
2119                    }
2120                    break;
2121                }
2122                break;
2123              case 4:
2124                switch (crm) {
2125                  case 0:
2126                    switch (op2) {
2127                      case 1:
2128                        return MISCREG_IFSR32_EL2;
2129                    }
2130                    break;
2131                  case 1:
2132                    switch (op2) {
2133                      case 0:
2134                        return MISCREG_AFSR0_EL2;
2135                      case 1:
2136                        return MISCREG_AFSR1_EL2;
2137                    }
2138                    break;
2139                  case 2:
2140                    switch (op2) {
2141                      case 0:
2142                        return MISCREG_ESR_EL2;
2143                      case 3:
2144                        return MISCREG_VSESR_EL2;
2145                    }
2146                    break;
2147                  case 3:
2148                    switch (op2) {
2149                      case 0:
2150                        return MISCREG_FPEXC32_EL2;
2151                    }
2152                    break;
2153                }
2154                break;
2155              case 6:
2156                switch (crm) {
2157                  case 1:
2158                    switch (op2) {
2159                      case 0:
2160                        return MISCREG_AFSR0_EL3;
2161                      case 1:
2162                        return MISCREG_AFSR1_EL3;
2163                    }
2164                    break;
2165                  case 2:
2166                    switch (op2) {
2167                      case 0:
2168                        return MISCREG_ESR_EL3;
2169                    }
2170                    break;
2171                }
2172                break;
2173            }
2174            break;
2175          case 6:
2176            switch (op1) {
2177              case 0:
2178                switch (crm) {
2179                  case 0:
2180                    switch (op2) {
2181                      case 0:
2182                        return MISCREG_FAR_EL1;
2183                    }
2184                    break;
2185                }
2186                break;
2187              case 4:
2188                switch (crm) {
2189                  case 0:
2190                    switch (op2) {
2191                      case 0:
2192                        return MISCREG_FAR_EL2;
2193                      case 4:
2194                        return MISCREG_HPFAR_EL2;
2195                    }
2196                    break;
2197                }
2198                break;
2199              case 6:
2200                switch (crm) {
2201                  case 0:
2202                    switch (op2) {
2203                      case 0:
2204                        return MISCREG_FAR_EL3;
2205                    }
2206                    break;
2207                }
2208                break;
2209            }
2210            break;
2211          case 7:
2212            switch (op1) {
2213              case 0:
2214                switch (crm) {
2215                  case 4:
2216                    switch (op2) {
2217                      case 0:
2218                        return MISCREG_PAR_EL1;
2219                    }
2220                    break;
2221                }
2222                break;
2223            }
2224            break;
2225          case 9:
2226            switch (op1) {
2227              case 0:
2228                switch (crm) {
2229                  case 14:
2230                    switch (op2) {
2231                      case 1:
2232                        return MISCREG_PMINTENSET_EL1;
2233                      case 2:
2234                        return MISCREG_PMINTENCLR_EL1;
2235                    }
2236                    break;
2237                }
2238                break;
2239              case 3:
2240                switch (crm) {
2241                  case 12:
2242                    switch (op2) {
2243                      case 0:
2244                        return MISCREG_PMCR_EL0;
2245                      case 1:
2246                        return MISCREG_PMCNTENSET_EL0;
2247                      case 2:
2248                        return MISCREG_PMCNTENCLR_EL0;
2249                      case 3:
2250                        return MISCREG_PMOVSCLR_EL0;
2251                      case 4:
2252                        return MISCREG_PMSWINC_EL0;
2253                      case 5:
2254                        return MISCREG_PMSELR_EL0;
2255                      case 6:
2256                        return MISCREG_PMCEID0_EL0;
2257                      case 7:
2258                        return MISCREG_PMCEID1_EL0;
2259                    }
2260                    break;
2261                  case 13:
2262                    switch (op2) {
2263                      case 0:
2264                        return MISCREG_PMCCNTR_EL0;
2265                      case 1:
2266                        return MISCREG_PMXEVTYPER_EL0;
2267                      case 2:
2268                        return MISCREG_PMXEVCNTR_EL0;
2269                    }
2270                    break;
2271                  case 14:
2272                    switch (op2) {
2273                      case 0:
2274                        return MISCREG_PMUSERENR_EL0;
2275                      case 3:
2276                        return MISCREG_PMOVSSET_EL0;
2277                    }
2278                    break;
2279                }
2280                break;
2281            }
2282            break;
2283          case 10:
2284            switch (op1) {
2285              case 0:
2286                switch (crm) {
2287                  case 2:
2288                    switch (op2) {
2289                      case 0:
2290                        return MISCREG_MAIR_EL1;
2291                    }
2292                    break;
2293                  case 3:
2294                    switch (op2) {
2295                      case 0:
2296                        return MISCREG_AMAIR_EL1;
2297                    }
2298                    break;
2299                }
2300                break;
2301              case 4:
2302                switch (crm) {
2303                  case 2:
2304                    switch (op2) {
2305                      case 0:
2306                        return MISCREG_MAIR_EL2;
2307                    }
2308                    break;
2309                  case 3:
2310                    switch (op2) {
2311                      case 0:
2312                        return MISCREG_AMAIR_EL2;
2313                    }
2314                    break;
2315                }
2316                break;
2317              case 6:
2318                switch (crm) {
2319                  case 2:
2320                    switch (op2) {
2321                      case 0:
2322                        return MISCREG_MAIR_EL3;
2323                    }
2324                    break;
2325                  case 3:
2326                    switch (op2) {
2327                      case 0:
2328                        return MISCREG_AMAIR_EL3;
2329                    }
2330                    break;
2331                }
2332                break;
2333            }
2334            break;
2335          case 11:
2336            switch (op1) {
2337              case 1:
2338                switch (crm) {
2339                  case 0:
2340                    switch (op2) {
2341                      case 2:
2342                        return MISCREG_L2CTLR_EL1;
2343                      case 3:
2344                        return MISCREG_L2ECTLR_EL1;
2345                    }
2346                    break;
2347                }
2348                M5_FALLTHROUGH;
2349              default:
2350                // S3_<op1>_11_<Cm>_<op2>
2351                return MISCREG_IMPDEF_UNIMPL;
2352            }
2353            M5_UNREACHABLE;
2354          case 12:
2355            switch (op1) {
2356              case 0:
2357                switch (crm) {
2358                  case 0:
2359                    switch (op2) {
2360                      case 0:
2361                        return MISCREG_VBAR_EL1;
2362                      case 1:
2363                        return MISCREG_RVBAR_EL1;
2364                    }
2365                    break;
2366                  case 1:
2367                    switch (op2) {
2368                      case 0:
2369                        return MISCREG_ISR_EL1;
2370                      case 1:
2371                        return MISCREG_DISR_EL1;
2372                    }
2373                    break;
2374                  case 8:
2375                    switch (op2) {
2376                      case 0:
2377                        return MISCREG_ICC_IAR0_EL1;
2378                      case 1:
2379                        return MISCREG_ICC_EOIR0_EL1;
2380                      case 2:
2381                        return MISCREG_ICC_HPPIR0_EL1;
2382                      case 3:
2383                        return MISCREG_ICC_BPR0_EL1;
2384                      case 4:
2385                        return MISCREG_ICC_AP0R0_EL1;
2386                      case 5:
2387                        return MISCREG_ICC_AP0R1_EL1;
2388                      case 6:
2389                        return MISCREG_ICC_AP0R2_EL1;
2390                      case 7:
2391                        return MISCREG_ICC_AP0R3_EL1;
2392                    }
2393                    break;
2394                  case 9:
2395                    switch (op2) {
2396                      case 0:
2397                        return MISCREG_ICC_AP1R0_EL1;
2398                      case 1:
2399                        return MISCREG_ICC_AP1R1_EL1;
2400                      case 2:
2401                        return MISCREG_ICC_AP1R2_EL1;
2402                      case 3:
2403                        return MISCREG_ICC_AP1R3_EL1;
2404                    }
2405                    break;
2406                  case 11:
2407                    switch (op2) {
2408                      case 1:
2409                        return MISCREG_ICC_DIR_EL1;
2410                      case 3:
2411                        return MISCREG_ICC_RPR_EL1;
2412                      case 5:
2413                        return MISCREG_ICC_SGI1R_EL1;
2414                      case 6:
2415                        return MISCREG_ICC_ASGI1R_EL1;
2416                      case 7:
2417                        return MISCREG_ICC_SGI0R_EL1;
2418                    }
2419                    break;
2420                  case 12:
2421                    switch (op2) {
2422                      case 0:
2423                        return MISCREG_ICC_IAR1_EL1;
2424                      case 1:
2425                        return MISCREG_ICC_EOIR1_EL1;
2426                      case 2:
2427                        return MISCREG_ICC_HPPIR1_EL1;
2428                      case 3:
2429                        return MISCREG_ICC_BPR1_EL1;
2430                      case 4:
2431                        return MISCREG_ICC_CTLR_EL1;
2432                      case 5:
2433                        return MISCREG_ICC_SRE_EL1;
2434                      case 6:
2435                        return MISCREG_ICC_IGRPEN0_EL1;
2436                      case 7:
2437                        return MISCREG_ICC_IGRPEN1_EL1;
2438                    }
2439                    break;
2440                }
2441                break;
2442              case 4:
2443                switch (crm) {
2444                  case 0:
2445                    switch (op2) {
2446                      case 0:
2447                        return MISCREG_VBAR_EL2;
2448                      case 1:
2449                        return MISCREG_RVBAR_EL2;
2450                    }
2451                    break;
2452                  case 1:
2453                    switch (op2) {
2454                      case 1:
2455                        return MISCREG_VDISR_EL2;
2456                    }
2457                    break;
2458                  case 8:
2459                    switch (op2) {
2460                      case 0:
2461                        return MISCREG_ICH_AP0R0_EL2;
2462                      case 1:
2463                        return MISCREG_ICH_AP0R1_EL2;
2464                      case 2:
2465                        return MISCREG_ICH_AP0R2_EL2;
2466                      case 3:
2467                        return MISCREG_ICH_AP0R3_EL2;
2468                    }
2469                    break;
2470                  case 9:
2471                    switch (op2) {
2472                      case 0:
2473                        return MISCREG_ICH_AP1R0_EL2;
2474                      case 1:
2475                        return MISCREG_ICH_AP1R1_EL2;
2476                      case 2:
2477                        return MISCREG_ICH_AP1R2_EL2;
2478                      case 3:
2479                        return MISCREG_ICH_AP1R3_EL2;
2480                      case 5:
2481                        return MISCREG_ICC_SRE_EL2;
2482                    }
2483                    break;
2484                  case 11:
2485                    switch (op2) {
2486                      case 0:
2487                        return MISCREG_ICH_HCR_EL2;
2488                      case 1:
2489                        return MISCREG_ICH_VTR_EL2;
2490                      case 2:
2491                        return MISCREG_ICH_MISR_EL2;
2492                      case 3:
2493                        return MISCREG_ICH_EISR_EL2;
2494                      case 5:
2495                        return MISCREG_ICH_ELRSR_EL2;
2496                      case 7:
2497                        return MISCREG_ICH_VMCR_EL2;
2498                    }
2499                    break;
2500                  case 12:
2501                    switch (op2) {
2502                      case 0:
2503                        return MISCREG_ICH_LR0_EL2;
2504                      case 1:
2505                        return MISCREG_ICH_LR1_EL2;
2506                      case 2:
2507                        return MISCREG_ICH_LR2_EL2;
2508                      case 3:
2509                        return MISCREG_ICH_LR3_EL2;
2510                      case 4:
2511                        return MISCREG_ICH_LR4_EL2;
2512                      case 5:
2513                        return MISCREG_ICH_LR5_EL2;
2514                      case 6:
2515                        return MISCREG_ICH_LR6_EL2;
2516                      case 7:
2517                        return MISCREG_ICH_LR7_EL2;
2518                    }
2519                    break;
2520                  case 13:
2521                    switch (op2) {
2522                      case 0:
2523                        return MISCREG_ICH_LR8_EL2;
2524                      case 1:
2525                        return MISCREG_ICH_LR9_EL2;
2526                      case 2:
2527                        return MISCREG_ICH_LR10_EL2;
2528                      case 3:
2529                        return MISCREG_ICH_LR11_EL2;
2530                      case 4:
2531                        return MISCREG_ICH_LR12_EL2;
2532                      case 5:
2533                        return MISCREG_ICH_LR13_EL2;
2534                      case 6:
2535                        return MISCREG_ICH_LR14_EL2;
2536                      case 7:
2537                        return MISCREG_ICH_LR15_EL2;
2538                    }
2539                    break;
2540                }
2541                break;
2542              case 6:
2543                switch (crm) {
2544                  case 0:
2545                    switch (op2) {
2546                      case 0:
2547                        return MISCREG_VBAR_EL3;
2548                      case 1:
2549                        return MISCREG_RVBAR_EL3;
2550                      case 2:
2551                        return MISCREG_RMR_EL3;
2552                    }
2553                    break;
2554                  case 12:
2555                    switch (op2) {
2556                      case 4:
2557                        return MISCREG_ICC_CTLR_EL3;
2558                      case 5:
2559                        return MISCREG_ICC_SRE_EL3;
2560                      case 7:
2561                        return MISCREG_ICC_IGRPEN1_EL3;
2562                    }
2563                    break;
2564                }
2565                break;
2566            }
2567            break;
2568          case 13:
2569            switch (op1) {
2570              case 0:
2571                switch (crm) {
2572                  case 0:
2573                    switch (op2) {
2574                      case 1:
2575                        return MISCREG_CONTEXTIDR_EL1;
2576                      case 4:
2577                        return MISCREG_TPIDR_EL1;
2578                    }
2579                    break;
2580                }
2581                break;
2582              case 3:
2583                switch (crm) {
2584                  case 0:
2585                    switch (op2) {
2586                      case 2:
2587                        return MISCREG_TPIDR_EL0;
2588                      case 3:
2589                        return MISCREG_TPIDRRO_EL0;
2590                    }
2591                    break;
2592                }
2593                break;
2594              case 4:
2595                switch (crm) {
2596                  case 0:
2597                    switch (op2) {
2598                      case 1:
2599                        return MISCREG_CONTEXTIDR_EL2;
2600                      case 2:
2601                        return MISCREG_TPIDR_EL2;
2602                    }
2603                    break;
2604                }
2605                break;
2606              case 6:
2607                switch (crm) {
2608                  case 0:
2609                    switch (op2) {
2610                      case 2:
2611                        return MISCREG_TPIDR_EL3;
2612                    }
2613                    break;
2614                }
2615                break;
2616            }
2617            break;
2618          case 14:
2619            switch (op1) {
2620              case 0:
2621                switch (crm) {
2622                  case 1:
2623                    switch (op2) {
2624                      case 0:
2625                        return MISCREG_CNTKCTL_EL1;
2626                    }
2627                    break;
2628                }
2629                break;
2630              case 3:
2631                switch (crm) {
2632                  case 0:
2633                    switch (op2) {
2634                      case 0:
2635                        return MISCREG_CNTFRQ_EL0;
2636                      case 1:
2637                        return MISCREG_CNTPCT_EL0;
2638                      case 2:
2639                        return MISCREG_CNTVCT_EL0;
2640                    }
2641                    break;
2642                  case 2:
2643                    switch (op2) {
2644                      case 0:
2645                        return MISCREG_CNTP_TVAL_EL0;
2646                      case 1:
2647                        return MISCREG_CNTP_CTL_EL0;
2648                      case 2:
2649                        return MISCREG_CNTP_CVAL_EL0;
2650                    }
2651                    break;
2652                  case 3:
2653                    switch (op2) {
2654                      case 0:
2655                        return MISCREG_CNTV_TVAL_EL0;
2656                      case 1:
2657                        return MISCREG_CNTV_CTL_EL0;
2658                      case 2:
2659                        return MISCREG_CNTV_CVAL_EL0;
2660                    }
2661                    break;
2662                  case 8:
2663                    switch (op2) {
2664                      case 0:
2665                        return MISCREG_PMEVCNTR0_EL0;
2666                      case 1:
2667                        return MISCREG_PMEVCNTR1_EL0;
2668                      case 2:
2669                        return MISCREG_PMEVCNTR2_EL0;
2670                      case 3:
2671                        return MISCREG_PMEVCNTR3_EL0;
2672                      case 4:
2673                        return MISCREG_PMEVCNTR4_EL0;
2674                      case 5:
2675                        return MISCREG_PMEVCNTR5_EL0;
2676                    }
2677                    break;
2678                  case 12:
2679                    switch (op2) {
2680                      case 0:
2681                        return MISCREG_PMEVTYPER0_EL0;
2682                      case 1:
2683                        return MISCREG_PMEVTYPER1_EL0;
2684                      case 2:
2685                        return MISCREG_PMEVTYPER2_EL0;
2686                      case 3:
2687                        return MISCREG_PMEVTYPER3_EL0;
2688                      case 4:
2689                        return MISCREG_PMEVTYPER4_EL0;
2690                      case 5:
2691                        return MISCREG_PMEVTYPER5_EL0;
2692                    }
2693                    break;
2694                  case 15:
2695                    switch (op2) {
2696                      case 7:
2697                        return MISCREG_PMCCFILTR_EL0;
2698                    }
2699                }
2700                break;
2701              case 4:
2702                switch (crm) {
2703                  case 0:
2704                    switch (op2) {
2705                      case 3:
2706                        return MISCREG_CNTVOFF_EL2;
2707                    }
2708                    break;
2709                  case 1:
2710                    switch (op2) {
2711                      case 0:
2712                        return MISCREG_CNTHCTL_EL2;
2713                    }
2714                    break;
2715                  case 2:
2716                    switch (op2) {
2717                      case 0:
2718                        return MISCREG_CNTHP_TVAL_EL2;
2719                      case 1:
2720                        return MISCREG_CNTHP_CTL_EL2;
2721                      case 2:
2722                        return MISCREG_CNTHP_CVAL_EL2;
2723                    }
2724                    break;
2725                  case 3:
2726                    switch (op2) {
2727                      case 0:
2728                        return MISCREG_CNTHV_TVAL_EL2;
2729                      case 1:
2730                        return MISCREG_CNTHV_CTL_EL2;
2731                      case 2:
2732                        return MISCREG_CNTHV_CVAL_EL2;
2733                    }
2734                    break;
2735                }
2736                break;
2737              case 7:
2738                switch (crm) {
2739                  case 2:
2740                    switch (op2) {
2741                      case 0:
2742                        return MISCREG_CNTPS_TVAL_EL1;
2743                      case 1:
2744                        return MISCREG_CNTPS_CTL_EL1;
2745                      case 2:
2746                        return MISCREG_CNTPS_CVAL_EL1;
2747                    }
2748                    break;
2749                }
2750                break;
2751            }
2752            break;
2753          case 15:
2754            switch (op1) {
2755              case 0:
2756                switch (crm) {
2757                  case 0:
2758                    switch (op2) {
2759                      case 0:
2760                        return MISCREG_IL1DATA0_EL1;
2761                      case 1:
2762                        return MISCREG_IL1DATA1_EL1;
2763                      case 2:
2764                        return MISCREG_IL1DATA2_EL1;
2765                      case 3:
2766                        return MISCREG_IL1DATA3_EL1;
2767                    }
2768                    break;
2769                  case 1:
2770                    switch (op2) {
2771                      case 0:
2772                        return MISCREG_DL1DATA0_EL1;
2773                      case 1:
2774                        return MISCREG_DL1DATA1_EL1;
2775                      case 2:
2776                        return MISCREG_DL1DATA2_EL1;
2777                      case 3:
2778                        return MISCREG_DL1DATA3_EL1;
2779                      case 4:
2780                        return MISCREG_DL1DATA4_EL1;
2781                    }
2782                    break;
2783                }
2784                break;
2785              case 1:
2786                switch (crm) {
2787                  case 0:
2788                    switch (op2) {
2789                      case 0:
2790                        return MISCREG_L2ACTLR_EL1;
2791                    }
2792                    break;
2793                  case 2:
2794                    switch (op2) {
2795                      case 0:
2796                        return MISCREG_CPUACTLR_EL1;
2797                      case 1:
2798                        return MISCREG_CPUECTLR_EL1;
2799                      case 2:
2800                        return MISCREG_CPUMERRSR_EL1;
2801                      case 3:
2802                        return MISCREG_L2MERRSR_EL1;
2803                    }
2804                    break;
2805                  case 3:
2806                    switch (op2) {
2807                      case 0:
2808                        return MISCREG_CBAR_EL1;
2809
2810                    }
2811                    break;
2812                }
2813                break;
2814            }
2815            // S3_<op1>_15_<Cm>_<op2>
2816            return MISCREG_IMPDEF_UNIMPL;
2817        }
2818        break;
2819    }
2820
2821    return MISCREG_UNKNOWN;
2822}
2823
2824bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2825
2826void
2827ISA::initializeMiscRegMetadata()
2828{
2829    // the MiscReg metadata tables are shared across all instances of the
2830    // ISA object, so there's no need to initialize them multiple times.
2831    static bool completed = false;
2832    if (completed)
2833        return;
2834
2835    // This boolean variable specifies if the system is running in aarch32 at
2836    // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2837    // is running in aarch64 (aarch32EL3 = false)
2838    bool aarch32EL3 = haveSecurity && !highestELIs64;
2839
2840    // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2841    // unsupported
2842    bool SPAN = false;
2843
2844    // Implicit error synchronization event enable (Arm 8.2+), unsupported
2845    bool IESB = false;
2846
2847    // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2848    // unsupported
2849    bool LSMAOE = false;
2850
2851    // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2852    bool nTLSMD = false;
2853
2854    // Pointer authentication (Arm 8.3+), unsupported
2855    bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2856    bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2857    bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2858    bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2859
2860    /**
2861     * Some registers alias with others, and therefore need to be translated.
2862     * When two mapping registers are given, they are the 32b lower and
2863     * upper halves, respectively, of the 64b register being mapped.
2864     * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2865     *
2866     * NAM = "not architecturally mandated",
2867     * from ARM DDI 0487A.i, template text
2868     * "AArch64 System register ___ can be mapped to
2869     *  AArch32 System register ___, but this is not
2870     *  architecturally mandated."
2871     */
2872
2873    InitReg(MISCREG_CPSR)
2874      .allPrivileges();
2875    InitReg(MISCREG_SPSR)
2876      .allPrivileges();
2877    InitReg(MISCREG_SPSR_FIQ)
2878      .allPrivileges();
2879    InitReg(MISCREG_SPSR_IRQ)
2880      .allPrivileges();
2881    InitReg(MISCREG_SPSR_SVC)
2882      .allPrivileges();
2883    InitReg(MISCREG_SPSR_MON)
2884      .allPrivileges();
2885    InitReg(MISCREG_SPSR_ABT)
2886      .allPrivileges();
2887    InitReg(MISCREG_SPSR_HYP)
2888      .allPrivileges();
2889    InitReg(MISCREG_SPSR_UND)
2890      .allPrivileges();
2891    InitReg(MISCREG_ELR_HYP)
2892      .allPrivileges();
2893    InitReg(MISCREG_FPSID)
2894      .allPrivileges();
2895    InitReg(MISCREG_FPSCR)
2896      .allPrivileges();
2897    InitReg(MISCREG_MVFR1)
2898      .allPrivileges();
2899    InitReg(MISCREG_MVFR0)
2900      .allPrivileges();
2901    InitReg(MISCREG_FPEXC)
2902      .allPrivileges();
2903
2904    // Helper registers
2905    InitReg(MISCREG_CPSR_MODE)
2906      .allPrivileges();
2907    InitReg(MISCREG_CPSR_Q)
2908      .allPrivileges();
2909    InitReg(MISCREG_FPSCR_EXC)
2910      .allPrivileges();
2911    InitReg(MISCREG_FPSCR_QC)
2912      .allPrivileges();
2913    InitReg(MISCREG_LOCKADDR)
2914      .allPrivileges();
2915    InitReg(MISCREG_LOCKFLAG)
2916      .allPrivileges();
2917    InitReg(MISCREG_PRRR_MAIR0)
2918      .mutex()
2919      .banked();
2920    InitReg(MISCREG_PRRR_MAIR0_NS)
2921      .mutex()
2922      .privSecure(!aarch32EL3)
2923      .bankedChild();
2924    InitReg(MISCREG_PRRR_MAIR0_S)
2925      .mutex()
2926      .bankedChild();
2927    InitReg(MISCREG_NMRR_MAIR1)
2928      .mutex()
2929      .banked();
2930    InitReg(MISCREG_NMRR_MAIR1_NS)
2931      .mutex()
2932      .privSecure(!aarch32EL3)
2933      .bankedChild();
2934    InitReg(MISCREG_NMRR_MAIR1_S)
2935      .mutex()
2936      .bankedChild();
2937    InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2938      .mutex();
2939    InitReg(MISCREG_SCTLR_RST)
2940      .allPrivileges();
2941    InitReg(MISCREG_SEV_MAILBOX)
2942      .allPrivileges();
2943
2944    // AArch32 CP14 registers
2945    InitReg(MISCREG_DBGDIDR)
2946      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2947    InitReg(MISCREG_DBGDSCRint)
2948      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2949    InitReg(MISCREG_DBGDCCINT)
2950      .unimplemented()
2951      .allPrivileges();
2952    InitReg(MISCREG_DBGDTRTXint)
2953      .unimplemented()
2954      .allPrivileges();
2955    InitReg(MISCREG_DBGDTRRXint)
2956      .unimplemented()
2957      .allPrivileges();
2958    InitReg(MISCREG_DBGWFAR)
2959      .unimplemented()
2960      .allPrivileges();
2961    InitReg(MISCREG_DBGVCR)
2962      .unimplemented()
2963      .allPrivileges();
2964    InitReg(MISCREG_DBGDTRRXext)
2965      .unimplemented()
2966      .allPrivileges();
2967    InitReg(MISCREG_DBGDSCRext)
2968      .unimplemented()
2969      .warnNotFail()
2970      .allPrivileges();
2971    InitReg(MISCREG_DBGDTRTXext)
2972      .unimplemented()
2973      .allPrivileges();
2974    InitReg(MISCREG_DBGOSECCR)
2975      .unimplemented()
2976      .allPrivileges();
2977    InitReg(MISCREG_DBGBVR0)
2978      .unimplemented()
2979      .allPrivileges();
2980    InitReg(MISCREG_DBGBVR1)
2981      .unimplemented()
2982      .allPrivileges();
2983    InitReg(MISCREG_DBGBVR2)
2984      .unimplemented()
2985      .allPrivileges();
2986    InitReg(MISCREG_DBGBVR3)
2987      .unimplemented()
2988      .allPrivileges();
2989    InitReg(MISCREG_DBGBVR4)
2990      .unimplemented()
2991      .allPrivileges();
2992    InitReg(MISCREG_DBGBVR5)
2993      .unimplemented()
2994      .allPrivileges();
2995    InitReg(MISCREG_DBGBCR0)
2996      .unimplemented()
2997      .allPrivileges();
2998    InitReg(MISCREG_DBGBCR1)
2999      .unimplemented()
3000      .allPrivileges();
3001    InitReg(MISCREG_DBGBCR2)
3002      .unimplemented()
3003      .allPrivileges();
3004    InitReg(MISCREG_DBGBCR3)
3005      .unimplemented()
3006      .allPrivileges();
3007    InitReg(MISCREG_DBGBCR4)
3008      .unimplemented()
3009      .allPrivileges();
3010    InitReg(MISCREG_DBGBCR5)
3011      .unimplemented()
3012      .allPrivileges();
3013    InitReg(MISCREG_DBGWVR0)
3014      .unimplemented()
3015      .allPrivileges();
3016    InitReg(MISCREG_DBGWVR1)
3017      .unimplemented()
3018      .allPrivileges();
3019    InitReg(MISCREG_DBGWVR2)
3020      .unimplemented()
3021      .allPrivileges();
3022    InitReg(MISCREG_DBGWVR3)
3023      .unimplemented()
3024      .allPrivileges();
3025    InitReg(MISCREG_DBGWCR0)
3026      .unimplemented()
3027      .allPrivileges();
3028    InitReg(MISCREG_DBGWCR1)
3029      .unimplemented()
3030      .allPrivileges();
3031    InitReg(MISCREG_DBGWCR2)
3032      .unimplemented()
3033      .allPrivileges();
3034    InitReg(MISCREG_DBGWCR3)
3035      .unimplemented()
3036      .allPrivileges();
3037    InitReg(MISCREG_DBGDRAR)
3038      .unimplemented()
3039      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3040    InitReg(MISCREG_DBGBXVR4)
3041      .unimplemented()
3042      .allPrivileges();
3043    InitReg(MISCREG_DBGBXVR5)
3044      .unimplemented()
3045      .allPrivileges();
3046    InitReg(MISCREG_DBGOSLAR)
3047      .unimplemented()
3048      .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3049    InitReg(MISCREG_DBGOSLSR)
3050      .unimplemented()
3051      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3052    InitReg(MISCREG_DBGOSDLR)
3053      .unimplemented()
3054      .allPrivileges();
3055    InitReg(MISCREG_DBGPRCR)
3056      .unimplemented()
3057      .allPrivileges();
3058    InitReg(MISCREG_DBGDSAR)
3059      .unimplemented()
3060      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3061    InitReg(MISCREG_DBGCLAIMSET)
3062      .unimplemented()
3063      .allPrivileges();
3064    InitReg(MISCREG_DBGCLAIMCLR)
3065      .unimplemented()
3066      .allPrivileges();
3067    InitReg(MISCREG_DBGAUTHSTATUS)
3068      .unimplemented()
3069      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3070    InitReg(MISCREG_DBGDEVID2)
3071      .unimplemented()
3072      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3073    InitReg(MISCREG_DBGDEVID1)
3074      .unimplemented()
3075      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3076    InitReg(MISCREG_DBGDEVID0)
3077      .unimplemented()
3078      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3079    InitReg(MISCREG_TEECR)
3080      .unimplemented()
3081      .allPrivileges();
3082    InitReg(MISCREG_JIDR)
3083      .allPrivileges();
3084    InitReg(MISCREG_TEEHBR)
3085      .allPrivileges();
3086    InitReg(MISCREG_JOSCR)
3087      .allPrivileges();
3088    InitReg(MISCREG_JMCR)
3089      .allPrivileges();
3090
3091    // AArch32 CP15 registers
3092    InitReg(MISCREG_MIDR)
3093      .allPrivileges().exceptUserMode().writes(0);
3094    InitReg(MISCREG_CTR)
3095      .allPrivileges().exceptUserMode().writes(0);
3096    InitReg(MISCREG_TCMTR)
3097      .allPrivileges().exceptUserMode().writes(0);
3098    InitReg(MISCREG_TLBTR)
3099      .allPrivileges().exceptUserMode().writes(0);
3100    InitReg(MISCREG_MPIDR)
3101      .allPrivileges().exceptUserMode().writes(0);
3102    InitReg(MISCREG_REVIDR)
3103      .unimplemented()
3104      .warnNotFail()
3105      .allPrivileges().exceptUserMode().writes(0);
3106    InitReg(MISCREG_ID_PFR0)
3107      .allPrivileges().exceptUserMode().writes(0);
3108    InitReg(MISCREG_ID_PFR1)
3109      .allPrivileges().exceptUserMode().writes(0);
3110    InitReg(MISCREG_ID_DFR0)
3111      .allPrivileges().exceptUserMode().writes(0);
3112    InitReg(MISCREG_ID_AFR0)
3113      .allPrivileges().exceptUserMode().writes(0);
3114    InitReg(MISCREG_ID_MMFR0)
3115      .allPrivileges().exceptUserMode().writes(0);
3116    InitReg(MISCREG_ID_MMFR1)
3117      .allPrivileges().exceptUserMode().writes(0);
3118    InitReg(MISCREG_ID_MMFR2)
3119      .allPrivileges().exceptUserMode().writes(0);
3120    InitReg(MISCREG_ID_MMFR3)
3121      .allPrivileges().exceptUserMode().writes(0);
3122    InitReg(MISCREG_ID_ISAR0)
3123      .allPrivileges().exceptUserMode().writes(0);
3124    InitReg(MISCREG_ID_ISAR1)
3125      .allPrivileges().exceptUserMode().writes(0);
3126    InitReg(MISCREG_ID_ISAR2)
3127      .allPrivileges().exceptUserMode().writes(0);
3128    InitReg(MISCREG_ID_ISAR3)
3129      .allPrivileges().exceptUserMode().writes(0);
3130    InitReg(MISCREG_ID_ISAR4)
3131      .allPrivileges().exceptUserMode().writes(0);
3132    InitReg(MISCREG_ID_ISAR5)
3133      .allPrivileges().exceptUserMode().writes(0);
3134    InitReg(MISCREG_CCSIDR)
3135      .allPrivileges().exceptUserMode().writes(0);
3136    InitReg(MISCREG_CLIDR)
3137      .allPrivileges().exceptUserMode().writes(0);
3138    InitReg(MISCREG_AIDR)
3139      .allPrivileges().exceptUserMode().writes(0);
3140    InitReg(MISCREG_CSSELR)
3141      .banked();
3142    InitReg(MISCREG_CSSELR_NS)
3143      .bankedChild()
3144      .privSecure(!aarch32EL3)
3145      .nonSecure().exceptUserMode();
3146    InitReg(MISCREG_CSSELR_S)
3147      .bankedChild()
3148      .secure().exceptUserMode();
3149    InitReg(MISCREG_VPIDR)
3150      .hyp().monNonSecure();
3151    InitReg(MISCREG_VMPIDR)
3152      .hyp().monNonSecure();
3153    InitReg(MISCREG_SCTLR)
3154      .banked()
3155      // readMiscRegNoEffect() uses this metadata
3156      // despite using children (below) as backing store
3157      .res0(0x8d22c600)
3158      .res1(0x00400800 | (SPAN   ? 0 : 0x800000)
3159                       | (LSMAOE ? 0 :     0x10)
3160                       | (nTLSMD ? 0 :      0x8));
3161    InitReg(MISCREG_SCTLR_NS)
3162      .bankedChild()
3163      .privSecure(!aarch32EL3)
3164      .nonSecure().exceptUserMode();
3165    InitReg(MISCREG_SCTLR_S)
3166      .bankedChild()
3167      .secure().exceptUserMode();
3168    InitReg(MISCREG_ACTLR)
3169      .banked();
3170    InitReg(MISCREG_ACTLR_NS)
3171      .bankedChild()
3172      .privSecure(!aarch32EL3)
3173      .nonSecure().exceptUserMode();
3174    InitReg(MISCREG_ACTLR_S)
3175      .bankedChild()
3176      .secure().exceptUserMode();
3177    InitReg(MISCREG_CPACR)
3178      .allPrivileges().exceptUserMode();
3179    InitReg(MISCREG_SCR)
3180      .mon().secure().exceptUserMode()
3181      .res0(0xff40)  // [31:16], [6]
3182      .res1(0x0030); // [5:4]
3183    InitReg(MISCREG_SDER)
3184      .mon();
3185    InitReg(MISCREG_NSACR)
3186      .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3187    InitReg(MISCREG_HSCTLR)
3188      .hyp().monNonSecure()
3189      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
3190                       | (IESB   ? 0 :   0x200000)
3191                       | (EnDA   ? 0 :  0x8000000)
3192                       | (EnIB   ? 0 : 0x40000000)
3193                       | (EnIA   ? 0 : 0x80000000))
3194      .res1(0x30c50830);
3195    InitReg(MISCREG_HACTLR)
3196      .hyp().monNonSecure();
3197    InitReg(MISCREG_HCR)
3198      .hyp().monNonSecure();
3199    InitReg(MISCREG_HDCR)
3200      .hyp().monNonSecure();
3201    InitReg(MISCREG_HCPTR)
3202      .hyp().monNonSecure();
3203    InitReg(MISCREG_HSTR)
3204      .hyp().monNonSecure();
3205    InitReg(MISCREG_HACR)
3206      .unimplemented()
3207      .warnNotFail()
3208      .hyp().monNonSecure();
3209    InitReg(MISCREG_TTBR0)
3210      .banked();
3211    InitReg(MISCREG_TTBR0_NS)
3212      .bankedChild()
3213      .privSecure(!aarch32EL3)
3214      .nonSecure().exceptUserMode();
3215    InitReg(MISCREG_TTBR0_S)
3216      .bankedChild()
3217      .secure().exceptUserMode();
3218    InitReg(MISCREG_TTBR1)
3219      .banked();
3220    InitReg(MISCREG_TTBR1_NS)
3221      .bankedChild()
3222      .privSecure(!aarch32EL3)
3223      .nonSecure().exceptUserMode();
3224    InitReg(MISCREG_TTBR1_S)
3225      .bankedChild()
3226      .secure().exceptUserMode();
3227    InitReg(MISCREG_TTBCR)
3228      .banked();
3229    InitReg(MISCREG_TTBCR_NS)
3230      .bankedChild()
3231      .privSecure(!aarch32EL3)
3232      .nonSecure().exceptUserMode();
3233    InitReg(MISCREG_TTBCR_S)
3234      .bankedChild()
3235      .secure().exceptUserMode();
3236    InitReg(MISCREG_HTCR)
3237      .hyp().monNonSecure();
3238    InitReg(MISCREG_VTCR)
3239      .hyp().monNonSecure();
3240    InitReg(MISCREG_DACR)
3241      .banked();
3242    InitReg(MISCREG_DACR_NS)
3243      .bankedChild()
3244      .privSecure(!aarch32EL3)
3245      .nonSecure().exceptUserMode();
3246    InitReg(MISCREG_DACR_S)
3247      .bankedChild()
3248      .secure().exceptUserMode();
3249    InitReg(MISCREG_DFSR)
3250      .banked();
3251    InitReg(MISCREG_DFSR_NS)
3252      .bankedChild()
3253      .privSecure(!aarch32EL3)
3254      .nonSecure().exceptUserMode();
3255    InitReg(MISCREG_DFSR_S)
3256      .bankedChild()
3257      .secure().exceptUserMode();
3258    InitReg(MISCREG_IFSR)
3259      .banked();
3260    InitReg(MISCREG_IFSR_NS)
3261      .bankedChild()
3262      .privSecure(!aarch32EL3)
3263      .nonSecure().exceptUserMode();
3264    InitReg(MISCREG_IFSR_S)
3265      .bankedChild()
3266      .secure().exceptUserMode();
3267    InitReg(MISCREG_ADFSR)
3268      .unimplemented()
3269      .warnNotFail()
3270      .banked();
3271    InitReg(MISCREG_ADFSR_NS)
3272      .unimplemented()
3273      .warnNotFail()
3274      .bankedChild()
3275      .privSecure(!aarch32EL3)
3276      .nonSecure().exceptUserMode();
3277    InitReg(MISCREG_ADFSR_S)
3278      .unimplemented()
3279      .warnNotFail()
3280      .bankedChild()
3281      .secure().exceptUserMode();
3282    InitReg(MISCREG_AIFSR)
3283      .unimplemented()
3284      .warnNotFail()
3285      .banked();
3286    InitReg(MISCREG_AIFSR_NS)
3287      .unimplemented()
3288      .warnNotFail()
3289      .bankedChild()
3290      .privSecure(!aarch32EL3)
3291      .nonSecure().exceptUserMode();
3292    InitReg(MISCREG_AIFSR_S)
3293      .unimplemented()
3294      .warnNotFail()
3295      .bankedChild()
3296      .secure().exceptUserMode();
3297    InitReg(MISCREG_HADFSR)
3298      .hyp().monNonSecure();
3299    InitReg(MISCREG_HAIFSR)
3300      .hyp().monNonSecure();
3301    InitReg(MISCREG_HSR)
3302      .hyp().monNonSecure();
3303    InitReg(MISCREG_DFAR)
3304      .banked();
3305    InitReg(MISCREG_DFAR_NS)
3306      .bankedChild()
3307      .privSecure(!aarch32EL3)
3308      .nonSecure().exceptUserMode();
3309    InitReg(MISCREG_DFAR_S)
3310      .bankedChild()
3311      .secure().exceptUserMode();
3312    InitReg(MISCREG_IFAR)
3313      .banked();
3314    InitReg(MISCREG_IFAR_NS)
3315      .bankedChild()
3316      .privSecure(!aarch32EL3)
3317      .nonSecure().exceptUserMode();
3318    InitReg(MISCREG_IFAR_S)
3319      .bankedChild()
3320      .secure().exceptUserMode();
3321    InitReg(MISCREG_HDFAR)
3322      .hyp().monNonSecure();
3323    InitReg(MISCREG_HIFAR)
3324      .hyp().monNonSecure();
3325    InitReg(MISCREG_HPFAR)
3326      .hyp().monNonSecure();
3327    InitReg(MISCREG_ICIALLUIS)
3328      .unimplemented()
3329      .warnNotFail()
3330      .writes(1).exceptUserMode();
3331    InitReg(MISCREG_BPIALLIS)
3332      .unimplemented()
3333      .warnNotFail()
3334      .writes(1).exceptUserMode();
3335    InitReg(MISCREG_PAR)
3336      .banked();
3337    InitReg(MISCREG_PAR_NS)
3338      .bankedChild()
3339      .privSecure(!aarch32EL3)
3340      .nonSecure().exceptUserMode();
3341    InitReg(MISCREG_PAR_S)
3342      .bankedChild()
3343      .secure().exceptUserMode();
3344    InitReg(MISCREG_ICIALLU)
3345      .writes(1).exceptUserMode();
3346    InitReg(MISCREG_ICIMVAU)
3347      .unimplemented()
3348      .warnNotFail()
3349      .writes(1).exceptUserMode();
3350    InitReg(MISCREG_CP15ISB)
3351      .writes(1);
3352    InitReg(MISCREG_BPIALL)
3353      .unimplemented()
3354      .warnNotFail()
3355      .writes(1).exceptUserMode();
3356    InitReg(MISCREG_BPIMVA)
3357      .unimplemented()
3358      .warnNotFail()
3359      .writes(1).exceptUserMode();
3360    InitReg(MISCREG_DCIMVAC)
3361      .unimplemented()
3362      .warnNotFail()
3363      .writes(1).exceptUserMode();
3364    InitReg(MISCREG_DCISW)
3365      .unimplemented()
3366      .warnNotFail()
3367      .writes(1).exceptUserMode();
3368    InitReg(MISCREG_ATS1CPR)
3369      .writes(1).exceptUserMode();
3370    InitReg(MISCREG_ATS1CPW)
3371      .writes(1).exceptUserMode();
3372    InitReg(MISCREG_ATS1CUR)
3373      .writes(1).exceptUserMode();
3374    InitReg(MISCREG_ATS1CUW)
3375      .writes(1).exceptUserMode();
3376    InitReg(MISCREG_ATS12NSOPR)
3377      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3378    InitReg(MISCREG_ATS12NSOPW)
3379      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3380    InitReg(MISCREG_ATS12NSOUR)
3381      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3382    InitReg(MISCREG_ATS12NSOUW)
3383      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3384    InitReg(MISCREG_DCCMVAC)
3385      .writes(1).exceptUserMode();
3386    InitReg(MISCREG_DCCSW)
3387      .unimplemented()
3388      .warnNotFail()
3389      .writes(1).exceptUserMode();
3390    InitReg(MISCREG_CP15DSB)
3391      .writes(1);
3392    InitReg(MISCREG_CP15DMB)
3393      .writes(1);
3394    InitReg(MISCREG_DCCMVAU)
3395      .unimplemented()
3396      .warnNotFail()
3397      .writes(1).exceptUserMode();
3398    InitReg(MISCREG_DCCIMVAC)
3399      .unimplemented()
3400      .warnNotFail()
3401      .writes(1).exceptUserMode();
3402    InitReg(MISCREG_DCCISW)
3403      .unimplemented()
3404      .warnNotFail()
3405      .writes(1).exceptUserMode();
3406    InitReg(MISCREG_ATS1HR)
3407      .monNonSecureWrite().hypWrite();
3408    InitReg(MISCREG_ATS1HW)
3409      .monNonSecureWrite().hypWrite();
3410    InitReg(MISCREG_TLBIALLIS)
3411      .writes(1).exceptUserMode();
3412    InitReg(MISCREG_TLBIMVAIS)
3413      .writes(1).exceptUserMode();
3414    InitReg(MISCREG_TLBIASIDIS)
3415      .writes(1).exceptUserMode();
3416    InitReg(MISCREG_TLBIMVAAIS)
3417      .writes(1).exceptUserMode();
3418    InitReg(MISCREG_TLBIMVALIS)
3419      .writes(1).exceptUserMode();
3420    InitReg(MISCREG_TLBIMVAALIS)
3421      .writes(1).exceptUserMode();
3422    InitReg(MISCREG_ITLBIALL)
3423      .writes(1).exceptUserMode();
3424    InitReg(MISCREG_ITLBIMVA)
3425      .writes(1).exceptUserMode();
3426    InitReg(MISCREG_ITLBIASID)
3427      .writes(1).exceptUserMode();
3428    InitReg(MISCREG_DTLBIALL)
3429      .writes(1).exceptUserMode();
3430    InitReg(MISCREG_DTLBIMVA)
3431      .writes(1).exceptUserMode();
3432    InitReg(MISCREG_DTLBIASID)
3433      .writes(1).exceptUserMode();
3434    InitReg(MISCREG_TLBIALL)
3435      .writes(1).exceptUserMode();
3436    InitReg(MISCREG_TLBIMVA)
3437      .writes(1).exceptUserMode();
3438    InitReg(MISCREG_TLBIASID)
3439      .writes(1).exceptUserMode();
3440    InitReg(MISCREG_TLBIMVAA)
3441      .writes(1).exceptUserMode();
3442    InitReg(MISCREG_TLBIMVAL)
3443      .writes(1).exceptUserMode();
3444    InitReg(MISCREG_TLBIMVAAL)
3445      .writes(1).exceptUserMode();
3446    InitReg(MISCREG_TLBIIPAS2IS)
3447      .monNonSecureWrite().hypWrite();
3448    InitReg(MISCREG_TLBIIPAS2LIS)
3449      .monNonSecureWrite().hypWrite();
3450    InitReg(MISCREG_TLBIALLHIS)
3451      .monNonSecureWrite().hypWrite();
3452    InitReg(MISCREG_TLBIMVAHIS)
3453      .monNonSecureWrite().hypWrite();
3454    InitReg(MISCREG_TLBIALLNSNHIS)
3455      .monNonSecureWrite().hypWrite();
3456    InitReg(MISCREG_TLBIMVALHIS)
3457      .monNonSecureWrite().hypWrite();
3458    InitReg(MISCREG_TLBIIPAS2)
3459      .monNonSecureWrite().hypWrite();
3460    InitReg(MISCREG_TLBIIPAS2L)
3461      .monNonSecureWrite().hypWrite();
3462    InitReg(MISCREG_TLBIALLH)
3463      .monNonSecureWrite().hypWrite();
3464    InitReg(MISCREG_TLBIMVAH)
3465      .monNonSecureWrite().hypWrite();
3466    InitReg(MISCREG_TLBIALLNSNH)
3467      .monNonSecureWrite().hypWrite();
3468    InitReg(MISCREG_TLBIMVALH)
3469      .monNonSecureWrite().hypWrite();
3470    InitReg(MISCREG_PMCR)
3471      .allPrivileges();
3472    InitReg(MISCREG_PMCNTENSET)
3473      .allPrivileges();
3474    InitReg(MISCREG_PMCNTENCLR)
3475      .allPrivileges();
3476    InitReg(MISCREG_PMOVSR)
3477      .allPrivileges();
3478    InitReg(MISCREG_PMSWINC)
3479      .allPrivileges();
3480    InitReg(MISCREG_PMSELR)
3481      .allPrivileges();
3482    InitReg(MISCREG_PMCEID0)
3483      .allPrivileges();
3484    InitReg(MISCREG_PMCEID1)
3485      .allPrivileges();
3486    InitReg(MISCREG_PMCCNTR)
3487      .allPrivileges();
3488    InitReg(MISCREG_PMXEVTYPER)
3489      .allPrivileges();
3490    InitReg(MISCREG_PMCCFILTR)
3491      .allPrivileges();
3492    InitReg(MISCREG_PMXEVCNTR)
3493      .allPrivileges();
3494    InitReg(MISCREG_PMUSERENR)
3495      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3496    InitReg(MISCREG_PMINTENSET)
3497      .allPrivileges().exceptUserMode();
3498    InitReg(MISCREG_PMINTENCLR)
3499      .allPrivileges().exceptUserMode();
3500    InitReg(MISCREG_PMOVSSET)
3501      .unimplemented()
3502      .allPrivileges();
3503    InitReg(MISCREG_L2CTLR)
3504      .allPrivileges().exceptUserMode();
3505    InitReg(MISCREG_L2ECTLR)
3506      .unimplemented()
3507      .allPrivileges().exceptUserMode();
3508    InitReg(MISCREG_PRRR)
3509      .banked();
3510    InitReg(MISCREG_PRRR_NS)
3511      .bankedChild()
3512      .privSecure(!aarch32EL3)
3513      .nonSecure().exceptUserMode();
3514    InitReg(MISCREG_PRRR_S)
3515      .bankedChild()
3516      .secure().exceptUserMode();
3517    InitReg(MISCREG_MAIR0)
3518      .banked();
3519    InitReg(MISCREG_MAIR0_NS)
3520      .bankedChild()
3521      .privSecure(!aarch32EL3)
3522      .nonSecure().exceptUserMode();
3523    InitReg(MISCREG_MAIR0_S)
3524      .bankedChild()
3525      .secure().exceptUserMode();
3526    InitReg(MISCREG_NMRR)
3527      .banked();
3528    InitReg(MISCREG_NMRR_NS)
3529      .bankedChild()
3530      .privSecure(!aarch32EL3)
3531      .nonSecure().exceptUserMode();
3532    InitReg(MISCREG_NMRR_S)
3533      .bankedChild()
3534      .secure().exceptUserMode();
3535    InitReg(MISCREG_MAIR1)
3536      .banked();
3537    InitReg(MISCREG_MAIR1_NS)
3538      .bankedChild()
3539      .privSecure(!aarch32EL3)
3540      .nonSecure().exceptUserMode();
3541    InitReg(MISCREG_MAIR1_S)
3542      .bankedChild()
3543      .secure().exceptUserMode();
3544    InitReg(MISCREG_AMAIR0)
3545      .banked();
3546    InitReg(MISCREG_AMAIR0_NS)
3547      .bankedChild()
3548      .privSecure(!aarch32EL3)
3549      .nonSecure().exceptUserMode();
3550    InitReg(MISCREG_AMAIR0_S)
3551      .bankedChild()
3552      .secure().exceptUserMode();
3553    InitReg(MISCREG_AMAIR1)
3554      .banked();
3555    InitReg(MISCREG_AMAIR1_NS)
3556      .bankedChild()
3557      .privSecure(!aarch32EL3)
3558      .nonSecure().exceptUserMode();
3559    InitReg(MISCREG_AMAIR1_S)
3560      .bankedChild()
3561      .secure().exceptUserMode();
3562    InitReg(MISCREG_HMAIR0)
3563      .hyp().monNonSecure();
3564    InitReg(MISCREG_HMAIR1)
3565      .hyp().monNonSecure();
3566    InitReg(MISCREG_HAMAIR0)
3567      .unimplemented()
3568      .warnNotFail()
3569      .hyp().monNonSecure();
3570    InitReg(MISCREG_HAMAIR1)
3571      .unimplemented()
3572      .warnNotFail()
3573      .hyp().monNonSecure();
3574    InitReg(MISCREG_VBAR)
3575      .banked();
3576    InitReg(MISCREG_VBAR_NS)
3577      .bankedChild()
3578      .privSecure(!aarch32EL3)
3579      .nonSecure().exceptUserMode();
3580    InitReg(MISCREG_VBAR_S)
3581      .bankedChild()
3582      .secure().exceptUserMode();
3583    InitReg(MISCREG_MVBAR)
3584      .mon().secure()
3585      .hypRead(FullSystem && system->highestEL() == EL2)
3586      .privRead(FullSystem && system->highestEL() == EL1)
3587      .exceptUserMode();
3588    InitReg(MISCREG_RMR)
3589      .unimplemented()
3590      .mon().secure().exceptUserMode();
3591    InitReg(MISCREG_ISR)
3592      .allPrivileges().exceptUserMode().writes(0);
3593    InitReg(MISCREG_HVBAR)
3594      .hyp().monNonSecure()
3595      .res0(0x1f);
3596    InitReg(MISCREG_FCSEIDR)
3597      .unimplemented()
3598      .warnNotFail()
3599      .allPrivileges().exceptUserMode();
3600    InitReg(MISCREG_CONTEXTIDR)
3601      .banked();
3602    InitReg(MISCREG_CONTEXTIDR_NS)
3603      .bankedChild()
3604      .privSecure(!aarch32EL3)
3605      .nonSecure().exceptUserMode();
3606    InitReg(MISCREG_CONTEXTIDR_S)
3607      .bankedChild()
3608      .secure().exceptUserMode();
3609    InitReg(MISCREG_TPIDRURW)
3610      .banked();
3611    InitReg(MISCREG_TPIDRURW_NS)
3612      .bankedChild()
3613      .allPrivileges()
3614      .privSecure(!aarch32EL3)
3615      .monSecure(0);
3616    InitReg(MISCREG_TPIDRURW_S)
3617      .bankedChild()
3618      .secure();
3619    InitReg(MISCREG_TPIDRURO)
3620      .banked();
3621    InitReg(MISCREG_TPIDRURO_NS)
3622      .bankedChild()
3623      .allPrivileges()
3624      .userNonSecureWrite(0).userSecureRead(1)
3625      .privSecure(!aarch32EL3)
3626      .monSecure(0);
3627    InitReg(MISCREG_TPIDRURO_S)
3628      .bankedChild()
3629      .secure().userSecureWrite(0);
3630    InitReg(MISCREG_TPIDRPRW)
3631      .banked();
3632    InitReg(MISCREG_TPIDRPRW_NS)
3633      .bankedChild()
3634      .nonSecure().exceptUserMode()
3635      .privSecure(!aarch32EL3);
3636    InitReg(MISCREG_TPIDRPRW_S)
3637      .bankedChild()
3638      .secure().exceptUserMode();
3639    InitReg(MISCREG_HTPIDR)
3640      .hyp().monNonSecure();
3641    InitReg(MISCREG_CNTFRQ)
3642      .unverifiable()
3643      .reads(1).mon();
3644    InitReg(MISCREG_CNTKCTL)
3645      .allPrivileges().exceptUserMode();
3646    InitReg(MISCREG_CNTP_TVAL)
3647      .banked();
3648    InitReg(MISCREG_CNTP_TVAL_NS)
3649      .bankedChild()
3650      .allPrivileges()
3651      .privSecure(!aarch32EL3)
3652      .monSecure(0);
3653    InitReg(MISCREG_CNTP_TVAL_S)
3654      .bankedChild()
3655      .secure().user(1);
3656    InitReg(MISCREG_CNTP_CTL)
3657      .banked();
3658    InitReg(MISCREG_CNTP_CTL_NS)
3659      .bankedChild()
3660      .allPrivileges()
3661      .privSecure(!aarch32EL3)
3662      .monSecure(0);
3663    InitReg(MISCREG_CNTP_CTL_S)
3664      .bankedChild()
3665      .secure().user(1);
3666    InitReg(MISCREG_CNTV_TVAL)
3667      .allPrivileges();
3668    InitReg(MISCREG_CNTV_CTL)
3669      .allPrivileges();
3670    InitReg(MISCREG_CNTHCTL)
3671      .hypWrite().monNonSecureRead();
3672    InitReg(MISCREG_CNTHP_TVAL)
3673      .hypWrite().monNonSecureRead();
3674    InitReg(MISCREG_CNTHP_CTL)
3675      .hypWrite().monNonSecureRead();
3676    InitReg(MISCREG_IL1DATA0)
3677      .unimplemented()
3678      .allPrivileges().exceptUserMode();
3679    InitReg(MISCREG_IL1DATA1)
3680      .unimplemented()
3681      .allPrivileges().exceptUserMode();
3682    InitReg(MISCREG_IL1DATA2)
3683      .unimplemented()
3684      .allPrivileges().exceptUserMode();
3685    InitReg(MISCREG_IL1DATA3)
3686      .unimplemented()
3687      .allPrivileges().exceptUserMode();
3688    InitReg(MISCREG_DL1DATA0)
3689      .unimplemented()
3690      .allPrivileges().exceptUserMode();
3691    InitReg(MISCREG_DL1DATA1)
3692      .unimplemented()
3693      .allPrivileges().exceptUserMode();
3694    InitReg(MISCREG_DL1DATA2)
3695      .unimplemented()
3696      .allPrivileges().exceptUserMode();
3697    InitReg(MISCREG_DL1DATA3)
3698      .unimplemented()
3699      .allPrivileges().exceptUserMode();
3700    InitReg(MISCREG_DL1DATA4)
3701      .unimplemented()
3702      .allPrivileges().exceptUserMode();
3703    InitReg(MISCREG_RAMINDEX)
3704      .unimplemented()
3705      .writes(1).exceptUserMode();
3706    InitReg(MISCREG_L2ACTLR)
3707      .unimplemented()
3708      .allPrivileges().exceptUserMode();
3709    InitReg(MISCREG_CBAR)
3710      .unimplemented()
3711      .allPrivileges().exceptUserMode().writes(0);
3712    InitReg(MISCREG_HTTBR)
3713      .hyp().monNonSecure();
3714    InitReg(MISCREG_VTTBR)
3715      .hyp().monNonSecure();
3716    InitReg(MISCREG_CNTPCT)
3717      .reads(1);
3718    InitReg(MISCREG_CNTVCT)
3719      .unverifiable()
3720      .reads(1);
3721    InitReg(MISCREG_CNTP_CVAL)
3722      .banked();
3723    InitReg(MISCREG_CNTP_CVAL_NS)
3724      .bankedChild()
3725      .allPrivileges()
3726      .privSecure(!aarch32EL3)
3727      .monSecure(0);
3728    InitReg(MISCREG_CNTP_CVAL_S)
3729      .bankedChild()
3730      .secure().user(1);
3731    InitReg(MISCREG_CNTV_CVAL)
3732      .allPrivileges();
3733    InitReg(MISCREG_CNTVOFF)
3734      .hyp().monNonSecure();
3735    InitReg(MISCREG_CNTHP_CVAL)
3736      .hypWrite().monNonSecureRead();
3737    InitReg(MISCREG_CPUMERRSR)
3738      .unimplemented()
3739      .allPrivileges().exceptUserMode();
3740    InitReg(MISCREG_L2MERRSR)
3741      .unimplemented()
3742      .warnNotFail()
3743      .allPrivileges().exceptUserMode();
3744
3745    // AArch64 registers (Op0=2);
3746    InitReg(MISCREG_MDCCINT_EL1)
3747      .allPrivileges();
3748    InitReg(MISCREG_OSDTRRX_EL1)
3749      .allPrivileges()
3750      .mapsTo(MISCREG_DBGDTRRXext);
3751    InitReg(MISCREG_MDSCR_EL1)
3752      .allPrivileges()
3753      .mapsTo(MISCREG_DBGDSCRext);
3754    InitReg(MISCREG_OSDTRTX_EL1)
3755      .allPrivileges()
3756      .mapsTo(MISCREG_DBGDTRTXext);
3757    InitReg(MISCREG_OSECCR_EL1)
3758      .allPrivileges()
3759      .mapsTo(MISCREG_DBGOSECCR);
3760    InitReg(MISCREG_DBGBVR0_EL1)
3761      .allPrivileges()
3762      .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3763    InitReg(MISCREG_DBGBVR1_EL1)
3764      .allPrivileges()
3765      .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3766    InitReg(MISCREG_DBGBVR2_EL1)
3767      .allPrivileges()
3768      .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3769    InitReg(MISCREG_DBGBVR3_EL1)
3770      .allPrivileges()
3771      .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3772    InitReg(MISCREG_DBGBVR4_EL1)
3773      .allPrivileges()
3774      .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3775    InitReg(MISCREG_DBGBVR5_EL1)
3776      .allPrivileges()
3777      .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3778    InitReg(MISCREG_DBGBCR0_EL1)
3779      .allPrivileges()
3780      .mapsTo(MISCREG_DBGBCR0);
3781    InitReg(MISCREG_DBGBCR1_EL1)
3782      .allPrivileges()
3783      .mapsTo(MISCREG_DBGBCR1);
3784    InitReg(MISCREG_DBGBCR2_EL1)
3785      .allPrivileges()
3786      .mapsTo(MISCREG_DBGBCR2);
3787    InitReg(MISCREG_DBGBCR3_EL1)
3788      .allPrivileges()
3789      .mapsTo(MISCREG_DBGBCR3);
3790    InitReg(MISCREG_DBGBCR4_EL1)
3791      .allPrivileges()
3792      .mapsTo(MISCREG_DBGBCR4);
3793    InitReg(MISCREG_DBGBCR5_EL1)
3794      .allPrivileges()
3795      .mapsTo(MISCREG_DBGBCR5);
3796    InitReg(MISCREG_DBGWVR0_EL1)
3797      .allPrivileges()
3798      .mapsTo(MISCREG_DBGWVR0);
3799    InitReg(MISCREG_DBGWVR1_EL1)
3800      .allPrivileges()
3801      .mapsTo(MISCREG_DBGWVR1);
3802    InitReg(MISCREG_DBGWVR2_EL1)
3803      .allPrivileges()
3804      .mapsTo(MISCREG_DBGWVR2);
3805    InitReg(MISCREG_DBGWVR3_EL1)
3806      .allPrivileges()
3807      .mapsTo(MISCREG_DBGWVR3);
3808    InitReg(MISCREG_DBGWCR0_EL1)
3809      .allPrivileges()
3810      .mapsTo(MISCREG_DBGWCR0);
3811    InitReg(MISCREG_DBGWCR1_EL1)
3812      .allPrivileges()
3813      .mapsTo(MISCREG_DBGWCR1);
3814    InitReg(MISCREG_DBGWCR2_EL1)
3815      .allPrivileges()
3816      .mapsTo(MISCREG_DBGWCR2);
3817    InitReg(MISCREG_DBGWCR3_EL1)
3818      .allPrivileges()
3819      .mapsTo(MISCREG_DBGWCR3);
3820    InitReg(MISCREG_MDCCSR_EL0)
3821      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3822      .mapsTo(MISCREG_DBGDSCRint);
3823    InitReg(MISCREG_MDDTR_EL0)
3824      .allPrivileges();
3825    InitReg(MISCREG_MDDTRTX_EL0)
3826      .allPrivileges();
3827    InitReg(MISCREG_MDDTRRX_EL0)
3828      .allPrivileges();
3829    InitReg(MISCREG_DBGVCR32_EL2)
3830      .allPrivileges()
3831      .mapsTo(MISCREG_DBGVCR);
3832    InitReg(MISCREG_MDRAR_EL1)
3833      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3834      .mapsTo(MISCREG_DBGDRAR);
3835    InitReg(MISCREG_OSLAR_EL1)
3836      .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3837      .mapsTo(MISCREG_DBGOSLAR);
3838    InitReg(MISCREG_OSLSR_EL1)
3839      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3840      .mapsTo(MISCREG_DBGOSLSR);
3841    InitReg(MISCREG_OSDLR_EL1)
3842      .allPrivileges()
3843      .mapsTo(MISCREG_DBGOSDLR);
3844    InitReg(MISCREG_DBGPRCR_EL1)
3845      .allPrivileges()
3846      .mapsTo(MISCREG_DBGPRCR);
3847    InitReg(MISCREG_DBGCLAIMSET_EL1)
3848      .allPrivileges()
3849      .mapsTo(MISCREG_DBGCLAIMSET);
3850    InitReg(MISCREG_DBGCLAIMCLR_EL1)
3851      .allPrivileges()
3852      .mapsTo(MISCREG_DBGCLAIMCLR);
3853    InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3854      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3855      .mapsTo(MISCREG_DBGAUTHSTATUS);
3856    InitReg(MISCREG_TEECR32_EL1);
3857    InitReg(MISCREG_TEEHBR32_EL1);
3858
3859    // AArch64 registers (Op0=1,3);
3860    InitReg(MISCREG_MIDR_EL1)
3861      .allPrivileges().exceptUserMode().writes(0);
3862    InitReg(MISCREG_MPIDR_EL1)
3863      .allPrivileges().exceptUserMode().writes(0);
3864    InitReg(MISCREG_REVIDR_EL1)
3865      .allPrivileges().exceptUserMode().writes(0);
3866    InitReg(MISCREG_ID_PFR0_EL1)
3867      .allPrivileges().exceptUserMode().writes(0)
3868      .mapsTo(MISCREG_ID_PFR0);
3869    InitReg(MISCREG_ID_PFR1_EL1)
3870      .allPrivileges().exceptUserMode().writes(0)
3871      .mapsTo(MISCREG_ID_PFR1);
3872    InitReg(MISCREG_ID_DFR0_EL1)
3873      .allPrivileges().exceptUserMode().writes(0)
3874      .mapsTo(MISCREG_ID_DFR0);
3875    InitReg(MISCREG_ID_AFR0_EL1)
3876      .allPrivileges().exceptUserMode().writes(0)
3877      .mapsTo(MISCREG_ID_AFR0);
3878    InitReg(MISCREG_ID_MMFR0_EL1)
3879      .allPrivileges().exceptUserMode().writes(0)
3880      .mapsTo(MISCREG_ID_MMFR0);
3881    InitReg(MISCREG_ID_MMFR1_EL1)
3882      .allPrivileges().exceptUserMode().writes(0)
3883      .mapsTo(MISCREG_ID_MMFR1);
3884    InitReg(MISCREG_ID_MMFR2_EL1)
3885      .allPrivileges().exceptUserMode().writes(0)
3886      .mapsTo(MISCREG_ID_MMFR2);
3887    InitReg(MISCREG_ID_MMFR3_EL1)
3888      .allPrivileges().exceptUserMode().writes(0)
3889      .mapsTo(MISCREG_ID_MMFR3);
3890    InitReg(MISCREG_ID_ISAR0_EL1)
3891      .allPrivileges().exceptUserMode().writes(0)
3892      .mapsTo(MISCREG_ID_ISAR0);
3893    InitReg(MISCREG_ID_ISAR1_EL1)
3894      .allPrivileges().exceptUserMode().writes(0)
3895      .mapsTo(MISCREG_ID_ISAR1);
3896    InitReg(MISCREG_ID_ISAR2_EL1)
3897      .allPrivileges().exceptUserMode().writes(0)
3898      .mapsTo(MISCREG_ID_ISAR2);
3899    InitReg(MISCREG_ID_ISAR3_EL1)
3900      .allPrivileges().exceptUserMode().writes(0)
3901      .mapsTo(MISCREG_ID_ISAR3);
3902    InitReg(MISCREG_ID_ISAR4_EL1)
3903      .allPrivileges().exceptUserMode().writes(0)
3904      .mapsTo(MISCREG_ID_ISAR4);
3905    InitReg(MISCREG_ID_ISAR5_EL1)
3906      .allPrivileges().exceptUserMode().writes(0)
3907      .mapsTo(MISCREG_ID_ISAR5);
3908    InitReg(MISCREG_MVFR0_EL1)
3909      .allPrivileges().exceptUserMode().writes(0);
3910    InitReg(MISCREG_MVFR1_EL1)
3911      .allPrivileges().exceptUserMode().writes(0);
3912    InitReg(MISCREG_MVFR2_EL1)
3913      .allPrivileges().exceptUserMode().writes(0);
3914    InitReg(MISCREG_ID_AA64PFR0_EL1)
3915      .allPrivileges().exceptUserMode().writes(0);
3916    InitReg(MISCREG_ID_AA64PFR1_EL1)
3917      .allPrivileges().exceptUserMode().writes(0);
3918    InitReg(MISCREG_ID_AA64DFR0_EL1)
3919      .allPrivileges().exceptUserMode().writes(0);
3920    InitReg(MISCREG_ID_AA64DFR1_EL1)
3921      .allPrivileges().exceptUserMode().writes(0);
3922    InitReg(MISCREG_ID_AA64AFR0_EL1)
3923      .allPrivileges().exceptUserMode().writes(0);
3924    InitReg(MISCREG_ID_AA64AFR1_EL1)
3925      .allPrivileges().exceptUserMode().writes(0);
3926    InitReg(MISCREG_ID_AA64ISAR0_EL1)
3927      .allPrivileges().exceptUserMode().writes(0);
3928    InitReg(MISCREG_ID_AA64ISAR1_EL1)
3929      .allPrivileges().exceptUserMode().writes(0);
3930    InitReg(MISCREG_ID_AA64MMFR0_EL1)
3931      .allPrivileges().exceptUserMode().writes(0);
3932    InitReg(MISCREG_ID_AA64MMFR1_EL1)
3933      .allPrivileges().exceptUserMode().writes(0);
3934    InitReg(MISCREG_ID_AA64MMFR2_EL1)
3935      .allPrivileges().exceptUserMode().writes(0);
3936    InitReg(MISCREG_CCSIDR_EL1)
3937      .allPrivileges().exceptUserMode().writes(0);
3938    InitReg(MISCREG_CLIDR_EL1)
3939      .allPrivileges().exceptUserMode().writes(0);
3940    InitReg(MISCREG_AIDR_EL1)
3941      .allPrivileges().exceptUserMode().writes(0);
3942    InitReg(MISCREG_CSSELR_EL1)
3943      .allPrivileges().exceptUserMode()
3944      .mapsTo(MISCREG_CSSELR_NS);
3945    InitReg(MISCREG_CTR_EL0)
3946      .reads(1);
3947    InitReg(MISCREG_DCZID_EL0)
3948      .reads(1);
3949    InitReg(MISCREG_VPIDR_EL2)
3950      .hyp().mon()
3951      .mapsTo(MISCREG_VPIDR);
3952    InitReg(MISCREG_VMPIDR_EL2)
3953      .hyp().mon()
3954      .mapsTo(MISCREG_VMPIDR);
3955    InitReg(MISCREG_SCTLR_EL1)
3956      .allPrivileges().exceptUserMode()
3957      .res0( 0x20440 | (EnDB   ? 0 :     0x2000)
3958                     | (IESB   ? 0 :   0x200000)
3959                     | (EnDA   ? 0 :  0x8000000)
3960                     | (EnIB   ? 0 : 0x40000000)
3961                     | (EnIA   ? 0 : 0x80000000))
3962      .res1(0x500800 | (SPAN   ? 0 :   0x800000)
3963                     | (nTLSMD ? 0 :  0x8000000)
3964                     | (LSMAOE ? 0 : 0x10000000))
3965      .mapsTo(MISCREG_SCTLR_NS);
3966    InitReg(MISCREG_ACTLR_EL1)
3967      .allPrivileges().exceptUserMode()
3968      .mapsTo(MISCREG_ACTLR_NS);
3969    InitReg(MISCREG_CPACR_EL1)
3970      .allPrivileges().exceptUserMode()
3971      .mapsTo(MISCREG_CPACR);
3972    InitReg(MISCREG_SCTLR_EL2)
3973      .hyp().mon()
3974      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
3975                       | (IESB   ? 0 :   0x200000)
3976                       | (EnDA   ? 0 :  0x8000000)
3977                       | (EnIB   ? 0 : 0x40000000)
3978                       | (EnIA   ? 0 : 0x80000000))
3979      .res1(0x30c50830)
3980      .mapsTo(MISCREG_HSCTLR);
3981    InitReg(MISCREG_ACTLR_EL2)
3982      .hyp().mon()
3983      .mapsTo(MISCREG_HACTLR);
3984    InitReg(MISCREG_HCR_EL2)
3985      .hyp().mon()
3986      .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3987    InitReg(MISCREG_MDCR_EL2)
3988      .hyp().mon()
3989      .mapsTo(MISCREG_HDCR);
3990    InitReg(MISCREG_CPTR_EL2)
3991      .hyp().mon()
3992      .mapsTo(MISCREG_HCPTR);
3993    InitReg(MISCREG_HSTR_EL2)
3994      .hyp().mon()
3995      .mapsTo(MISCREG_HSTR);
3996    InitReg(MISCREG_HACR_EL2)
3997      .hyp().mon()
3998      .mapsTo(MISCREG_HACR);
3999    InitReg(MISCREG_SCTLR_EL3)
4000      .mon()
4001      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
4002                       | (IESB   ? 0 :   0x200000)
4003                       | (EnDA   ? 0 :  0x8000000)
4004                       | (EnIB   ? 0 : 0x40000000)
4005                       | (EnIA   ? 0 : 0x80000000))
4006      .res1(0x30c50830);
4007    InitReg(MISCREG_ACTLR_EL3)
4008      .mon();
4009    InitReg(MISCREG_SCR_EL3)
4010      .mon()
4011      .mapsTo(MISCREG_SCR); // NAM D7-2005
4012    InitReg(MISCREG_SDER32_EL3)
4013      .mon()
4014      .mapsTo(MISCREG_SDER);
4015    InitReg(MISCREG_CPTR_EL3)
4016      .mon();
4017    InitReg(MISCREG_MDCR_EL3)
4018      .mon();
4019    InitReg(MISCREG_TTBR0_EL1)
4020      .allPrivileges().exceptUserMode()
4021      .mapsTo(MISCREG_TTBR0_NS);
4022    InitReg(MISCREG_TTBR1_EL1)
4023      .allPrivileges().exceptUserMode()
4024      .mapsTo(MISCREG_TTBR1_NS);
4025    InitReg(MISCREG_TCR_EL1)
4026      .allPrivileges().exceptUserMode()
4027      .mapsTo(MISCREG_TTBCR_NS);
4028    InitReg(MISCREG_TTBR0_EL2)
4029      .hyp().mon()
4030      .mapsTo(MISCREG_HTTBR);
4031    InitReg(MISCREG_TTBR1_EL2)
4032      .hyp().mon();
4033    InitReg(MISCREG_TCR_EL2)
4034      .hyp().mon()
4035      .mapsTo(MISCREG_HTCR);
4036    InitReg(MISCREG_VTTBR_EL2)
4037      .hyp().mon()
4038      .mapsTo(MISCREG_VTTBR);
4039    InitReg(MISCREG_VTCR_EL2)
4040      .hyp().mon()
4041      .mapsTo(MISCREG_VTCR);
4042    InitReg(MISCREG_TTBR0_EL3)
4043      .mon();
4044    InitReg(MISCREG_TCR_EL3)
4045      .mon();
4046    InitReg(MISCREG_DACR32_EL2)
4047      .hyp().mon()
4048      .mapsTo(MISCREG_DACR_NS);
4049    InitReg(MISCREG_SPSR_EL1)
4050      .allPrivileges().exceptUserMode()
4051      .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4052    InitReg(MISCREG_ELR_EL1)
4053      .allPrivileges().exceptUserMode();
4054    InitReg(MISCREG_SP_EL0)
4055      .allPrivileges().exceptUserMode();
4056    InitReg(MISCREG_SPSEL)
4057      .allPrivileges().exceptUserMode();
4058    InitReg(MISCREG_CURRENTEL)
4059      .allPrivileges().exceptUserMode().writes(0);
4060    InitReg(MISCREG_NZCV)
4061      .allPrivileges();
4062    InitReg(MISCREG_DAIF)
4063      .allPrivileges();
4064    InitReg(MISCREG_FPCR)
4065      .allPrivileges();
4066    InitReg(MISCREG_FPSR)
4067      .allPrivileges();
4068    InitReg(MISCREG_DSPSR_EL0)
4069      .allPrivileges();
4070    InitReg(MISCREG_DLR_EL0)
4071      .allPrivileges();
4072    InitReg(MISCREG_SPSR_EL2)
4073      .hyp().mon()
4074      .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4075    InitReg(MISCREG_ELR_EL2)
4076      .hyp().mon();
4077    InitReg(MISCREG_SP_EL1)
4078      .hyp().mon();
4079    InitReg(MISCREG_SPSR_IRQ_AA64)
4080      .hyp().mon();
4081    InitReg(MISCREG_SPSR_ABT_AA64)
4082      .hyp().mon();
4083    InitReg(MISCREG_SPSR_UND_AA64)
4084      .hyp().mon();
4085    InitReg(MISCREG_SPSR_FIQ_AA64)
4086      .hyp().mon();
4087    InitReg(MISCREG_SPSR_EL3)
4088      .mon()
4089      .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4090    InitReg(MISCREG_ELR_EL3)
4091      .mon();
4092    InitReg(MISCREG_SP_EL2)
4093      .mon();
4094    InitReg(MISCREG_AFSR0_EL1)
4095      .allPrivileges().exceptUserMode()
4096      .mapsTo(MISCREG_ADFSR_NS);
4097    InitReg(MISCREG_AFSR1_EL1)
4098      .allPrivileges().exceptUserMode()
4099      .mapsTo(MISCREG_AIFSR_NS);
4100    InitReg(MISCREG_ESR_EL1)
4101      .allPrivileges().exceptUserMode();
4102    InitReg(MISCREG_IFSR32_EL2)
4103      .hyp().mon()
4104      .mapsTo(MISCREG_IFSR_NS);
4105    InitReg(MISCREG_AFSR0_EL2)
4106      .hyp().mon()
4107      .mapsTo(MISCREG_HADFSR);
4108    InitReg(MISCREG_AFSR1_EL2)
4109      .hyp().mon()
4110      .mapsTo(MISCREG_HAIFSR);
4111    InitReg(MISCREG_ESR_EL2)
4112      .hyp().mon()
4113      .mapsTo(MISCREG_HSR);
4114    InitReg(MISCREG_FPEXC32_EL2)
4115      .hyp().mon().mapsTo(MISCREG_FPEXC);
4116    InitReg(MISCREG_AFSR0_EL3)
4117      .mon();
4118    InitReg(MISCREG_AFSR1_EL3)
4119      .mon();
4120    InitReg(MISCREG_ESR_EL3)
4121      .mon();
4122    InitReg(MISCREG_FAR_EL1)
4123      .allPrivileges().exceptUserMode()
4124      .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4125    InitReg(MISCREG_FAR_EL2)
4126      .hyp().mon()
4127      .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4128    InitReg(MISCREG_HPFAR_EL2)
4129      .hyp().mon()
4130      .mapsTo(MISCREG_HPFAR);
4131    InitReg(MISCREG_FAR_EL3)
4132      .mon();
4133    InitReg(MISCREG_IC_IALLUIS)
4134      .warnNotFail()
4135      .writes(1).exceptUserMode();
4136    InitReg(MISCREG_PAR_EL1)
4137      .allPrivileges().exceptUserMode()
4138      .mapsTo(MISCREG_PAR_NS);
4139    InitReg(MISCREG_IC_IALLU)
4140      .warnNotFail()
4141      .writes(1).exceptUserMode();
4142    InitReg(MISCREG_DC_IVAC_Xt)
4143      .warnNotFail()
4144      .writes(1).exceptUserMode();
4145    InitReg(MISCREG_DC_ISW_Xt)
4146      .warnNotFail()
4147      .writes(1).exceptUserMode();
4148    InitReg(MISCREG_AT_S1E1R_Xt)
4149      .writes(1).exceptUserMode();
4150    InitReg(MISCREG_AT_S1E1W_Xt)
4151      .writes(1).exceptUserMode();
4152    InitReg(MISCREG_AT_S1E0R_Xt)
4153      .writes(1).exceptUserMode();
4154    InitReg(MISCREG_AT_S1E0W_Xt)
4155      .writes(1).exceptUserMode();
4156    InitReg(MISCREG_DC_CSW_Xt)
4157      .warnNotFail()
4158      .writes(1).exceptUserMode();
4159    InitReg(MISCREG_DC_CISW_Xt)
4160      .warnNotFail()
4161      .writes(1).exceptUserMode();
4162    InitReg(MISCREG_DC_ZVA_Xt)
4163      .warnNotFail()
4164      .writes(1).userSecureWrite(0);
4165    InitReg(MISCREG_IC_IVAU_Xt)
4166      .writes(1);
4167    InitReg(MISCREG_DC_CVAC_Xt)
4168      .warnNotFail()
4169      .writes(1);
4170    InitReg(MISCREG_DC_CVAU_Xt)
4171      .warnNotFail()
4172      .writes(1);
4173    InitReg(MISCREG_DC_CIVAC_Xt)
4174      .warnNotFail()
4175      .writes(1);
4176    InitReg(MISCREG_AT_S1E2R_Xt)
4177      .monNonSecureWrite().hypWrite();
4178    InitReg(MISCREG_AT_S1E2W_Xt)
4179      .monNonSecureWrite().hypWrite();
4180    InitReg(MISCREG_AT_S12E1R_Xt)
4181      .hypWrite().monSecureWrite().monNonSecureWrite();
4182    InitReg(MISCREG_AT_S12E1W_Xt)
4183      .hypWrite().monSecureWrite().monNonSecureWrite();
4184    InitReg(MISCREG_AT_S12E0R_Xt)
4185      .hypWrite().monSecureWrite().monNonSecureWrite();
4186    InitReg(MISCREG_AT_S12E0W_Xt)
4187      .hypWrite().monSecureWrite().monNonSecureWrite();
4188    InitReg(MISCREG_AT_S1E3R_Xt)
4189      .monSecureWrite().monNonSecureWrite();
4190    InitReg(MISCREG_AT_S1E3W_Xt)
4191      .monSecureWrite().monNonSecureWrite();
4192    InitReg(MISCREG_TLBI_VMALLE1IS)
4193      .writes(1).exceptUserMode();
4194    InitReg(MISCREG_TLBI_VAE1IS_Xt)
4195      .writes(1).exceptUserMode();
4196    InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4197      .writes(1).exceptUserMode();
4198    InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4199      .writes(1).exceptUserMode();
4200    InitReg(MISCREG_TLBI_VALE1IS_Xt)
4201      .writes(1).exceptUserMode();
4202    InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4203      .writes(1).exceptUserMode();
4204    InitReg(MISCREG_TLBI_VMALLE1)
4205      .writes(1).exceptUserMode();
4206    InitReg(MISCREG_TLBI_VAE1_Xt)
4207      .writes(1).exceptUserMode();
4208    InitReg(MISCREG_TLBI_ASIDE1_Xt)
4209      .writes(1).exceptUserMode();
4210    InitReg(MISCREG_TLBI_VAAE1_Xt)
4211      .writes(1).exceptUserMode();
4212    InitReg(MISCREG_TLBI_VALE1_Xt)
4213      .writes(1).exceptUserMode();
4214    InitReg(MISCREG_TLBI_VAALE1_Xt)
4215      .writes(1).exceptUserMode();
4216    InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4217      .hypWrite().monSecureWrite().monNonSecureWrite();
4218    InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4219      .hypWrite().monSecureWrite().monNonSecureWrite();
4220    InitReg(MISCREG_TLBI_ALLE2IS)
4221      .monNonSecureWrite().hypWrite();
4222    InitReg(MISCREG_TLBI_VAE2IS_Xt)
4223      .monNonSecureWrite().hypWrite();
4224    InitReg(MISCREG_TLBI_ALLE1IS)
4225      .hypWrite().monSecureWrite().monNonSecureWrite();
4226    InitReg(MISCREG_TLBI_VALE2IS_Xt)
4227      .monNonSecureWrite().hypWrite();
4228    InitReg(MISCREG_TLBI_VMALLS12E1IS)
4229      .hypWrite().monSecureWrite().monNonSecureWrite();
4230    InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4231      .hypWrite().monSecureWrite().monNonSecureWrite();
4232    InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4233      .hypWrite().monSecureWrite().monNonSecureWrite();
4234    InitReg(MISCREG_TLBI_ALLE2)
4235      .monNonSecureWrite().hypWrite();
4236    InitReg(MISCREG_TLBI_VAE2_Xt)
4237      .monNonSecureWrite().hypWrite();
4238    InitReg(MISCREG_TLBI_ALLE1)
4239      .hypWrite().monSecureWrite().monNonSecureWrite();
4240    InitReg(MISCREG_TLBI_VALE2_Xt)
4241      .monNonSecureWrite().hypWrite();
4242    InitReg(MISCREG_TLBI_VMALLS12E1)
4243      .hypWrite().monSecureWrite().monNonSecureWrite();
4244    InitReg(MISCREG_TLBI_ALLE3IS)
4245      .monSecureWrite().monNonSecureWrite();
4246    InitReg(MISCREG_TLBI_VAE3IS_Xt)
4247      .monSecureWrite().monNonSecureWrite();
4248    InitReg(MISCREG_TLBI_VALE3IS_Xt)
4249      .monSecureWrite().monNonSecureWrite();
4250    InitReg(MISCREG_TLBI_ALLE3)
4251      .monSecureWrite().monNonSecureWrite();
4252    InitReg(MISCREG_TLBI_VAE3_Xt)
4253      .monSecureWrite().monNonSecureWrite();
4254    InitReg(MISCREG_TLBI_VALE3_Xt)
4255      .monSecureWrite().monNonSecureWrite();
4256    InitReg(MISCREG_PMINTENSET_EL1)
4257      .allPrivileges().exceptUserMode()
4258      .mapsTo(MISCREG_PMINTENSET);
4259    InitReg(MISCREG_PMINTENCLR_EL1)
4260      .allPrivileges().exceptUserMode()
4261      .mapsTo(MISCREG_PMINTENCLR);
4262    InitReg(MISCREG_PMCR_EL0)
4263      .allPrivileges()
4264      .mapsTo(MISCREG_PMCR);
4265    InitReg(MISCREG_PMCNTENSET_EL0)
4266      .allPrivileges()
4267      .mapsTo(MISCREG_PMCNTENSET);
4268    InitReg(MISCREG_PMCNTENCLR_EL0)
4269      .allPrivileges()
4270      .mapsTo(MISCREG_PMCNTENCLR);
4271    InitReg(MISCREG_PMOVSCLR_EL0)
4272      .allPrivileges();
4273//    .mapsTo(MISCREG_PMOVSCLR);
4274    InitReg(MISCREG_PMSWINC_EL0)
4275      .writes(1).user()
4276      .mapsTo(MISCREG_PMSWINC);
4277    InitReg(MISCREG_PMSELR_EL0)
4278      .allPrivileges()
4279      .mapsTo(MISCREG_PMSELR);
4280    InitReg(MISCREG_PMCEID0_EL0)
4281      .reads(1).user()
4282      .mapsTo(MISCREG_PMCEID0);
4283    InitReg(MISCREG_PMCEID1_EL0)
4284      .reads(1).user()
4285      .mapsTo(MISCREG_PMCEID1);
4286    InitReg(MISCREG_PMCCNTR_EL0)
4287      .allPrivileges()
4288      .mapsTo(MISCREG_PMCCNTR);
4289    InitReg(MISCREG_PMXEVTYPER_EL0)
4290      .allPrivileges()
4291      .mapsTo(MISCREG_PMXEVTYPER);
4292    InitReg(MISCREG_PMCCFILTR_EL0)
4293      .allPrivileges();
4294    InitReg(MISCREG_PMXEVCNTR_EL0)
4295      .allPrivileges()
4296      .mapsTo(MISCREG_PMXEVCNTR);
4297    InitReg(MISCREG_PMUSERENR_EL0)
4298      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4299      .mapsTo(MISCREG_PMUSERENR);
4300    InitReg(MISCREG_PMOVSSET_EL0)
4301      .allPrivileges()
4302      .mapsTo(MISCREG_PMOVSSET);
4303    InitReg(MISCREG_MAIR_EL1)
4304      .allPrivileges().exceptUserMode()
4305      .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4306    InitReg(MISCREG_AMAIR_EL1)
4307      .allPrivileges().exceptUserMode()
4308      .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4309    InitReg(MISCREG_MAIR_EL2)
4310      .hyp().mon()
4311      .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4312    InitReg(MISCREG_AMAIR_EL2)
4313      .hyp().mon()
4314      .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4315    InitReg(MISCREG_MAIR_EL3)
4316      .mon();
4317    InitReg(MISCREG_AMAIR_EL3)
4318      .mon();
4319    InitReg(MISCREG_L2CTLR_EL1)
4320      .allPrivileges().exceptUserMode();
4321    InitReg(MISCREG_L2ECTLR_EL1)
4322      .allPrivileges().exceptUserMode();
4323    InitReg(MISCREG_VBAR_EL1)
4324      .allPrivileges().exceptUserMode()
4325      .mapsTo(MISCREG_VBAR_NS);
4326    InitReg(MISCREG_RVBAR_EL1)
4327      .allPrivileges().exceptUserMode().writes(0);
4328    InitReg(MISCREG_ISR_EL1)
4329      .allPrivileges().exceptUserMode().writes(0);
4330    InitReg(MISCREG_VBAR_EL2)
4331      .hyp().mon()
4332      .res0(0x7ff)
4333      .mapsTo(MISCREG_HVBAR);
4334    InitReg(MISCREG_RVBAR_EL2)
4335      .mon().hyp().writes(0);
4336    InitReg(MISCREG_VBAR_EL3)
4337      .mon();
4338    InitReg(MISCREG_RVBAR_EL3)
4339      .mon().writes(0);
4340    InitReg(MISCREG_RMR_EL3)
4341      .mon();
4342    InitReg(MISCREG_CONTEXTIDR_EL1)
4343      .allPrivileges().exceptUserMode()
4344      .mapsTo(MISCREG_CONTEXTIDR_NS);
4345    InitReg(MISCREG_TPIDR_EL1)
4346      .allPrivileges().exceptUserMode()
4347      .mapsTo(MISCREG_TPIDRPRW_NS);
4348    InitReg(MISCREG_TPIDR_EL0)
4349      .allPrivileges()
4350      .mapsTo(MISCREG_TPIDRURW_NS);
4351    InitReg(MISCREG_TPIDRRO_EL0)
4352      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4353      .mapsTo(MISCREG_TPIDRURO_NS);
4354    InitReg(MISCREG_TPIDR_EL2)
4355      .hyp().mon()
4356      .mapsTo(MISCREG_HTPIDR);
4357    InitReg(MISCREG_TPIDR_EL3)
4358      .mon();
4359    InitReg(MISCREG_CNTKCTL_EL1)
4360      .allPrivileges().exceptUserMode()
4361      .mapsTo(MISCREG_CNTKCTL);
4362    InitReg(MISCREG_CNTFRQ_EL0)
4363      .reads(1).mon()
4364      .mapsTo(MISCREG_CNTFRQ);
4365    InitReg(MISCREG_CNTPCT_EL0)
4366      .reads(1)
4367      .mapsTo(MISCREG_CNTPCT); /* 64b */
4368    InitReg(MISCREG_CNTVCT_EL0)
4369      .unverifiable()
4370      .reads(1)
4371      .mapsTo(MISCREG_CNTVCT); /* 64b */
4372    InitReg(MISCREG_CNTP_TVAL_EL0)
4373      .allPrivileges()
4374      .mapsTo(MISCREG_CNTP_TVAL_NS);
4375    InitReg(MISCREG_CNTP_CTL_EL0)
4376      .allPrivileges()
4377      .mapsTo(MISCREG_CNTP_CTL_NS);
4378    InitReg(MISCREG_CNTP_CVAL_EL0)
4379      .allPrivileges()
4380      .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
4381    InitReg(MISCREG_CNTV_TVAL_EL0)
4382      .allPrivileges()
4383      .mapsTo(MISCREG_CNTV_TVAL);
4384    InitReg(MISCREG_CNTV_CTL_EL0)
4385      .allPrivileges()
4386      .mapsTo(MISCREG_CNTV_CTL);
4387    InitReg(MISCREG_CNTV_CVAL_EL0)
4388      .allPrivileges()
4389      .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4390    InitReg(MISCREG_PMEVCNTR0_EL0)
4391      .allPrivileges();
4392//    .mapsTo(MISCREG_PMEVCNTR0);
4393    InitReg(MISCREG_PMEVCNTR1_EL0)
4394      .allPrivileges();
4395//    .mapsTo(MISCREG_PMEVCNTR1);
4396    InitReg(MISCREG_PMEVCNTR2_EL0)
4397      .allPrivileges();
4398//    .mapsTo(MISCREG_PMEVCNTR2);
4399    InitReg(MISCREG_PMEVCNTR3_EL0)
4400      .allPrivileges();
4401//    .mapsTo(MISCREG_PMEVCNTR3);
4402    InitReg(MISCREG_PMEVCNTR4_EL0)
4403      .allPrivileges();
4404//    .mapsTo(MISCREG_PMEVCNTR4);
4405    InitReg(MISCREG_PMEVCNTR5_EL0)
4406      .allPrivileges();
4407//    .mapsTo(MISCREG_PMEVCNTR5);
4408    InitReg(MISCREG_PMEVTYPER0_EL0)
4409      .allPrivileges();
4410//    .mapsTo(MISCREG_PMEVTYPER0);
4411    InitReg(MISCREG_PMEVTYPER1_EL0)
4412      .allPrivileges();
4413//    .mapsTo(MISCREG_PMEVTYPER1);
4414    InitReg(MISCREG_PMEVTYPER2_EL0)
4415      .allPrivileges();
4416//    .mapsTo(MISCREG_PMEVTYPER2);
4417    InitReg(MISCREG_PMEVTYPER3_EL0)
4418      .allPrivileges();
4419//    .mapsTo(MISCREG_PMEVTYPER3);
4420    InitReg(MISCREG_PMEVTYPER4_EL0)
4421      .allPrivileges();
4422//    .mapsTo(MISCREG_PMEVTYPER4);
4423    InitReg(MISCREG_PMEVTYPER5_EL0)
4424      .allPrivileges();
4425//    .mapsTo(MISCREG_PMEVTYPER5);
4426    InitReg(MISCREG_CNTVOFF_EL2)
4427      .hyp().mon()
4428      .mapsTo(MISCREG_CNTVOFF); /* 64b */
4429    InitReg(MISCREG_CNTHCTL_EL2)
4430      .mon().hyp()
4431      .mapsTo(MISCREG_CNTHCTL);
4432    InitReg(MISCREG_CNTHP_TVAL_EL2)
4433      .mon().hyp()
4434      .mapsTo(MISCREG_CNTHP_TVAL);
4435    InitReg(MISCREG_CNTHP_CTL_EL2)
4436      .mon().hyp()
4437      .mapsTo(MISCREG_CNTHP_CTL);
4438    InitReg(MISCREG_CNTHP_CVAL_EL2)
4439      .mon().hyp()
4440      .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4441    InitReg(MISCREG_CNTPS_TVAL_EL1)
4442      .mon().privSecure();
4443    InitReg(MISCREG_CNTPS_CTL_EL1)
4444      .mon().privSecure();
4445    InitReg(MISCREG_CNTPS_CVAL_EL1)
4446      .mon().privSecure();
4447    InitReg(MISCREG_IL1DATA0_EL1)
4448      .allPrivileges().exceptUserMode();
4449    InitReg(MISCREG_IL1DATA1_EL1)
4450      .allPrivileges().exceptUserMode();
4451    InitReg(MISCREG_IL1DATA2_EL1)
4452      .allPrivileges().exceptUserMode();
4453    InitReg(MISCREG_IL1DATA3_EL1)
4454      .allPrivileges().exceptUserMode();
4455    InitReg(MISCREG_DL1DATA0_EL1)
4456      .allPrivileges().exceptUserMode();
4457    InitReg(MISCREG_DL1DATA1_EL1)
4458      .allPrivileges().exceptUserMode();
4459    InitReg(MISCREG_DL1DATA2_EL1)
4460      .allPrivileges().exceptUserMode();
4461    InitReg(MISCREG_DL1DATA3_EL1)
4462      .allPrivileges().exceptUserMode();
4463    InitReg(MISCREG_DL1DATA4_EL1)
4464      .allPrivileges().exceptUserMode();
4465    InitReg(MISCREG_L2ACTLR_EL1)
4466      .allPrivileges().exceptUserMode();
4467    InitReg(MISCREG_CPUACTLR_EL1)
4468      .allPrivileges().exceptUserMode();
4469    InitReg(MISCREG_CPUECTLR_EL1)
4470      .allPrivileges().exceptUserMode();
4471    InitReg(MISCREG_CPUMERRSR_EL1)
4472      .allPrivileges().exceptUserMode();
4473    InitReg(MISCREG_L2MERRSR_EL1)
4474      .unimplemented()
4475      .warnNotFail()
4476      .allPrivileges().exceptUserMode();
4477    InitReg(MISCREG_CBAR_EL1)
4478      .allPrivileges().exceptUserMode().writes(0);
4479    InitReg(MISCREG_CONTEXTIDR_EL2)
4480      .mon().hyp();
4481
4482    // GICv3 AArch64
4483    InitReg(MISCREG_ICC_PMR_EL1)
4484        .res0(0xffffff00) // [31:8]
4485        .allPrivileges().exceptUserMode()
4486        .mapsTo(MISCREG_ICC_PMR);
4487    InitReg(MISCREG_ICC_IAR0_EL1)
4488        .allPrivileges().exceptUserMode().writes(0)
4489        .mapsTo(MISCREG_ICC_IAR0);
4490    InitReg(MISCREG_ICC_EOIR0_EL1)
4491        .allPrivileges().exceptUserMode().reads(0)
4492        .mapsTo(MISCREG_ICC_EOIR0);
4493    InitReg(MISCREG_ICC_HPPIR0_EL1)
4494        .allPrivileges().exceptUserMode().writes(0)
4495        .mapsTo(MISCREG_ICC_HPPIR0);
4496    InitReg(MISCREG_ICC_BPR0_EL1)
4497        .res0(0xfffffff8) // [31:3]
4498        .allPrivileges().exceptUserMode()
4499        .mapsTo(MISCREG_ICC_BPR0);
4500    InitReg(MISCREG_ICC_AP0R0_EL1)
4501        .allPrivileges().exceptUserMode()
4502        .mapsTo(MISCREG_ICC_AP0R0);
4503    InitReg(MISCREG_ICC_AP0R1_EL1)
4504        .allPrivileges().exceptUserMode()
4505        .mapsTo(MISCREG_ICC_AP0R1);
4506    InitReg(MISCREG_ICC_AP0R2_EL1)
4507        .allPrivileges().exceptUserMode()
4508        .mapsTo(MISCREG_ICC_AP0R2);
4509    InitReg(MISCREG_ICC_AP0R3_EL1)
4510        .allPrivileges().exceptUserMode()
4511        .mapsTo(MISCREG_ICC_AP0R3);
4512    InitReg(MISCREG_ICC_AP1R0_EL1)
4513        .banked()
4514        .mapsTo(MISCREG_ICC_AP1R0);
4515    InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4516        .bankedChild()
4517        .allPrivileges().exceptUserMode()
4518        .mapsTo(MISCREG_ICC_AP1R0_NS);
4519    InitReg(MISCREG_ICC_AP1R0_EL1_S)
4520        .bankedChild()
4521        .allPrivileges().exceptUserMode()
4522        .mapsTo(MISCREG_ICC_AP1R0_S);
4523    InitReg(MISCREG_ICC_AP1R1_EL1)
4524        .banked()
4525        .mapsTo(MISCREG_ICC_AP1R1);
4526    InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4527        .bankedChild()
4528        .allPrivileges().exceptUserMode()
4529        .mapsTo(MISCREG_ICC_AP1R1_NS);
4530    InitReg(MISCREG_ICC_AP1R1_EL1_S)
4531        .bankedChild()
4532        .allPrivileges().exceptUserMode()
4533        .mapsTo(MISCREG_ICC_AP1R1_S);
4534    InitReg(MISCREG_ICC_AP1R2_EL1)
4535        .banked()
4536        .mapsTo(MISCREG_ICC_AP1R2);
4537    InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4538        .bankedChild()
4539        .allPrivileges().exceptUserMode()
4540        .mapsTo(MISCREG_ICC_AP1R2_NS);
4541    InitReg(MISCREG_ICC_AP1R2_EL1_S)
4542        .bankedChild()
4543        .allPrivileges().exceptUserMode()
4544        .mapsTo(MISCREG_ICC_AP1R2_S);
4545    InitReg(MISCREG_ICC_AP1R3_EL1)
4546        .banked()
4547        .mapsTo(MISCREG_ICC_AP1R3);
4548    InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4549        .bankedChild()
4550        .allPrivileges().exceptUserMode()
4551        .mapsTo(MISCREG_ICC_AP1R3_NS);
4552    InitReg(MISCREG_ICC_AP1R3_EL1_S)
4553        .bankedChild()
4554        .allPrivileges().exceptUserMode()
4555        .mapsTo(MISCREG_ICC_AP1R3_S);
4556    InitReg(MISCREG_ICC_DIR_EL1)
4557        .res0(0xFF000000) // [31:24]
4558        .allPrivileges().exceptUserMode().reads(0)
4559        .mapsTo(MISCREG_ICC_DIR);
4560    InitReg(MISCREG_ICC_RPR_EL1)
4561        .allPrivileges().exceptUserMode().writes(0)
4562        .mapsTo(MISCREG_ICC_RPR);
4563    InitReg(MISCREG_ICC_SGI1R_EL1)
4564        .allPrivileges().exceptUserMode().reads(0)
4565        .mapsTo(MISCREG_ICC_SGI1R);
4566    InitReg(MISCREG_ICC_ASGI1R_EL1)
4567        .allPrivileges().exceptUserMode().reads(0)
4568        .mapsTo(MISCREG_ICC_ASGI1R);
4569    InitReg(MISCREG_ICC_SGI0R_EL1)
4570        .allPrivileges().exceptUserMode().reads(0)
4571        .mapsTo(MISCREG_ICC_SGI0R);
4572    InitReg(MISCREG_ICC_IAR1_EL1)
4573        .allPrivileges().exceptUserMode().writes(0)
4574        .mapsTo(MISCREG_ICC_IAR1);
4575    InitReg(MISCREG_ICC_EOIR1_EL1)
4576        .res0(0xFF000000) // [31:24]
4577        .allPrivileges().exceptUserMode().reads(0)
4578        .mapsTo(MISCREG_ICC_EOIR1);
4579    InitReg(MISCREG_ICC_HPPIR1_EL1)
4580        .allPrivileges().exceptUserMode().writes(0)
4581        .mapsTo(MISCREG_ICC_HPPIR1);
4582    InitReg(MISCREG_ICC_BPR1_EL1)
4583        .banked()
4584        .mapsTo(MISCREG_ICC_BPR1);
4585    InitReg(MISCREG_ICC_BPR1_EL1_NS)
4586        .bankedChild()
4587        .res0(0xfffffff8) // [31:3]
4588        .allPrivileges().exceptUserMode()
4589        .mapsTo(MISCREG_ICC_BPR1_NS);
4590    InitReg(MISCREG_ICC_BPR1_EL1_S)
4591        .bankedChild()
4592        .res0(0xfffffff8) // [31:3]
4593        .secure().exceptUserMode()
4594        .mapsTo(MISCREG_ICC_BPR1_S);
4595    InitReg(MISCREG_ICC_CTLR_EL1)
4596        .banked()
4597        .mapsTo(MISCREG_ICC_CTLR);
4598    InitReg(MISCREG_ICC_CTLR_EL1_NS)
4599        .bankedChild()
4600        .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4601        .allPrivileges().exceptUserMode()
4602        .mapsTo(MISCREG_ICC_CTLR_NS);
4603    InitReg(MISCREG_ICC_CTLR_EL1_S)
4604        .bankedChild()
4605        .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4606        .secure().exceptUserMode()
4607        .mapsTo(MISCREG_ICC_CTLR_S);
4608    InitReg(MISCREG_ICC_SRE_EL1)
4609        .banked()
4610        .mapsTo(MISCREG_ICC_SRE);
4611    InitReg(MISCREG_ICC_SRE_EL1_NS)
4612        .bankedChild()
4613        .res0(0xFFFFFFF8) // [31:3]
4614        .allPrivileges().exceptUserMode()
4615        .mapsTo(MISCREG_ICC_SRE_NS);
4616    InitReg(MISCREG_ICC_SRE_EL1_S)
4617        .bankedChild()
4618        .res0(0xFFFFFFF8) // [31:3]
4619        .secure().exceptUserMode()
4620        .mapsTo(MISCREG_ICC_SRE_S);
4621    InitReg(MISCREG_ICC_IGRPEN0_EL1)
4622        .res0(0xFFFFFFFE) // [31:1]
4623        .allPrivileges().exceptUserMode()
4624        .mapsTo(MISCREG_ICC_IGRPEN0);
4625    InitReg(MISCREG_ICC_IGRPEN1_EL1)
4626        .banked()
4627        .mapsTo(MISCREG_ICC_IGRPEN1);
4628    InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4629        .bankedChild()
4630        .res0(0xFFFFFFFE) // [31:1]
4631        .allPrivileges().exceptUserMode()
4632        .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4633    InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4634        .bankedChild()
4635        .res0(0xFFFFFFFE) // [31:1]
4636        .secure().exceptUserMode()
4637        .mapsTo(MISCREG_ICC_IGRPEN1_S);
4638    InitReg(MISCREG_ICC_SRE_EL2)
4639        .hyp().mon()
4640        .mapsTo(MISCREG_ICC_HSRE);
4641    InitReg(MISCREG_ICC_CTLR_EL3)
4642        .allPrivileges().exceptUserMode()
4643        .mapsTo(MISCREG_ICC_MCTLR);
4644    InitReg(MISCREG_ICC_SRE_EL3)
4645        .allPrivileges().exceptUserMode()
4646        .mapsTo(MISCREG_ICC_MSRE);
4647    InitReg(MISCREG_ICC_IGRPEN1_EL3)
4648        .allPrivileges().exceptUserMode()
4649        .mapsTo(MISCREG_ICC_MGRPEN1);
4650
4651    InitReg(MISCREG_ICH_AP0R0_EL2)
4652        .hyp().mon()
4653        .mapsTo(MISCREG_ICH_AP0R0);
4654    InitReg(MISCREG_ICH_AP0R1_EL2)
4655        .hyp().mon()
4656        .unimplemented()
4657        .mapsTo(MISCREG_ICH_AP0R1);
4658    InitReg(MISCREG_ICH_AP0R2_EL2)
4659        .hyp().mon()
4660        .unimplemented()
4661        .mapsTo(MISCREG_ICH_AP0R2);
4662    InitReg(MISCREG_ICH_AP0R3_EL2)
4663        .hyp().mon()
4664        .unimplemented()
4665        .mapsTo(MISCREG_ICH_AP0R3);
4666    InitReg(MISCREG_ICH_AP1R0_EL2)
4667        .hyp().mon()
4668        .mapsTo(MISCREG_ICH_AP1R0);
4669    InitReg(MISCREG_ICH_AP1R1_EL2)
4670        .hyp().mon()
4671        .unimplemented()
4672        .mapsTo(MISCREG_ICH_AP1R1);
4673    InitReg(MISCREG_ICH_AP1R2_EL2)
4674        .hyp().mon()
4675        .unimplemented()
4676        .mapsTo(MISCREG_ICH_AP1R2);
4677    InitReg(MISCREG_ICH_AP1R3_EL2)
4678        .hyp().mon()
4679        .unimplemented()
4680        .mapsTo(MISCREG_ICH_AP1R3);
4681    InitReg(MISCREG_ICH_HCR_EL2)
4682        .hyp().mon()
4683        .mapsTo(MISCREG_ICH_HCR);
4684    InitReg(MISCREG_ICH_VTR_EL2)
4685        .hyp().mon().writes(0)
4686        .mapsTo(MISCREG_ICH_VTR);
4687    InitReg(MISCREG_ICH_MISR_EL2)
4688        .hyp().mon().writes(0)
4689        .mapsTo(MISCREG_ICH_MISR);
4690    InitReg(MISCREG_ICH_EISR_EL2)
4691        .hyp().mon().writes(0)
4692        .mapsTo(MISCREG_ICH_EISR);
4693    InitReg(MISCREG_ICH_ELRSR_EL2)
4694        .hyp().mon().writes(0)
4695        .mapsTo(MISCREG_ICH_ELRSR);
4696    InitReg(MISCREG_ICH_VMCR_EL2)
4697        .hyp().mon()
4698        .mapsTo(MISCREG_ICH_VMCR);
4699    InitReg(MISCREG_ICH_LR0_EL2)
4700        .hyp().mon()
4701        .allPrivileges().exceptUserMode();
4702    InitReg(MISCREG_ICH_LR1_EL2)
4703        .hyp().mon()
4704        .allPrivileges().exceptUserMode();
4705    InitReg(MISCREG_ICH_LR2_EL2)
4706        .hyp().mon()
4707        .allPrivileges().exceptUserMode();
4708    InitReg(MISCREG_ICH_LR3_EL2)
4709        .hyp().mon()
4710        .allPrivileges().exceptUserMode();
4711    InitReg(MISCREG_ICH_LR4_EL2)
4712        .hyp().mon()
4713        .allPrivileges().exceptUserMode();
4714    InitReg(MISCREG_ICH_LR5_EL2)
4715        .hyp().mon()
4716        .allPrivileges().exceptUserMode();
4717    InitReg(MISCREG_ICH_LR6_EL2)
4718        .hyp().mon()
4719        .allPrivileges().exceptUserMode();
4720    InitReg(MISCREG_ICH_LR7_EL2)
4721        .hyp().mon()
4722        .allPrivileges().exceptUserMode();
4723    InitReg(MISCREG_ICH_LR8_EL2)
4724        .hyp().mon()
4725        .allPrivileges().exceptUserMode();
4726    InitReg(MISCREG_ICH_LR9_EL2)
4727        .hyp().mon()
4728        .allPrivileges().exceptUserMode();
4729    InitReg(MISCREG_ICH_LR10_EL2)
4730        .hyp().mon()
4731        .allPrivileges().exceptUserMode();
4732    InitReg(MISCREG_ICH_LR11_EL2)
4733        .hyp().mon()
4734        .allPrivileges().exceptUserMode();
4735    InitReg(MISCREG_ICH_LR12_EL2)
4736        .hyp().mon()
4737        .allPrivileges().exceptUserMode();
4738    InitReg(MISCREG_ICH_LR13_EL2)
4739        .hyp().mon()
4740        .allPrivileges().exceptUserMode();
4741    InitReg(MISCREG_ICH_LR14_EL2)
4742        .hyp().mon()
4743        .allPrivileges().exceptUserMode();
4744    InitReg(MISCREG_ICH_LR15_EL2)
4745        .hyp().mon()
4746        .allPrivileges().exceptUserMode();
4747
4748    // GICv3 AArch32
4749    InitReg(MISCREG_ICC_AP0R0)
4750        .allPrivileges().exceptUserMode();
4751    InitReg(MISCREG_ICC_AP0R1)
4752        .allPrivileges().exceptUserMode();
4753    InitReg(MISCREG_ICC_AP0R2)
4754        .allPrivileges().exceptUserMode();
4755    InitReg(MISCREG_ICC_AP0R3)
4756        .allPrivileges().exceptUserMode();
4757    InitReg(MISCREG_ICC_AP1R0)
4758        .allPrivileges().exceptUserMode();
4759    InitReg(MISCREG_ICC_AP1R0_NS)
4760        .allPrivileges().exceptUserMode();
4761    InitReg(MISCREG_ICC_AP1R0_S)
4762        .allPrivileges().exceptUserMode();
4763    InitReg(MISCREG_ICC_AP1R1)
4764        .allPrivileges().exceptUserMode();
4765    InitReg(MISCREG_ICC_AP1R1_NS)
4766        .allPrivileges().exceptUserMode();
4767    InitReg(MISCREG_ICC_AP1R1_S)
4768        .allPrivileges().exceptUserMode();
4769    InitReg(MISCREG_ICC_AP1R2)
4770        .allPrivileges().exceptUserMode();
4771    InitReg(MISCREG_ICC_AP1R2_NS)
4772        .allPrivileges().exceptUserMode();
4773    InitReg(MISCREG_ICC_AP1R2_S)
4774        .allPrivileges().exceptUserMode();
4775    InitReg(MISCREG_ICC_AP1R3)
4776        .allPrivileges().exceptUserMode();
4777    InitReg(MISCREG_ICC_AP1R3_NS)
4778        .allPrivileges().exceptUserMode();
4779    InitReg(MISCREG_ICC_AP1R3_S)
4780        .allPrivileges().exceptUserMode();
4781    InitReg(MISCREG_ICC_ASGI1R)
4782        .allPrivileges().exceptUserMode().reads(0);
4783    InitReg(MISCREG_ICC_BPR0)
4784        .allPrivileges().exceptUserMode();
4785    InitReg(MISCREG_ICC_BPR1)
4786        .allPrivileges().exceptUserMode();
4787    InitReg(MISCREG_ICC_BPR1_NS)
4788        .allPrivileges().exceptUserMode();
4789    InitReg(MISCREG_ICC_BPR1_S)
4790        .allPrivileges().exceptUserMode();
4791    InitReg(MISCREG_ICC_CTLR)
4792        .allPrivileges().exceptUserMode();
4793    InitReg(MISCREG_ICC_CTLR_NS)
4794        .allPrivileges().exceptUserMode();
4795    InitReg(MISCREG_ICC_CTLR_S)
4796        .allPrivileges().exceptUserMode();
4797    InitReg(MISCREG_ICC_DIR)
4798        .allPrivileges().exceptUserMode().reads(0);
4799    InitReg(MISCREG_ICC_EOIR0)
4800        .allPrivileges().exceptUserMode().reads(0);
4801    InitReg(MISCREG_ICC_EOIR1)
4802        .allPrivileges().exceptUserMode().reads(0);
4803    InitReg(MISCREG_ICC_HPPIR0)
4804        .allPrivileges().exceptUserMode().writes(0);
4805    InitReg(MISCREG_ICC_HPPIR1)
4806        .allPrivileges().exceptUserMode().writes(0);
4807    InitReg(MISCREG_ICC_HSRE)
4808        .allPrivileges().exceptUserMode();
4809    InitReg(MISCREG_ICC_IAR0)
4810        .allPrivileges().exceptUserMode().writes(0);
4811    InitReg(MISCREG_ICC_IAR1)
4812        .allPrivileges().exceptUserMode().writes(0);
4813    InitReg(MISCREG_ICC_IGRPEN0)
4814        .allPrivileges().exceptUserMode();
4815    InitReg(MISCREG_ICC_IGRPEN1)
4816        .allPrivileges().exceptUserMode();
4817    InitReg(MISCREG_ICC_IGRPEN1_NS)
4818        .allPrivileges().exceptUserMode();
4819    InitReg(MISCREG_ICC_IGRPEN1_S)
4820        .allPrivileges().exceptUserMode();
4821    InitReg(MISCREG_ICC_MCTLR)
4822        .allPrivileges().exceptUserMode();
4823    InitReg(MISCREG_ICC_MGRPEN1)
4824        .allPrivileges().exceptUserMode();
4825    InitReg(MISCREG_ICC_MSRE)
4826        .allPrivileges().exceptUserMode();
4827    InitReg(MISCREG_ICC_PMR)
4828        .allPrivileges().exceptUserMode();
4829    InitReg(MISCREG_ICC_RPR)
4830        .allPrivileges().exceptUserMode().writes(0);
4831    InitReg(MISCREG_ICC_SGI0R)
4832        .allPrivileges().exceptUserMode().reads(0);
4833    InitReg(MISCREG_ICC_SGI1R)
4834        .allPrivileges().exceptUserMode().reads(0);
4835    InitReg(MISCREG_ICC_SRE)
4836        .allPrivileges().exceptUserMode();
4837    InitReg(MISCREG_ICC_SRE_NS)
4838        .allPrivileges().exceptUserMode();
4839    InitReg(MISCREG_ICC_SRE_S)
4840        .allPrivileges().exceptUserMode();
4841
4842    InitReg(MISCREG_ICH_AP0R0)
4843        .hyp().mon();
4844    InitReg(MISCREG_ICH_AP0R1)
4845        .hyp().mon();
4846    InitReg(MISCREG_ICH_AP0R2)
4847        .hyp().mon();
4848    InitReg(MISCREG_ICH_AP0R3)
4849        .hyp().mon();
4850    InitReg(MISCREG_ICH_AP1R0)
4851        .hyp().mon();
4852    InitReg(MISCREG_ICH_AP1R1)
4853        .hyp().mon();
4854    InitReg(MISCREG_ICH_AP1R2)
4855        .hyp().mon();
4856    InitReg(MISCREG_ICH_AP1R3)
4857        .hyp().mon();
4858    InitReg(MISCREG_ICH_HCR)
4859        .hyp().mon();
4860    InitReg(MISCREG_ICH_VTR)
4861        .hyp().mon().writes(0);
4862    InitReg(MISCREG_ICH_MISR)
4863        .hyp().mon().writes(0);
4864    InitReg(MISCREG_ICH_EISR)
4865        .hyp().mon().writes(0);
4866    InitReg(MISCREG_ICH_ELRSR)
4867        .hyp().mon().writes(0);
4868    InitReg(MISCREG_ICH_VMCR)
4869        .hyp().mon();
4870    InitReg(MISCREG_ICH_LR0)
4871        .hyp().mon();
4872    InitReg(MISCREG_ICH_LR1)
4873        .hyp().mon();
4874    InitReg(MISCREG_ICH_LR2)
4875        .hyp().mon();
4876    InitReg(MISCREG_ICH_LR3)
4877        .hyp().mon();
4878    InitReg(MISCREG_ICH_LR4)
4879        .hyp().mon();
4880    InitReg(MISCREG_ICH_LR5)
4881        .hyp().mon();
4882    InitReg(MISCREG_ICH_LR6)
4883        .hyp().mon();
4884    InitReg(MISCREG_ICH_LR7)
4885        .hyp().mon();
4886    InitReg(MISCREG_ICH_LR8)
4887        .hyp().mon();
4888    InitReg(MISCREG_ICH_LR9)
4889        .hyp().mon();
4890    InitReg(MISCREG_ICH_LR10)
4891        .hyp().mon();
4892    InitReg(MISCREG_ICH_LR11)
4893        .hyp().mon();
4894    InitReg(MISCREG_ICH_LR12)
4895        .hyp().mon();
4896    InitReg(MISCREG_ICH_LR13)
4897        .hyp().mon();
4898    InitReg(MISCREG_ICH_LR14)
4899        .hyp().mon();
4900    InitReg(MISCREG_ICH_LR15)
4901        .hyp().mon();
4902    InitReg(MISCREG_ICH_LRC0)
4903        .mapsTo(MISCREG_ICH_LR0)
4904        .hyp().mon();
4905    InitReg(MISCREG_ICH_LRC1)
4906        .mapsTo(MISCREG_ICH_LR1)
4907        .hyp().mon();
4908    InitReg(MISCREG_ICH_LRC2)
4909        .mapsTo(MISCREG_ICH_LR2)
4910        .hyp().mon();
4911    InitReg(MISCREG_ICH_LRC3)
4912        .mapsTo(MISCREG_ICH_LR3)
4913        .hyp().mon();
4914    InitReg(MISCREG_ICH_LRC4)
4915        .mapsTo(MISCREG_ICH_LR4)
4916        .hyp().mon();
4917    InitReg(MISCREG_ICH_LRC5)
4918        .mapsTo(MISCREG_ICH_LR5)
4919        .hyp().mon();
4920    InitReg(MISCREG_ICH_LRC6)
4921        .mapsTo(MISCREG_ICH_LR6)
4922        .hyp().mon();
4923    InitReg(MISCREG_ICH_LRC7)
4924        .mapsTo(MISCREG_ICH_LR7)
4925        .hyp().mon();
4926    InitReg(MISCREG_ICH_LRC8)
4927        .mapsTo(MISCREG_ICH_LR8)
4928        .hyp().mon();
4929    InitReg(MISCREG_ICH_LRC9)
4930        .mapsTo(MISCREG_ICH_LR9)
4931        .hyp().mon();
4932    InitReg(MISCREG_ICH_LRC10)
4933        .mapsTo(MISCREG_ICH_LR10)
4934        .hyp().mon();
4935    InitReg(MISCREG_ICH_LRC11)
4936        .mapsTo(MISCREG_ICH_LR11)
4937        .hyp().mon();
4938    InitReg(MISCREG_ICH_LRC12)
4939        .mapsTo(MISCREG_ICH_LR12)
4940        .hyp().mon();
4941    InitReg(MISCREG_ICH_LRC13)
4942        .mapsTo(MISCREG_ICH_LR13)
4943        .hyp().mon();
4944    InitReg(MISCREG_ICH_LRC14)
4945        .mapsTo(MISCREG_ICH_LR14)
4946        .hyp().mon();
4947    InitReg(MISCREG_ICH_LRC15)
4948        .mapsTo(MISCREG_ICH_LR15)
4949        .hyp().mon();
4950
4951    InitReg(MISCREG_CNTHV_CTL_EL2)
4952      .mon().hyp();
4953    InitReg(MISCREG_CNTHV_CVAL_EL2)
4954      .mon().hyp();
4955    InitReg(MISCREG_CNTHV_TVAL_EL2)
4956      .mon().hyp();
4957
4958    // SVE
4959    InitReg(MISCREG_ID_AA64ZFR0_EL1)
4960        .allPrivileges().exceptUserMode().writes(0);
4961    InitReg(MISCREG_ZCR_EL3)
4962        .mon();
4963    InitReg(MISCREG_ZCR_EL2)
4964        .hyp().mon();
4965    InitReg(MISCREG_ZCR_EL12)
4966        .unimplemented().warnNotFail();
4967    InitReg(MISCREG_ZCR_EL1)
4968        .allPrivileges().exceptUserMode();
4969
4970    // Dummy registers
4971    InitReg(MISCREG_NOP)
4972      .allPrivileges();
4973    InitReg(MISCREG_RAZ)
4974      .allPrivileges().exceptUserMode().writes(0);
4975    InitReg(MISCREG_CP14_UNIMPL)
4976      .unimplemented()
4977      .warnNotFail();
4978    InitReg(MISCREG_CP15_UNIMPL)
4979      .unimplemented()
4980      .warnNotFail();
4981    InitReg(MISCREG_UNKNOWN);
4982    InitReg(MISCREG_IMPDEF_UNIMPL)
4983      .unimplemented()
4984      .warnNotFail(impdefAsNop);
4985
4986    // RAS extension (unimplemented)
4987    InitReg(MISCREG_ERRIDR_EL1)
4988      .unimplemented()
4989      .warnNotFail();
4990    InitReg(MISCREG_ERRSELR_EL1)
4991      .unimplemented()
4992      .warnNotFail();
4993    InitReg(MISCREG_ERXFR_EL1)
4994      .unimplemented()
4995      .warnNotFail();
4996    InitReg(MISCREG_ERXCTLR_EL1)
4997      .unimplemented()
4998      .warnNotFail();
4999    InitReg(MISCREG_ERXSTATUS_EL1)
5000      .unimplemented()
5001      .warnNotFail();
5002    InitReg(MISCREG_ERXADDR_EL1)
5003      .unimplemented()
5004      .warnNotFail();
5005    InitReg(MISCREG_ERXMISC0_EL1)
5006      .unimplemented()
5007      .warnNotFail();
5008    InitReg(MISCREG_ERXMISC1_EL1)
5009      .unimplemented()
5010      .warnNotFail();
5011    InitReg(MISCREG_DISR_EL1)
5012      .unimplemented()
5013      .warnNotFail();
5014    InitReg(MISCREG_VSESR_EL2)
5015      .unimplemented()
5016      .warnNotFail();
5017    InitReg(MISCREG_VDISR_EL2)
5018      .unimplemented()
5019      .warnNotFail();
5020
5021    // Register mappings for some unimplemented registers:
5022    // ESR_EL1 -> DFSR
5023    // RMR_EL1 -> RMR
5024    // RMR_EL2 -> HRMR
5025    // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5026    // DBGDTRRX_EL0 -> DBGDTRRXint
5027    // DBGDTRTX_EL0 -> DBGDTRRXint
5028    // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5029
5030    completed = true;
5031}
5032
5033} // namespace ArmISA
5034