miscregs.cc revision 13531:e6f1bf55d038 
1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 *          Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57    switch(crn) {
58      case 0:
59        switch (opc1) {
60          case 0:
61            switch (opc2) {
62              case 0:
63                switch (crm) {
64                  case 0:
65                    return MISCREG_DBGDIDR;
66                  case 1:
67                    return MISCREG_DBGDSCRint;
68                }
69                break;
70            }
71            break;
72          case 7:
73            switch (opc2) {
74              case 0:
75                switch (crm) {
76                  case 0:
77                    return MISCREG_JIDR;
78                }
79              break;
80            }
81            break;
82        }
83        break;
84      case 1:
85        switch (opc1) {
86          case 6:
87            switch (crm) {
88              case 0:
89                switch (opc2) {
90                  case 0:
91                    return MISCREG_TEEHBR;
92                }
93                break;
94            }
95            break;
96          case 7:
97            switch (crm) {
98              case 0:
99                switch (opc2) {
100                  case 0:
101                    return MISCREG_JOSCR;
102                }
103                break;
104            }
105            break;
106        }
107        break;
108      case 2:
109        switch (opc1) {
110          case 7:
111            switch (crm) {
112              case 0:
113                switch (opc2) {
114                  case 0:
115                    return MISCREG_JMCR;
116                }
117                break;
118            }
119            break;
120        }
121        break;
122    }
123    // If we get here then it must be a register that we haven't implemented
124    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125         crn, opc1, crm, opc2);
126    return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134    switch (crn) {
135      case 0:
136        switch (opc1) {
137          case 0:
138            switch (crm) {
139              case 0:
140                switch (opc2) {
141                  case 1:
142                    return MISCREG_CTR;
143                  case 2:
144                    return MISCREG_TCMTR;
145                  case 3:
146                    return MISCREG_TLBTR;
147                  case 5:
148                    return MISCREG_MPIDR;
149                  case 6:
150                    return MISCREG_REVIDR;
151                  default:
152                    return MISCREG_MIDR;
153                }
154                break;
155              case 1:
156                switch (opc2) {
157                  case 0:
158                    return MISCREG_ID_PFR0;
159                  case 1:
160                    return MISCREG_ID_PFR1;
161                  case 2:
162                    return MISCREG_ID_DFR0;
163                  case 3:
164                    return MISCREG_ID_AFR0;
165                  case 4:
166                    return MISCREG_ID_MMFR0;
167                  case 5:
168                    return MISCREG_ID_MMFR1;
169                  case 6:
170                    return MISCREG_ID_MMFR2;
171                  case 7:
172                    return MISCREG_ID_MMFR3;
173                }
174                break;
175              case 2:
176                switch (opc2) {
177                  case 0:
178                    return MISCREG_ID_ISAR0;
179                  case 1:
180                    return MISCREG_ID_ISAR1;
181                  case 2:
182                    return MISCREG_ID_ISAR2;
183                  case 3:
184                    return MISCREG_ID_ISAR3;
185                  case 4:
186                    return MISCREG_ID_ISAR4;
187                  case 5:
188                    return MISCREG_ID_ISAR5;
189                  case 6:
190                  case 7:
191                    return MISCREG_RAZ; // read as zero
192                }
193                break;
194              default:
195                return MISCREG_RAZ; // read as zero
196            }
197            break;
198          case 1:
199            if (crm == 0) {
200                switch (opc2) {
201                  case 0:
202                    return MISCREG_CCSIDR;
203                  case 1:
204                    return MISCREG_CLIDR;
205                  case 7:
206                    return MISCREG_AIDR;
207                }
208            }
209            break;
210          case 2:
211            if (crm == 0 && opc2 == 0) {
212                return MISCREG_CSSELR;
213            }
214            break;
215          case 4:
216            if (crm == 0) {
217                if (opc2 == 0)
218                    return MISCREG_VPIDR;
219                else if (opc2 == 5)
220                    return MISCREG_VMPIDR;
221            }
222            break;
223        }
224        break;
225      case 1:
226        if (opc1 == 0) {
227            if (crm == 0) {
228                switch (opc2) {
229                  case 0:
230                    return MISCREG_SCTLR;
231                  case 1:
232                    return MISCREG_ACTLR;
233                  case 0x2:
234                    return MISCREG_CPACR;
235                }
236            } else if (crm == 1) {
237                switch (opc2) {
238                  case 0:
239                    return MISCREG_SCR;
240                  case 1:
241                    return MISCREG_SDER;
242                  case 2:
243                    return MISCREG_NSACR;
244                }
245            }
246        } else if (opc1 == 4) {
247            if (crm == 0) {
248                if (opc2 == 0)
249                    return MISCREG_HSCTLR;
250                else if (opc2 == 1)
251                    return MISCREG_HACTLR;
252            } else if (crm == 1) {
253                switch (opc2) {
254                  case 0:
255                    return MISCREG_HCR;
256                  case 1:
257                    return MISCREG_HDCR;
258                  case 2:
259                    return MISCREG_HCPTR;
260                  case 3:
261                    return MISCREG_HSTR;
262                  case 7:
263                    return MISCREG_HACR;
264                }
265            }
266        }
267        break;
268      case 2:
269        if (opc1 == 0 && crm == 0) {
270            switch (opc2) {
271              case 0:
272                return MISCREG_TTBR0;
273              case 1:
274                return MISCREG_TTBR1;
275              case 2:
276                return MISCREG_TTBCR;
277            }
278        } else if (opc1 == 4) {
279            if (crm == 0 && opc2 == 2)
280                return MISCREG_HTCR;
281            else if (crm == 1 && opc2 == 2)
282                return MISCREG_VTCR;
283        }
284        break;
285      case 3:
286        if (opc1 == 0 && crm == 0 && opc2 == 0) {
287            return MISCREG_DACR;
288        }
289        break;
290      case 4:
291        if (opc1 == 0 && crm == 6 && opc2 == 0) {
292            return MISCREG_ICC_PMR;
293        }
294        break;
295      case 5:
296        if (opc1 == 0) {
297            if (crm == 0) {
298                if (opc2 == 0) {
299                    return MISCREG_DFSR;
300                } else if (opc2 == 1) {
301                    return MISCREG_IFSR;
302                }
303            } else if (crm == 1) {
304                if (opc2 == 0) {
305                    return MISCREG_ADFSR;
306                } else if (opc2 == 1) {
307                    return MISCREG_AIFSR;
308                }
309            }
310        } else if (opc1 == 4) {
311            if (crm == 1) {
312                if (opc2 == 0)
313                    return MISCREG_HADFSR;
314                else if (opc2 == 1)
315                    return MISCREG_HAIFSR;
316            } else if (crm == 2 && opc2 == 0) {
317                return MISCREG_HSR;
318            }
319        }
320        break;
321      case 6:
322        if (opc1 == 0 && crm == 0) {
323            switch (opc2) {
324              case 0:
325                return MISCREG_DFAR;
326              case 2:
327                return MISCREG_IFAR;
328            }
329        } else if (opc1 == 4 && crm == 0) {
330            switch (opc2) {
331              case 0:
332                return MISCREG_HDFAR;
333              case 2:
334                return MISCREG_HIFAR;
335              case 4:
336                return MISCREG_HPFAR;
337            }
338        }
339        break;
340      case 7:
341        if (opc1 == 0) {
342            switch (crm) {
343              case 0:
344                if (opc2 == 4) {
345                    return MISCREG_NOP;
346                }
347                break;
348              case 1:
349                switch (opc2) {
350                  case 0:
351                    return MISCREG_ICIALLUIS;
352                  case 6:
353                    return MISCREG_BPIALLIS;
354                }
355                break;
356              case 4:
357                if (opc2 == 0) {
358                    return MISCREG_PAR;
359                }
360                break;
361              case 5:
362                switch (opc2) {
363                  case 0:
364                    return MISCREG_ICIALLU;
365                  case 1:
366                    return MISCREG_ICIMVAU;
367                  case 4:
368                    return MISCREG_CP15ISB;
369                  case 6:
370                    return MISCREG_BPIALL;
371                  case 7:
372                    return MISCREG_BPIMVA;
373                }
374                break;
375              case 6:
376                if (opc2 == 1) {
377                    return MISCREG_DCIMVAC;
378                } else if (opc2 == 2) {
379                    return MISCREG_DCISW;
380                }
381                break;
382              case 8:
383                switch (opc2) {
384                  case 0:
385                    return MISCREG_ATS1CPR;
386                  case 1:
387                    return MISCREG_ATS1CPW;
388                  case 2:
389                    return MISCREG_ATS1CUR;
390                  case 3:
391                    return MISCREG_ATS1CUW;
392                  case 4:
393                    return MISCREG_ATS12NSOPR;
394                  case 5:
395                    return MISCREG_ATS12NSOPW;
396                  case 6:
397                    return MISCREG_ATS12NSOUR;
398                  case 7:
399                    return MISCREG_ATS12NSOUW;
400                }
401                break;
402              case 10:
403                switch (opc2) {
404                  case 1:
405                    return MISCREG_DCCMVAC;
406                  case 2:
407                    return MISCREG_DCCSW;
408                  case 4:
409                    return MISCREG_CP15DSB;
410                  case 5:
411                    return MISCREG_CP15DMB;
412                }
413                break;
414              case 11:
415                if (opc2 == 1) {
416                    return MISCREG_DCCMVAU;
417                }
418                break;
419              case 13:
420                if (opc2 == 1) {
421                    return MISCREG_NOP;
422                }
423                break;
424              case 14:
425                if (opc2 == 1) {
426                    return MISCREG_DCCIMVAC;
427                } else if (opc2 == 2) {
428                    return MISCREG_DCCISW;
429                }
430                break;
431            }
432        } else if (opc1 == 4 && crm == 8) {
433            if (opc2 == 0)
434                return MISCREG_ATS1HR;
435            else if (opc2 == 1)
436                return MISCREG_ATS1HW;
437        }
438        break;
439      case 8:
440        if (opc1 == 0) {
441            switch (crm) {
442              case 3:
443                switch (opc2) {
444                  case 0:
445                    return MISCREG_TLBIALLIS;
446                  case 1:
447                    return MISCREG_TLBIMVAIS;
448                  case 2:
449                    return MISCREG_TLBIASIDIS;
450                  case 3:
451                    return MISCREG_TLBIMVAAIS;
452                  case 5:
453                    return MISCREG_TLBIMVALIS;
454                  case 7:
455                    return MISCREG_TLBIMVAALIS;
456                }
457                break;
458              case 5:
459                switch (opc2) {
460                  case 0:
461                    return MISCREG_ITLBIALL;
462                  case 1:
463                    return MISCREG_ITLBIMVA;
464                  case 2:
465                    return MISCREG_ITLBIASID;
466                }
467                break;
468              case 6:
469                switch (opc2) {
470                  case 0:
471                    return MISCREG_DTLBIALL;
472                  case 1:
473                    return MISCREG_DTLBIMVA;
474                  case 2:
475                    return MISCREG_DTLBIASID;
476                }
477                break;
478              case 7:
479                switch (opc2) {
480                  case 0:
481                    return MISCREG_TLBIALL;
482                  case 1:
483                    return MISCREG_TLBIMVA;
484                  case 2:
485                    return MISCREG_TLBIASID;
486                  case 3:
487                    return MISCREG_TLBIMVAA;
488                  case 5:
489                    return MISCREG_TLBIMVAL;
490                  case 7:
491                    return MISCREG_TLBIMVAAL;
492                }
493                break;
494            }
495        } else if (opc1 == 4) {
496            if (crm == 0) {
497                switch (opc2) {
498                  case 1:
499                    return MISCREG_TLBIIPAS2IS;
500                  case 5:
501                    return MISCREG_TLBIIPAS2LIS;
502                }
503            } else if (crm == 3) {
504                switch (opc2) {
505                  case 0:
506                    return MISCREG_TLBIALLHIS;
507                  case 1:
508                    return MISCREG_TLBIMVAHIS;
509                  case 4:
510                    return MISCREG_TLBIALLNSNHIS;
511                  case 5:
512                    return MISCREG_TLBIMVALHIS;
513                }
514            } else if (crm == 4) {
515                switch (opc2) {
516                  case 1:
517                    return MISCREG_TLBIIPAS2;
518                  case 5:
519                    return MISCREG_TLBIIPAS2L;
520                }
521            } else if (crm == 7) {
522                switch (opc2) {
523                  case 0:
524                    return MISCREG_TLBIALLH;
525                  case 1:
526                    return MISCREG_TLBIMVAH;
527                  case 4:
528                    return MISCREG_TLBIALLNSNH;
529                  case 5:
530                    return MISCREG_TLBIMVALH;
531                }
532            }
533        }
534        break;
535      case 9:
536        // Every cop register with CRn = 9 and CRm in
537        // {0-2}, {5-8} is implementation defined regardless
538        // of opc1 and opc2.
539        switch (crm) {
540          case 0:
541          case 1:
542          case 2:
543          case 5:
544          case 6:
545          case 7:
546          case 8:
547            return MISCREG_IMPDEF_UNIMPL;
548        }
549        if (opc1 == 0) {
550            switch (crm) {
551              case 12:
552                switch (opc2) {
553                  case 0:
554                    return MISCREG_PMCR;
555                  case 1:
556                    return MISCREG_PMCNTENSET;
557                  case 2:
558                    return MISCREG_PMCNTENCLR;
559                  case 3:
560                    return MISCREG_PMOVSR;
561                  case 4:
562                    return MISCREG_PMSWINC;
563                  case 5:
564                    return MISCREG_PMSELR;
565                  case 6:
566                    return MISCREG_PMCEID0;
567                  case 7:
568                    return MISCREG_PMCEID1;
569                }
570                break;
571              case 13:
572                switch (opc2) {
573                  case 0:
574                    return MISCREG_PMCCNTR;
575                  case 1:
576                    // Selector is PMSELR.SEL
577                    return MISCREG_PMXEVTYPER_PMCCFILTR;
578                  case 2:
579                    return MISCREG_PMXEVCNTR;
580                }
581                break;
582              case 14:
583                switch (opc2) {
584                  case 0:
585                    return MISCREG_PMUSERENR;
586                  case 1:
587                    return MISCREG_PMINTENSET;
588                  case 2:
589                    return MISCREG_PMINTENCLR;
590                  case 3:
591                    return MISCREG_PMOVSSET;
592                }
593                break;
594            }
595        } else if (opc1 == 1) {
596            switch (crm) {
597              case 0:
598                switch (opc2) {
599                  case 2: // L2CTLR, L2 Control Register
600                    return MISCREG_L2CTLR;
601                  case 3:
602                    return MISCREG_L2ECTLR;
603                }
604                break;
605                break;
606            }
607        }
608        break;
609      case 10:
610        if (opc1 == 0) {
611            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
612            if (crm < 2) {
613                return MISCREG_IMPDEF_UNIMPL;
614            } else if (crm == 2) { // TEX Remap Registers
615                if (opc2 == 0) {
616                    // Selector is TTBCR.EAE
617                    return MISCREG_PRRR_MAIR0;
618                } else if (opc2 == 1) {
619                    // Selector is TTBCR.EAE
620                    return MISCREG_NMRR_MAIR1;
621                }
622            } else if (crm == 3) {
623                if (opc2 == 0) {
624                    return MISCREG_AMAIR0;
625                } else if (opc2 == 1) {
626                    return MISCREG_AMAIR1;
627                }
628            }
629        } else if (opc1 == 4) {
630            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
631            if (crm == 2) {
632                if (opc2 == 0)
633                    return MISCREG_HMAIR0;
634                else if (opc2 == 1)
635                    return MISCREG_HMAIR1;
636            } else if (crm == 3) {
637                if (opc2 == 0)
638                    return MISCREG_HAMAIR0;
639                else if (opc2 == 1)
640                    return MISCREG_HAMAIR1;
641            }
642        }
643        break;
644      case 11:
645        if (opc1 <=7) {
646            switch (crm) {
647              case 0:
648              case 1:
649              case 2:
650              case 3:
651              case 4:
652              case 5:
653              case 6:
654              case 7:
655              case 8:
656              case 15:
657                // Reserved for DMA operations for TCM access
658                return MISCREG_IMPDEF_UNIMPL;
659              default:
660                break;
661            }
662        }
663        break;
664      case 12:
665        if (opc1 == 0) {
666            if (crm == 0) {
667                if (opc2 == 0) {
668                    return MISCREG_VBAR;
669                } else if (opc2 == 1) {
670                    return MISCREG_MVBAR;
671                }
672            } else if (crm == 1) {
673                if (opc2 == 0) {
674                    return MISCREG_ISR;
675                }
676            } else if (crm == 8) {
677                switch (opc2) {
678                    case 0:
679                        return MISCREG_ICC_IAR0;
680                    case 1:
681                        return MISCREG_ICC_EOIR0;
682                    case 2:
683                        return MISCREG_ICC_HPPIR0;
684                    case 3:
685                        return MISCREG_ICC_BPR0;
686                    case 4:
687                        return MISCREG_ICC_AP0R0;
688                    case 5:
689                        return MISCREG_ICC_AP0R1;
690                    case 6:
691                        return MISCREG_ICC_AP0R2;
692                    case 7:
693                        return MISCREG_ICC_AP0R3;
694                }
695            } else if (crm == 9) {
696                switch (opc2) {
697                    case 0:
698                        return MISCREG_ICC_AP1R0;
699                    case 1:
700                        return MISCREG_ICC_AP1R1;
701                    case 2:
702                        return MISCREG_ICC_AP1R2;
703                    case 3:
704                        return MISCREG_ICC_AP1R3;
705                }
706            } else if (crm == 11) {
707                switch (opc2) {
708                    case 1:
709                        return MISCREG_ICC_DIR;
710                    case 3:
711                        return MISCREG_ICC_RPR;
712                }
713            } else if (crm == 12) {
714                switch (opc2) {
715                    case 0:
716                        return MISCREG_ICC_IAR1;
717                    case 1:
718                        return MISCREG_ICC_EOIR1;
719                    case 2:
720                        return MISCREG_ICC_HPPIR1;
721                    case 3:
722                        return MISCREG_ICC_BPR1;
723                    case 4:
724                        return MISCREG_ICC_CTLR;
725                    case 5:
726                        return MISCREG_ICC_SRE;
727                    case 6:
728                        return MISCREG_ICC_IGRPEN0;
729                    case 7:
730                        return MISCREG_ICC_IGRPEN1;
731                }
732            }
733        } else if (opc1 == 4) {
734            if (crm == 0 && opc2 == 0) {
735                return MISCREG_HVBAR;
736            } else if (crm == 8) {
737                switch (opc2) {
738                    case 0:
739                        return MISCREG_ICH_AP0R0;
740                    case 1:
741                        return MISCREG_ICH_AP0R1;
742                    case 2:
743                        return MISCREG_ICH_AP0R2;
744                    case 3:
745                        return MISCREG_ICH_AP0R3;
746                }
747            } else if (crm == 9) {
748                switch (opc2) {
749                    case 0:
750                        return MISCREG_ICH_AP1R0;
751                    case 1:
752                        return MISCREG_ICH_AP1R1;
753                    case 2:
754                        return MISCREG_ICH_AP1R2;
755                    case 3:
756                        return MISCREG_ICH_AP1R3;
757                    case 5:
758                        return MISCREG_ICC_HSRE;
759                }
760            } else if (crm == 11) {
761                switch (opc2) {
762                    case 0:
763                        return MISCREG_ICH_HCR;
764                    case 1:
765                        return MISCREG_ICH_VTR;
766                    case 2:
767                        return MISCREG_ICH_MISR;
768                    case 3:
769                        return MISCREG_ICH_EISR;
770                    case 5:
771                        return MISCREG_ICH_ELRSR;
772                    case 7:
773                        return MISCREG_ICH_VMCR;
774                }
775            } else if (crm == 12) {
776                switch (opc2) {
777                    case 0:
778                        return MISCREG_ICH_LR0;
779                    case 1:
780                        return MISCREG_ICH_LR1;
781                    case 2:
782                        return MISCREG_ICH_LR2;
783                    case 3:
784                        return MISCREG_ICH_LR3;
785                    case 4:
786                        return MISCREG_ICH_LR4;
787                    case 5:
788                        return MISCREG_ICH_LR5;
789                    case 6:
790                        return MISCREG_ICH_LR6;
791                    case 7:
792                        return MISCREG_ICH_LR7;
793                }
794            } else if (crm == 13) {
795                switch (opc2) {
796                    case 0:
797                        return MISCREG_ICH_LR8;
798                    case 1:
799                        return MISCREG_ICH_LR9;
800                    case 2:
801                        return MISCREG_ICH_LR10;
802                    case 3:
803                        return MISCREG_ICH_LR11;
804                    case 4:
805                        return MISCREG_ICH_LR12;
806                    case 5:
807                        return MISCREG_ICH_LR13;
808                    case 6:
809                        return MISCREG_ICH_LR14;
810                    case 7:
811                        return MISCREG_ICH_LR15;
812                }
813            } else if (crm == 14) {
814                switch (opc2) {
815                    case 0:
816                        return MISCREG_ICH_LRC0;
817                    case 1:
818                        return MISCREG_ICH_LRC1;
819                    case 2:
820                        return MISCREG_ICH_LRC2;
821                    case 3:
822                        return MISCREG_ICH_LRC3;
823                    case 4:
824                        return MISCREG_ICH_LRC4;
825                    case 5:
826                        return MISCREG_ICH_LRC5;
827                    case 6:
828                        return MISCREG_ICH_LRC6;
829                    case 7:
830                        return MISCREG_ICH_LRC7;
831                }
832            } else if (crm == 15) {
833                switch (opc2) {
834                    case 0:
835                        return MISCREG_ICH_LRC8;
836                    case 1:
837                        return MISCREG_ICH_LRC9;
838                    case 2:
839                        return MISCREG_ICH_LRC10;
840                    case 3:
841                        return MISCREG_ICH_LRC11;
842                    case 4:
843                        return MISCREG_ICH_LRC12;
844                    case 5:
845                        return MISCREG_ICH_LRC13;
846                    case 6:
847                        return MISCREG_ICH_LRC14;
848                    case 7:
849                        return MISCREG_ICH_LRC15;
850                }
851            }
852        } else if (opc1 == 6) {
853            if (crm == 12) {
854                switch (opc2) {
855                    case 4:
856                        return MISCREG_ICC_MCTLR;
857                    case 5:
858                        return MISCREG_ICC_MSRE;
859                    case 7:
860                        return MISCREG_ICC_MGRPEN1;
861                }
862            }
863        }
864        break;
865      case 13:
866        if (opc1 == 0) {
867            if (crm == 0) {
868                switch (opc2) {
869                  case 0:
870                    return MISCREG_FCSEIDR;
871                  case 1:
872                    return MISCREG_CONTEXTIDR;
873                  case 2:
874                    return MISCREG_TPIDRURW;
875                  case 3:
876                    return MISCREG_TPIDRURO;
877                  case 4:
878                    return MISCREG_TPIDRPRW;
879                }
880            }
881        } else if (opc1 == 4) {
882            if (crm == 0 && opc2 == 2)
883                return MISCREG_HTPIDR;
884        }
885        break;
886      case 14:
887        if (opc1 == 0) {
888            switch (crm) {
889              case 0:
890                if (opc2 == 0)
891                    return MISCREG_CNTFRQ;
892                break;
893              case 1:
894                if (opc2 == 0)
895                    return MISCREG_CNTKCTL;
896                break;
897              case 2:
898                if (opc2 == 0)
899                    return MISCREG_CNTP_TVAL;
900                else if (opc2 == 1)
901                    return MISCREG_CNTP_CTL;
902                break;
903              case 3:
904                if (opc2 == 0)
905                    return MISCREG_CNTV_TVAL;
906                else if (opc2 == 1)
907                    return MISCREG_CNTV_CTL;
908                break;
909            }
910        } else if (opc1 == 4) {
911            if (crm == 1 && opc2 == 0) {
912                return MISCREG_CNTHCTL;
913            } else if (crm == 2) {
914                if (opc2 == 0)
915                    return MISCREG_CNTHP_TVAL;
916                else if (opc2 == 1)
917                    return MISCREG_CNTHP_CTL;
918            }
919        }
920        break;
921      case 15:
922        // Implementation defined
923        return MISCREG_IMPDEF_UNIMPL;
924    }
925    // Unrecognized register
926    return MISCREG_CP15_UNIMPL;
927}
928
929MiscRegIndex
930decodeCP15Reg64(unsigned crm, unsigned opc1)
931{
932    switch (crm) {
933      case 2:
934        switch (opc1) {
935          case 0:
936            return MISCREG_TTBR0;
937          case 1:
938            return MISCREG_TTBR1;
939          case 4:
940            return MISCREG_HTTBR;
941          case 6:
942            return MISCREG_VTTBR;
943        }
944        break;
945      case 7:
946        if (opc1 == 0)
947            return MISCREG_PAR;
948        break;
949      case 14:
950        switch (opc1) {
951          case 0:
952            return MISCREG_CNTPCT;
953          case 1:
954            return MISCREG_CNTVCT;
955          case 2:
956            return MISCREG_CNTP_CVAL;
957          case 3:
958            return MISCREG_CNTV_CVAL;
959          case 4:
960            return MISCREG_CNTVOFF;
961          case 6:
962            return MISCREG_CNTHP_CVAL;
963        }
964        break;
965      case 15:
966        if (opc1 == 0)
967            return MISCREG_CPUMERRSR;
968        else if (opc1 == 1)
969            return MISCREG_L2MERRSR;
970        break;
971    }
972    // Unrecognized register
973    return MISCREG_CP15_UNIMPL;
974}
975
976std::tuple<bool, bool>
977canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
978{
979    bool secure = !scr.ns;
980    bool canRead = false;
981    bool undefined = false;
982
983    switch (cpsr.mode) {
984      case MODE_USER:
985        canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
986                           miscRegInfo[reg][MISCREG_USR_NS_RD];
987        break;
988      case MODE_FIQ:
989      case MODE_IRQ:
990      case MODE_SVC:
991      case MODE_ABORT:
992      case MODE_UNDEFINED:
993      case MODE_SYSTEM:
994        canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
995                           miscRegInfo[reg][MISCREG_PRI_NS_RD];
996        break;
997      case MODE_MON:
998        canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
999                           miscRegInfo[reg][MISCREG_MON_NS1_RD];
1000        break;
1001      case MODE_HYP:
1002        canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1003        break;
1004      default:
1005        undefined = true;
1006    }
1007    // can't do permissions checkes on the root of a banked pair of regs
1008    assert(!miscRegInfo[reg][MISCREG_BANKED]);
1009    return std::make_tuple(canRead, undefined);
1010}
1011
1012std::tuple<bool, bool>
1013canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1014{
1015    bool secure = !scr.ns;
1016    bool canWrite = false;
1017    bool undefined = false;
1018
1019    switch (cpsr.mode) {
1020      case MODE_USER:
1021        canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1022                            miscRegInfo[reg][MISCREG_USR_NS_WR];
1023        break;
1024      case MODE_FIQ:
1025      case MODE_IRQ:
1026      case MODE_SVC:
1027      case MODE_ABORT:
1028      case MODE_UNDEFINED:
1029      case MODE_SYSTEM:
1030        canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1031                            miscRegInfo[reg][MISCREG_PRI_NS_WR];
1032        break;
1033      case MODE_MON:
1034        canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1035                            miscRegInfo[reg][MISCREG_MON_NS1_WR];
1036        break;
1037      case MODE_HYP:
1038        canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
1039        break;
1040      default:
1041        undefined = true;
1042    }
1043    // can't do permissions checkes on the root of a banked pair of regs
1044    assert(!miscRegInfo[reg][MISCREG_BANKED]);
1045    return std::make_tuple(canWrite, undefined);
1046}
1047
1048int
1049snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1050{
1051    SCR scr = tc->readMiscReg(MISCREG_SCR);
1052    return snsBankedIndex(reg, tc, scr.ns);
1053}
1054
1055int
1056snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1057{
1058    int reg_as_int = static_cast<int>(reg);
1059    if (miscRegInfo[reg][MISCREG_BANKED]) {
1060        reg_as_int += (ArmSystem::haveSecurity(tc) &&
1061                      !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1062    }
1063    return reg_as_int;
1064}
1065
1066
1067/**
1068 * If the reg is a child reg of a banked set, then the parent is the last
1069 * banked one in the list. This is messy, and the wish is to eventually have
1070 * the bitmap replaced with a better data structure. the preUnflatten function
1071 * initializes a lookup table to speed up the search for these banked
1072 * registers.
1073 */
1074
1075int unflattenResultMiscReg[NUM_MISCREGS];
1076
1077void
1078preUnflattenMiscReg()
1079{
1080    int reg = -1;
1081    for (int i = 0 ; i < NUM_MISCREGS; i++){
1082        if (miscRegInfo[i][MISCREG_BANKED])
1083            reg = i;
1084        if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1085            unflattenResultMiscReg[i] = reg;
1086        else
1087            unflattenResultMiscReg[i] = i;
1088        // if this assert fails, no parent was found, and something is broken
1089        assert(unflattenResultMiscReg[i] > -1);
1090    }
1091}
1092
1093int
1094unflattenMiscReg(int reg)
1095{
1096    return unflattenResultMiscReg[reg];
1097}
1098
1099bool
1100canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1101{
1102    // Check for SP_EL0 access while SPSEL == 0
1103    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1104        return false;
1105
1106    // Check for RVBAR access
1107    if (reg == MISCREG_RVBAR_EL1) {
1108        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1109        if (highest_el == EL2 || highest_el == EL3)
1110            return false;
1111    }
1112    if (reg == MISCREG_RVBAR_EL2) {
1113        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1114        if (highest_el == EL3)
1115            return false;
1116    }
1117
1118    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1119
1120    switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
1121      case EL0:
1122        return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1123            miscRegInfo[reg][MISCREG_USR_NS_RD];
1124      case EL1:
1125        return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1126            miscRegInfo[reg][MISCREG_PRI_NS_RD];
1127      case EL2:
1128        return miscRegInfo[reg][MISCREG_HYP_RD];
1129      case EL3:
1130        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1131            miscRegInfo[reg][MISCREG_MON_NS1_RD];
1132      default:
1133        panic("Invalid exception level");
1134    }
1135}
1136
1137bool
1138canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1139{
1140    // Check for SP_EL0 access while SPSEL == 0
1141    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1142        return false;
1143    ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
1144    if (reg == MISCREG_DAIF) {
1145        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1146        if (el == EL0 && !sctlr.uma)
1147            return false;
1148    }
1149    if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1150        // In syscall-emulation mode, this test is skipped and DCZVA is always
1151        // allowed at EL0
1152        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1153        if (el == EL0 && !sctlr.dze)
1154            return false;
1155    }
1156    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1157        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1158        if (el == EL0 && !sctlr.uci)
1159            return false;
1160    }
1161
1162    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1163
1164    switch (el) {
1165      case EL0:
1166        return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1167            miscRegInfo[reg][MISCREG_USR_NS_WR];
1168      case EL1:
1169        return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1170            miscRegInfo[reg][MISCREG_PRI_NS_WR];
1171      case EL2:
1172        return miscRegInfo[reg][MISCREG_HYP_WR];
1173      case EL3:
1174        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1175            miscRegInfo[reg][MISCREG_MON_NS1_WR];
1176      default:
1177        panic("Invalid exception level");
1178    }
1179}
1180
1181MiscRegIndex
1182decodeAArch64SysReg(unsigned op0, unsigned op1,
1183                    unsigned crn, unsigned crm,
1184                    unsigned op2)
1185{
1186    switch (op0) {
1187      case 1:
1188        switch (crn) {
1189          case 7:
1190            switch (op1) {
1191              case 0:
1192                switch (crm) {
1193                  case 1:
1194                    switch (op2) {
1195                      case 0:
1196                        return MISCREG_IC_IALLUIS;
1197                    }
1198                    break;
1199                  case 5:
1200                    switch (op2) {
1201                      case 0:
1202                        return MISCREG_IC_IALLU;
1203                    }
1204                    break;
1205                  case 6:
1206                    switch (op2) {
1207                      case 1:
1208                        return MISCREG_DC_IVAC_Xt;
1209                      case 2:
1210                        return MISCREG_DC_ISW_Xt;
1211                    }
1212                    break;
1213                  case 8:
1214                    switch (op2) {
1215                      case 0:
1216                        return MISCREG_AT_S1E1R_Xt;
1217                      case 1:
1218                        return MISCREG_AT_S1E1W_Xt;
1219                      case 2:
1220                        return MISCREG_AT_S1E0R_Xt;
1221                      case 3:
1222                        return MISCREG_AT_S1E0W_Xt;
1223                    }
1224                    break;
1225                  case 10:
1226                    switch (op2) {
1227                      case 2:
1228                        return MISCREG_DC_CSW_Xt;
1229                    }
1230                    break;
1231                  case 14:
1232                    switch (op2) {
1233                      case 2:
1234                        return MISCREG_DC_CISW_Xt;
1235                    }
1236                    break;
1237                }
1238                break;
1239              case 3:
1240                switch (crm) {
1241                  case 4:
1242                    switch (op2) {
1243                      case 1:
1244                        return MISCREG_DC_ZVA_Xt;
1245                    }
1246                    break;
1247                  case 5:
1248                    switch (op2) {
1249                      case 1:
1250                        return MISCREG_IC_IVAU_Xt;
1251                    }
1252                    break;
1253                  case 10:
1254                    switch (op2) {
1255                      case 1:
1256                        return MISCREG_DC_CVAC_Xt;
1257                    }
1258                    break;
1259                  case 11:
1260                    switch (op2) {
1261                      case 1:
1262                        return MISCREG_DC_CVAU_Xt;
1263                    }
1264                    break;
1265                  case 14:
1266                    switch (op2) {
1267                      case 1:
1268                        return MISCREG_DC_CIVAC_Xt;
1269                    }
1270                    break;
1271                }
1272                break;
1273              case 4:
1274                switch (crm) {
1275                  case 8:
1276                    switch (op2) {
1277                      case 0:
1278                        return MISCREG_AT_S1E2R_Xt;
1279                      case 1:
1280                        return MISCREG_AT_S1E2W_Xt;
1281                      case 4:
1282                        return MISCREG_AT_S12E1R_Xt;
1283                      case 5:
1284                        return MISCREG_AT_S12E1W_Xt;
1285                      case 6:
1286                        return MISCREG_AT_S12E0R_Xt;
1287                      case 7:
1288                        return MISCREG_AT_S12E0W_Xt;
1289                    }
1290                    break;
1291                }
1292                break;
1293              case 6:
1294                switch (crm) {
1295                  case 8:
1296                    switch (op2) {
1297                      case 0:
1298                        return MISCREG_AT_S1E3R_Xt;
1299                      case 1:
1300                        return MISCREG_AT_S1E3W_Xt;
1301                    }
1302                    break;
1303                }
1304                break;
1305            }
1306            break;
1307          case 8:
1308            switch (op1) {
1309              case 0:
1310                switch (crm) {
1311                  case 3:
1312                    switch (op2) {
1313                      case 0:
1314                        return MISCREG_TLBI_VMALLE1IS;
1315                      case 1:
1316                        return MISCREG_TLBI_VAE1IS_Xt;
1317                      case 2:
1318                        return MISCREG_TLBI_ASIDE1IS_Xt;
1319                      case 3:
1320                        return MISCREG_TLBI_VAAE1IS_Xt;
1321                      case 5:
1322                        return MISCREG_TLBI_VALE1IS_Xt;
1323                      case 7:
1324                        return MISCREG_TLBI_VAALE1IS_Xt;
1325                    }
1326                    break;
1327                  case 7:
1328                    switch (op2) {
1329                      case 0:
1330                        return MISCREG_TLBI_VMALLE1;
1331                      case 1:
1332                        return MISCREG_TLBI_VAE1_Xt;
1333                      case 2:
1334                        return MISCREG_TLBI_ASIDE1_Xt;
1335                      case 3:
1336                        return MISCREG_TLBI_VAAE1_Xt;
1337                      case 5:
1338                        return MISCREG_TLBI_VALE1_Xt;
1339                      case 7:
1340                        return MISCREG_TLBI_VAALE1_Xt;
1341                    }
1342                    break;
1343                }
1344                break;
1345              case 4:
1346                switch (crm) {
1347                  case 0:
1348                    switch (op2) {
1349                      case 1:
1350                        return MISCREG_TLBI_IPAS2E1IS_Xt;
1351                      case 5:
1352                        return MISCREG_TLBI_IPAS2LE1IS_Xt;
1353                    }
1354                    break;
1355                  case 3:
1356                    switch (op2) {
1357                      case 0:
1358                        return MISCREG_TLBI_ALLE2IS;
1359                      case 1:
1360                        return MISCREG_TLBI_VAE2IS_Xt;
1361                      case 4:
1362                        return MISCREG_TLBI_ALLE1IS;
1363                      case 5:
1364                        return MISCREG_TLBI_VALE2IS_Xt;
1365                      case 6:
1366                        return MISCREG_TLBI_VMALLS12E1IS;
1367                    }
1368                    break;
1369                  case 4:
1370                    switch (op2) {
1371                      case 1:
1372                        return MISCREG_TLBI_IPAS2E1_Xt;
1373                      case 5:
1374                        return MISCREG_TLBI_IPAS2LE1_Xt;
1375                    }
1376                    break;
1377                  case 7:
1378                    switch (op2) {
1379                      case 0:
1380                        return MISCREG_TLBI_ALLE2;
1381                      case 1:
1382                        return MISCREG_TLBI_VAE2_Xt;
1383                      case 4:
1384                        return MISCREG_TLBI_ALLE1;
1385                      case 5:
1386                        return MISCREG_TLBI_VALE2_Xt;
1387                      case 6:
1388                        return MISCREG_TLBI_VMALLS12E1;
1389                    }
1390                    break;
1391                }
1392                break;
1393              case 6:
1394                switch (crm) {
1395                  case 3:
1396                    switch (op2) {
1397                      case 0:
1398                        return MISCREG_TLBI_ALLE3IS;
1399                      case 1:
1400                        return MISCREG_TLBI_VAE3IS_Xt;
1401                      case 5:
1402                        return MISCREG_TLBI_VALE3IS_Xt;
1403                    }
1404                    break;
1405                  case 7:
1406                    switch (op2) {
1407                      case 0:
1408                        return MISCREG_TLBI_ALLE3;
1409                      case 1:
1410                        return MISCREG_TLBI_VAE3_Xt;
1411                      case 5:
1412                        return MISCREG_TLBI_VALE3_Xt;
1413                    }
1414                    break;
1415                }
1416                break;
1417            }
1418            break;
1419          case 11:
1420          case 15:
1421            // SYS Instruction with CRn = { 11, 15 }
1422            // (Trappable by HCR_EL2.TIDCP)
1423            return MISCREG_IMPDEF_UNIMPL;
1424        }
1425        break;
1426      case 2:
1427        switch (crn) {
1428          case 0:
1429            switch (op1) {
1430              case 0:
1431                switch (crm) {
1432                  case 0:
1433                    switch (op2) {
1434                      case 2:
1435                        return MISCREG_OSDTRRX_EL1;
1436                      case 4:
1437                        return MISCREG_DBGBVR0_EL1;
1438                      case 5:
1439                        return MISCREG_DBGBCR0_EL1;
1440                      case 6:
1441                        return MISCREG_DBGWVR0_EL1;
1442                      case 7:
1443                        return MISCREG_DBGWCR0_EL1;
1444                    }
1445                    break;
1446                  case 1:
1447                    switch (op2) {
1448                      case 4:
1449                        return MISCREG_DBGBVR1_EL1;
1450                      case 5:
1451                        return MISCREG_DBGBCR1_EL1;
1452                      case 6:
1453                        return MISCREG_DBGWVR1_EL1;
1454                      case 7:
1455                        return MISCREG_DBGWCR1_EL1;
1456                    }
1457                    break;
1458                  case 2:
1459                    switch (op2) {
1460                      case 0:
1461                        return MISCREG_MDCCINT_EL1;
1462                      case 2:
1463                        return MISCREG_MDSCR_EL1;
1464                      case 4:
1465                        return MISCREG_DBGBVR2_EL1;
1466                      case 5:
1467                        return MISCREG_DBGBCR2_EL1;
1468                      case 6:
1469                        return MISCREG_DBGWVR2_EL1;
1470                      case 7:
1471                        return MISCREG_DBGWCR2_EL1;
1472                    }
1473                    break;
1474                  case 3:
1475                    switch (op2) {
1476                      case 2:
1477                        return MISCREG_OSDTRTX_EL1;
1478                      case 4:
1479                        return MISCREG_DBGBVR3_EL1;
1480                      case 5:
1481                        return MISCREG_DBGBCR3_EL1;
1482                      case 6:
1483                        return MISCREG_DBGWVR3_EL1;
1484                      case 7:
1485                        return MISCREG_DBGWCR3_EL1;
1486                    }
1487                    break;
1488                  case 4:
1489                    switch (op2) {
1490                      case 4:
1491                        return MISCREG_DBGBVR4_EL1;
1492                      case 5:
1493                        return MISCREG_DBGBCR4_EL1;
1494                    }
1495                    break;
1496                  case 5:
1497                    switch (op2) {
1498                      case 4:
1499                        return MISCREG_DBGBVR5_EL1;
1500                      case 5:
1501                        return MISCREG_DBGBCR5_EL1;
1502                    }
1503                    break;
1504                  case 6:
1505                    switch (op2) {
1506                      case 2:
1507                        return MISCREG_OSECCR_EL1;
1508                    }
1509                    break;
1510                }
1511                break;
1512              case 2:
1513                switch (crm) {
1514                  case 0:
1515                    switch (op2) {
1516                      case 0:
1517                        return MISCREG_TEECR32_EL1;
1518                    }
1519                    break;
1520                }
1521                break;
1522              case 3:
1523                switch (crm) {
1524                  case 1:
1525                    switch (op2) {
1526                      case 0:
1527                        return MISCREG_MDCCSR_EL0;
1528                    }
1529                    break;
1530                  case 4:
1531                    switch (op2) {
1532                      case 0:
1533                        return MISCREG_MDDTR_EL0;
1534                    }
1535                    break;
1536                  case 5:
1537                    switch (op2) {
1538                      case 0:
1539                        return MISCREG_MDDTRRX_EL0;
1540                    }
1541                    break;
1542                }
1543                break;
1544              case 4:
1545                switch (crm) {
1546                  case 7:
1547                    switch (op2) {
1548                      case 0:
1549                        return MISCREG_DBGVCR32_EL2;
1550                    }
1551                    break;
1552                }
1553                break;
1554            }
1555            break;
1556          case 1:
1557            switch (op1) {
1558              case 0:
1559                switch (crm) {
1560                  case 0:
1561                    switch (op2) {
1562                      case 0:
1563                        return MISCREG_MDRAR_EL1;
1564                      case 4:
1565                        return MISCREG_OSLAR_EL1;
1566                    }
1567                    break;
1568                  case 1:
1569                    switch (op2) {
1570                      case 4:
1571                        return MISCREG_OSLSR_EL1;
1572                    }
1573                    break;
1574                  case 3:
1575                    switch (op2) {
1576                      case 4:
1577                        return MISCREG_OSDLR_EL1;
1578                    }
1579                    break;
1580                  case 4:
1581                    switch (op2) {
1582                      case 4:
1583                        return MISCREG_DBGPRCR_EL1;
1584                    }
1585                    break;
1586                }
1587                break;
1588              case 2:
1589                switch (crm) {
1590                  case 0:
1591                    switch (op2) {
1592                      case 0:
1593                        return MISCREG_TEEHBR32_EL1;
1594                    }
1595                    break;
1596                }
1597                break;
1598            }
1599            break;
1600          case 7:
1601            switch (op1) {
1602              case 0:
1603                switch (crm) {
1604                  case 8:
1605                    switch (op2) {
1606                      case 6:
1607                        return MISCREG_DBGCLAIMSET_EL1;
1608                    }
1609                    break;
1610                  case 9:
1611                    switch (op2) {
1612                      case 6:
1613                        return MISCREG_DBGCLAIMCLR_EL1;
1614                    }
1615                    break;
1616                  case 14:
1617                    switch (op2) {
1618                      case 6:
1619                        return MISCREG_DBGAUTHSTATUS_EL1;
1620                    }
1621                    break;
1622                }
1623                break;
1624            }
1625            break;
1626        }
1627        break;
1628      case 3:
1629        switch (crn) {
1630          case 0:
1631            switch (op1) {
1632              case 0:
1633                switch (crm) {
1634                  case 0:
1635                    switch (op2) {
1636                      case 0:
1637                        return MISCREG_MIDR_EL1;
1638                      case 5:
1639                        return MISCREG_MPIDR_EL1;
1640                      case 6:
1641                        return MISCREG_REVIDR_EL1;
1642                    }
1643                    break;
1644                  case 1:
1645                    switch (op2) {
1646                      case 0:
1647                        return MISCREG_ID_PFR0_EL1;
1648                      case 1:
1649                        return MISCREG_ID_PFR1_EL1;
1650                      case 2:
1651                        return MISCREG_ID_DFR0_EL1;
1652                      case 3:
1653                        return MISCREG_ID_AFR0_EL1;
1654                      case 4:
1655                        return MISCREG_ID_MMFR0_EL1;
1656                      case 5:
1657                        return MISCREG_ID_MMFR1_EL1;
1658                      case 6:
1659                        return MISCREG_ID_MMFR2_EL1;
1660                      case 7:
1661                        return MISCREG_ID_MMFR3_EL1;
1662                    }
1663                    break;
1664                  case 2:
1665                    switch (op2) {
1666                      case 0:
1667                        return MISCREG_ID_ISAR0_EL1;
1668                      case 1:
1669                        return MISCREG_ID_ISAR1_EL1;
1670                      case 2:
1671                        return MISCREG_ID_ISAR2_EL1;
1672                      case 3:
1673                        return MISCREG_ID_ISAR3_EL1;
1674                      case 4:
1675                        return MISCREG_ID_ISAR4_EL1;
1676                      case 5:
1677                        return MISCREG_ID_ISAR5_EL1;
1678                    }
1679                    break;
1680                  case 3:
1681                    switch (op2) {
1682                      case 0:
1683                        return MISCREG_MVFR0_EL1;
1684                      case 1:
1685                        return MISCREG_MVFR1_EL1;
1686                      case 2:
1687                        return MISCREG_MVFR2_EL1;
1688                      case 3 ... 7:
1689                        return MISCREG_RAZ;
1690                    }
1691                    break;
1692                  case 4:
1693                    switch (op2) {
1694                      case 0:
1695                        return MISCREG_ID_AA64PFR0_EL1;
1696                      case 1:
1697                        return MISCREG_ID_AA64PFR1_EL1;
1698                      case 2 ... 7:
1699                        return MISCREG_RAZ;
1700                    }
1701                    break;
1702                  case 5:
1703                    switch (op2) {
1704                      case 0:
1705                        return MISCREG_ID_AA64DFR0_EL1;
1706                      case 1:
1707                        return MISCREG_ID_AA64DFR1_EL1;
1708                      case 4:
1709                        return MISCREG_ID_AA64AFR0_EL1;
1710                      case 5:
1711                        return MISCREG_ID_AA64AFR1_EL1;
1712                      case 2:
1713                      case 3:
1714                      case 6:
1715                      case 7:
1716                        return MISCREG_RAZ;
1717                    }
1718                    break;
1719                  case 6:
1720                    switch (op2) {
1721                      case 0:
1722                        return MISCREG_ID_AA64ISAR0_EL1;
1723                      case 1:
1724                        return MISCREG_ID_AA64ISAR1_EL1;
1725                      case 2 ... 7:
1726                        return MISCREG_RAZ;
1727                    }
1728                    break;
1729                  case 7:
1730                    switch (op2) {
1731                      case 0:
1732                        return MISCREG_ID_AA64MMFR0_EL1;
1733                      case 1:
1734                        return MISCREG_ID_AA64MMFR1_EL1;
1735                      case 2:
1736                        return MISCREG_ID_AA64MMFR2_EL1;
1737                      case 3 ... 7:
1738                        return MISCREG_RAZ;
1739                    }
1740                    break;
1741                }
1742                break;
1743              case 1:
1744                switch (crm) {
1745                  case 0:
1746                    switch (op2) {
1747                      case 0:
1748                        return MISCREG_CCSIDR_EL1;
1749                      case 1:
1750                        return MISCREG_CLIDR_EL1;
1751                      case 7:
1752                        return MISCREG_AIDR_EL1;
1753                    }
1754                    break;
1755                }
1756                break;
1757              case 2:
1758                switch (crm) {
1759                  case 0:
1760                    switch (op2) {
1761                      case 0:
1762                        return MISCREG_CSSELR_EL1;
1763                    }
1764                    break;
1765                }
1766                break;
1767              case 3:
1768                switch (crm) {
1769                  case 0:
1770                    switch (op2) {
1771                      case 1:
1772                        return MISCREG_CTR_EL0;
1773                      case 7:
1774                        return MISCREG_DCZID_EL0;
1775                    }
1776                    break;
1777                }
1778                break;
1779              case 4:
1780                switch (crm) {
1781                  case 0:
1782                    switch (op2) {
1783                      case 0:
1784                        return MISCREG_VPIDR_EL2;
1785                      case 5:
1786                        return MISCREG_VMPIDR_EL2;
1787                    }
1788                    break;
1789                }
1790                break;
1791            }
1792            break;
1793          case 1:
1794            switch (op1) {
1795              case 0:
1796                switch (crm) {
1797                  case 0:
1798                    switch (op2) {
1799                      case 0:
1800                        return MISCREG_SCTLR_EL1;
1801                      case 1:
1802                        return MISCREG_ACTLR_EL1;
1803                      case 2:
1804                        return MISCREG_CPACR_EL1;
1805                    }
1806                    break;
1807                }
1808                break;
1809              case 4:
1810                switch (crm) {
1811                  case 0:
1812                    switch (op2) {
1813                      case 0:
1814                        return MISCREG_SCTLR_EL2;
1815                      case 1:
1816                        return MISCREG_ACTLR_EL2;
1817                    }
1818                    break;
1819                  case 1:
1820                    switch (op2) {
1821                      case 0:
1822                        return MISCREG_HCR_EL2;
1823                      case 1:
1824                        return MISCREG_MDCR_EL2;
1825                      case 2:
1826                        return MISCREG_CPTR_EL2;
1827                      case 3:
1828                        return MISCREG_HSTR_EL2;
1829                      case 7:
1830                        return MISCREG_HACR_EL2;
1831                    }
1832                    break;
1833                }
1834                break;
1835              case 6:
1836                switch (crm) {
1837                  case 0:
1838                    switch (op2) {
1839                      case 0:
1840                        return MISCREG_SCTLR_EL3;
1841                      case 1:
1842                        return MISCREG_ACTLR_EL3;
1843                    }
1844                    break;
1845                  case 1:
1846                    switch (op2) {
1847                      case 0:
1848                        return MISCREG_SCR_EL3;
1849                      case 1:
1850                        return MISCREG_SDER32_EL3;
1851                      case 2:
1852                        return MISCREG_CPTR_EL3;
1853                    }
1854                    break;
1855                  case 3:
1856                    switch (op2) {
1857                      case 1:
1858                        return MISCREG_MDCR_EL3;
1859                    }
1860                    break;
1861                }
1862                break;
1863            }
1864            break;
1865          case 2:
1866            switch (op1) {
1867              case 0:
1868                switch (crm) {
1869                  case 0:
1870                    switch (op2) {
1871                      case 0:
1872                        return MISCREG_TTBR0_EL1;
1873                      case 1:
1874                        return MISCREG_TTBR1_EL1;
1875                      case 2:
1876                        return MISCREG_TCR_EL1;
1877                    }
1878                    break;
1879                }
1880                break;
1881              case 4:
1882                switch (crm) {
1883                  case 0:
1884                    switch (op2) {
1885                      case 0:
1886                        return MISCREG_TTBR0_EL2;
1887                      case 1:
1888                        return MISCREG_TTBR1_EL2;
1889                      case 2:
1890                        return MISCREG_TCR_EL2;
1891                    }
1892                    break;
1893                  case 1:
1894                    switch (op2) {
1895                      case 0:
1896                        return MISCREG_VTTBR_EL2;
1897                      case 2:
1898                        return MISCREG_VTCR_EL2;
1899                    }
1900                    break;
1901                }
1902                break;
1903              case 6:
1904                switch (crm) {
1905                  case 0:
1906                    switch (op2) {
1907                      case 0:
1908                        return MISCREG_TTBR0_EL3;
1909                      case 2:
1910                        return MISCREG_TCR_EL3;
1911                    }
1912                    break;
1913                }
1914                break;
1915            }
1916            break;
1917          case 3:
1918            switch (op1) {
1919              case 4:
1920                switch (crm) {
1921                  case 0:
1922                    switch (op2) {
1923                      case 0:
1924                        return MISCREG_DACR32_EL2;
1925                    }
1926                    break;
1927                }
1928                break;
1929            }
1930            break;
1931          case 4:
1932            switch (op1) {
1933              case 0:
1934                switch (crm) {
1935                  case 0:
1936                    switch (op2) {
1937                      case 0:
1938                        return MISCREG_SPSR_EL1;
1939                      case 1:
1940                        return MISCREG_ELR_EL1;
1941                    }
1942                    break;
1943                  case 1:
1944                    switch (op2) {
1945                      case 0:
1946                        return MISCREG_SP_EL0;
1947                    }
1948                    break;
1949                  case 2:
1950                    switch (op2) {
1951                      case 0:
1952                        return MISCREG_SPSEL;
1953                      case 2:
1954                        return MISCREG_CURRENTEL;
1955                    }
1956                    break;
1957                  case 6:
1958                    switch (op2) {
1959                      case 0:
1960                        return MISCREG_ICC_PMR_EL1;
1961                    }
1962                    break;
1963                }
1964                break;
1965              case 3:
1966                switch (crm) {
1967                  case 2:
1968                    switch (op2) {
1969                      case 0:
1970                        return MISCREG_NZCV;
1971                      case 1:
1972                        return MISCREG_DAIF;
1973                    }
1974                    break;
1975                  case 4:
1976                    switch (op2) {
1977                      case 0:
1978                        return MISCREG_FPCR;
1979                      case 1:
1980                        return MISCREG_FPSR;
1981                    }
1982                    break;
1983                  case 5:
1984                    switch (op2) {
1985                      case 0:
1986                        return MISCREG_DSPSR_EL0;
1987                      case 1:
1988                        return MISCREG_DLR_EL0;
1989                    }
1990                    break;
1991                }
1992                break;
1993              case 4:
1994                switch (crm) {
1995                  case 0:
1996                    switch (op2) {
1997                      case 0:
1998                        return MISCREG_SPSR_EL2;
1999                      case 1:
2000                        return MISCREG_ELR_EL2;
2001                    }
2002                    break;
2003                  case 1:
2004                    switch (op2) {
2005                      case 0:
2006                        return MISCREG_SP_EL1;
2007                    }
2008                    break;
2009                  case 3:
2010                    switch (op2) {
2011                      case 0:
2012                        return MISCREG_SPSR_IRQ_AA64;
2013                      case 1:
2014                        return MISCREG_SPSR_ABT_AA64;
2015                      case 2:
2016                        return MISCREG_SPSR_UND_AA64;
2017                      case 3:
2018                        return MISCREG_SPSR_FIQ_AA64;
2019                    }
2020                    break;
2021                }
2022                break;
2023              case 6:
2024                switch (crm) {
2025                  case 0:
2026                    switch (op2) {
2027                      case 0:
2028                        return MISCREG_SPSR_EL3;
2029                      case 1:
2030                        return MISCREG_ELR_EL3;
2031                    }
2032                    break;
2033                  case 1:
2034                    switch (op2) {
2035                      case 0:
2036                        return MISCREG_SP_EL2;
2037                    }
2038                    break;
2039                }
2040                break;
2041            }
2042            break;
2043          case 5:
2044            switch (op1) {
2045              case 0:
2046                switch (crm) {
2047                  case 1:
2048                    switch (op2) {
2049                      case 0:
2050                        return MISCREG_AFSR0_EL1;
2051                      case 1:
2052                        return MISCREG_AFSR1_EL1;
2053                    }
2054                    break;
2055                  case 2:
2056                    switch (op2) {
2057                      case 0:
2058                        return MISCREG_ESR_EL1;
2059                    }
2060                    break;
2061                  case 3:
2062                    switch (op2) {
2063                      case 0:
2064                        return MISCREG_ERRIDR_EL1;
2065                      case 1:
2066                        return MISCREG_ERRSELR_EL1;
2067                    }
2068                    break;
2069                  case 4:
2070                    switch (op2) {
2071                      case 0:
2072                        return MISCREG_ERXFR_EL1;
2073                      case 1:
2074                        return MISCREG_ERXCTLR_EL1;
2075                      case 2:
2076                        return MISCREG_ERXSTATUS_EL1;
2077                      case 3:
2078                        return MISCREG_ERXADDR_EL1;
2079                    }
2080                    break;
2081                  case 5:
2082                    switch (op2) {
2083                      case 0:
2084                        return MISCREG_ERXMISC0_EL1;
2085                      case 1:
2086                        return MISCREG_ERXMISC1_EL1;
2087                    }
2088                    break;
2089                }
2090                break;
2091              case 4:
2092                switch (crm) {
2093                  case 0:
2094                    switch (op2) {
2095                      case 1:
2096                        return MISCREG_IFSR32_EL2;
2097                    }
2098                    break;
2099                  case 1:
2100                    switch (op2) {
2101                      case 0:
2102                        return MISCREG_AFSR0_EL2;
2103                      case 1:
2104                        return MISCREG_AFSR1_EL2;
2105                    }
2106                    break;
2107                  case 2:
2108                    switch (op2) {
2109                      case 0:
2110                        return MISCREG_ESR_EL2;
2111                      case 3:
2112                        return MISCREG_VSESR_EL2;
2113                    }
2114                    break;
2115                  case 3:
2116                    switch (op2) {
2117                      case 0:
2118                        return MISCREG_FPEXC32_EL2;
2119                    }
2120                    break;
2121                }
2122                break;
2123              case 6:
2124                switch (crm) {
2125                  case 1:
2126                    switch (op2) {
2127                      case 0:
2128                        return MISCREG_AFSR0_EL3;
2129                      case 1:
2130                        return MISCREG_AFSR1_EL3;
2131                    }
2132                    break;
2133                  case 2:
2134                    switch (op2) {
2135                      case 0:
2136                        return MISCREG_ESR_EL3;
2137                    }
2138                    break;
2139                }
2140                break;
2141            }
2142            break;
2143          case 6:
2144            switch (op1) {
2145              case 0:
2146                switch (crm) {
2147                  case 0:
2148                    switch (op2) {
2149                      case 0:
2150                        return MISCREG_FAR_EL1;
2151                    }
2152                    break;
2153                }
2154                break;
2155              case 4:
2156                switch (crm) {
2157                  case 0:
2158                    switch (op2) {
2159                      case 0:
2160                        return MISCREG_FAR_EL2;
2161                      case 4:
2162                        return MISCREG_HPFAR_EL2;
2163                    }
2164                    break;
2165                }
2166                break;
2167              case 6:
2168                switch (crm) {
2169                  case 0:
2170                    switch (op2) {
2171                      case 0:
2172                        return MISCREG_FAR_EL3;
2173                    }
2174                    break;
2175                }
2176                break;
2177            }
2178            break;
2179          case 7:
2180            switch (op1) {
2181              case 0:
2182                switch (crm) {
2183                  case 4:
2184                    switch (op2) {
2185                      case 0:
2186                        return MISCREG_PAR_EL1;
2187                    }
2188                    break;
2189                }
2190                break;
2191            }
2192            break;
2193          case 9:
2194            switch (op1) {
2195              case 0:
2196                switch (crm) {
2197                  case 14:
2198                    switch (op2) {
2199                      case 1:
2200                        return MISCREG_PMINTENSET_EL1;
2201                      case 2:
2202                        return MISCREG_PMINTENCLR_EL1;
2203                    }
2204                    break;
2205                }
2206                break;
2207              case 3:
2208                switch (crm) {
2209                  case 12:
2210                    switch (op2) {
2211                      case 0:
2212                        return MISCREG_PMCR_EL0;
2213                      case 1:
2214                        return MISCREG_PMCNTENSET_EL0;
2215                      case 2:
2216                        return MISCREG_PMCNTENCLR_EL0;
2217                      case 3:
2218                        return MISCREG_PMOVSCLR_EL0;
2219                      case 4:
2220                        return MISCREG_PMSWINC_EL0;
2221                      case 5:
2222                        return MISCREG_PMSELR_EL0;
2223                      case 6:
2224                        return MISCREG_PMCEID0_EL0;
2225                      case 7:
2226                        return MISCREG_PMCEID1_EL0;
2227                    }
2228                    break;
2229                  case 13:
2230                    switch (op2) {
2231                      case 0:
2232                        return MISCREG_PMCCNTR_EL0;
2233                      case 1:
2234                        return MISCREG_PMXEVTYPER_EL0;
2235                      case 2:
2236                        return MISCREG_PMXEVCNTR_EL0;
2237                    }
2238                    break;
2239                  case 14:
2240                    switch (op2) {
2241                      case 0:
2242                        return MISCREG_PMUSERENR_EL0;
2243                      case 3:
2244                        return MISCREG_PMOVSSET_EL0;
2245                    }
2246                    break;
2247                }
2248                break;
2249            }
2250            break;
2251          case 10:
2252            switch (op1) {
2253              case 0:
2254                switch (crm) {
2255                  case 2:
2256                    switch (op2) {
2257                      case 0:
2258                        return MISCREG_MAIR_EL1;
2259                    }
2260                    break;
2261                  case 3:
2262                    switch (op2) {
2263                      case 0:
2264                        return MISCREG_AMAIR_EL1;
2265                    }
2266                    break;
2267                }
2268                break;
2269              case 4:
2270                switch (crm) {
2271                  case 2:
2272                    switch (op2) {
2273                      case 0:
2274                        return MISCREG_MAIR_EL2;
2275                    }
2276                    break;
2277                  case 3:
2278                    switch (op2) {
2279                      case 0:
2280                        return MISCREG_AMAIR_EL2;
2281                    }
2282                    break;
2283                }
2284                break;
2285              case 6:
2286                switch (crm) {
2287                  case 2:
2288                    switch (op2) {
2289                      case 0:
2290                        return MISCREG_MAIR_EL3;
2291                    }
2292                    break;
2293                  case 3:
2294                    switch (op2) {
2295                      case 0:
2296                        return MISCREG_AMAIR_EL3;
2297                    }
2298                    break;
2299                }
2300                break;
2301            }
2302            break;
2303          case 11:
2304            switch (op1) {
2305              case 1:
2306                switch (crm) {
2307                  case 0:
2308                    switch (op2) {
2309                      case 2:
2310                        return MISCREG_L2CTLR_EL1;
2311                      case 3:
2312                        return MISCREG_L2ECTLR_EL1;
2313                    }
2314                    break;
2315                }
2316                M5_FALLTHROUGH;
2317              default:
2318                // S3_<op1>_11_<Cm>_<op2>
2319                return MISCREG_IMPDEF_UNIMPL;
2320            }
2321            M5_UNREACHABLE;
2322          case 12:
2323            switch (op1) {
2324              case 0:
2325                switch (crm) {
2326                  case 0:
2327                    switch (op2) {
2328                      case 0:
2329                        return MISCREG_VBAR_EL1;
2330                      case 1:
2331                        return MISCREG_RVBAR_EL1;
2332                    }
2333                    break;
2334                  case 1:
2335                    switch (op2) {
2336                      case 0:
2337                        return MISCREG_ISR_EL1;
2338                      case 1:
2339                        return MISCREG_DISR_EL1;
2340                    }
2341                    break;
2342                  case 8:
2343                    switch (op2) {
2344                      case 0:
2345                        return MISCREG_ICC_IAR0_EL1;
2346                      case 1:
2347                        return MISCREG_ICC_EOIR0_EL1;
2348                      case 2:
2349                        return MISCREG_ICC_HPPIR0_EL1;
2350                      case 3:
2351                        return MISCREG_ICC_BPR0_EL1;
2352                      case 4:
2353                        return MISCREG_ICC_AP0R0_EL1;
2354                      case 5:
2355                        return MISCREG_ICC_AP0R1_EL1;
2356                      case 6:
2357                        return MISCREG_ICC_AP0R2_EL1;
2358                      case 7:
2359                        return MISCREG_ICC_AP0R3_EL1;
2360                    }
2361                    break;
2362                  case 9:
2363                    switch (op2) {
2364                      case 0:
2365                        return MISCREG_ICC_AP1R0_EL1;
2366                      case 1:
2367                        return MISCREG_ICC_AP1R1_EL1;
2368                      case 2:
2369                        return MISCREG_ICC_AP1R2_EL1;
2370                      case 3:
2371                        return MISCREG_ICC_AP1R3_EL1;
2372                    }
2373                    break;
2374                  case 11:
2375                    switch (op2) {
2376                      case 1:
2377                        return MISCREG_ICC_DIR_EL1;
2378                      case 3:
2379                        return MISCREG_ICC_RPR_EL1;
2380                      case 5:
2381                        return MISCREG_ICC_SGI1R_EL1;
2382                      case 6:
2383                        return MISCREG_ICC_ASGI1R_EL1;
2384                      case 7:
2385                        return MISCREG_ICC_SGI0R_EL1;
2386                    }
2387                    break;
2388                  case 12:
2389                    switch (op2) {
2390                      case 0:
2391                        return MISCREG_ICC_IAR1_EL1;
2392                      case 1:
2393                        return MISCREG_ICC_EOIR1_EL1;
2394                      case 2:
2395                        return MISCREG_ICC_HPPIR1_EL1;
2396                      case 3:
2397                        return MISCREG_ICC_BPR1_EL1;
2398                      case 4:
2399                        return MISCREG_ICC_CTLR_EL1;
2400                      case 5:
2401                        return MISCREG_ICC_SRE_EL1;
2402                      case 6:
2403                        return MISCREG_ICC_IGRPEN0_EL1;
2404                      case 7:
2405                        return MISCREG_ICC_IGRPEN1_EL1;
2406                    }
2407                    break;
2408                }
2409                break;
2410              case 4:
2411                switch (crm) {
2412                  case 0:
2413                    switch (op2) {
2414                      case 0:
2415                        return MISCREG_VBAR_EL2;
2416                      case 1:
2417                        return MISCREG_RVBAR_EL2;
2418                    }
2419                    break;
2420                  case 1:
2421                    switch (op2) {
2422                      case 1:
2423                        return MISCREG_VDISR_EL2;
2424                    }
2425                    break;
2426                  case 8:
2427                    switch (op2) {
2428                      case 0:
2429                        return MISCREG_ICH_AP0R0_EL2;
2430                      case 1:
2431                        return MISCREG_ICH_AP0R1_EL2;
2432                      case 2:
2433                        return MISCREG_ICH_AP0R2_EL2;
2434                      case 3:
2435                        return MISCREG_ICH_AP0R3_EL2;
2436                    }
2437                    break;
2438                  case 9:
2439                    switch (op2) {
2440                      case 0:
2441                        return MISCREG_ICH_AP1R0_EL2;
2442                      case 1:
2443                        return MISCREG_ICH_AP1R1_EL2;
2444                      case 2:
2445                        return MISCREG_ICH_AP1R2_EL2;
2446                      case 3:
2447                        return MISCREG_ICH_AP1R3_EL2;
2448                      case 5:
2449                        return MISCREG_ICC_SRE_EL2;
2450                    }
2451                    break;
2452                  case 11:
2453                    switch (op2) {
2454                      case 0:
2455                        return MISCREG_ICH_HCR_EL2;
2456                      case 1:
2457                        return MISCREG_ICH_VTR_EL2;
2458                      case 2:
2459                        return MISCREG_ICH_MISR_EL2;
2460                      case 3:
2461                        return MISCREG_ICH_EISR_EL2;
2462                      case 5:
2463                        return MISCREG_ICH_ELRSR_EL2;
2464                      case 7:
2465                        return MISCREG_ICH_VMCR_EL2;
2466                    }
2467                    break;
2468                  case 12:
2469                    switch (op2) {
2470                      case 0:
2471                        return MISCREG_ICH_LR0_EL2;
2472                      case 1:
2473                        return MISCREG_ICH_LR1_EL2;
2474                      case 2:
2475                        return MISCREG_ICH_LR2_EL2;
2476                      case 3:
2477                        return MISCREG_ICH_LR3_EL2;
2478                      case 4:
2479                        return MISCREG_ICH_LR4_EL2;
2480                      case 5:
2481                        return MISCREG_ICH_LR5_EL2;
2482                      case 6:
2483                        return MISCREG_ICH_LR6_EL2;
2484                      case 7:
2485                        return MISCREG_ICH_LR7_EL2;
2486                    }
2487                    break;
2488                  case 13:
2489                    switch (op2) {
2490                      case 0:
2491                        return MISCREG_ICH_LR8_EL2;
2492                      case 1:
2493                        return MISCREG_ICH_LR9_EL2;
2494                      case 2:
2495                        return MISCREG_ICH_LR10_EL2;
2496                      case 3:
2497                        return MISCREG_ICH_LR11_EL2;
2498                      case 4:
2499                        return MISCREG_ICH_LR12_EL2;
2500                      case 5:
2501                        return MISCREG_ICH_LR13_EL2;
2502                      case 6:
2503                        return MISCREG_ICH_LR14_EL2;
2504                      case 7:
2505                        return MISCREG_ICH_LR15_EL2;
2506                    }
2507                    break;
2508                }
2509                break;
2510              case 6:
2511                switch (crm) {
2512                  case 0:
2513                    switch (op2) {
2514                      case 0:
2515                        return MISCREG_VBAR_EL3;
2516                      case 1:
2517                        return MISCREG_RVBAR_EL3;
2518                      case 2:
2519                        return MISCREG_RMR_EL3;
2520                    }
2521                    break;
2522                  case 12:
2523                    switch (op2) {
2524                      case 4:
2525                        return MISCREG_ICC_CTLR_EL3;
2526                      case 5:
2527                        return MISCREG_ICC_SRE_EL3;
2528                      case 7:
2529                        return MISCREG_ICC_IGRPEN1_EL3;
2530                    }
2531                    break;
2532                }
2533                break;
2534            }
2535            break;
2536          case 13:
2537            switch (op1) {
2538              case 0:
2539                switch (crm) {
2540                  case 0:
2541                    switch (op2) {
2542                      case 1:
2543                        return MISCREG_CONTEXTIDR_EL1;
2544                      case 4:
2545                        return MISCREG_TPIDR_EL1;
2546                    }
2547                    break;
2548                }
2549                break;
2550              case 3:
2551                switch (crm) {
2552                  case 0:
2553                    switch (op2) {
2554                      case 2:
2555                        return MISCREG_TPIDR_EL0;
2556                      case 3:
2557                        return MISCREG_TPIDRRO_EL0;
2558                    }
2559                    break;
2560                }
2561                break;
2562              case 4:
2563                switch (crm) {
2564                  case 0:
2565                    switch (op2) {
2566                      case 1:
2567                        return MISCREG_CONTEXTIDR_EL2;
2568                      case 2:
2569                        return MISCREG_TPIDR_EL2;
2570                    }
2571                    break;
2572                }
2573                break;
2574              case 6:
2575                switch (crm) {
2576                  case 0:
2577                    switch (op2) {
2578                      case 2:
2579                        return MISCREG_TPIDR_EL3;
2580                    }
2581                    break;
2582                }
2583                break;
2584            }
2585            break;
2586          case 14:
2587            switch (op1) {
2588              case 0:
2589                switch (crm) {
2590                  case 1:
2591                    switch (op2) {
2592                      case 0:
2593                        return MISCREG_CNTKCTL_EL1;
2594                    }
2595                    break;
2596                }
2597                break;
2598              case 3:
2599                switch (crm) {
2600                  case 0:
2601                    switch (op2) {
2602                      case 0:
2603                        return MISCREG_CNTFRQ_EL0;
2604                      case 1:
2605                        return MISCREG_CNTPCT_EL0;
2606                      case 2:
2607                        return MISCREG_CNTVCT_EL0;
2608                    }
2609                    break;
2610                  case 2:
2611                    switch (op2) {
2612                      case 0:
2613                        return MISCREG_CNTP_TVAL_EL0;
2614                      case 1:
2615                        return MISCREG_CNTP_CTL_EL0;
2616                      case 2:
2617                        return MISCREG_CNTP_CVAL_EL0;
2618                    }
2619                    break;
2620                  case 3:
2621                    switch (op2) {
2622                      case 0:
2623                        return MISCREG_CNTV_TVAL_EL0;
2624                      case 1:
2625                        return MISCREG_CNTV_CTL_EL0;
2626                      case 2:
2627                        return MISCREG_CNTV_CVAL_EL0;
2628                    }
2629                    break;
2630                  case 8:
2631                    switch (op2) {
2632                      case 0:
2633                        return MISCREG_PMEVCNTR0_EL0;
2634                      case 1:
2635                        return MISCREG_PMEVCNTR1_EL0;
2636                      case 2:
2637                        return MISCREG_PMEVCNTR2_EL0;
2638                      case 3:
2639                        return MISCREG_PMEVCNTR3_EL0;
2640                      case 4:
2641                        return MISCREG_PMEVCNTR4_EL0;
2642                      case 5:
2643                        return MISCREG_PMEVCNTR5_EL0;
2644                    }
2645                    break;
2646                  case 12:
2647                    switch (op2) {
2648                      case 0:
2649                        return MISCREG_PMEVTYPER0_EL0;
2650                      case 1:
2651                        return MISCREG_PMEVTYPER1_EL0;
2652                      case 2:
2653                        return MISCREG_PMEVTYPER2_EL0;
2654                      case 3:
2655                        return MISCREG_PMEVTYPER3_EL0;
2656                      case 4:
2657                        return MISCREG_PMEVTYPER4_EL0;
2658                      case 5:
2659                        return MISCREG_PMEVTYPER5_EL0;
2660                    }
2661                    break;
2662                  case 15:
2663                    switch (op2) {
2664                      case 7:
2665                        return MISCREG_PMCCFILTR_EL0;
2666                    }
2667                }
2668                break;
2669              case 4:
2670                switch (crm) {
2671                  case 0:
2672                    switch (op2) {
2673                      case 3:
2674                        return MISCREG_CNTVOFF_EL2;
2675                    }
2676                    break;
2677                  case 1:
2678                    switch (op2) {
2679                      case 0:
2680                        return MISCREG_CNTHCTL_EL2;
2681                    }
2682                    break;
2683                  case 2:
2684                    switch (op2) {
2685                      case 0:
2686                        return MISCREG_CNTHP_TVAL_EL2;
2687                      case 1:
2688                        return MISCREG_CNTHP_CTL_EL2;
2689                      case 2:
2690                        return MISCREG_CNTHP_CVAL_EL2;
2691                    }
2692                    break;
2693                  case 3:
2694                    switch (op2) {
2695                      case 0:
2696                        return MISCREG_CNTHV_TVAL_EL2;
2697                      case 1:
2698                        return MISCREG_CNTHV_CTL_EL2;
2699                      case 2:
2700                        return MISCREG_CNTHV_CVAL_EL2;
2701                    }
2702                    break;
2703                }
2704                break;
2705              case 7:
2706                switch (crm) {
2707                  case 2:
2708                    switch (op2) {
2709                      case 0:
2710                        return MISCREG_CNTPS_TVAL_EL1;
2711                      case 1:
2712                        return MISCREG_CNTPS_CTL_EL1;
2713                      case 2:
2714                        return MISCREG_CNTPS_CVAL_EL1;
2715                    }
2716                    break;
2717                }
2718                break;
2719            }
2720            break;
2721          case 15:
2722            switch (op1) {
2723              case 0:
2724                switch (crm) {
2725                  case 0:
2726                    switch (op2) {
2727                      case 0:
2728                        return MISCREG_IL1DATA0_EL1;
2729                      case 1:
2730                        return MISCREG_IL1DATA1_EL1;
2731                      case 2:
2732                        return MISCREG_IL1DATA2_EL1;
2733                      case 3:
2734                        return MISCREG_IL1DATA3_EL1;
2735                    }
2736                    break;
2737                  case 1:
2738                    switch (op2) {
2739                      case 0:
2740                        return MISCREG_DL1DATA0_EL1;
2741                      case 1:
2742                        return MISCREG_DL1DATA1_EL1;
2743                      case 2:
2744                        return MISCREG_DL1DATA2_EL1;
2745                      case 3:
2746                        return MISCREG_DL1DATA3_EL1;
2747                      case 4:
2748                        return MISCREG_DL1DATA4_EL1;
2749                    }
2750                    break;
2751                }
2752                break;
2753              case 1:
2754                switch (crm) {
2755                  case 0:
2756                    switch (op2) {
2757                      case 0:
2758                        return MISCREG_L2ACTLR_EL1;
2759                    }
2760                    break;
2761                  case 2:
2762                    switch (op2) {
2763                      case 0:
2764                        return MISCREG_CPUACTLR_EL1;
2765                      case 1:
2766                        return MISCREG_CPUECTLR_EL1;
2767                      case 2:
2768                        return MISCREG_CPUMERRSR_EL1;
2769                      case 3:
2770                        return MISCREG_L2MERRSR_EL1;
2771                    }
2772                    break;
2773                  case 3:
2774                    switch (op2) {
2775                      case 0:
2776                        return MISCREG_CBAR_EL1;
2777
2778                    }
2779                    break;
2780                }
2781                break;
2782            }
2783            // S3_<op1>_15_<Cm>_<op2>
2784            return MISCREG_IMPDEF_UNIMPL;
2785        }
2786        break;
2787    }
2788
2789    return MISCREG_UNKNOWN;
2790}
2791
2792bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2793
2794void
2795ISA::initializeMiscRegMetadata()
2796{
2797    // the MiscReg metadata tables are shared across all instances of the
2798    // ISA object, so there's no need to initialize them multiple times.
2799    static bool completed = false;
2800    if (completed)
2801        return;
2802
2803    // This boolean variable specifies if the system is running in aarch32 at
2804    // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2805    // is running in aarch64 (aarch32EL3 = false)
2806    bool aarch32EL3 = haveSecurity && !highestELIs64;
2807
2808    // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2809    // unsupported
2810    bool SPAN = false;
2811
2812    // Implicit error synchronization event enable (Arm 8.2+), unsupported
2813    bool IESB = false;
2814
2815    // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2816    // unsupported
2817    bool LSMAOE = false;
2818
2819    // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2820    bool nTLSMD = false;
2821
2822    // Pointer authentication (Arm 8.3+), unsupported
2823    bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2824    bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2825    bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2826    bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2827
2828    /**
2829     * Some registers alias with others, and therefore need to be translated.
2830     * When two mapping registers are given, they are the 32b lower and
2831     * upper halves, respectively, of the 64b register being mapped.
2832     * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2833     *
2834     * NAM = "not architecturally mandated",
2835     * from ARM DDI 0487A.i, template text
2836     * "AArch64 System register ___ can be mapped to
2837     *  AArch32 System register ___, but this is not
2838     *  architecturally mandated."
2839     */
2840
2841    InitReg(MISCREG_CPSR)
2842      .allPrivileges();
2843    InitReg(MISCREG_SPSR)
2844      .allPrivileges();
2845    InitReg(MISCREG_SPSR_FIQ)
2846      .allPrivileges();
2847    InitReg(MISCREG_SPSR_IRQ)
2848      .allPrivileges();
2849    InitReg(MISCREG_SPSR_SVC)
2850      .allPrivileges();
2851    InitReg(MISCREG_SPSR_MON)
2852      .allPrivileges();
2853    InitReg(MISCREG_SPSR_ABT)
2854      .allPrivileges();
2855    InitReg(MISCREG_SPSR_HYP)
2856      .allPrivileges();
2857    InitReg(MISCREG_SPSR_UND)
2858      .allPrivileges();
2859    InitReg(MISCREG_ELR_HYP)
2860      .allPrivileges();
2861    InitReg(MISCREG_FPSID)
2862      .allPrivileges();
2863    InitReg(MISCREG_FPSCR)
2864      .allPrivileges();
2865    InitReg(MISCREG_MVFR1)
2866      .allPrivileges();
2867    InitReg(MISCREG_MVFR0)
2868      .allPrivileges();
2869    InitReg(MISCREG_FPEXC)
2870      .allPrivileges();
2871
2872    // Helper registers
2873    InitReg(MISCREG_CPSR_MODE)
2874      .allPrivileges();
2875    InitReg(MISCREG_CPSR_Q)
2876      .allPrivileges();
2877    InitReg(MISCREG_FPSCR_EXC)
2878      .allPrivileges();
2879    InitReg(MISCREG_FPSCR_QC)
2880      .allPrivileges();
2881    InitReg(MISCREG_LOCKADDR)
2882      .allPrivileges();
2883    InitReg(MISCREG_LOCKFLAG)
2884      .allPrivileges();
2885    InitReg(MISCREG_PRRR_MAIR0)
2886      .mutex()
2887      .banked();
2888    InitReg(MISCREG_PRRR_MAIR0_NS)
2889      .mutex()
2890      .privSecure(!aarch32EL3)
2891      .bankedChild();
2892    InitReg(MISCREG_PRRR_MAIR0_S)
2893      .mutex()
2894      .bankedChild();
2895    InitReg(MISCREG_NMRR_MAIR1)
2896      .mutex()
2897      .banked();
2898    InitReg(MISCREG_NMRR_MAIR1_NS)
2899      .mutex()
2900      .privSecure(!aarch32EL3)
2901      .bankedChild();
2902    InitReg(MISCREG_NMRR_MAIR1_S)
2903      .mutex()
2904      .bankedChild();
2905    InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2906      .mutex();
2907    InitReg(MISCREG_SCTLR_RST)
2908      .allPrivileges();
2909    InitReg(MISCREG_SEV_MAILBOX)
2910      .allPrivileges();
2911
2912    // AArch32 CP14 registers
2913    InitReg(MISCREG_DBGDIDR)
2914      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2915    InitReg(MISCREG_DBGDSCRint)
2916      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2917    InitReg(MISCREG_DBGDCCINT)
2918      .unimplemented()
2919      .allPrivileges();
2920    InitReg(MISCREG_DBGDTRTXint)
2921      .unimplemented()
2922      .allPrivileges();
2923    InitReg(MISCREG_DBGDTRRXint)
2924      .unimplemented()
2925      .allPrivileges();
2926    InitReg(MISCREG_DBGWFAR)
2927      .unimplemented()
2928      .allPrivileges();
2929    InitReg(MISCREG_DBGVCR)
2930      .unimplemented()
2931      .allPrivileges();
2932    InitReg(MISCREG_DBGDTRRXext)
2933      .unimplemented()
2934      .allPrivileges();
2935    InitReg(MISCREG_DBGDSCRext)
2936      .unimplemented()
2937      .warnNotFail()
2938      .allPrivileges();
2939    InitReg(MISCREG_DBGDTRTXext)
2940      .unimplemented()
2941      .allPrivileges();
2942    InitReg(MISCREG_DBGOSECCR)
2943      .unimplemented()
2944      .allPrivileges();
2945    InitReg(MISCREG_DBGBVR0)
2946      .unimplemented()
2947      .allPrivileges();
2948    InitReg(MISCREG_DBGBVR1)
2949      .unimplemented()
2950      .allPrivileges();
2951    InitReg(MISCREG_DBGBVR2)
2952      .unimplemented()
2953      .allPrivileges();
2954    InitReg(MISCREG_DBGBVR3)
2955      .unimplemented()
2956      .allPrivileges();
2957    InitReg(MISCREG_DBGBVR4)
2958      .unimplemented()
2959      .allPrivileges();
2960    InitReg(MISCREG_DBGBVR5)
2961      .unimplemented()
2962      .allPrivileges();
2963    InitReg(MISCREG_DBGBCR0)
2964      .unimplemented()
2965      .allPrivileges();
2966    InitReg(MISCREG_DBGBCR1)
2967      .unimplemented()
2968      .allPrivileges();
2969    InitReg(MISCREG_DBGBCR2)
2970      .unimplemented()
2971      .allPrivileges();
2972    InitReg(MISCREG_DBGBCR3)
2973      .unimplemented()
2974      .allPrivileges();
2975    InitReg(MISCREG_DBGBCR4)
2976      .unimplemented()
2977      .allPrivileges();
2978    InitReg(MISCREG_DBGBCR5)
2979      .unimplemented()
2980      .allPrivileges();
2981    InitReg(MISCREG_DBGWVR0)
2982      .unimplemented()
2983      .allPrivileges();
2984    InitReg(MISCREG_DBGWVR1)
2985      .unimplemented()
2986      .allPrivileges();
2987    InitReg(MISCREG_DBGWVR2)
2988      .unimplemented()
2989      .allPrivileges();
2990    InitReg(MISCREG_DBGWVR3)
2991      .unimplemented()
2992      .allPrivileges();
2993    InitReg(MISCREG_DBGWCR0)
2994      .unimplemented()
2995      .allPrivileges();
2996    InitReg(MISCREG_DBGWCR1)
2997      .unimplemented()
2998      .allPrivileges();
2999    InitReg(MISCREG_DBGWCR2)
3000      .unimplemented()
3001      .allPrivileges();
3002    InitReg(MISCREG_DBGWCR3)
3003      .unimplemented()
3004      .allPrivileges();
3005    InitReg(MISCREG_DBGDRAR)
3006      .unimplemented()
3007      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3008    InitReg(MISCREG_DBGBXVR4)
3009      .unimplemented()
3010      .allPrivileges();
3011    InitReg(MISCREG_DBGBXVR5)
3012      .unimplemented()
3013      .allPrivileges();
3014    InitReg(MISCREG_DBGOSLAR)
3015      .unimplemented()
3016      .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3017    InitReg(MISCREG_DBGOSLSR)
3018      .unimplemented()
3019      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3020    InitReg(MISCREG_DBGOSDLR)
3021      .unimplemented()
3022      .allPrivileges();
3023    InitReg(MISCREG_DBGPRCR)
3024      .unimplemented()
3025      .allPrivileges();
3026    InitReg(MISCREG_DBGDSAR)
3027      .unimplemented()
3028      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3029    InitReg(MISCREG_DBGCLAIMSET)
3030      .unimplemented()
3031      .allPrivileges();
3032    InitReg(MISCREG_DBGCLAIMCLR)
3033      .unimplemented()
3034      .allPrivileges();
3035    InitReg(MISCREG_DBGAUTHSTATUS)
3036      .unimplemented()
3037      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3038    InitReg(MISCREG_DBGDEVID2)
3039      .unimplemented()
3040      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3041    InitReg(MISCREG_DBGDEVID1)
3042      .unimplemented()
3043      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3044    InitReg(MISCREG_DBGDEVID0)
3045      .unimplemented()
3046      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3047    InitReg(MISCREG_TEECR)
3048      .unimplemented()
3049      .allPrivileges();
3050    InitReg(MISCREG_JIDR)
3051      .allPrivileges();
3052    InitReg(MISCREG_TEEHBR)
3053      .allPrivileges();
3054    InitReg(MISCREG_JOSCR)
3055      .allPrivileges();
3056    InitReg(MISCREG_JMCR)
3057      .allPrivileges();
3058
3059    // AArch32 CP15 registers
3060    InitReg(MISCREG_MIDR)
3061      .allPrivileges().exceptUserMode().writes(0);
3062    InitReg(MISCREG_CTR)
3063      .allPrivileges().exceptUserMode().writes(0);
3064    InitReg(MISCREG_TCMTR)
3065      .allPrivileges().exceptUserMode().writes(0);
3066    InitReg(MISCREG_TLBTR)
3067      .allPrivileges().exceptUserMode().writes(0);
3068    InitReg(MISCREG_MPIDR)
3069      .allPrivileges().exceptUserMode().writes(0);
3070    InitReg(MISCREG_REVIDR)
3071      .unimplemented()
3072      .warnNotFail()
3073      .allPrivileges().exceptUserMode().writes(0);
3074    InitReg(MISCREG_ID_PFR0)
3075      .allPrivileges().exceptUserMode().writes(0);
3076    InitReg(MISCREG_ID_PFR1)
3077      .allPrivileges().exceptUserMode().writes(0);
3078    InitReg(MISCREG_ID_DFR0)
3079      .allPrivileges().exceptUserMode().writes(0);
3080    InitReg(MISCREG_ID_AFR0)
3081      .allPrivileges().exceptUserMode().writes(0);
3082    InitReg(MISCREG_ID_MMFR0)
3083      .allPrivileges().exceptUserMode().writes(0);
3084    InitReg(MISCREG_ID_MMFR1)
3085      .allPrivileges().exceptUserMode().writes(0);
3086    InitReg(MISCREG_ID_MMFR2)
3087      .allPrivileges().exceptUserMode().writes(0);
3088    InitReg(MISCREG_ID_MMFR3)
3089      .allPrivileges().exceptUserMode().writes(0);
3090    InitReg(MISCREG_ID_ISAR0)
3091      .allPrivileges().exceptUserMode().writes(0);
3092    InitReg(MISCREG_ID_ISAR1)
3093      .allPrivileges().exceptUserMode().writes(0);
3094    InitReg(MISCREG_ID_ISAR2)
3095      .allPrivileges().exceptUserMode().writes(0);
3096    InitReg(MISCREG_ID_ISAR3)
3097      .allPrivileges().exceptUserMode().writes(0);
3098    InitReg(MISCREG_ID_ISAR4)
3099      .allPrivileges().exceptUserMode().writes(0);
3100    InitReg(MISCREG_ID_ISAR5)
3101      .allPrivileges().exceptUserMode().writes(0);
3102    InitReg(MISCREG_CCSIDR)
3103      .allPrivileges().exceptUserMode().writes(0);
3104    InitReg(MISCREG_CLIDR)
3105      .allPrivileges().exceptUserMode().writes(0);
3106    InitReg(MISCREG_AIDR)
3107      .allPrivileges().exceptUserMode().writes(0);
3108    InitReg(MISCREG_CSSELR)
3109      .banked();
3110    InitReg(MISCREG_CSSELR_NS)
3111      .bankedChild()
3112      .privSecure(!aarch32EL3)
3113      .nonSecure().exceptUserMode();
3114    InitReg(MISCREG_CSSELR_S)
3115      .bankedChild()
3116      .secure().exceptUserMode();
3117    InitReg(MISCREG_VPIDR)
3118      .hyp().monNonSecure();
3119    InitReg(MISCREG_VMPIDR)
3120      .hyp().monNonSecure();
3121    InitReg(MISCREG_SCTLR)
3122      .banked()
3123      // readMiscRegNoEffect() uses this metadata
3124      // despite using children (below) as backing store
3125      .res0(0x8d22c600)
3126      .res1(0x00400800 | (SPAN   ? 0 : 0x800000)
3127                       | (LSMAOE ? 0 :     0x10)
3128                       | (nTLSMD ? 0 :      0x8));
3129    InitReg(MISCREG_SCTLR_NS)
3130      .bankedChild()
3131      .privSecure(!aarch32EL3)
3132      .nonSecure().exceptUserMode();
3133    InitReg(MISCREG_SCTLR_S)
3134      .bankedChild()
3135      .secure().exceptUserMode();
3136    InitReg(MISCREG_ACTLR)
3137      .banked();
3138    InitReg(MISCREG_ACTLR_NS)
3139      .bankedChild()
3140      .privSecure(!aarch32EL3)
3141      .nonSecure().exceptUserMode();
3142    InitReg(MISCREG_ACTLR_S)
3143      .bankedChild()
3144      .secure().exceptUserMode();
3145    InitReg(MISCREG_CPACR)
3146      .allPrivileges().exceptUserMode();
3147    InitReg(MISCREG_SCR)
3148      .mon().secure().exceptUserMode()
3149      .res0(0xff40)  // [31:16], [6]
3150      .res1(0x0030); // [5:4]
3151    InitReg(MISCREG_SDER)
3152      .mon();
3153    InitReg(MISCREG_NSACR)
3154      .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3155    InitReg(MISCREG_HSCTLR)
3156      .hyp().monNonSecure()
3157      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
3158                       | (IESB   ? 0 :   0x200000)
3159                       | (EnDA   ? 0 :  0x8000000)
3160                       | (EnIB   ? 0 : 0x40000000)
3161                       | (EnIA   ? 0 : 0x80000000))
3162      .res1(0x30c50830);
3163    InitReg(MISCREG_HACTLR)
3164      .hyp().monNonSecure();
3165    InitReg(MISCREG_HCR)
3166      .hyp().monNonSecure();
3167    InitReg(MISCREG_HDCR)
3168      .hyp().monNonSecure();
3169    InitReg(MISCREG_HCPTR)
3170      .hyp().monNonSecure();
3171    InitReg(MISCREG_HSTR)
3172      .hyp().monNonSecure();
3173    InitReg(MISCREG_HACR)
3174      .unimplemented()
3175      .warnNotFail()
3176      .hyp().monNonSecure();
3177    InitReg(MISCREG_TTBR0)
3178      .banked();
3179    InitReg(MISCREG_TTBR0_NS)
3180      .bankedChild()
3181      .privSecure(!aarch32EL3)
3182      .nonSecure().exceptUserMode();
3183    InitReg(MISCREG_TTBR0_S)
3184      .bankedChild()
3185      .secure().exceptUserMode();
3186    InitReg(MISCREG_TTBR1)
3187      .banked();
3188    InitReg(MISCREG_TTBR1_NS)
3189      .bankedChild()
3190      .privSecure(!aarch32EL3)
3191      .nonSecure().exceptUserMode();
3192    InitReg(MISCREG_TTBR1_S)
3193      .bankedChild()
3194      .secure().exceptUserMode();
3195    InitReg(MISCREG_TTBCR)
3196      .banked();
3197    InitReg(MISCREG_TTBCR_NS)
3198      .bankedChild()
3199      .privSecure(!aarch32EL3)
3200      .nonSecure().exceptUserMode();
3201    InitReg(MISCREG_TTBCR_S)
3202      .bankedChild()
3203      .secure().exceptUserMode();
3204    InitReg(MISCREG_HTCR)
3205      .hyp().monNonSecure();
3206    InitReg(MISCREG_VTCR)
3207      .hyp().monNonSecure();
3208    InitReg(MISCREG_DACR)
3209      .banked();
3210    InitReg(MISCREG_DACR_NS)
3211      .bankedChild()
3212      .privSecure(!aarch32EL3)
3213      .nonSecure().exceptUserMode();
3214    InitReg(MISCREG_DACR_S)
3215      .bankedChild()
3216      .secure().exceptUserMode();
3217    InitReg(MISCREG_DFSR)
3218      .banked();
3219    InitReg(MISCREG_DFSR_NS)
3220      .bankedChild()
3221      .privSecure(!aarch32EL3)
3222      .nonSecure().exceptUserMode();
3223    InitReg(MISCREG_DFSR_S)
3224      .bankedChild()
3225      .secure().exceptUserMode();
3226    InitReg(MISCREG_IFSR)
3227      .banked();
3228    InitReg(MISCREG_IFSR_NS)
3229      .bankedChild()
3230      .privSecure(!aarch32EL3)
3231      .nonSecure().exceptUserMode();
3232    InitReg(MISCREG_IFSR_S)
3233      .bankedChild()
3234      .secure().exceptUserMode();
3235    InitReg(MISCREG_ADFSR)
3236      .unimplemented()
3237      .warnNotFail()
3238      .banked();
3239    InitReg(MISCREG_ADFSR_NS)
3240      .unimplemented()
3241      .warnNotFail()
3242      .bankedChild()
3243      .privSecure(!aarch32EL3)
3244      .nonSecure().exceptUserMode();
3245    InitReg(MISCREG_ADFSR_S)
3246      .unimplemented()
3247      .warnNotFail()
3248      .bankedChild()
3249      .secure().exceptUserMode();
3250    InitReg(MISCREG_AIFSR)
3251      .unimplemented()
3252      .warnNotFail()
3253      .banked();
3254    InitReg(MISCREG_AIFSR_NS)
3255      .unimplemented()
3256      .warnNotFail()
3257      .bankedChild()
3258      .privSecure(!aarch32EL3)
3259      .nonSecure().exceptUserMode();
3260    InitReg(MISCREG_AIFSR_S)
3261      .unimplemented()
3262      .warnNotFail()
3263      .bankedChild()
3264      .secure().exceptUserMode();
3265    InitReg(MISCREG_HADFSR)
3266      .hyp().monNonSecure();
3267    InitReg(MISCREG_HAIFSR)
3268      .hyp().monNonSecure();
3269    InitReg(MISCREG_HSR)
3270      .hyp().monNonSecure();
3271    InitReg(MISCREG_DFAR)
3272      .banked();
3273    InitReg(MISCREG_DFAR_NS)
3274      .bankedChild()
3275      .privSecure(!aarch32EL3)
3276      .nonSecure().exceptUserMode();
3277    InitReg(MISCREG_DFAR_S)
3278      .bankedChild()
3279      .secure().exceptUserMode();
3280    InitReg(MISCREG_IFAR)
3281      .banked();
3282    InitReg(MISCREG_IFAR_NS)
3283      .bankedChild()
3284      .privSecure(!aarch32EL3)
3285      .nonSecure().exceptUserMode();
3286    InitReg(MISCREG_IFAR_S)
3287      .bankedChild()
3288      .secure().exceptUserMode();
3289    InitReg(MISCREG_HDFAR)
3290      .hyp().monNonSecure();
3291    InitReg(MISCREG_HIFAR)
3292      .hyp().monNonSecure();
3293    InitReg(MISCREG_HPFAR)
3294      .hyp().monNonSecure();
3295    InitReg(MISCREG_ICIALLUIS)
3296      .unimplemented()
3297      .warnNotFail()
3298      .writes(1).exceptUserMode();
3299    InitReg(MISCREG_BPIALLIS)
3300      .unimplemented()
3301      .warnNotFail()
3302      .writes(1).exceptUserMode();
3303    InitReg(MISCREG_PAR)
3304      .banked();
3305    InitReg(MISCREG_PAR_NS)
3306      .bankedChild()
3307      .privSecure(!aarch32EL3)
3308      .nonSecure().exceptUserMode();
3309    InitReg(MISCREG_PAR_S)
3310      .bankedChild()
3311      .secure().exceptUserMode();
3312    InitReg(MISCREG_ICIALLU)
3313      .writes(1).exceptUserMode();
3314    InitReg(MISCREG_ICIMVAU)
3315      .unimplemented()
3316      .warnNotFail()
3317      .writes(1).exceptUserMode();
3318    InitReg(MISCREG_CP15ISB)
3319      .writes(1);
3320    InitReg(MISCREG_BPIALL)
3321      .unimplemented()
3322      .warnNotFail()
3323      .writes(1).exceptUserMode();
3324    InitReg(MISCREG_BPIMVA)
3325      .unimplemented()
3326      .warnNotFail()
3327      .writes(1).exceptUserMode();
3328    InitReg(MISCREG_DCIMVAC)
3329      .unimplemented()
3330      .warnNotFail()
3331      .writes(1).exceptUserMode();
3332    InitReg(MISCREG_DCISW)
3333      .unimplemented()
3334      .warnNotFail()
3335      .writes(1).exceptUserMode();
3336    InitReg(MISCREG_ATS1CPR)
3337      .writes(1).exceptUserMode();
3338    InitReg(MISCREG_ATS1CPW)
3339      .writes(1).exceptUserMode();
3340    InitReg(MISCREG_ATS1CUR)
3341      .writes(1).exceptUserMode();
3342    InitReg(MISCREG_ATS1CUW)
3343      .writes(1).exceptUserMode();
3344    InitReg(MISCREG_ATS12NSOPR)
3345      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3346    InitReg(MISCREG_ATS12NSOPW)
3347      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3348    InitReg(MISCREG_ATS12NSOUR)
3349      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3350    InitReg(MISCREG_ATS12NSOUW)
3351      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3352    InitReg(MISCREG_DCCMVAC)
3353      .writes(1).exceptUserMode();
3354    InitReg(MISCREG_DCCSW)
3355      .unimplemented()
3356      .warnNotFail()
3357      .writes(1).exceptUserMode();
3358    InitReg(MISCREG_CP15DSB)
3359      .writes(1);
3360    InitReg(MISCREG_CP15DMB)
3361      .writes(1);
3362    InitReg(MISCREG_DCCMVAU)
3363      .unimplemented()
3364      .warnNotFail()
3365      .writes(1).exceptUserMode();
3366    InitReg(MISCREG_DCCIMVAC)
3367      .unimplemented()
3368      .warnNotFail()
3369      .writes(1).exceptUserMode();
3370    InitReg(MISCREG_DCCISW)
3371      .unimplemented()
3372      .warnNotFail()
3373      .writes(1).exceptUserMode();
3374    InitReg(MISCREG_ATS1HR)
3375      .monNonSecureWrite().hypWrite();
3376    InitReg(MISCREG_ATS1HW)
3377      .monNonSecureWrite().hypWrite();
3378    InitReg(MISCREG_TLBIALLIS)
3379      .writes(1).exceptUserMode();
3380    InitReg(MISCREG_TLBIMVAIS)
3381      .writes(1).exceptUserMode();
3382    InitReg(MISCREG_TLBIASIDIS)
3383      .writes(1).exceptUserMode();
3384    InitReg(MISCREG_TLBIMVAAIS)
3385      .writes(1).exceptUserMode();
3386    InitReg(MISCREG_TLBIMVALIS)
3387      .writes(1).exceptUserMode();
3388    InitReg(MISCREG_TLBIMVAALIS)
3389      .writes(1).exceptUserMode();
3390    InitReg(MISCREG_ITLBIALL)
3391      .writes(1).exceptUserMode();
3392    InitReg(MISCREG_ITLBIMVA)
3393      .writes(1).exceptUserMode();
3394    InitReg(MISCREG_ITLBIASID)
3395      .writes(1).exceptUserMode();
3396    InitReg(MISCREG_DTLBIALL)
3397      .writes(1).exceptUserMode();
3398    InitReg(MISCREG_DTLBIMVA)
3399      .writes(1).exceptUserMode();
3400    InitReg(MISCREG_DTLBIASID)
3401      .writes(1).exceptUserMode();
3402    InitReg(MISCREG_TLBIALL)
3403      .writes(1).exceptUserMode();
3404    InitReg(MISCREG_TLBIMVA)
3405      .writes(1).exceptUserMode();
3406    InitReg(MISCREG_TLBIASID)
3407      .writes(1).exceptUserMode();
3408    InitReg(MISCREG_TLBIMVAA)
3409      .writes(1).exceptUserMode();
3410    InitReg(MISCREG_TLBIMVAL)
3411      .writes(1).exceptUserMode();
3412    InitReg(MISCREG_TLBIMVAAL)
3413      .writes(1).exceptUserMode();
3414    InitReg(MISCREG_TLBIIPAS2IS)
3415      .monNonSecureWrite().hypWrite();
3416    InitReg(MISCREG_TLBIIPAS2LIS)
3417      .monNonSecureWrite().hypWrite();
3418    InitReg(MISCREG_TLBIALLHIS)
3419      .monNonSecureWrite().hypWrite();
3420    InitReg(MISCREG_TLBIMVAHIS)
3421      .monNonSecureWrite().hypWrite();
3422    InitReg(MISCREG_TLBIALLNSNHIS)
3423      .monNonSecureWrite().hypWrite();
3424    InitReg(MISCREG_TLBIMVALHIS)
3425      .monNonSecureWrite().hypWrite();
3426    InitReg(MISCREG_TLBIIPAS2)
3427      .monNonSecureWrite().hypWrite();
3428    InitReg(MISCREG_TLBIIPAS2L)
3429      .monNonSecureWrite().hypWrite();
3430    InitReg(MISCREG_TLBIALLH)
3431      .monNonSecureWrite().hypWrite();
3432    InitReg(MISCREG_TLBIMVAH)
3433      .monNonSecureWrite().hypWrite();
3434    InitReg(MISCREG_TLBIALLNSNH)
3435      .monNonSecureWrite().hypWrite();
3436    InitReg(MISCREG_TLBIMVALH)
3437      .monNonSecureWrite().hypWrite();
3438    InitReg(MISCREG_PMCR)
3439      .allPrivileges();
3440    InitReg(MISCREG_PMCNTENSET)
3441      .allPrivileges();
3442    InitReg(MISCREG_PMCNTENCLR)
3443      .allPrivileges();
3444    InitReg(MISCREG_PMOVSR)
3445      .allPrivileges();
3446    InitReg(MISCREG_PMSWINC)
3447      .allPrivileges();
3448    InitReg(MISCREG_PMSELR)
3449      .allPrivileges();
3450    InitReg(MISCREG_PMCEID0)
3451      .allPrivileges();
3452    InitReg(MISCREG_PMCEID1)
3453      .allPrivileges();
3454    InitReg(MISCREG_PMCCNTR)
3455      .allPrivileges();
3456    InitReg(MISCREG_PMXEVTYPER)
3457      .allPrivileges();
3458    InitReg(MISCREG_PMCCFILTR)
3459      .allPrivileges();
3460    InitReg(MISCREG_PMXEVCNTR)
3461      .allPrivileges();
3462    InitReg(MISCREG_PMUSERENR)
3463      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3464    InitReg(MISCREG_PMINTENSET)
3465      .allPrivileges().exceptUserMode();
3466    InitReg(MISCREG_PMINTENCLR)
3467      .allPrivileges().exceptUserMode();
3468    InitReg(MISCREG_PMOVSSET)
3469      .unimplemented()
3470      .allPrivileges();
3471    InitReg(MISCREG_L2CTLR)
3472      .allPrivileges().exceptUserMode();
3473    InitReg(MISCREG_L2ECTLR)
3474      .unimplemented()
3475      .allPrivileges().exceptUserMode();
3476    InitReg(MISCREG_PRRR)
3477      .banked();
3478    InitReg(MISCREG_PRRR_NS)
3479      .bankedChild()
3480      .privSecure(!aarch32EL3)
3481      .nonSecure().exceptUserMode();
3482    InitReg(MISCREG_PRRR_S)
3483      .bankedChild()
3484      .secure().exceptUserMode();
3485    InitReg(MISCREG_MAIR0)
3486      .banked();
3487    InitReg(MISCREG_MAIR0_NS)
3488      .bankedChild()
3489      .privSecure(!aarch32EL3)
3490      .nonSecure().exceptUserMode();
3491    InitReg(MISCREG_MAIR0_S)
3492      .bankedChild()
3493      .secure().exceptUserMode();
3494    InitReg(MISCREG_NMRR)
3495      .banked();
3496    InitReg(MISCREG_NMRR_NS)
3497      .bankedChild()
3498      .privSecure(!aarch32EL3)
3499      .nonSecure().exceptUserMode();
3500    InitReg(MISCREG_NMRR_S)
3501      .bankedChild()
3502      .secure().exceptUserMode();
3503    InitReg(MISCREG_MAIR1)
3504      .banked();
3505    InitReg(MISCREG_MAIR1_NS)
3506      .bankedChild()
3507      .privSecure(!aarch32EL3)
3508      .nonSecure().exceptUserMode();
3509    InitReg(MISCREG_MAIR1_S)
3510      .bankedChild()
3511      .secure().exceptUserMode();
3512    InitReg(MISCREG_AMAIR0)
3513      .banked();
3514    InitReg(MISCREG_AMAIR0_NS)
3515      .bankedChild()
3516      .privSecure(!aarch32EL3)
3517      .nonSecure().exceptUserMode();
3518    InitReg(MISCREG_AMAIR0_S)
3519      .bankedChild()
3520      .secure().exceptUserMode();
3521    InitReg(MISCREG_AMAIR1)
3522      .banked();
3523    InitReg(MISCREG_AMAIR1_NS)
3524      .bankedChild()
3525      .privSecure(!aarch32EL3)
3526      .nonSecure().exceptUserMode();
3527    InitReg(MISCREG_AMAIR1_S)
3528      .bankedChild()
3529      .secure().exceptUserMode();
3530    InitReg(MISCREG_HMAIR0)
3531      .hyp().monNonSecure();
3532    InitReg(MISCREG_HMAIR1)
3533      .hyp().monNonSecure();
3534    InitReg(MISCREG_HAMAIR0)
3535      .unimplemented()
3536      .warnNotFail()
3537      .hyp().monNonSecure();
3538    InitReg(MISCREG_HAMAIR1)
3539      .unimplemented()
3540      .warnNotFail()
3541      .hyp().monNonSecure();
3542    InitReg(MISCREG_VBAR)
3543      .banked();
3544    InitReg(MISCREG_VBAR_NS)
3545      .bankedChild()
3546      .privSecure(!aarch32EL3)
3547      .nonSecure().exceptUserMode();
3548    InitReg(MISCREG_VBAR_S)
3549      .bankedChild()
3550      .secure().exceptUserMode();
3551    InitReg(MISCREG_MVBAR)
3552      .mon().secure()
3553      .hypRead(FullSystem && system->highestEL() == EL2)
3554      .privRead(FullSystem && system->highestEL() == EL1)
3555      .exceptUserMode();
3556    InitReg(MISCREG_RMR)
3557      .unimplemented()
3558      .mon().secure().exceptUserMode();
3559    InitReg(MISCREG_ISR)
3560      .allPrivileges().exceptUserMode().writes(0);
3561    InitReg(MISCREG_HVBAR)
3562      .hyp().monNonSecure()
3563      .res0(0x1f);
3564    InitReg(MISCREG_FCSEIDR)
3565      .unimplemented()
3566      .warnNotFail()
3567      .allPrivileges().exceptUserMode();
3568    InitReg(MISCREG_CONTEXTIDR)
3569      .banked();
3570    InitReg(MISCREG_CONTEXTIDR_NS)
3571      .bankedChild()
3572      .privSecure(!aarch32EL3)
3573      .nonSecure().exceptUserMode();
3574    InitReg(MISCREG_CONTEXTIDR_S)
3575      .bankedChild()
3576      .secure().exceptUserMode();
3577    InitReg(MISCREG_TPIDRURW)
3578      .banked();
3579    InitReg(MISCREG_TPIDRURW_NS)
3580      .bankedChild()
3581      .allPrivileges()
3582      .privSecure(!aarch32EL3)
3583      .monSecure(0);
3584    InitReg(MISCREG_TPIDRURW_S)
3585      .bankedChild()
3586      .secure();
3587    InitReg(MISCREG_TPIDRURO)
3588      .banked();
3589    InitReg(MISCREG_TPIDRURO_NS)
3590      .bankedChild()
3591      .allPrivileges()
3592      .userNonSecureWrite(0).userSecureRead(1)
3593      .privSecure(!aarch32EL3)
3594      .monSecure(0);
3595    InitReg(MISCREG_TPIDRURO_S)
3596      .bankedChild()
3597      .secure().userSecureWrite(0);
3598    InitReg(MISCREG_TPIDRPRW)
3599      .banked();
3600    InitReg(MISCREG_TPIDRPRW_NS)
3601      .bankedChild()
3602      .nonSecure().exceptUserMode()
3603      .privSecure(!aarch32EL3);
3604    InitReg(MISCREG_TPIDRPRW_S)
3605      .bankedChild()
3606      .secure().exceptUserMode();
3607    InitReg(MISCREG_HTPIDR)
3608      .hyp().monNonSecure();
3609    InitReg(MISCREG_CNTFRQ)
3610      .unverifiable()
3611      .reads(1).mon();
3612    InitReg(MISCREG_CNTKCTL)
3613      .allPrivileges().exceptUserMode();
3614    InitReg(MISCREG_CNTP_TVAL)
3615      .banked();
3616    InitReg(MISCREG_CNTP_TVAL_NS)
3617      .bankedChild()
3618      .allPrivileges()
3619      .privSecure(!aarch32EL3)
3620      .monSecure(0);
3621    InitReg(MISCREG_CNTP_TVAL_S)
3622      .bankedChild()
3623      .secure().user(1);
3624    InitReg(MISCREG_CNTP_CTL)
3625      .banked();
3626    InitReg(MISCREG_CNTP_CTL_NS)
3627      .bankedChild()
3628      .allPrivileges()
3629      .privSecure(!aarch32EL3)
3630      .monSecure(0);
3631    InitReg(MISCREG_CNTP_CTL_S)
3632      .bankedChild()
3633      .secure().user(1);
3634    InitReg(MISCREG_CNTV_TVAL)
3635      .allPrivileges();
3636    InitReg(MISCREG_CNTV_CTL)
3637      .allPrivileges();
3638    InitReg(MISCREG_CNTHCTL)
3639      .hypWrite().monNonSecureRead();
3640    InitReg(MISCREG_CNTHP_TVAL)
3641      .hypWrite().monNonSecureRead();
3642    InitReg(MISCREG_CNTHP_CTL)
3643      .hypWrite().monNonSecureRead();
3644    InitReg(MISCREG_IL1DATA0)
3645      .unimplemented()
3646      .allPrivileges().exceptUserMode();
3647    InitReg(MISCREG_IL1DATA1)
3648      .unimplemented()
3649      .allPrivileges().exceptUserMode();
3650    InitReg(MISCREG_IL1DATA2)
3651      .unimplemented()
3652      .allPrivileges().exceptUserMode();
3653    InitReg(MISCREG_IL1DATA3)
3654      .unimplemented()
3655      .allPrivileges().exceptUserMode();
3656    InitReg(MISCREG_DL1DATA0)
3657      .unimplemented()
3658      .allPrivileges().exceptUserMode();
3659    InitReg(MISCREG_DL1DATA1)
3660      .unimplemented()
3661      .allPrivileges().exceptUserMode();
3662    InitReg(MISCREG_DL1DATA2)
3663      .unimplemented()
3664      .allPrivileges().exceptUserMode();
3665    InitReg(MISCREG_DL1DATA3)
3666      .unimplemented()
3667      .allPrivileges().exceptUserMode();
3668    InitReg(MISCREG_DL1DATA4)
3669      .unimplemented()
3670      .allPrivileges().exceptUserMode();
3671    InitReg(MISCREG_RAMINDEX)
3672      .unimplemented()
3673      .writes(1).exceptUserMode();
3674    InitReg(MISCREG_L2ACTLR)
3675      .unimplemented()
3676      .allPrivileges().exceptUserMode();
3677    InitReg(MISCREG_CBAR)
3678      .unimplemented()
3679      .allPrivileges().exceptUserMode().writes(0);
3680    InitReg(MISCREG_HTTBR)
3681      .hyp().monNonSecure();
3682    InitReg(MISCREG_VTTBR)
3683      .hyp().monNonSecure();
3684    InitReg(MISCREG_CNTPCT)
3685      .reads(1);
3686    InitReg(MISCREG_CNTVCT)
3687      .unverifiable()
3688      .reads(1);
3689    InitReg(MISCREG_CNTP_CVAL)
3690      .banked();
3691    InitReg(MISCREG_CNTP_CVAL_NS)
3692      .bankedChild()
3693      .allPrivileges()
3694      .privSecure(!aarch32EL3)
3695      .monSecure(0);
3696    InitReg(MISCREG_CNTP_CVAL_S)
3697      .bankedChild()
3698      .secure().user(1);
3699    InitReg(MISCREG_CNTV_CVAL)
3700      .allPrivileges();
3701    InitReg(MISCREG_CNTVOFF)
3702      .hyp().monNonSecure();
3703    InitReg(MISCREG_CNTHP_CVAL)
3704      .hypWrite().monNonSecureRead();
3705    InitReg(MISCREG_CPUMERRSR)
3706      .unimplemented()
3707      .allPrivileges().exceptUserMode();
3708    InitReg(MISCREG_L2MERRSR)
3709      .unimplemented()
3710      .warnNotFail()
3711      .allPrivileges().exceptUserMode();
3712
3713    // AArch64 registers (Op0=2);
3714    InitReg(MISCREG_MDCCINT_EL1)
3715      .allPrivileges();
3716    InitReg(MISCREG_OSDTRRX_EL1)
3717      .allPrivileges()
3718      .mapsTo(MISCREG_DBGDTRRXext);
3719    InitReg(MISCREG_MDSCR_EL1)
3720      .allPrivileges()
3721      .mapsTo(MISCREG_DBGDSCRext);
3722    InitReg(MISCREG_OSDTRTX_EL1)
3723      .allPrivileges()
3724      .mapsTo(MISCREG_DBGDTRTXext);
3725    InitReg(MISCREG_OSECCR_EL1)
3726      .allPrivileges()
3727      .mapsTo(MISCREG_DBGOSECCR);
3728    InitReg(MISCREG_DBGBVR0_EL1)
3729      .allPrivileges()
3730      .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3731    InitReg(MISCREG_DBGBVR1_EL1)
3732      .allPrivileges()
3733      .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3734    InitReg(MISCREG_DBGBVR2_EL1)
3735      .allPrivileges()
3736      .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3737    InitReg(MISCREG_DBGBVR3_EL1)
3738      .allPrivileges()
3739      .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3740    InitReg(MISCREG_DBGBVR4_EL1)
3741      .allPrivileges()
3742      .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3743    InitReg(MISCREG_DBGBVR5_EL1)
3744      .allPrivileges()
3745      .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3746    InitReg(MISCREG_DBGBCR0_EL1)
3747      .allPrivileges()
3748      .mapsTo(MISCREG_DBGBCR0);
3749    InitReg(MISCREG_DBGBCR1_EL1)
3750      .allPrivileges()
3751      .mapsTo(MISCREG_DBGBCR1);
3752    InitReg(MISCREG_DBGBCR2_EL1)
3753      .allPrivileges()
3754      .mapsTo(MISCREG_DBGBCR2);
3755    InitReg(MISCREG_DBGBCR3_EL1)
3756      .allPrivileges()
3757      .mapsTo(MISCREG_DBGBCR3);
3758    InitReg(MISCREG_DBGBCR4_EL1)
3759      .allPrivileges()
3760      .mapsTo(MISCREG_DBGBCR4);
3761    InitReg(MISCREG_DBGBCR5_EL1)
3762      .allPrivileges()
3763      .mapsTo(MISCREG_DBGBCR5);
3764    InitReg(MISCREG_DBGWVR0_EL1)
3765      .allPrivileges()
3766      .mapsTo(MISCREG_DBGWVR0);
3767    InitReg(MISCREG_DBGWVR1_EL1)
3768      .allPrivileges()
3769      .mapsTo(MISCREG_DBGWVR1);
3770    InitReg(MISCREG_DBGWVR2_EL1)
3771      .allPrivileges()
3772      .mapsTo(MISCREG_DBGWVR2);
3773    InitReg(MISCREG_DBGWVR3_EL1)
3774      .allPrivileges()
3775      .mapsTo(MISCREG_DBGWVR3);
3776    InitReg(MISCREG_DBGWCR0_EL1)
3777      .allPrivileges()
3778      .mapsTo(MISCREG_DBGWCR0);
3779    InitReg(MISCREG_DBGWCR1_EL1)
3780      .allPrivileges()
3781      .mapsTo(MISCREG_DBGWCR1);
3782    InitReg(MISCREG_DBGWCR2_EL1)
3783      .allPrivileges()
3784      .mapsTo(MISCREG_DBGWCR2);
3785    InitReg(MISCREG_DBGWCR3_EL1)
3786      .allPrivileges()
3787      .mapsTo(MISCREG_DBGWCR3);
3788    InitReg(MISCREG_MDCCSR_EL0)
3789      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3790      .mapsTo(MISCREG_DBGDSCRint);
3791    InitReg(MISCREG_MDDTR_EL0)
3792      .allPrivileges();
3793    InitReg(MISCREG_MDDTRTX_EL0)
3794      .allPrivileges();
3795    InitReg(MISCREG_MDDTRRX_EL0)
3796      .allPrivileges();
3797    InitReg(MISCREG_DBGVCR32_EL2)
3798      .allPrivileges()
3799      .mapsTo(MISCREG_DBGVCR);
3800    InitReg(MISCREG_MDRAR_EL1)
3801      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3802      .mapsTo(MISCREG_DBGDRAR);
3803    InitReg(MISCREG_OSLAR_EL1)
3804      .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3805      .mapsTo(MISCREG_DBGOSLAR);
3806    InitReg(MISCREG_OSLSR_EL1)
3807      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3808      .mapsTo(MISCREG_DBGOSLSR);
3809    InitReg(MISCREG_OSDLR_EL1)
3810      .allPrivileges()
3811      .mapsTo(MISCREG_DBGOSDLR);
3812    InitReg(MISCREG_DBGPRCR_EL1)
3813      .allPrivileges()
3814      .mapsTo(MISCREG_DBGPRCR);
3815    InitReg(MISCREG_DBGCLAIMSET_EL1)
3816      .allPrivileges()
3817      .mapsTo(MISCREG_DBGCLAIMSET);
3818    InitReg(MISCREG_DBGCLAIMCLR_EL1)
3819      .allPrivileges()
3820      .mapsTo(MISCREG_DBGCLAIMCLR);
3821    InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3822      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3823      .mapsTo(MISCREG_DBGAUTHSTATUS);
3824    InitReg(MISCREG_TEECR32_EL1);
3825    InitReg(MISCREG_TEEHBR32_EL1);
3826
3827    // AArch64 registers (Op0=1,3);
3828    InitReg(MISCREG_MIDR_EL1)
3829      .allPrivileges().exceptUserMode().writes(0);
3830    InitReg(MISCREG_MPIDR_EL1)
3831      .allPrivileges().exceptUserMode().writes(0);
3832    InitReg(MISCREG_REVIDR_EL1)
3833      .allPrivileges().exceptUserMode().writes(0);
3834    InitReg(MISCREG_ID_PFR0_EL1)
3835      .allPrivileges().exceptUserMode().writes(0)
3836      .mapsTo(MISCREG_ID_PFR0);
3837    InitReg(MISCREG_ID_PFR1_EL1)
3838      .allPrivileges().exceptUserMode().writes(0)
3839      .mapsTo(MISCREG_ID_PFR1);
3840    InitReg(MISCREG_ID_DFR0_EL1)
3841      .allPrivileges().exceptUserMode().writes(0)
3842      .mapsTo(MISCREG_ID_DFR0);
3843    InitReg(MISCREG_ID_AFR0_EL1)
3844      .allPrivileges().exceptUserMode().writes(0)
3845      .mapsTo(MISCREG_ID_AFR0);
3846    InitReg(MISCREG_ID_MMFR0_EL1)
3847      .allPrivileges().exceptUserMode().writes(0)
3848      .mapsTo(MISCREG_ID_MMFR0);
3849    InitReg(MISCREG_ID_MMFR1_EL1)
3850      .allPrivileges().exceptUserMode().writes(0)
3851      .mapsTo(MISCREG_ID_MMFR1);
3852    InitReg(MISCREG_ID_MMFR2_EL1)
3853      .allPrivileges().exceptUserMode().writes(0)
3854      .mapsTo(MISCREG_ID_MMFR2);
3855    InitReg(MISCREG_ID_MMFR3_EL1)
3856      .allPrivileges().exceptUserMode().writes(0)
3857      .mapsTo(MISCREG_ID_MMFR3);
3858    InitReg(MISCREG_ID_ISAR0_EL1)
3859      .allPrivileges().exceptUserMode().writes(0)
3860      .mapsTo(MISCREG_ID_ISAR0);
3861    InitReg(MISCREG_ID_ISAR1_EL1)
3862      .allPrivileges().exceptUserMode().writes(0)
3863      .mapsTo(MISCREG_ID_ISAR1);
3864    InitReg(MISCREG_ID_ISAR2_EL1)
3865      .allPrivileges().exceptUserMode().writes(0)
3866      .mapsTo(MISCREG_ID_ISAR2);
3867    InitReg(MISCREG_ID_ISAR3_EL1)
3868      .allPrivileges().exceptUserMode().writes(0)
3869      .mapsTo(MISCREG_ID_ISAR3);
3870    InitReg(MISCREG_ID_ISAR4_EL1)
3871      .allPrivileges().exceptUserMode().writes(0)
3872      .mapsTo(MISCREG_ID_ISAR4);
3873    InitReg(MISCREG_ID_ISAR5_EL1)
3874      .allPrivileges().exceptUserMode().writes(0)
3875      .mapsTo(MISCREG_ID_ISAR5);
3876    InitReg(MISCREG_MVFR0_EL1)
3877      .allPrivileges().exceptUserMode().writes(0);
3878    InitReg(MISCREG_MVFR1_EL1)
3879      .allPrivileges().exceptUserMode().writes(0);
3880    InitReg(MISCREG_MVFR2_EL1)
3881      .allPrivileges().exceptUserMode().writes(0);
3882    InitReg(MISCREG_ID_AA64PFR0_EL1)
3883      .allPrivileges().exceptUserMode().writes(0);
3884    InitReg(MISCREG_ID_AA64PFR1_EL1)
3885      .allPrivileges().exceptUserMode().writes(0);
3886    InitReg(MISCREG_ID_AA64DFR0_EL1)
3887      .allPrivileges().exceptUserMode().writes(0);
3888    InitReg(MISCREG_ID_AA64DFR1_EL1)
3889      .allPrivileges().exceptUserMode().writes(0);
3890    InitReg(MISCREG_ID_AA64AFR0_EL1)
3891      .allPrivileges().exceptUserMode().writes(0);
3892    InitReg(MISCREG_ID_AA64AFR1_EL1)
3893      .allPrivileges().exceptUserMode().writes(0);
3894    InitReg(MISCREG_ID_AA64ISAR0_EL1)
3895      .allPrivileges().exceptUserMode().writes(0);
3896    InitReg(MISCREG_ID_AA64ISAR1_EL1)
3897      .allPrivileges().exceptUserMode().writes(0);
3898    InitReg(MISCREG_ID_AA64MMFR0_EL1)
3899      .allPrivileges().exceptUserMode().writes(0);
3900    InitReg(MISCREG_ID_AA64MMFR1_EL1)
3901      .allPrivileges().exceptUserMode().writes(0);
3902    InitReg(MISCREG_ID_AA64MMFR2_EL1)
3903      .allPrivileges().exceptUserMode().writes(0);
3904    InitReg(MISCREG_CCSIDR_EL1)
3905      .allPrivileges().exceptUserMode().writes(0);
3906    InitReg(MISCREG_CLIDR_EL1)
3907      .allPrivileges().exceptUserMode().writes(0);
3908    InitReg(MISCREG_AIDR_EL1)
3909      .allPrivileges().exceptUserMode().writes(0);
3910    InitReg(MISCREG_CSSELR_EL1)
3911      .allPrivileges().exceptUserMode()
3912      .mapsTo(MISCREG_CSSELR_NS);
3913    InitReg(MISCREG_CTR_EL0)
3914      .reads(1);
3915    InitReg(MISCREG_DCZID_EL0)
3916      .reads(1);
3917    InitReg(MISCREG_VPIDR_EL2)
3918      .hyp().mon()
3919      .mapsTo(MISCREG_VPIDR);
3920    InitReg(MISCREG_VMPIDR_EL2)
3921      .hyp().mon()
3922      .mapsTo(MISCREG_VMPIDR);
3923    InitReg(MISCREG_SCTLR_EL1)
3924      .allPrivileges().exceptUserMode()
3925      .res0( 0x20440 | (EnDB   ? 0 :     0x2000)
3926                     | (IESB   ? 0 :   0x200000)
3927                     | (EnDA   ? 0 :  0x8000000)
3928                     | (EnIB   ? 0 : 0x40000000)
3929                     | (EnIA   ? 0 : 0x80000000))
3930      .res1(0x500800 | (SPAN   ? 0 :   0x800000)
3931                     | (nTLSMD ? 0 :  0x8000000)
3932                     | (LSMAOE ? 0 : 0x10000000))
3933      .mapsTo(MISCREG_SCTLR_NS);
3934    InitReg(MISCREG_ACTLR_EL1)
3935      .allPrivileges().exceptUserMode()
3936      .mapsTo(MISCREG_ACTLR_NS);
3937    InitReg(MISCREG_CPACR_EL1)
3938      .allPrivileges().exceptUserMode()
3939      .mapsTo(MISCREG_CPACR);
3940    InitReg(MISCREG_SCTLR_EL2)
3941      .hyp().mon()
3942      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
3943                       | (IESB   ? 0 :   0x200000)
3944                       | (EnDA   ? 0 :  0x8000000)
3945                       | (EnIB   ? 0 : 0x40000000)
3946                       | (EnIA   ? 0 : 0x80000000))
3947      .res1(0x30c50830)
3948      .mapsTo(MISCREG_HSCTLR);
3949    InitReg(MISCREG_ACTLR_EL2)
3950      .hyp().mon()
3951      .mapsTo(MISCREG_HACTLR);
3952    InitReg(MISCREG_HCR_EL2)
3953      .hyp().mon()
3954      .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3955    InitReg(MISCREG_MDCR_EL2)
3956      .hyp().mon()
3957      .mapsTo(MISCREG_HDCR);
3958    InitReg(MISCREG_CPTR_EL2)
3959      .hyp().mon()
3960      .mapsTo(MISCREG_HCPTR);
3961    InitReg(MISCREG_HSTR_EL2)
3962      .hyp().mon()
3963      .mapsTo(MISCREG_HSTR);
3964    InitReg(MISCREG_HACR_EL2)
3965      .hyp().mon()
3966      .mapsTo(MISCREG_HACR);
3967    InitReg(MISCREG_SCTLR_EL3)
3968      .mon()
3969      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
3970                       | (IESB   ? 0 :   0x200000)
3971                       | (EnDA   ? 0 :  0x8000000)
3972                       | (EnIB   ? 0 : 0x40000000)
3973                       | (EnIA   ? 0 : 0x80000000))
3974      .res1(0x30c50830);
3975    InitReg(MISCREG_ACTLR_EL3)
3976      .mon();
3977    InitReg(MISCREG_SCR_EL3)
3978      .mon()
3979      .mapsTo(MISCREG_SCR); // NAM D7-2005
3980    InitReg(MISCREG_SDER32_EL3)
3981      .mon()
3982      .mapsTo(MISCREG_SDER);
3983    InitReg(MISCREG_CPTR_EL3)
3984      .mon();
3985    InitReg(MISCREG_MDCR_EL3)
3986      .mon();
3987    InitReg(MISCREG_TTBR0_EL1)
3988      .allPrivileges().exceptUserMode()
3989      .mapsTo(MISCREG_TTBR0_NS);
3990    InitReg(MISCREG_TTBR1_EL1)
3991      .allPrivileges().exceptUserMode()
3992      .mapsTo(MISCREG_TTBR1_NS);
3993    InitReg(MISCREG_TCR_EL1)
3994      .allPrivileges().exceptUserMode()
3995      .mapsTo(MISCREG_TTBCR_NS);
3996    InitReg(MISCREG_TTBR0_EL2)
3997      .hyp().mon()
3998      .mapsTo(MISCREG_HTTBR);
3999    InitReg(MISCREG_TTBR1_EL2)
4000      .hyp().mon();
4001    InitReg(MISCREG_TCR_EL2)
4002      .hyp().mon()
4003      .mapsTo(MISCREG_HTCR);
4004    InitReg(MISCREG_VTTBR_EL2)
4005      .hyp().mon()
4006      .mapsTo(MISCREG_VTTBR);
4007    InitReg(MISCREG_VTCR_EL2)
4008      .hyp().mon()
4009      .mapsTo(MISCREG_VTCR);
4010    InitReg(MISCREG_TTBR0_EL3)
4011      .mon();
4012    InitReg(MISCREG_TCR_EL3)
4013      .mon();
4014    InitReg(MISCREG_DACR32_EL2)
4015      .hyp().mon()
4016      .mapsTo(MISCREG_DACR_NS);
4017    InitReg(MISCREG_SPSR_EL1)
4018      .allPrivileges().exceptUserMode()
4019      .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4020    InitReg(MISCREG_ELR_EL1)
4021      .allPrivileges().exceptUserMode();
4022    InitReg(MISCREG_SP_EL0)
4023      .allPrivileges().exceptUserMode();
4024    InitReg(MISCREG_SPSEL)
4025      .allPrivileges().exceptUserMode();
4026    InitReg(MISCREG_CURRENTEL)
4027      .allPrivileges().exceptUserMode().writes(0);
4028    InitReg(MISCREG_NZCV)
4029      .allPrivileges();
4030    InitReg(MISCREG_DAIF)
4031      .allPrivileges();
4032    InitReg(MISCREG_FPCR)
4033      .allPrivileges();
4034    InitReg(MISCREG_FPSR)
4035      .allPrivileges();
4036    InitReg(MISCREG_DSPSR_EL0)
4037      .allPrivileges();
4038    InitReg(MISCREG_DLR_EL0)
4039      .allPrivileges();
4040    InitReg(MISCREG_SPSR_EL2)
4041      .hyp().mon()
4042      .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4043    InitReg(MISCREG_ELR_EL2)
4044      .hyp().mon();
4045    InitReg(MISCREG_SP_EL1)
4046      .hyp().mon();
4047    InitReg(MISCREG_SPSR_IRQ_AA64)
4048      .hyp().mon();
4049    InitReg(MISCREG_SPSR_ABT_AA64)
4050      .hyp().mon();
4051    InitReg(MISCREG_SPSR_UND_AA64)
4052      .hyp().mon();
4053    InitReg(MISCREG_SPSR_FIQ_AA64)
4054      .hyp().mon();
4055    InitReg(MISCREG_SPSR_EL3)
4056      .mon()
4057      .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4058    InitReg(MISCREG_ELR_EL3)
4059      .mon();
4060    InitReg(MISCREG_SP_EL2)
4061      .mon();
4062    InitReg(MISCREG_AFSR0_EL1)
4063      .allPrivileges().exceptUserMode()
4064      .mapsTo(MISCREG_ADFSR_NS);
4065    InitReg(MISCREG_AFSR1_EL1)
4066      .allPrivileges().exceptUserMode()
4067      .mapsTo(MISCREG_AIFSR_NS);
4068    InitReg(MISCREG_ESR_EL1)
4069      .allPrivileges().exceptUserMode();
4070    InitReg(MISCREG_IFSR32_EL2)
4071      .hyp().mon()
4072      .mapsTo(MISCREG_IFSR_NS);
4073    InitReg(MISCREG_AFSR0_EL2)
4074      .hyp().mon()
4075      .mapsTo(MISCREG_HADFSR);
4076    InitReg(MISCREG_AFSR1_EL2)
4077      .hyp().mon()
4078      .mapsTo(MISCREG_HAIFSR);
4079    InitReg(MISCREG_ESR_EL2)
4080      .hyp().mon()
4081      .mapsTo(MISCREG_HSR);
4082    InitReg(MISCREG_FPEXC32_EL2)
4083      .hyp().mon().mapsTo(MISCREG_FPEXC);
4084    InitReg(MISCREG_AFSR0_EL3)
4085      .mon();
4086    InitReg(MISCREG_AFSR1_EL3)
4087      .mon();
4088    InitReg(MISCREG_ESR_EL3)
4089      .mon();
4090    InitReg(MISCREG_FAR_EL1)
4091      .allPrivileges().exceptUserMode()
4092      .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4093    InitReg(MISCREG_FAR_EL2)
4094      .hyp().mon()
4095      .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4096    InitReg(MISCREG_HPFAR_EL2)
4097      .hyp().mon()
4098      .mapsTo(MISCREG_HPFAR);
4099    InitReg(MISCREG_FAR_EL3)
4100      .mon();
4101    InitReg(MISCREG_IC_IALLUIS)
4102      .warnNotFail()
4103      .writes(1).exceptUserMode();
4104    InitReg(MISCREG_PAR_EL1)
4105      .allPrivileges().exceptUserMode()
4106      .mapsTo(MISCREG_PAR_NS);
4107    InitReg(MISCREG_IC_IALLU)
4108      .warnNotFail()
4109      .writes(1).exceptUserMode();
4110    InitReg(MISCREG_DC_IVAC_Xt)
4111      .warnNotFail()
4112      .writes(1).exceptUserMode();
4113    InitReg(MISCREG_DC_ISW_Xt)
4114      .warnNotFail()
4115      .writes(1).exceptUserMode();
4116    InitReg(MISCREG_AT_S1E1R_Xt)
4117      .writes(1).exceptUserMode();
4118    InitReg(MISCREG_AT_S1E1W_Xt)
4119      .writes(1).exceptUserMode();
4120    InitReg(MISCREG_AT_S1E0R_Xt)
4121      .writes(1).exceptUserMode();
4122    InitReg(MISCREG_AT_S1E0W_Xt)
4123      .writes(1).exceptUserMode();
4124    InitReg(MISCREG_DC_CSW_Xt)
4125      .warnNotFail()
4126      .writes(1).exceptUserMode();
4127    InitReg(MISCREG_DC_CISW_Xt)
4128      .warnNotFail()
4129      .writes(1).exceptUserMode();
4130    InitReg(MISCREG_DC_ZVA_Xt)
4131      .warnNotFail()
4132      .writes(1).userSecureWrite(0);
4133    InitReg(MISCREG_IC_IVAU_Xt)
4134      .writes(1);
4135    InitReg(MISCREG_DC_CVAC_Xt)
4136      .warnNotFail()
4137      .writes(1);
4138    InitReg(MISCREG_DC_CVAU_Xt)
4139      .warnNotFail()
4140      .writes(1);
4141    InitReg(MISCREG_DC_CIVAC_Xt)
4142      .warnNotFail()
4143      .writes(1);
4144    InitReg(MISCREG_AT_S1E2R_Xt)
4145      .monNonSecureWrite().hypWrite();
4146    InitReg(MISCREG_AT_S1E2W_Xt)
4147      .monNonSecureWrite().hypWrite();
4148    InitReg(MISCREG_AT_S12E1R_Xt)
4149      .hypWrite().monSecureWrite().monNonSecureWrite();
4150    InitReg(MISCREG_AT_S12E1W_Xt)
4151      .hypWrite().monSecureWrite().monNonSecureWrite();
4152    InitReg(MISCREG_AT_S12E0R_Xt)
4153      .hypWrite().monSecureWrite().monNonSecureWrite();
4154    InitReg(MISCREG_AT_S12E0W_Xt)
4155      .hypWrite().monSecureWrite().monNonSecureWrite();
4156    InitReg(MISCREG_AT_S1E3R_Xt)
4157      .monSecureWrite().monNonSecureWrite();
4158    InitReg(MISCREG_AT_S1E3W_Xt)
4159      .monSecureWrite().monNonSecureWrite();
4160    InitReg(MISCREG_TLBI_VMALLE1IS)
4161      .writes(1).exceptUserMode();
4162    InitReg(MISCREG_TLBI_VAE1IS_Xt)
4163      .writes(1).exceptUserMode();
4164    InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4165      .writes(1).exceptUserMode();
4166    InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4167      .writes(1).exceptUserMode();
4168    InitReg(MISCREG_TLBI_VALE1IS_Xt)
4169      .writes(1).exceptUserMode();
4170    InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4171      .writes(1).exceptUserMode();
4172    InitReg(MISCREG_TLBI_VMALLE1)
4173      .writes(1).exceptUserMode();
4174    InitReg(MISCREG_TLBI_VAE1_Xt)
4175      .writes(1).exceptUserMode();
4176    InitReg(MISCREG_TLBI_ASIDE1_Xt)
4177      .writes(1).exceptUserMode();
4178    InitReg(MISCREG_TLBI_VAAE1_Xt)
4179      .writes(1).exceptUserMode();
4180    InitReg(MISCREG_TLBI_VALE1_Xt)
4181      .writes(1).exceptUserMode();
4182    InitReg(MISCREG_TLBI_VAALE1_Xt)
4183      .writes(1).exceptUserMode();
4184    InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4185      .hypWrite().monSecureWrite().monNonSecureWrite();
4186    InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4187      .hypWrite().monSecureWrite().monNonSecureWrite();
4188    InitReg(MISCREG_TLBI_ALLE2IS)
4189      .monNonSecureWrite().hypWrite();
4190    InitReg(MISCREG_TLBI_VAE2IS_Xt)
4191      .monNonSecureWrite().hypWrite();
4192    InitReg(MISCREG_TLBI_ALLE1IS)
4193      .hypWrite().monSecureWrite().monNonSecureWrite();
4194    InitReg(MISCREG_TLBI_VALE2IS_Xt)
4195      .monNonSecureWrite().hypWrite();
4196    InitReg(MISCREG_TLBI_VMALLS12E1IS)
4197      .hypWrite().monSecureWrite().monNonSecureWrite();
4198    InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4199      .hypWrite().monSecureWrite().monNonSecureWrite();
4200    InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4201      .hypWrite().monSecureWrite().monNonSecureWrite();
4202    InitReg(MISCREG_TLBI_ALLE2)
4203      .monNonSecureWrite().hypWrite();
4204    InitReg(MISCREG_TLBI_VAE2_Xt)
4205      .monNonSecureWrite().hypWrite();
4206    InitReg(MISCREG_TLBI_ALLE1)
4207      .hypWrite().monSecureWrite().monNonSecureWrite();
4208    InitReg(MISCREG_TLBI_VALE2_Xt)
4209      .monNonSecureWrite().hypWrite();
4210    InitReg(MISCREG_TLBI_VMALLS12E1)
4211      .hypWrite().monSecureWrite().monNonSecureWrite();
4212    InitReg(MISCREG_TLBI_ALLE3IS)
4213      .monSecureWrite().monNonSecureWrite();
4214    InitReg(MISCREG_TLBI_VAE3IS_Xt)
4215      .monSecureWrite().monNonSecureWrite();
4216    InitReg(MISCREG_TLBI_VALE3IS_Xt)
4217      .monSecureWrite().monNonSecureWrite();
4218    InitReg(MISCREG_TLBI_ALLE3)
4219      .monSecureWrite().monNonSecureWrite();
4220    InitReg(MISCREG_TLBI_VAE3_Xt)
4221      .monSecureWrite().monNonSecureWrite();
4222    InitReg(MISCREG_TLBI_VALE3_Xt)
4223      .monSecureWrite().monNonSecureWrite();
4224    InitReg(MISCREG_PMINTENSET_EL1)
4225      .allPrivileges().exceptUserMode()
4226      .mapsTo(MISCREG_PMINTENSET);
4227    InitReg(MISCREG_PMINTENCLR_EL1)
4228      .allPrivileges().exceptUserMode()
4229      .mapsTo(MISCREG_PMINTENCLR);
4230    InitReg(MISCREG_PMCR_EL0)
4231      .allPrivileges()
4232      .mapsTo(MISCREG_PMCR);
4233    InitReg(MISCREG_PMCNTENSET_EL0)
4234      .allPrivileges()
4235      .mapsTo(MISCREG_PMCNTENSET);
4236    InitReg(MISCREG_PMCNTENCLR_EL0)
4237      .allPrivileges()
4238      .mapsTo(MISCREG_PMCNTENCLR);
4239    InitReg(MISCREG_PMOVSCLR_EL0)
4240      .allPrivileges();
4241//    .mapsTo(MISCREG_PMOVSCLR);
4242    InitReg(MISCREG_PMSWINC_EL0)
4243      .writes(1).user()
4244      .mapsTo(MISCREG_PMSWINC);
4245    InitReg(MISCREG_PMSELR_EL0)
4246      .allPrivileges()
4247      .mapsTo(MISCREG_PMSELR);
4248    InitReg(MISCREG_PMCEID0_EL0)
4249      .reads(1).user()
4250      .mapsTo(MISCREG_PMCEID0);
4251    InitReg(MISCREG_PMCEID1_EL0)
4252      .reads(1).user()
4253      .mapsTo(MISCREG_PMCEID1);
4254    InitReg(MISCREG_PMCCNTR_EL0)
4255      .allPrivileges()
4256      .mapsTo(MISCREG_PMCCNTR);
4257    InitReg(MISCREG_PMXEVTYPER_EL0)
4258      .allPrivileges()
4259      .mapsTo(MISCREG_PMXEVTYPER);
4260    InitReg(MISCREG_PMCCFILTR_EL0)
4261      .allPrivileges();
4262    InitReg(MISCREG_PMXEVCNTR_EL0)
4263      .allPrivileges()
4264      .mapsTo(MISCREG_PMXEVCNTR);
4265    InitReg(MISCREG_PMUSERENR_EL0)
4266      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4267      .mapsTo(MISCREG_PMUSERENR);
4268    InitReg(MISCREG_PMOVSSET_EL0)
4269      .allPrivileges()
4270      .mapsTo(MISCREG_PMOVSSET);
4271    InitReg(MISCREG_MAIR_EL1)
4272      .allPrivileges().exceptUserMode()
4273      .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4274    InitReg(MISCREG_AMAIR_EL1)
4275      .allPrivileges().exceptUserMode()
4276      .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4277    InitReg(MISCREG_MAIR_EL2)
4278      .hyp().mon()
4279      .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4280    InitReg(MISCREG_AMAIR_EL2)
4281      .hyp().mon()
4282      .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4283    InitReg(MISCREG_MAIR_EL3)
4284      .mon();
4285    InitReg(MISCREG_AMAIR_EL3)
4286      .mon();
4287    InitReg(MISCREG_L2CTLR_EL1)
4288      .allPrivileges().exceptUserMode();
4289    InitReg(MISCREG_L2ECTLR_EL1)
4290      .allPrivileges().exceptUserMode();
4291    InitReg(MISCREG_VBAR_EL1)
4292      .allPrivileges().exceptUserMode()
4293      .mapsTo(MISCREG_VBAR_NS);
4294    InitReg(MISCREG_RVBAR_EL1)
4295      .allPrivileges().exceptUserMode().writes(0);
4296    InitReg(MISCREG_ISR_EL1)
4297      .allPrivileges().exceptUserMode().writes(0);
4298    InitReg(MISCREG_VBAR_EL2)
4299      .hyp().mon()
4300      .res0(0x7ff)
4301      .mapsTo(MISCREG_HVBAR);
4302    InitReg(MISCREG_RVBAR_EL2)
4303      .mon().hyp().writes(0);
4304    InitReg(MISCREG_VBAR_EL3)
4305      .mon();
4306    InitReg(MISCREG_RVBAR_EL3)
4307      .mon().writes(0);
4308    InitReg(MISCREG_RMR_EL3)
4309      .mon();
4310    InitReg(MISCREG_CONTEXTIDR_EL1)
4311      .allPrivileges().exceptUserMode()
4312      .mapsTo(MISCREG_CONTEXTIDR_NS);
4313    InitReg(MISCREG_TPIDR_EL1)
4314      .allPrivileges().exceptUserMode()
4315      .mapsTo(MISCREG_TPIDRPRW_NS);
4316    InitReg(MISCREG_TPIDR_EL0)
4317      .allPrivileges()
4318      .mapsTo(MISCREG_TPIDRURW_NS);
4319    InitReg(MISCREG_TPIDRRO_EL0)
4320      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4321      .mapsTo(MISCREG_TPIDRURO_NS);
4322    InitReg(MISCREG_TPIDR_EL2)
4323      .hyp().mon()
4324      .mapsTo(MISCREG_HTPIDR);
4325    InitReg(MISCREG_TPIDR_EL3)
4326      .mon();
4327    InitReg(MISCREG_CNTKCTL_EL1)
4328      .allPrivileges().exceptUserMode()
4329      .mapsTo(MISCREG_CNTKCTL);
4330    InitReg(MISCREG_CNTFRQ_EL0)
4331      .reads(1).mon()
4332      .mapsTo(MISCREG_CNTFRQ);
4333    InitReg(MISCREG_CNTPCT_EL0)
4334      .reads(1)
4335      .mapsTo(MISCREG_CNTPCT); /* 64b */
4336    InitReg(MISCREG_CNTVCT_EL0)
4337      .unverifiable()
4338      .reads(1)
4339      .mapsTo(MISCREG_CNTVCT); /* 64b */
4340    InitReg(MISCREG_CNTP_TVAL_EL0)
4341      .allPrivileges()
4342      .mapsTo(MISCREG_CNTP_TVAL_NS);
4343    InitReg(MISCREG_CNTP_CTL_EL0)
4344      .allPrivileges()
4345      .mapsTo(MISCREG_CNTP_CTL_NS);
4346    InitReg(MISCREG_CNTP_CVAL_EL0)
4347      .allPrivileges()
4348      .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
4349    InitReg(MISCREG_CNTV_TVAL_EL0)
4350      .allPrivileges()
4351      .mapsTo(MISCREG_CNTV_TVAL);
4352    InitReg(MISCREG_CNTV_CTL_EL0)
4353      .allPrivileges()
4354      .mapsTo(MISCREG_CNTV_CTL);
4355    InitReg(MISCREG_CNTV_CVAL_EL0)
4356      .allPrivileges()
4357      .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4358    InitReg(MISCREG_PMEVCNTR0_EL0)
4359      .allPrivileges();
4360//    .mapsTo(MISCREG_PMEVCNTR0);
4361    InitReg(MISCREG_PMEVCNTR1_EL0)
4362      .allPrivileges();
4363//    .mapsTo(MISCREG_PMEVCNTR1);
4364    InitReg(MISCREG_PMEVCNTR2_EL0)
4365      .allPrivileges();
4366//    .mapsTo(MISCREG_PMEVCNTR2);
4367    InitReg(MISCREG_PMEVCNTR3_EL0)
4368      .allPrivileges();
4369//    .mapsTo(MISCREG_PMEVCNTR3);
4370    InitReg(MISCREG_PMEVCNTR4_EL0)
4371      .allPrivileges();
4372//    .mapsTo(MISCREG_PMEVCNTR4);
4373    InitReg(MISCREG_PMEVCNTR5_EL0)
4374      .allPrivileges();
4375//    .mapsTo(MISCREG_PMEVCNTR5);
4376    InitReg(MISCREG_PMEVTYPER0_EL0)
4377      .allPrivileges();
4378//    .mapsTo(MISCREG_PMEVTYPER0);
4379    InitReg(MISCREG_PMEVTYPER1_EL0)
4380      .allPrivileges();
4381//    .mapsTo(MISCREG_PMEVTYPER1);
4382    InitReg(MISCREG_PMEVTYPER2_EL0)
4383      .allPrivileges();
4384//    .mapsTo(MISCREG_PMEVTYPER2);
4385    InitReg(MISCREG_PMEVTYPER3_EL0)
4386      .allPrivileges();
4387//    .mapsTo(MISCREG_PMEVTYPER3);
4388    InitReg(MISCREG_PMEVTYPER4_EL0)
4389      .allPrivileges();
4390//    .mapsTo(MISCREG_PMEVTYPER4);
4391    InitReg(MISCREG_PMEVTYPER5_EL0)
4392      .allPrivileges();
4393//    .mapsTo(MISCREG_PMEVTYPER5);
4394    InitReg(MISCREG_CNTVOFF_EL2)
4395      .hyp().mon()
4396      .mapsTo(MISCREG_CNTVOFF); /* 64b */
4397    InitReg(MISCREG_CNTHCTL_EL2)
4398      .mon().hyp()
4399      .mapsTo(MISCREG_CNTHCTL);
4400    InitReg(MISCREG_CNTHP_TVAL_EL2)
4401      .mon().hyp()
4402      .mapsTo(MISCREG_CNTHP_TVAL);
4403    InitReg(MISCREG_CNTHP_CTL_EL2)
4404      .mon().hyp()
4405      .mapsTo(MISCREG_CNTHP_CTL);
4406    InitReg(MISCREG_CNTHP_CVAL_EL2)
4407      .mon().hyp()
4408      .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4409    InitReg(MISCREG_CNTPS_TVAL_EL1)
4410      .mon().privSecure();
4411    InitReg(MISCREG_CNTPS_CTL_EL1)
4412      .mon().privSecure();
4413    InitReg(MISCREG_CNTPS_CVAL_EL1)
4414      .mon().privSecure();
4415    InitReg(MISCREG_IL1DATA0_EL1)
4416      .allPrivileges().exceptUserMode();
4417    InitReg(MISCREG_IL1DATA1_EL1)
4418      .allPrivileges().exceptUserMode();
4419    InitReg(MISCREG_IL1DATA2_EL1)
4420      .allPrivileges().exceptUserMode();
4421    InitReg(MISCREG_IL1DATA3_EL1)
4422      .allPrivileges().exceptUserMode();
4423    InitReg(MISCREG_DL1DATA0_EL1)
4424      .allPrivileges().exceptUserMode();
4425    InitReg(MISCREG_DL1DATA1_EL1)
4426      .allPrivileges().exceptUserMode();
4427    InitReg(MISCREG_DL1DATA2_EL1)
4428      .allPrivileges().exceptUserMode();
4429    InitReg(MISCREG_DL1DATA3_EL1)
4430      .allPrivileges().exceptUserMode();
4431    InitReg(MISCREG_DL1DATA4_EL1)
4432      .allPrivileges().exceptUserMode();
4433    InitReg(MISCREG_L2ACTLR_EL1)
4434      .allPrivileges().exceptUserMode();
4435    InitReg(MISCREG_CPUACTLR_EL1)
4436      .allPrivileges().exceptUserMode();
4437    InitReg(MISCREG_CPUECTLR_EL1)
4438      .allPrivileges().exceptUserMode();
4439    InitReg(MISCREG_CPUMERRSR_EL1)
4440      .allPrivileges().exceptUserMode();
4441    InitReg(MISCREG_L2MERRSR_EL1)
4442      .unimplemented()
4443      .warnNotFail()
4444      .allPrivileges().exceptUserMode();
4445    InitReg(MISCREG_CBAR_EL1)
4446      .allPrivileges().exceptUserMode().writes(0);
4447    InitReg(MISCREG_CONTEXTIDR_EL2)
4448      .mon().hyp();
4449
4450    // GICv3 AArch64
4451    InitReg(MISCREG_ICC_PMR_EL1)
4452        .res0(0xffffff00) // [31:8]
4453        .allPrivileges().exceptUserMode()
4454        .mapsTo(MISCREG_ICC_PMR);
4455    InitReg(MISCREG_ICC_IAR0_EL1)
4456        .allPrivileges().exceptUserMode().writes(0)
4457        .mapsTo(MISCREG_ICC_IAR0);
4458    InitReg(MISCREG_ICC_EOIR0_EL1)
4459        .allPrivileges().exceptUserMode().reads(0)
4460        .mapsTo(MISCREG_ICC_EOIR0);
4461    InitReg(MISCREG_ICC_HPPIR0_EL1)
4462        .allPrivileges().exceptUserMode().writes(0)
4463        .mapsTo(MISCREG_ICC_HPPIR0);
4464    InitReg(MISCREG_ICC_BPR0_EL1)
4465        .res0(0xfffffff8) // [31:3]
4466        .allPrivileges().exceptUserMode()
4467        .mapsTo(MISCREG_ICC_BPR0);
4468    InitReg(MISCREG_ICC_AP0R0_EL1)
4469        .allPrivileges().exceptUserMode()
4470        .mapsTo(MISCREG_ICC_AP0R0);
4471    InitReg(MISCREG_ICC_AP0R1_EL1)
4472        .allPrivileges().exceptUserMode()
4473        .mapsTo(MISCREG_ICC_AP0R1);
4474    InitReg(MISCREG_ICC_AP0R2_EL1)
4475        .allPrivileges().exceptUserMode()
4476        .mapsTo(MISCREG_ICC_AP0R2);
4477    InitReg(MISCREG_ICC_AP0R3_EL1)
4478        .allPrivileges().exceptUserMode()
4479        .mapsTo(MISCREG_ICC_AP0R3);
4480    InitReg(MISCREG_ICC_AP1R0_EL1)
4481        .banked()
4482        .mapsTo(MISCREG_ICC_AP1R0);
4483    InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4484        .bankedChild()
4485        .allPrivileges().exceptUserMode()
4486        .mapsTo(MISCREG_ICC_AP1R0_NS);
4487    InitReg(MISCREG_ICC_AP1R0_EL1_S)
4488        .bankedChild()
4489        .allPrivileges().exceptUserMode()
4490        .mapsTo(MISCREG_ICC_AP1R0_S);
4491    InitReg(MISCREG_ICC_AP1R1_EL1)
4492        .banked()
4493        .mapsTo(MISCREG_ICC_AP1R1);
4494    InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4495        .bankedChild()
4496        .allPrivileges().exceptUserMode()
4497        .mapsTo(MISCREG_ICC_AP1R1_NS);
4498    InitReg(MISCREG_ICC_AP1R1_EL1_S)
4499        .bankedChild()
4500        .allPrivileges().exceptUserMode()
4501        .mapsTo(MISCREG_ICC_AP1R1_S);
4502    InitReg(MISCREG_ICC_AP1R2_EL1)
4503        .banked()
4504        .mapsTo(MISCREG_ICC_AP1R2);
4505    InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4506        .bankedChild()
4507        .allPrivileges().exceptUserMode()
4508        .mapsTo(MISCREG_ICC_AP1R2_NS);
4509    InitReg(MISCREG_ICC_AP1R2_EL1_S)
4510        .bankedChild()
4511        .allPrivileges().exceptUserMode()
4512        .mapsTo(MISCREG_ICC_AP1R2_S);
4513    InitReg(MISCREG_ICC_AP1R3_EL1)
4514        .banked()
4515        .mapsTo(MISCREG_ICC_AP1R3);
4516    InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4517        .bankedChild()
4518        .allPrivileges().exceptUserMode()
4519        .mapsTo(MISCREG_ICC_AP1R3_NS);
4520    InitReg(MISCREG_ICC_AP1R3_EL1_S)
4521        .bankedChild()
4522        .allPrivileges().exceptUserMode()
4523        .mapsTo(MISCREG_ICC_AP1R3_S);
4524    InitReg(MISCREG_ICC_DIR_EL1)
4525        .res0(0xFF000000) // [31:24]
4526        .allPrivileges().exceptUserMode().reads(0)
4527        .mapsTo(MISCREG_ICC_DIR);
4528    InitReg(MISCREG_ICC_RPR_EL1)
4529        .allPrivileges().exceptUserMode().writes(0)
4530        .mapsTo(MISCREG_ICC_RPR);
4531    InitReg(MISCREG_ICC_SGI1R_EL1)
4532        .allPrivileges().exceptUserMode().reads(0)
4533        .mapsTo(MISCREG_ICC_SGI1R);
4534    InitReg(MISCREG_ICC_ASGI1R_EL1)
4535        .allPrivileges().exceptUserMode().reads(0)
4536        .mapsTo(MISCREG_ICC_ASGI1R);
4537    InitReg(MISCREG_ICC_SGI0R_EL1)
4538        .allPrivileges().exceptUserMode().reads(0)
4539        .mapsTo(MISCREG_ICC_SGI0R);
4540    InitReg(MISCREG_ICC_IAR1_EL1)
4541        .allPrivileges().exceptUserMode().writes(0)
4542        .mapsTo(MISCREG_ICC_IAR1);
4543    InitReg(MISCREG_ICC_EOIR1_EL1)
4544        .res0(0xFF000000) // [31:24]
4545        .allPrivileges().exceptUserMode().reads(0)
4546        .mapsTo(MISCREG_ICC_EOIR1);
4547    InitReg(MISCREG_ICC_HPPIR1_EL1)
4548        .allPrivileges().exceptUserMode().writes(0)
4549        .mapsTo(MISCREG_ICC_HPPIR1);
4550    InitReg(MISCREG_ICC_BPR1_EL1)
4551        .banked()
4552        .mapsTo(MISCREG_ICC_BPR1);
4553    InitReg(MISCREG_ICC_BPR1_EL1_NS)
4554        .bankedChild()
4555        .res0(0xfffffff8) // [31:3]
4556        .allPrivileges().exceptUserMode()
4557        .mapsTo(MISCREG_ICC_BPR1_NS);
4558    InitReg(MISCREG_ICC_BPR1_EL1_S)
4559        .bankedChild()
4560        .res0(0xfffffff8) // [31:3]
4561        .secure().exceptUserMode()
4562        .mapsTo(MISCREG_ICC_BPR1_S);
4563    InitReg(MISCREG_ICC_CTLR_EL1)
4564        .banked()
4565        .mapsTo(MISCREG_ICC_CTLR);
4566    InitReg(MISCREG_ICC_CTLR_EL1_NS)
4567        .bankedChild()
4568        .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4569        .allPrivileges().exceptUserMode()
4570        .mapsTo(MISCREG_ICC_CTLR_NS);
4571    InitReg(MISCREG_ICC_CTLR_EL1_S)
4572        .bankedChild()
4573        .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4574        .secure().exceptUserMode()
4575        .mapsTo(MISCREG_ICC_CTLR_S);
4576    InitReg(MISCREG_ICC_SRE_EL1)
4577        .banked()
4578        .mapsTo(MISCREG_ICC_SRE);
4579    InitReg(MISCREG_ICC_SRE_EL1_NS)
4580        .bankedChild()
4581        .res0(0xFFFFFFF8) // [31:3]
4582        .allPrivileges().exceptUserMode()
4583        .mapsTo(MISCREG_ICC_SRE_NS);
4584    InitReg(MISCREG_ICC_SRE_EL1_S)
4585        .bankedChild()
4586        .res0(0xFFFFFFF8) // [31:3]
4587        .secure().exceptUserMode()
4588        .mapsTo(MISCREG_ICC_SRE_S);
4589    InitReg(MISCREG_ICC_IGRPEN0_EL1)
4590        .res0(0xFFFFFFFE) // [31:1]
4591        .allPrivileges().exceptUserMode()
4592        .mapsTo(MISCREG_ICC_IGRPEN0);
4593    InitReg(MISCREG_ICC_IGRPEN1_EL1)
4594        .banked()
4595        .mapsTo(MISCREG_ICC_IGRPEN1);
4596    InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4597        .bankedChild()
4598        .res0(0xFFFFFFFE) // [31:1]
4599        .allPrivileges().exceptUserMode()
4600        .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4601    InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4602        .bankedChild()
4603        .res0(0xFFFFFFFE) // [31:1]
4604        .secure().exceptUserMode()
4605        .mapsTo(MISCREG_ICC_IGRPEN1_S);
4606    InitReg(MISCREG_ICC_SRE_EL2)
4607        .hyp().mon()
4608        .mapsTo(MISCREG_ICC_HSRE);
4609    InitReg(MISCREG_ICC_CTLR_EL3)
4610        .allPrivileges().exceptUserMode()
4611        .mapsTo(MISCREG_ICC_MCTLR);
4612    InitReg(MISCREG_ICC_SRE_EL3)
4613        .allPrivileges().exceptUserMode()
4614        .mapsTo(MISCREG_ICC_MSRE);
4615    InitReg(MISCREG_ICC_IGRPEN1_EL3)
4616        .allPrivileges().exceptUserMode()
4617        .mapsTo(MISCREG_ICC_MGRPEN1);
4618
4619    InitReg(MISCREG_ICH_AP0R0_EL2)
4620        .hyp().mon()
4621        .mapsTo(MISCREG_ICH_AP0R0);
4622    InitReg(MISCREG_ICH_AP0R1_EL2)
4623        .hyp().mon()
4624        .unimplemented()
4625        .mapsTo(MISCREG_ICH_AP0R1);
4626    InitReg(MISCREG_ICH_AP0R2_EL2)
4627        .hyp().mon()
4628        .unimplemented()
4629        .mapsTo(MISCREG_ICH_AP0R2);
4630    InitReg(MISCREG_ICH_AP0R3_EL2)
4631        .hyp().mon()
4632        .unimplemented()
4633        .mapsTo(MISCREG_ICH_AP0R3);
4634    InitReg(MISCREG_ICH_AP1R0_EL2)
4635        .hyp().mon()
4636        .mapsTo(MISCREG_ICH_AP1R0);
4637    InitReg(MISCREG_ICH_AP1R1_EL2)
4638        .hyp().mon()
4639        .unimplemented()
4640        .mapsTo(MISCREG_ICH_AP1R1);
4641    InitReg(MISCREG_ICH_AP1R2_EL2)
4642        .hyp().mon()
4643        .unimplemented()
4644        .mapsTo(MISCREG_ICH_AP1R2);
4645    InitReg(MISCREG_ICH_AP1R3_EL2)
4646        .hyp().mon()
4647        .unimplemented()
4648        .mapsTo(MISCREG_ICH_AP1R3);
4649    InitReg(MISCREG_ICH_HCR_EL2)
4650        .hyp().mon()
4651        .mapsTo(MISCREG_ICH_HCR);
4652    InitReg(MISCREG_ICH_VTR_EL2)
4653        .hyp().mon().writes(0)
4654        .mapsTo(MISCREG_ICH_VTR);
4655    InitReg(MISCREG_ICH_MISR_EL2)
4656        .hyp().mon().writes(0)
4657        .mapsTo(MISCREG_ICH_MISR);
4658    InitReg(MISCREG_ICH_EISR_EL2)
4659        .hyp().mon().writes(0)
4660        .mapsTo(MISCREG_ICH_EISR);
4661    InitReg(MISCREG_ICH_ELRSR_EL2)
4662        .hyp().mon().writes(0)
4663        .mapsTo(MISCREG_ICH_ELRSR);
4664    InitReg(MISCREG_ICH_VMCR_EL2)
4665        .hyp().mon()
4666        .mapsTo(MISCREG_ICH_VMCR);
4667    InitReg(MISCREG_ICH_LR0_EL2)
4668        .hyp().mon()
4669        .allPrivileges().exceptUserMode();
4670    InitReg(MISCREG_ICH_LR1_EL2)
4671        .hyp().mon()
4672        .allPrivileges().exceptUserMode();
4673    InitReg(MISCREG_ICH_LR2_EL2)
4674        .hyp().mon()
4675        .allPrivileges().exceptUserMode();
4676    InitReg(MISCREG_ICH_LR3_EL2)
4677        .hyp().mon()
4678        .allPrivileges().exceptUserMode();
4679    InitReg(MISCREG_ICH_LR4_EL2)
4680        .hyp().mon()
4681        .allPrivileges().exceptUserMode();
4682    InitReg(MISCREG_ICH_LR5_EL2)
4683        .hyp().mon()
4684        .allPrivileges().exceptUserMode();
4685    InitReg(MISCREG_ICH_LR6_EL2)
4686        .hyp().mon()
4687        .allPrivileges().exceptUserMode();
4688    InitReg(MISCREG_ICH_LR7_EL2)
4689        .hyp().mon()
4690        .allPrivileges().exceptUserMode();
4691    InitReg(MISCREG_ICH_LR8_EL2)
4692        .hyp().mon()
4693        .allPrivileges().exceptUserMode();
4694    InitReg(MISCREG_ICH_LR9_EL2)
4695        .hyp().mon()
4696        .allPrivileges().exceptUserMode();
4697    InitReg(MISCREG_ICH_LR10_EL2)
4698        .hyp().mon()
4699        .allPrivileges().exceptUserMode();
4700    InitReg(MISCREG_ICH_LR11_EL2)
4701        .hyp().mon()
4702        .allPrivileges().exceptUserMode();
4703    InitReg(MISCREG_ICH_LR12_EL2)
4704        .hyp().mon()
4705        .allPrivileges().exceptUserMode();
4706    InitReg(MISCREG_ICH_LR13_EL2)
4707        .hyp().mon()
4708        .allPrivileges().exceptUserMode();
4709    InitReg(MISCREG_ICH_LR14_EL2)
4710        .hyp().mon()
4711        .allPrivileges().exceptUserMode();
4712    InitReg(MISCREG_ICH_LR15_EL2)
4713        .hyp().mon()
4714        .allPrivileges().exceptUserMode();
4715
4716    // GICv3 AArch32
4717    InitReg(MISCREG_ICC_AP0R0)
4718        .allPrivileges().exceptUserMode();
4719    InitReg(MISCREG_ICC_AP0R1)
4720        .allPrivileges().exceptUserMode();
4721    InitReg(MISCREG_ICC_AP0R2)
4722        .allPrivileges().exceptUserMode();
4723    InitReg(MISCREG_ICC_AP0R3)
4724        .allPrivileges().exceptUserMode();
4725    InitReg(MISCREG_ICC_AP1R0)
4726        .allPrivileges().exceptUserMode();
4727    InitReg(MISCREG_ICC_AP1R0_NS)
4728        .allPrivileges().exceptUserMode();
4729    InitReg(MISCREG_ICC_AP1R0_S)
4730        .allPrivileges().exceptUserMode();
4731    InitReg(MISCREG_ICC_AP1R1)
4732        .allPrivileges().exceptUserMode();
4733    InitReg(MISCREG_ICC_AP1R1_NS)
4734        .allPrivileges().exceptUserMode();
4735    InitReg(MISCREG_ICC_AP1R1_S)
4736        .allPrivileges().exceptUserMode();
4737    InitReg(MISCREG_ICC_AP1R2)
4738        .allPrivileges().exceptUserMode();
4739    InitReg(MISCREG_ICC_AP1R2_NS)
4740        .allPrivileges().exceptUserMode();
4741    InitReg(MISCREG_ICC_AP1R2_S)
4742        .allPrivileges().exceptUserMode();
4743    InitReg(MISCREG_ICC_AP1R3)
4744        .allPrivileges().exceptUserMode();
4745    InitReg(MISCREG_ICC_AP1R3_NS)
4746        .allPrivileges().exceptUserMode();
4747    InitReg(MISCREG_ICC_AP1R3_S)
4748        .allPrivileges().exceptUserMode();
4749    InitReg(MISCREG_ICC_ASGI1R)
4750        .allPrivileges().exceptUserMode().reads(0);
4751    InitReg(MISCREG_ICC_BPR0)
4752        .allPrivileges().exceptUserMode();
4753    InitReg(MISCREG_ICC_BPR1)
4754        .allPrivileges().exceptUserMode();
4755    InitReg(MISCREG_ICC_BPR1_NS)
4756        .allPrivileges().exceptUserMode();
4757    InitReg(MISCREG_ICC_BPR1_S)
4758        .allPrivileges().exceptUserMode();
4759    InitReg(MISCREG_ICC_CTLR)
4760        .allPrivileges().exceptUserMode();
4761    InitReg(MISCREG_ICC_CTLR_NS)
4762        .allPrivileges().exceptUserMode();
4763    InitReg(MISCREG_ICC_CTLR_S)
4764        .allPrivileges().exceptUserMode();
4765    InitReg(MISCREG_ICC_DIR)
4766        .allPrivileges().exceptUserMode().reads(0);
4767    InitReg(MISCREG_ICC_EOIR0)
4768        .allPrivileges().exceptUserMode().reads(0);
4769    InitReg(MISCREG_ICC_EOIR1)
4770        .allPrivileges().exceptUserMode().reads(0);
4771    InitReg(MISCREG_ICC_HPPIR0)
4772        .allPrivileges().exceptUserMode().writes(0);
4773    InitReg(MISCREG_ICC_HPPIR1)
4774        .allPrivileges().exceptUserMode().writes(0);
4775    InitReg(MISCREG_ICC_HSRE)
4776        .allPrivileges().exceptUserMode();
4777    InitReg(MISCREG_ICC_IAR0)
4778        .allPrivileges().exceptUserMode().writes(0);
4779    InitReg(MISCREG_ICC_IAR1)
4780        .allPrivileges().exceptUserMode().writes(0);
4781    InitReg(MISCREG_ICC_IGRPEN0)
4782        .allPrivileges().exceptUserMode();
4783    InitReg(MISCREG_ICC_IGRPEN1)
4784        .allPrivileges().exceptUserMode();
4785    InitReg(MISCREG_ICC_IGRPEN1_NS)
4786        .allPrivileges().exceptUserMode();
4787    InitReg(MISCREG_ICC_IGRPEN1_S)
4788        .allPrivileges().exceptUserMode();
4789    InitReg(MISCREG_ICC_MCTLR)
4790        .allPrivileges().exceptUserMode();
4791    InitReg(MISCREG_ICC_MGRPEN1)
4792        .allPrivileges().exceptUserMode();
4793    InitReg(MISCREG_ICC_MSRE)
4794        .allPrivileges().exceptUserMode();
4795    InitReg(MISCREG_ICC_PMR)
4796        .allPrivileges().exceptUserMode();
4797    InitReg(MISCREG_ICC_RPR)
4798        .allPrivileges().exceptUserMode().writes(0);
4799    InitReg(MISCREG_ICC_SGI0R)
4800        .allPrivileges().exceptUserMode().reads(0);
4801    InitReg(MISCREG_ICC_SGI1R)
4802        .allPrivileges().exceptUserMode().reads(0);
4803    InitReg(MISCREG_ICC_SRE)
4804        .allPrivileges().exceptUserMode();
4805    InitReg(MISCREG_ICC_SRE_NS)
4806        .allPrivileges().exceptUserMode();
4807    InitReg(MISCREG_ICC_SRE_S)
4808        .allPrivileges().exceptUserMode();
4809
4810    InitReg(MISCREG_ICH_AP0R0)
4811        .hyp().mon();
4812    InitReg(MISCREG_ICH_AP0R1)
4813        .hyp().mon();
4814    InitReg(MISCREG_ICH_AP0R2)
4815        .hyp().mon();
4816    InitReg(MISCREG_ICH_AP0R3)
4817        .hyp().mon();
4818    InitReg(MISCREG_ICH_AP1R0)
4819        .hyp().mon();
4820    InitReg(MISCREG_ICH_AP1R1)
4821        .hyp().mon();
4822    InitReg(MISCREG_ICH_AP1R2)
4823        .hyp().mon();
4824    InitReg(MISCREG_ICH_AP1R3)
4825        .hyp().mon();
4826    InitReg(MISCREG_ICH_HCR)
4827        .hyp().mon();
4828    InitReg(MISCREG_ICH_VTR)
4829        .hyp().mon().writes(0);
4830    InitReg(MISCREG_ICH_MISR)
4831        .hyp().mon().writes(0);
4832    InitReg(MISCREG_ICH_EISR)
4833        .hyp().mon().writes(0);
4834    InitReg(MISCREG_ICH_ELRSR)
4835        .hyp().mon().writes(0);
4836    InitReg(MISCREG_ICH_VMCR)
4837        .hyp().mon();
4838    InitReg(MISCREG_ICH_LR0)
4839        .hyp().mon();
4840    InitReg(MISCREG_ICH_LR1)
4841        .hyp().mon();
4842    InitReg(MISCREG_ICH_LR2)
4843        .hyp().mon();
4844    InitReg(MISCREG_ICH_LR3)
4845        .hyp().mon();
4846    InitReg(MISCREG_ICH_LR4)
4847        .hyp().mon();
4848    InitReg(MISCREG_ICH_LR5)
4849        .hyp().mon();
4850    InitReg(MISCREG_ICH_LR6)
4851        .hyp().mon();
4852    InitReg(MISCREG_ICH_LR7)
4853        .hyp().mon();
4854    InitReg(MISCREG_ICH_LR8)
4855        .hyp().mon();
4856    InitReg(MISCREG_ICH_LR9)
4857        .hyp().mon();
4858    InitReg(MISCREG_ICH_LR10)
4859        .hyp().mon();
4860    InitReg(MISCREG_ICH_LR11)
4861        .hyp().mon();
4862    InitReg(MISCREG_ICH_LR12)
4863        .hyp().mon();
4864    InitReg(MISCREG_ICH_LR13)
4865        .hyp().mon();
4866    InitReg(MISCREG_ICH_LR14)
4867        .hyp().mon();
4868    InitReg(MISCREG_ICH_LR15)
4869        .hyp().mon();
4870    InitReg(MISCREG_ICH_LRC0)
4871        .mapsTo(MISCREG_ICH_LR0)
4872        .hyp().mon();
4873    InitReg(MISCREG_ICH_LRC1)
4874        .mapsTo(MISCREG_ICH_LR1)
4875        .hyp().mon();
4876    InitReg(MISCREG_ICH_LRC2)
4877        .mapsTo(MISCREG_ICH_LR2)
4878        .hyp().mon();
4879    InitReg(MISCREG_ICH_LRC3)
4880        .mapsTo(MISCREG_ICH_LR3)
4881        .hyp().mon();
4882    InitReg(MISCREG_ICH_LRC4)
4883        .mapsTo(MISCREG_ICH_LR4)
4884        .hyp().mon();
4885    InitReg(MISCREG_ICH_LRC5)
4886        .mapsTo(MISCREG_ICH_LR5)
4887        .hyp().mon();
4888    InitReg(MISCREG_ICH_LRC6)
4889        .mapsTo(MISCREG_ICH_LR6)
4890        .hyp().mon();
4891    InitReg(MISCREG_ICH_LRC7)
4892        .mapsTo(MISCREG_ICH_LR7)
4893        .hyp().mon();
4894    InitReg(MISCREG_ICH_LRC8)
4895        .mapsTo(MISCREG_ICH_LR8)
4896        .hyp().mon();
4897    InitReg(MISCREG_ICH_LRC9)
4898        .mapsTo(MISCREG_ICH_LR9)
4899        .hyp().mon();
4900    InitReg(MISCREG_ICH_LRC10)
4901        .mapsTo(MISCREG_ICH_LR10)
4902        .hyp().mon();
4903    InitReg(MISCREG_ICH_LRC11)
4904        .mapsTo(MISCREG_ICH_LR11)
4905        .hyp().mon();
4906    InitReg(MISCREG_ICH_LRC12)
4907        .mapsTo(MISCREG_ICH_LR12)
4908        .hyp().mon();
4909    InitReg(MISCREG_ICH_LRC13)
4910        .mapsTo(MISCREG_ICH_LR13)
4911        .hyp().mon();
4912    InitReg(MISCREG_ICH_LRC14)
4913        .mapsTo(MISCREG_ICH_LR14)
4914        .hyp().mon();
4915    InitReg(MISCREG_ICH_LRC15)
4916        .mapsTo(MISCREG_ICH_LR15)
4917        .hyp().mon();
4918
4919    InitReg(MISCREG_CNTHV_CTL_EL2)
4920      .mon().hyp();
4921    InitReg(MISCREG_CNTHV_CVAL_EL2)
4922      .mon().hyp();
4923    InitReg(MISCREG_CNTHV_TVAL_EL2)
4924      .mon().hyp();
4925
4926    // Dummy registers
4927    InitReg(MISCREG_NOP)
4928      .allPrivileges();
4929    InitReg(MISCREG_RAZ)
4930      .allPrivileges().exceptUserMode().writes(0);
4931    InitReg(MISCREG_CP14_UNIMPL)
4932      .unimplemented()
4933      .warnNotFail();
4934    InitReg(MISCREG_CP15_UNIMPL)
4935      .unimplemented()
4936      .warnNotFail();
4937    InitReg(MISCREG_UNKNOWN);
4938    InitReg(MISCREG_IMPDEF_UNIMPL)
4939      .unimplemented()
4940      .warnNotFail(impdefAsNop);
4941
4942    // RAS extension (unimplemented)
4943    InitReg(MISCREG_ERRIDR_EL1)
4944      .unimplemented()
4945      .warnNotFail();
4946    InitReg(MISCREG_ERRSELR_EL1)
4947      .unimplemented()
4948      .warnNotFail();
4949    InitReg(MISCREG_ERXFR_EL1)
4950      .unimplemented()
4951      .warnNotFail();
4952    InitReg(MISCREG_ERXCTLR_EL1)
4953      .unimplemented()
4954      .warnNotFail();
4955    InitReg(MISCREG_ERXSTATUS_EL1)
4956      .unimplemented()
4957      .warnNotFail();
4958    InitReg(MISCREG_ERXADDR_EL1)
4959      .unimplemented()
4960      .warnNotFail();
4961    InitReg(MISCREG_ERXMISC0_EL1)
4962      .unimplemented()
4963      .warnNotFail();
4964    InitReg(MISCREG_ERXMISC1_EL1)
4965      .unimplemented()
4966      .warnNotFail();
4967    InitReg(MISCREG_DISR_EL1)
4968      .unimplemented()
4969      .warnNotFail();
4970    InitReg(MISCREG_VSESR_EL2)
4971      .unimplemented()
4972      .warnNotFail();
4973    InitReg(MISCREG_VDISR_EL2)
4974      .unimplemented()
4975      .warnNotFail();
4976
4977    // Register mappings for some unimplemented registers:
4978    // ESR_EL1 -> DFSR
4979    // RMR_EL1 -> RMR
4980    // RMR_EL2 -> HRMR
4981    // DBGDTR_EL0 -> DBGDTR{R or T}Xint
4982    // DBGDTRRX_EL0 -> DBGDTRRXint
4983    // DBGDTRTX_EL0 -> DBGDTRRXint
4984    // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
4985
4986    completed = true;
4987}
4988
4989} // namespace ArmISA
4990