miscregs.cc revision 13116:d3c3e2533928
1/* 2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 * Giacomo Gabrielli 40 */ 41 42#include "arch/arm/miscregs.hh" 43 44#include <tuple> 45 46#include "arch/arm/isa.hh" 47#include "base/logging.hh" 48#include "cpu/thread_context.hh" 49#include "sim/full_system.hh" 50 51namespace ArmISA 52{ 53 54MiscRegIndex 55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 56{ 57 switch(crn) { 58 case 0: 59 switch (opc1) { 60 case 0: 61 switch (opc2) { 62 case 0: 63 switch (crm) { 64 case 0: 65 return MISCREG_DBGDIDR; 66 case 1: 67 return MISCREG_DBGDSCRint; 68 } 69 break; 70 } 71 break; 72 case 7: 73 switch (opc2) { 74 case 0: 75 switch (crm) { 76 case 0: 77 return MISCREG_JIDR; 78 } 79 break; 80 } 81 break; 82 } 83 break; 84 case 1: 85 switch (opc1) { 86 case 6: 87 switch (crm) { 88 case 0: 89 switch (opc2) { 90 case 0: 91 return MISCREG_TEEHBR; 92 } 93 break; 94 } 95 break; 96 case 7: 97 switch (crm) { 98 case 0: 99 switch (opc2) { 100 case 0: 101 return MISCREG_JOSCR; 102 } 103 break; 104 } 105 break; 106 } 107 break; 108 case 2: 109 switch (opc1) { 110 case 7: 111 switch (crm) { 112 case 0: 113 switch (opc2) { 114 case 0: 115 return MISCREG_JMCR; 116 } 117 break; 118 } 119 break; 120 } 121 break; 122 } 123 // If we get here then it must be a register that we haven't implemented 124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 125 crn, opc1, crm, opc2); 126 return MISCREG_CP14_UNIMPL; 127} 128 129using namespace std; 130 131MiscRegIndex 132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 133{ 134 switch (crn) { 135 case 0: 136 switch (opc1) { 137 case 0: 138 switch (crm) { 139 case 0: 140 switch (opc2) { 141 case 1: 142 return MISCREG_CTR; 143 case 2: 144 return MISCREG_TCMTR; 145 case 3: 146 return MISCREG_TLBTR; 147 case 5: 148 return MISCREG_MPIDR; 149 case 6: 150 return MISCREG_REVIDR; 151 default: 152 return MISCREG_MIDR; 153 } 154 break; 155 case 1: 156 switch (opc2) { 157 case 0: 158 return MISCREG_ID_PFR0; 159 case 1: 160 return MISCREG_ID_PFR1; 161 case 2: 162 return MISCREG_ID_DFR0; 163 case 3: 164 return MISCREG_ID_AFR0; 165 case 4: 166 return MISCREG_ID_MMFR0; 167 case 5: 168 return MISCREG_ID_MMFR1; 169 case 6: 170 return MISCREG_ID_MMFR2; 171 case 7: 172 return MISCREG_ID_MMFR3; 173 } 174 break; 175 case 2: 176 switch (opc2) { 177 case 0: 178 return MISCREG_ID_ISAR0; 179 case 1: 180 return MISCREG_ID_ISAR1; 181 case 2: 182 return MISCREG_ID_ISAR2; 183 case 3: 184 return MISCREG_ID_ISAR3; 185 case 4: 186 return MISCREG_ID_ISAR4; 187 case 5: 188 return MISCREG_ID_ISAR5; 189 case 6: 190 case 7: 191 return MISCREG_RAZ; // read as zero 192 } 193 break; 194 default: 195 return MISCREG_RAZ; // read as zero 196 } 197 break; 198 case 1: 199 if (crm == 0) { 200 switch (opc2) { 201 case 0: 202 return MISCREG_CCSIDR; 203 case 1: 204 return MISCREG_CLIDR; 205 case 7: 206 return MISCREG_AIDR; 207 } 208 } 209 break; 210 case 2: 211 if (crm == 0 && opc2 == 0) { 212 return MISCREG_CSSELR; 213 } 214 break; 215 case 4: 216 if (crm == 0) { 217 if (opc2 == 0) 218 return MISCREG_VPIDR; 219 else if (opc2 == 5) 220 return MISCREG_VMPIDR; 221 } 222 break; 223 } 224 break; 225 case 1: 226 if (opc1 == 0) { 227 if (crm == 0) { 228 switch (opc2) { 229 case 0: 230 return MISCREG_SCTLR; 231 case 1: 232 return MISCREG_ACTLR; 233 case 0x2: 234 return MISCREG_CPACR; 235 } 236 } else if (crm == 1) { 237 switch (opc2) { 238 case 0: 239 return MISCREG_SCR; 240 case 1: 241 return MISCREG_SDER; 242 case 2: 243 return MISCREG_NSACR; 244 } 245 } 246 } else if (opc1 == 4) { 247 if (crm == 0) { 248 if (opc2 == 0) 249 return MISCREG_HSCTLR; 250 else if (opc2 == 1) 251 return MISCREG_HACTLR; 252 } else if (crm == 1) { 253 switch (opc2) { 254 case 0: 255 return MISCREG_HCR; 256 case 1: 257 return MISCREG_HDCR; 258 case 2: 259 return MISCREG_HCPTR; 260 case 3: 261 return MISCREG_HSTR; 262 case 7: 263 return MISCREG_HACR; 264 } 265 } 266 } 267 break; 268 case 2: 269 if (opc1 == 0 && crm == 0) { 270 switch (opc2) { 271 case 0: 272 return MISCREG_TTBR0; 273 case 1: 274 return MISCREG_TTBR1; 275 case 2: 276 return MISCREG_TTBCR; 277 } 278 } else if (opc1 == 4) { 279 if (crm == 0 && opc2 == 2) 280 return MISCREG_HTCR; 281 else if (crm == 1 && opc2 == 2) 282 return MISCREG_VTCR; 283 } 284 break; 285 case 3: 286 if (opc1 == 0 && crm == 0 && opc2 == 0) { 287 return MISCREG_DACR; 288 } 289 break; 290 case 5: 291 if (opc1 == 0) { 292 if (crm == 0) { 293 if (opc2 == 0) { 294 return MISCREG_DFSR; 295 } else if (opc2 == 1) { 296 return MISCREG_IFSR; 297 } 298 } else if (crm == 1) { 299 if (opc2 == 0) { 300 return MISCREG_ADFSR; 301 } else if (opc2 == 1) { 302 return MISCREG_AIFSR; 303 } 304 } 305 } else if (opc1 == 4) { 306 if (crm == 1) { 307 if (opc2 == 0) 308 return MISCREG_HADFSR; 309 else if (opc2 == 1) 310 return MISCREG_HAIFSR; 311 } else if (crm == 2 && opc2 == 0) { 312 return MISCREG_HSR; 313 } 314 } 315 break; 316 case 6: 317 if (opc1 == 0 && crm == 0) { 318 switch (opc2) { 319 case 0: 320 return MISCREG_DFAR; 321 case 2: 322 return MISCREG_IFAR; 323 } 324 } else if (opc1 == 4 && crm == 0) { 325 switch (opc2) { 326 case 0: 327 return MISCREG_HDFAR; 328 case 2: 329 return MISCREG_HIFAR; 330 case 4: 331 return MISCREG_HPFAR; 332 } 333 } 334 break; 335 case 7: 336 if (opc1 == 0) { 337 switch (crm) { 338 case 0: 339 if (opc2 == 4) { 340 return MISCREG_NOP; 341 } 342 break; 343 case 1: 344 switch (opc2) { 345 case 0: 346 return MISCREG_ICIALLUIS; 347 case 6: 348 return MISCREG_BPIALLIS; 349 } 350 break; 351 case 4: 352 if (opc2 == 0) { 353 return MISCREG_PAR; 354 } 355 break; 356 case 5: 357 switch (opc2) { 358 case 0: 359 return MISCREG_ICIALLU; 360 case 1: 361 return MISCREG_ICIMVAU; 362 case 4: 363 return MISCREG_CP15ISB; 364 case 6: 365 return MISCREG_BPIALL; 366 case 7: 367 return MISCREG_BPIMVA; 368 } 369 break; 370 case 6: 371 if (opc2 == 1) { 372 return MISCREG_DCIMVAC; 373 } else if (opc2 == 2) { 374 return MISCREG_DCISW; 375 } 376 break; 377 case 8: 378 switch (opc2) { 379 case 0: 380 return MISCREG_ATS1CPR; 381 case 1: 382 return MISCREG_ATS1CPW; 383 case 2: 384 return MISCREG_ATS1CUR; 385 case 3: 386 return MISCREG_ATS1CUW; 387 case 4: 388 return MISCREG_ATS12NSOPR; 389 case 5: 390 return MISCREG_ATS12NSOPW; 391 case 6: 392 return MISCREG_ATS12NSOUR; 393 case 7: 394 return MISCREG_ATS12NSOUW; 395 } 396 break; 397 case 10: 398 switch (opc2) { 399 case 1: 400 return MISCREG_DCCMVAC; 401 case 2: 402 return MISCREG_DCCSW; 403 case 4: 404 return MISCREG_CP15DSB; 405 case 5: 406 return MISCREG_CP15DMB; 407 } 408 break; 409 case 11: 410 if (opc2 == 1) { 411 return MISCREG_DCCMVAU; 412 } 413 break; 414 case 13: 415 if (opc2 == 1) { 416 return MISCREG_NOP; 417 } 418 break; 419 case 14: 420 if (opc2 == 1) { 421 return MISCREG_DCCIMVAC; 422 } else if (opc2 == 2) { 423 return MISCREG_DCCISW; 424 } 425 break; 426 } 427 } else if (opc1 == 4 && crm == 8) { 428 if (opc2 == 0) 429 return MISCREG_ATS1HR; 430 else if (opc2 == 1) 431 return MISCREG_ATS1HW; 432 } 433 break; 434 case 8: 435 if (opc1 == 0) { 436 switch (crm) { 437 case 3: 438 switch (opc2) { 439 case 0: 440 return MISCREG_TLBIALLIS; 441 case 1: 442 return MISCREG_TLBIMVAIS; 443 case 2: 444 return MISCREG_TLBIASIDIS; 445 case 3: 446 return MISCREG_TLBIMVAAIS; 447 case 5: 448 return MISCREG_TLBIMVALIS; 449 case 7: 450 return MISCREG_TLBIMVAALIS; 451 } 452 break; 453 case 5: 454 switch (opc2) { 455 case 0: 456 return MISCREG_ITLBIALL; 457 case 1: 458 return MISCREG_ITLBIMVA; 459 case 2: 460 return MISCREG_ITLBIASID; 461 } 462 break; 463 case 6: 464 switch (opc2) { 465 case 0: 466 return MISCREG_DTLBIALL; 467 case 1: 468 return MISCREG_DTLBIMVA; 469 case 2: 470 return MISCREG_DTLBIASID; 471 } 472 break; 473 case 7: 474 switch (opc2) { 475 case 0: 476 return MISCREG_TLBIALL; 477 case 1: 478 return MISCREG_TLBIMVA; 479 case 2: 480 return MISCREG_TLBIASID; 481 case 3: 482 return MISCREG_TLBIMVAA; 483 case 5: 484 return MISCREG_TLBIMVAL; 485 case 7: 486 return MISCREG_TLBIMVAAL; 487 } 488 break; 489 } 490 } else if (opc1 == 4) { 491 if (crm == 0) { 492 switch (opc2) { 493 case 1: 494 return MISCREG_TLBIIPAS2IS; 495 case 5: 496 return MISCREG_TLBIIPAS2LIS; 497 } 498 } else if (crm == 3) { 499 switch (opc2) { 500 case 0: 501 return MISCREG_TLBIALLHIS; 502 case 1: 503 return MISCREG_TLBIMVAHIS; 504 case 4: 505 return MISCREG_TLBIALLNSNHIS; 506 case 5: 507 return MISCREG_TLBIMVALHIS; 508 } 509 } else if (crm == 4) { 510 switch (opc2) { 511 case 1: 512 return MISCREG_TLBIIPAS2; 513 case 5: 514 return MISCREG_TLBIIPAS2L; 515 } 516 } else if (crm == 7) { 517 switch (opc2) { 518 case 0: 519 return MISCREG_TLBIALLH; 520 case 1: 521 return MISCREG_TLBIMVAH; 522 case 4: 523 return MISCREG_TLBIALLNSNH; 524 case 5: 525 return MISCREG_TLBIMVALH; 526 } 527 } 528 } 529 break; 530 case 9: 531 // Every cop register with CRn = 9 and CRm in 532 // {0-2}, {5-8} is implementation defined regardless 533 // of opc1 and opc2. 534 switch (crm) { 535 case 0: 536 case 1: 537 case 2: 538 case 5: 539 case 6: 540 case 7: 541 case 8: 542 return MISCREG_IMPDEF_UNIMPL; 543 } 544 if (opc1 == 0) { 545 switch (crm) { 546 case 12: 547 switch (opc2) { 548 case 0: 549 return MISCREG_PMCR; 550 case 1: 551 return MISCREG_PMCNTENSET; 552 case 2: 553 return MISCREG_PMCNTENCLR; 554 case 3: 555 return MISCREG_PMOVSR; 556 case 4: 557 return MISCREG_PMSWINC; 558 case 5: 559 return MISCREG_PMSELR; 560 case 6: 561 return MISCREG_PMCEID0; 562 case 7: 563 return MISCREG_PMCEID1; 564 } 565 break; 566 case 13: 567 switch (opc2) { 568 case 0: 569 return MISCREG_PMCCNTR; 570 case 1: 571 // Selector is PMSELR.SEL 572 return MISCREG_PMXEVTYPER_PMCCFILTR; 573 case 2: 574 return MISCREG_PMXEVCNTR; 575 } 576 break; 577 case 14: 578 switch (opc2) { 579 case 0: 580 return MISCREG_PMUSERENR; 581 case 1: 582 return MISCREG_PMINTENSET; 583 case 2: 584 return MISCREG_PMINTENCLR; 585 case 3: 586 return MISCREG_PMOVSSET; 587 } 588 break; 589 } 590 } else if (opc1 == 1) { 591 switch (crm) { 592 case 0: 593 switch (opc2) { 594 case 2: // L2CTLR, L2 Control Register 595 return MISCREG_L2CTLR; 596 case 3: 597 return MISCREG_L2ECTLR; 598 } 599 break; 600 break; 601 } 602 } 603 break; 604 case 10: 605 if (opc1 == 0) { 606 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 607 if (crm < 2) { 608 return MISCREG_IMPDEF_UNIMPL; 609 } else if (crm == 2) { // TEX Remap Registers 610 if (opc2 == 0) { 611 // Selector is TTBCR.EAE 612 return MISCREG_PRRR_MAIR0; 613 } else if (opc2 == 1) { 614 // Selector is TTBCR.EAE 615 return MISCREG_NMRR_MAIR1; 616 } 617 } else if (crm == 3) { 618 if (opc2 == 0) { 619 return MISCREG_AMAIR0; 620 } else if (opc2 == 1) { 621 return MISCREG_AMAIR1; 622 } 623 } 624 } else if (opc1 == 4) { 625 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 626 if (crm == 2) { 627 if (opc2 == 0) 628 return MISCREG_HMAIR0; 629 else if (opc2 == 1) 630 return MISCREG_HMAIR1; 631 } else if (crm == 3) { 632 if (opc2 == 0) 633 return MISCREG_HAMAIR0; 634 else if (opc2 == 1) 635 return MISCREG_HAMAIR1; 636 } 637 } 638 break; 639 case 11: 640 if (opc1 <=7) { 641 switch (crm) { 642 case 0: 643 case 1: 644 case 2: 645 case 3: 646 case 4: 647 case 5: 648 case 6: 649 case 7: 650 case 8: 651 case 15: 652 // Reserved for DMA operations for TCM access 653 return MISCREG_IMPDEF_UNIMPL; 654 default: 655 break; 656 } 657 } 658 break; 659 case 12: 660 if (opc1 == 0) { 661 if (crm == 0) { 662 if (opc2 == 0) { 663 return MISCREG_VBAR; 664 } else if (opc2 == 1) { 665 return MISCREG_MVBAR; 666 } 667 } else if (crm == 1) { 668 if (opc2 == 0) { 669 return MISCREG_ISR; 670 } 671 } 672 } else if (opc1 == 4) { 673 if (crm == 0 && opc2 == 0) 674 return MISCREG_HVBAR; 675 } 676 break; 677 case 13: 678 if (opc1 == 0) { 679 if (crm == 0) { 680 switch (opc2) { 681 case 0: 682 return MISCREG_FCSEIDR; 683 case 1: 684 return MISCREG_CONTEXTIDR; 685 case 2: 686 return MISCREG_TPIDRURW; 687 case 3: 688 return MISCREG_TPIDRURO; 689 case 4: 690 return MISCREG_TPIDRPRW; 691 } 692 } 693 } else if (opc1 == 4) { 694 if (crm == 0 && opc2 == 2) 695 return MISCREG_HTPIDR; 696 } 697 break; 698 case 14: 699 if (opc1 == 0) { 700 switch (crm) { 701 case 0: 702 if (opc2 == 0) 703 return MISCREG_CNTFRQ; 704 break; 705 case 1: 706 if (opc2 == 0) 707 return MISCREG_CNTKCTL; 708 break; 709 case 2: 710 if (opc2 == 0) 711 return MISCREG_CNTP_TVAL; 712 else if (opc2 == 1) 713 return MISCREG_CNTP_CTL; 714 break; 715 case 3: 716 if (opc2 == 0) 717 return MISCREG_CNTV_TVAL; 718 else if (opc2 == 1) 719 return MISCREG_CNTV_CTL; 720 break; 721 } 722 } else if (opc1 == 4) { 723 if (crm == 1 && opc2 == 0) { 724 return MISCREG_CNTHCTL; 725 } else if (crm == 2) { 726 if (opc2 == 0) 727 return MISCREG_CNTHP_TVAL; 728 else if (opc2 == 1) 729 return MISCREG_CNTHP_CTL; 730 } 731 } 732 break; 733 case 15: 734 // Implementation defined 735 return MISCREG_IMPDEF_UNIMPL; 736 } 737 // Unrecognized register 738 return MISCREG_CP15_UNIMPL; 739} 740 741MiscRegIndex 742decodeCP15Reg64(unsigned crm, unsigned opc1) 743{ 744 switch (crm) { 745 case 2: 746 switch (opc1) { 747 case 0: 748 return MISCREG_TTBR0; 749 case 1: 750 return MISCREG_TTBR1; 751 case 4: 752 return MISCREG_HTTBR; 753 case 6: 754 return MISCREG_VTTBR; 755 } 756 break; 757 case 7: 758 if (opc1 == 0) 759 return MISCREG_PAR; 760 break; 761 case 14: 762 switch (opc1) { 763 case 0: 764 return MISCREG_CNTPCT; 765 case 1: 766 return MISCREG_CNTVCT; 767 case 2: 768 return MISCREG_CNTP_CVAL; 769 case 3: 770 return MISCREG_CNTV_CVAL; 771 case 4: 772 return MISCREG_CNTVOFF; 773 case 6: 774 return MISCREG_CNTHP_CVAL; 775 } 776 break; 777 case 15: 778 if (opc1 == 0) 779 return MISCREG_CPUMERRSR; 780 else if (opc1 == 1) 781 return MISCREG_L2MERRSR; 782 break; 783 } 784 // Unrecognized register 785 return MISCREG_CP15_UNIMPL; 786} 787 788std::tuple<bool, bool> 789canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 790{ 791 bool secure = !scr.ns; 792 bool canRead = false; 793 bool undefined = false; 794 795 switch (cpsr.mode) { 796 case MODE_USER: 797 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 798 miscRegInfo[reg][MISCREG_USR_NS_RD]; 799 break; 800 case MODE_FIQ: 801 case MODE_IRQ: 802 case MODE_SVC: 803 case MODE_ABORT: 804 case MODE_UNDEFINED: 805 case MODE_SYSTEM: 806 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 807 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 808 break; 809 case MODE_MON: 810 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 811 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 812 break; 813 case MODE_HYP: 814 canRead = miscRegInfo[reg][MISCREG_HYP_RD]; 815 break; 816 default: 817 undefined = true; 818 } 819 // can't do permissions checkes on the root of a banked pair of regs 820 assert(!miscRegInfo[reg][MISCREG_BANKED]); 821 return std::make_tuple(canRead, undefined); 822} 823 824std::tuple<bool, bool> 825canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 826{ 827 bool secure = !scr.ns; 828 bool canWrite = false; 829 bool undefined = false; 830 831 switch (cpsr.mode) { 832 case MODE_USER: 833 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 834 miscRegInfo[reg][MISCREG_USR_NS_WR]; 835 break; 836 case MODE_FIQ: 837 case MODE_IRQ: 838 case MODE_SVC: 839 case MODE_ABORT: 840 case MODE_UNDEFINED: 841 case MODE_SYSTEM: 842 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 843 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 844 break; 845 case MODE_MON: 846 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 847 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 848 break; 849 case MODE_HYP: 850 canWrite = miscRegInfo[reg][MISCREG_HYP_WR]; 851 break; 852 default: 853 undefined = true; 854 } 855 // can't do permissions checkes on the root of a banked pair of regs 856 assert(!miscRegInfo[reg][MISCREG_BANKED]); 857 return std::make_tuple(canWrite, undefined); 858} 859 860int 861snsBankedIndex(MiscRegIndex reg, ThreadContext *tc) 862{ 863 SCR scr = tc->readMiscReg(MISCREG_SCR); 864 return snsBankedIndex(reg, tc, scr.ns); 865} 866 867int 868snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns) 869{ 870 int reg_as_int = static_cast<int>(reg); 871 if (miscRegInfo[reg][MISCREG_BANKED]) { 872 reg_as_int += (ArmSystem::haveSecurity(tc) && 873 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1; 874 } 875 return reg_as_int; 876} 877 878 879/** 880 * If the reg is a child reg of a banked set, then the parent is the last 881 * banked one in the list. This is messy, and the wish is to eventually have 882 * the bitmap replaced with a better data structure. the preUnflatten function 883 * initializes a lookup table to speed up the search for these banked 884 * registers. 885 */ 886 887int unflattenResultMiscReg[NUM_MISCREGS]; 888 889void 890preUnflattenMiscReg() 891{ 892 int reg = -1; 893 for (int i = 0 ; i < NUM_MISCREGS; i++){ 894 if (miscRegInfo[i][MISCREG_BANKED]) 895 reg = i; 896 if (miscRegInfo[i][MISCREG_BANKED_CHILD]) 897 unflattenResultMiscReg[i] = reg; 898 else 899 unflattenResultMiscReg[i] = i; 900 // if this assert fails, no parent was found, and something is broken 901 assert(unflattenResultMiscReg[i] > -1); 902 } 903} 904 905int 906unflattenMiscReg(int reg) 907{ 908 return unflattenResultMiscReg[reg]; 909} 910 911bool 912canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 913{ 914 // Check for SP_EL0 access while SPSEL == 0 915 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 916 return false; 917 918 // Check for RVBAR access 919 if (reg == MISCREG_RVBAR_EL1) { 920 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 921 if (highest_el == EL2 || highest_el == EL3) 922 return false; 923 } 924 if (reg == MISCREG_RVBAR_EL2) { 925 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 926 if (highest_el == EL3) 927 return false; 928 } 929 930 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 931 932 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) { 933 case EL0: 934 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 935 miscRegInfo[reg][MISCREG_USR_NS_RD]; 936 case EL1: 937 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 938 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 939 case EL2: 940 return miscRegInfo[reg][MISCREG_HYP_RD]; 941 case EL3: 942 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 943 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 944 default: 945 panic("Invalid exception level"); 946 } 947} 948 949bool 950canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 951{ 952 // Check for SP_EL0 access while SPSEL == 0 953 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 954 return false; 955 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode); 956 if (reg == MISCREG_DAIF) { 957 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 958 if (el == EL0 && !sctlr.uma) 959 return false; 960 } 961 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) { 962 // In syscall-emulation mode, this test is skipped and DCZVA is always 963 // allowed at EL0 964 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 965 if (el == EL0 && !sctlr.dze) 966 return false; 967 } 968 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) { 969 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 970 if (el == EL0 && !sctlr.uci) 971 return false; 972 } 973 974 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 975 976 switch (el) { 977 case EL0: 978 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 979 miscRegInfo[reg][MISCREG_USR_NS_WR]; 980 case EL1: 981 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 982 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 983 case EL2: 984 return miscRegInfo[reg][MISCREG_HYP_WR]; 985 case EL3: 986 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 987 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 988 default: 989 panic("Invalid exception level"); 990 } 991} 992 993MiscRegIndex 994decodeAArch64SysReg(unsigned op0, unsigned op1, 995 unsigned crn, unsigned crm, 996 unsigned op2) 997{ 998 switch (op0) { 999 case 1: 1000 switch (crn) { 1001 case 7: 1002 switch (op1) { 1003 case 0: 1004 switch (crm) { 1005 case 1: 1006 switch (op2) { 1007 case 0: 1008 return MISCREG_IC_IALLUIS; 1009 } 1010 break; 1011 case 5: 1012 switch (op2) { 1013 case 0: 1014 return MISCREG_IC_IALLU; 1015 } 1016 break; 1017 case 6: 1018 switch (op2) { 1019 case 1: 1020 return MISCREG_DC_IVAC_Xt; 1021 case 2: 1022 return MISCREG_DC_ISW_Xt; 1023 } 1024 break; 1025 case 8: 1026 switch (op2) { 1027 case 0: 1028 return MISCREG_AT_S1E1R_Xt; 1029 case 1: 1030 return MISCREG_AT_S1E1W_Xt; 1031 case 2: 1032 return MISCREG_AT_S1E0R_Xt; 1033 case 3: 1034 return MISCREG_AT_S1E0W_Xt; 1035 } 1036 break; 1037 case 10: 1038 switch (op2) { 1039 case 2: 1040 return MISCREG_DC_CSW_Xt; 1041 } 1042 break; 1043 case 14: 1044 switch (op2) { 1045 case 2: 1046 return MISCREG_DC_CISW_Xt; 1047 } 1048 break; 1049 } 1050 break; 1051 case 3: 1052 switch (crm) { 1053 case 4: 1054 switch (op2) { 1055 case 1: 1056 return MISCREG_DC_ZVA_Xt; 1057 } 1058 break; 1059 case 5: 1060 switch (op2) { 1061 case 1: 1062 return MISCREG_IC_IVAU_Xt; 1063 } 1064 break; 1065 case 10: 1066 switch (op2) { 1067 case 1: 1068 return MISCREG_DC_CVAC_Xt; 1069 } 1070 break; 1071 case 11: 1072 switch (op2) { 1073 case 1: 1074 return MISCREG_DC_CVAU_Xt; 1075 } 1076 break; 1077 case 14: 1078 switch (op2) { 1079 case 1: 1080 return MISCREG_DC_CIVAC_Xt; 1081 } 1082 break; 1083 } 1084 break; 1085 case 4: 1086 switch (crm) { 1087 case 8: 1088 switch (op2) { 1089 case 0: 1090 return MISCREG_AT_S1E2R_Xt; 1091 case 1: 1092 return MISCREG_AT_S1E2W_Xt; 1093 case 4: 1094 return MISCREG_AT_S12E1R_Xt; 1095 case 5: 1096 return MISCREG_AT_S12E1W_Xt; 1097 case 6: 1098 return MISCREG_AT_S12E0R_Xt; 1099 case 7: 1100 return MISCREG_AT_S12E0W_Xt; 1101 } 1102 break; 1103 } 1104 break; 1105 case 6: 1106 switch (crm) { 1107 case 8: 1108 switch (op2) { 1109 case 0: 1110 return MISCREG_AT_S1E3R_Xt; 1111 case 1: 1112 return MISCREG_AT_S1E3W_Xt; 1113 } 1114 break; 1115 } 1116 break; 1117 } 1118 break; 1119 case 8: 1120 switch (op1) { 1121 case 0: 1122 switch (crm) { 1123 case 3: 1124 switch (op2) { 1125 case 0: 1126 return MISCREG_TLBI_VMALLE1IS; 1127 case 1: 1128 return MISCREG_TLBI_VAE1IS_Xt; 1129 case 2: 1130 return MISCREG_TLBI_ASIDE1IS_Xt; 1131 case 3: 1132 return MISCREG_TLBI_VAAE1IS_Xt; 1133 case 5: 1134 return MISCREG_TLBI_VALE1IS_Xt; 1135 case 7: 1136 return MISCREG_TLBI_VAALE1IS_Xt; 1137 } 1138 break; 1139 case 7: 1140 switch (op2) { 1141 case 0: 1142 return MISCREG_TLBI_VMALLE1; 1143 case 1: 1144 return MISCREG_TLBI_VAE1_Xt; 1145 case 2: 1146 return MISCREG_TLBI_ASIDE1_Xt; 1147 case 3: 1148 return MISCREG_TLBI_VAAE1_Xt; 1149 case 5: 1150 return MISCREG_TLBI_VALE1_Xt; 1151 case 7: 1152 return MISCREG_TLBI_VAALE1_Xt; 1153 } 1154 break; 1155 } 1156 break; 1157 case 4: 1158 switch (crm) { 1159 case 0: 1160 switch (op2) { 1161 case 1: 1162 return MISCREG_TLBI_IPAS2E1IS_Xt; 1163 case 5: 1164 return MISCREG_TLBI_IPAS2LE1IS_Xt; 1165 } 1166 break; 1167 case 3: 1168 switch (op2) { 1169 case 0: 1170 return MISCREG_TLBI_ALLE2IS; 1171 case 1: 1172 return MISCREG_TLBI_VAE2IS_Xt; 1173 case 4: 1174 return MISCREG_TLBI_ALLE1IS; 1175 case 5: 1176 return MISCREG_TLBI_VALE2IS_Xt; 1177 case 6: 1178 return MISCREG_TLBI_VMALLS12E1IS; 1179 } 1180 break; 1181 case 4: 1182 switch (op2) { 1183 case 1: 1184 return MISCREG_TLBI_IPAS2E1_Xt; 1185 case 5: 1186 return MISCREG_TLBI_IPAS2LE1_Xt; 1187 } 1188 break; 1189 case 7: 1190 switch (op2) { 1191 case 0: 1192 return MISCREG_TLBI_ALLE2; 1193 case 1: 1194 return MISCREG_TLBI_VAE2_Xt; 1195 case 4: 1196 return MISCREG_TLBI_ALLE1; 1197 case 5: 1198 return MISCREG_TLBI_VALE2_Xt; 1199 case 6: 1200 return MISCREG_TLBI_VMALLS12E1; 1201 } 1202 break; 1203 } 1204 break; 1205 case 6: 1206 switch (crm) { 1207 case 3: 1208 switch (op2) { 1209 case 0: 1210 return MISCREG_TLBI_ALLE3IS; 1211 case 1: 1212 return MISCREG_TLBI_VAE3IS_Xt; 1213 case 5: 1214 return MISCREG_TLBI_VALE3IS_Xt; 1215 } 1216 break; 1217 case 7: 1218 switch (op2) { 1219 case 0: 1220 return MISCREG_TLBI_ALLE3; 1221 case 1: 1222 return MISCREG_TLBI_VAE3_Xt; 1223 case 5: 1224 return MISCREG_TLBI_VALE3_Xt; 1225 } 1226 break; 1227 } 1228 break; 1229 } 1230 break; 1231 } 1232 break; 1233 case 2: 1234 switch (crn) { 1235 case 0: 1236 switch (op1) { 1237 case 0: 1238 switch (crm) { 1239 case 0: 1240 switch (op2) { 1241 case 2: 1242 return MISCREG_OSDTRRX_EL1; 1243 case 4: 1244 return MISCREG_DBGBVR0_EL1; 1245 case 5: 1246 return MISCREG_DBGBCR0_EL1; 1247 case 6: 1248 return MISCREG_DBGWVR0_EL1; 1249 case 7: 1250 return MISCREG_DBGWCR0_EL1; 1251 } 1252 break; 1253 case 1: 1254 switch (op2) { 1255 case 4: 1256 return MISCREG_DBGBVR1_EL1; 1257 case 5: 1258 return MISCREG_DBGBCR1_EL1; 1259 case 6: 1260 return MISCREG_DBGWVR1_EL1; 1261 case 7: 1262 return MISCREG_DBGWCR1_EL1; 1263 } 1264 break; 1265 case 2: 1266 switch (op2) { 1267 case 0: 1268 return MISCREG_MDCCINT_EL1; 1269 case 2: 1270 return MISCREG_MDSCR_EL1; 1271 case 4: 1272 return MISCREG_DBGBVR2_EL1; 1273 case 5: 1274 return MISCREG_DBGBCR2_EL1; 1275 case 6: 1276 return MISCREG_DBGWVR2_EL1; 1277 case 7: 1278 return MISCREG_DBGWCR2_EL1; 1279 } 1280 break; 1281 case 3: 1282 switch (op2) { 1283 case 2: 1284 return MISCREG_OSDTRTX_EL1; 1285 case 4: 1286 return MISCREG_DBGBVR3_EL1; 1287 case 5: 1288 return MISCREG_DBGBCR3_EL1; 1289 case 6: 1290 return MISCREG_DBGWVR3_EL1; 1291 case 7: 1292 return MISCREG_DBGWCR3_EL1; 1293 } 1294 break; 1295 case 4: 1296 switch (op2) { 1297 case 4: 1298 return MISCREG_DBGBVR4_EL1; 1299 case 5: 1300 return MISCREG_DBGBCR4_EL1; 1301 } 1302 break; 1303 case 5: 1304 switch (op2) { 1305 case 4: 1306 return MISCREG_DBGBVR5_EL1; 1307 case 5: 1308 return MISCREG_DBGBCR5_EL1; 1309 } 1310 break; 1311 case 6: 1312 switch (op2) { 1313 case 2: 1314 return MISCREG_OSECCR_EL1; 1315 } 1316 break; 1317 } 1318 break; 1319 case 2: 1320 switch (crm) { 1321 case 0: 1322 switch (op2) { 1323 case 0: 1324 return MISCREG_TEECR32_EL1; 1325 } 1326 break; 1327 } 1328 break; 1329 case 3: 1330 switch (crm) { 1331 case 1: 1332 switch (op2) { 1333 case 0: 1334 return MISCREG_MDCCSR_EL0; 1335 } 1336 break; 1337 case 4: 1338 switch (op2) { 1339 case 0: 1340 return MISCREG_MDDTR_EL0; 1341 } 1342 break; 1343 case 5: 1344 switch (op2) { 1345 case 0: 1346 return MISCREG_MDDTRRX_EL0; 1347 } 1348 break; 1349 } 1350 break; 1351 case 4: 1352 switch (crm) { 1353 case 7: 1354 switch (op2) { 1355 case 0: 1356 return MISCREG_DBGVCR32_EL2; 1357 } 1358 break; 1359 } 1360 break; 1361 } 1362 break; 1363 case 1: 1364 switch (op1) { 1365 case 0: 1366 switch (crm) { 1367 case 0: 1368 switch (op2) { 1369 case 0: 1370 return MISCREG_MDRAR_EL1; 1371 case 4: 1372 return MISCREG_OSLAR_EL1; 1373 } 1374 break; 1375 case 1: 1376 switch (op2) { 1377 case 4: 1378 return MISCREG_OSLSR_EL1; 1379 } 1380 break; 1381 case 3: 1382 switch (op2) { 1383 case 4: 1384 return MISCREG_OSDLR_EL1; 1385 } 1386 break; 1387 case 4: 1388 switch (op2) { 1389 case 4: 1390 return MISCREG_DBGPRCR_EL1; 1391 } 1392 break; 1393 } 1394 break; 1395 case 2: 1396 switch (crm) { 1397 case 0: 1398 switch (op2) { 1399 case 0: 1400 return MISCREG_TEEHBR32_EL1; 1401 } 1402 break; 1403 } 1404 break; 1405 } 1406 break; 1407 case 7: 1408 switch (op1) { 1409 case 0: 1410 switch (crm) { 1411 case 8: 1412 switch (op2) { 1413 case 6: 1414 return MISCREG_DBGCLAIMSET_EL1; 1415 } 1416 break; 1417 case 9: 1418 switch (op2) { 1419 case 6: 1420 return MISCREG_DBGCLAIMCLR_EL1; 1421 } 1422 break; 1423 case 14: 1424 switch (op2) { 1425 case 6: 1426 return MISCREG_DBGAUTHSTATUS_EL1; 1427 } 1428 break; 1429 } 1430 break; 1431 } 1432 break; 1433 } 1434 break; 1435 case 3: 1436 switch (crn) { 1437 case 0: 1438 switch (op1) { 1439 case 0: 1440 switch (crm) { 1441 case 0: 1442 switch (op2) { 1443 case 0: 1444 return MISCREG_MIDR_EL1; 1445 case 5: 1446 return MISCREG_MPIDR_EL1; 1447 case 6: 1448 return MISCREG_REVIDR_EL1; 1449 } 1450 break; 1451 case 1: 1452 switch (op2) { 1453 case 0: 1454 return MISCREG_ID_PFR0_EL1; 1455 case 1: 1456 return MISCREG_ID_PFR1_EL1; 1457 case 2: 1458 return MISCREG_ID_DFR0_EL1; 1459 case 3: 1460 return MISCREG_ID_AFR0_EL1; 1461 case 4: 1462 return MISCREG_ID_MMFR0_EL1; 1463 case 5: 1464 return MISCREG_ID_MMFR1_EL1; 1465 case 6: 1466 return MISCREG_ID_MMFR2_EL1; 1467 case 7: 1468 return MISCREG_ID_MMFR3_EL1; 1469 } 1470 break; 1471 case 2: 1472 switch (op2) { 1473 case 0: 1474 return MISCREG_ID_ISAR0_EL1; 1475 case 1: 1476 return MISCREG_ID_ISAR1_EL1; 1477 case 2: 1478 return MISCREG_ID_ISAR2_EL1; 1479 case 3: 1480 return MISCREG_ID_ISAR3_EL1; 1481 case 4: 1482 return MISCREG_ID_ISAR4_EL1; 1483 case 5: 1484 return MISCREG_ID_ISAR5_EL1; 1485 } 1486 break; 1487 case 3: 1488 switch (op2) { 1489 case 0: 1490 return MISCREG_MVFR0_EL1; 1491 case 1: 1492 return MISCREG_MVFR1_EL1; 1493 case 2: 1494 return MISCREG_MVFR2_EL1; 1495 case 3 ... 7: 1496 return MISCREG_RAZ; 1497 } 1498 break; 1499 case 4: 1500 switch (op2) { 1501 case 0: 1502 return MISCREG_ID_AA64PFR0_EL1; 1503 case 1: 1504 return MISCREG_ID_AA64PFR1_EL1; 1505 case 2 ... 7: 1506 return MISCREG_RAZ; 1507 } 1508 break; 1509 case 5: 1510 switch (op2) { 1511 case 0: 1512 return MISCREG_ID_AA64DFR0_EL1; 1513 case 1: 1514 return MISCREG_ID_AA64DFR1_EL1; 1515 case 4: 1516 return MISCREG_ID_AA64AFR0_EL1; 1517 case 5: 1518 return MISCREG_ID_AA64AFR1_EL1; 1519 case 2: 1520 case 3: 1521 case 6: 1522 case 7: 1523 return MISCREG_RAZ; 1524 } 1525 break; 1526 case 6: 1527 switch (op2) { 1528 case 0: 1529 return MISCREG_ID_AA64ISAR0_EL1; 1530 case 1: 1531 return MISCREG_ID_AA64ISAR1_EL1; 1532 case 2 ... 7: 1533 return MISCREG_RAZ; 1534 } 1535 break; 1536 case 7: 1537 switch (op2) { 1538 case 0: 1539 return MISCREG_ID_AA64MMFR0_EL1; 1540 case 1: 1541 return MISCREG_ID_AA64MMFR1_EL1; 1542 case 2: 1543 return MISCREG_ID_AA64MMFR2_EL1; 1544 case 3 ... 7: 1545 return MISCREG_RAZ; 1546 } 1547 break; 1548 } 1549 break; 1550 case 1: 1551 switch (crm) { 1552 case 0: 1553 switch (op2) { 1554 case 0: 1555 return MISCREG_CCSIDR_EL1; 1556 case 1: 1557 return MISCREG_CLIDR_EL1; 1558 case 7: 1559 return MISCREG_AIDR_EL1; 1560 } 1561 break; 1562 } 1563 break; 1564 case 2: 1565 switch (crm) { 1566 case 0: 1567 switch (op2) { 1568 case 0: 1569 return MISCREG_CSSELR_EL1; 1570 } 1571 break; 1572 } 1573 break; 1574 case 3: 1575 switch (crm) { 1576 case 0: 1577 switch (op2) { 1578 case 1: 1579 return MISCREG_CTR_EL0; 1580 case 7: 1581 return MISCREG_DCZID_EL0; 1582 } 1583 break; 1584 } 1585 break; 1586 case 4: 1587 switch (crm) { 1588 case 0: 1589 switch (op2) { 1590 case 0: 1591 return MISCREG_VPIDR_EL2; 1592 case 5: 1593 return MISCREG_VMPIDR_EL2; 1594 } 1595 break; 1596 } 1597 break; 1598 } 1599 break; 1600 case 1: 1601 switch (op1) { 1602 case 0: 1603 switch (crm) { 1604 case 0: 1605 switch (op2) { 1606 case 0: 1607 return MISCREG_SCTLR_EL1; 1608 case 1: 1609 return MISCREG_ACTLR_EL1; 1610 case 2: 1611 return MISCREG_CPACR_EL1; 1612 } 1613 break; 1614 } 1615 break; 1616 case 4: 1617 switch (crm) { 1618 case 0: 1619 switch (op2) { 1620 case 0: 1621 return MISCREG_SCTLR_EL2; 1622 case 1: 1623 return MISCREG_ACTLR_EL2; 1624 } 1625 break; 1626 case 1: 1627 switch (op2) { 1628 case 0: 1629 return MISCREG_HCR_EL2; 1630 case 1: 1631 return MISCREG_MDCR_EL2; 1632 case 2: 1633 return MISCREG_CPTR_EL2; 1634 case 3: 1635 return MISCREG_HSTR_EL2; 1636 case 7: 1637 return MISCREG_HACR_EL2; 1638 } 1639 break; 1640 } 1641 break; 1642 case 6: 1643 switch (crm) { 1644 case 0: 1645 switch (op2) { 1646 case 0: 1647 return MISCREG_SCTLR_EL3; 1648 case 1: 1649 return MISCREG_ACTLR_EL3; 1650 } 1651 break; 1652 case 1: 1653 switch (op2) { 1654 case 0: 1655 return MISCREG_SCR_EL3; 1656 case 1: 1657 return MISCREG_SDER32_EL3; 1658 case 2: 1659 return MISCREG_CPTR_EL3; 1660 } 1661 break; 1662 case 3: 1663 switch (op2) { 1664 case 1: 1665 return MISCREG_MDCR_EL3; 1666 } 1667 break; 1668 } 1669 break; 1670 } 1671 break; 1672 case 2: 1673 switch (op1) { 1674 case 0: 1675 switch (crm) { 1676 case 0: 1677 switch (op2) { 1678 case 0: 1679 return MISCREG_TTBR0_EL1; 1680 case 1: 1681 return MISCREG_TTBR1_EL1; 1682 case 2: 1683 return MISCREG_TCR_EL1; 1684 } 1685 break; 1686 } 1687 break; 1688 case 4: 1689 switch (crm) { 1690 case 0: 1691 switch (op2) { 1692 case 0: 1693 return MISCREG_TTBR0_EL2; 1694 case 1: 1695 return MISCREG_TTBR1_EL2; 1696 case 2: 1697 return MISCREG_TCR_EL2; 1698 } 1699 break; 1700 case 1: 1701 switch (op2) { 1702 case 0: 1703 return MISCREG_VTTBR_EL2; 1704 case 2: 1705 return MISCREG_VTCR_EL2; 1706 } 1707 break; 1708 } 1709 break; 1710 case 6: 1711 switch (crm) { 1712 case 0: 1713 switch (op2) { 1714 case 0: 1715 return MISCREG_TTBR0_EL3; 1716 case 2: 1717 return MISCREG_TCR_EL3; 1718 } 1719 break; 1720 } 1721 break; 1722 } 1723 break; 1724 case 3: 1725 switch (op1) { 1726 case 4: 1727 switch (crm) { 1728 case 0: 1729 switch (op2) { 1730 case 0: 1731 return MISCREG_DACR32_EL2; 1732 } 1733 break; 1734 } 1735 break; 1736 } 1737 break; 1738 case 4: 1739 switch (op1) { 1740 case 0: 1741 switch (crm) { 1742 case 0: 1743 switch (op2) { 1744 case 0: 1745 return MISCREG_SPSR_EL1; 1746 case 1: 1747 return MISCREG_ELR_EL1; 1748 } 1749 break; 1750 case 1: 1751 switch (op2) { 1752 case 0: 1753 return MISCREG_SP_EL0; 1754 } 1755 break; 1756 case 2: 1757 switch (op2) { 1758 case 0: 1759 return MISCREG_SPSEL; 1760 case 2: 1761 return MISCREG_CURRENTEL; 1762 } 1763 break; 1764 } 1765 break; 1766 case 3: 1767 switch (crm) { 1768 case 2: 1769 switch (op2) { 1770 case 0: 1771 return MISCREG_NZCV; 1772 case 1: 1773 return MISCREG_DAIF; 1774 } 1775 break; 1776 case 4: 1777 switch (op2) { 1778 case 0: 1779 return MISCREG_FPCR; 1780 case 1: 1781 return MISCREG_FPSR; 1782 } 1783 break; 1784 case 5: 1785 switch (op2) { 1786 case 0: 1787 return MISCREG_DSPSR_EL0; 1788 case 1: 1789 return MISCREG_DLR_EL0; 1790 } 1791 break; 1792 } 1793 break; 1794 case 4: 1795 switch (crm) { 1796 case 0: 1797 switch (op2) { 1798 case 0: 1799 return MISCREG_SPSR_EL2; 1800 case 1: 1801 return MISCREG_ELR_EL2; 1802 } 1803 break; 1804 case 1: 1805 switch (op2) { 1806 case 0: 1807 return MISCREG_SP_EL1; 1808 } 1809 break; 1810 case 3: 1811 switch (op2) { 1812 case 0: 1813 return MISCREG_SPSR_IRQ_AA64; 1814 case 1: 1815 return MISCREG_SPSR_ABT_AA64; 1816 case 2: 1817 return MISCREG_SPSR_UND_AA64; 1818 case 3: 1819 return MISCREG_SPSR_FIQ_AA64; 1820 } 1821 break; 1822 } 1823 break; 1824 case 6: 1825 switch (crm) { 1826 case 0: 1827 switch (op2) { 1828 case 0: 1829 return MISCREG_SPSR_EL3; 1830 case 1: 1831 return MISCREG_ELR_EL3; 1832 } 1833 break; 1834 case 1: 1835 switch (op2) { 1836 case 0: 1837 return MISCREG_SP_EL2; 1838 } 1839 break; 1840 } 1841 break; 1842 } 1843 break; 1844 case 5: 1845 switch (op1) { 1846 case 0: 1847 switch (crm) { 1848 case 1: 1849 switch (op2) { 1850 case 0: 1851 return MISCREG_AFSR0_EL1; 1852 case 1: 1853 return MISCREG_AFSR1_EL1; 1854 } 1855 break; 1856 case 2: 1857 switch (op2) { 1858 case 0: 1859 return MISCREG_ESR_EL1; 1860 } 1861 break; 1862 case 3: 1863 switch (op2) { 1864 case 0: 1865 return MISCREG_ERRIDR_EL1; 1866 case 1: 1867 return MISCREG_ERRSELR_EL1; 1868 } 1869 break; 1870 case 4: 1871 switch (op2) { 1872 case 0: 1873 return MISCREG_ERXFR_EL1; 1874 case 1: 1875 return MISCREG_ERXCTLR_EL1; 1876 case 2: 1877 return MISCREG_ERXSTATUS_EL1; 1878 case 3: 1879 return MISCREG_ERXADDR_EL1; 1880 } 1881 break; 1882 case 5: 1883 switch (op2) { 1884 case 0: 1885 return MISCREG_ERXMISC0_EL1; 1886 case 1: 1887 return MISCREG_ERXMISC1_EL1; 1888 } 1889 break; 1890 } 1891 break; 1892 case 4: 1893 switch (crm) { 1894 case 0: 1895 switch (op2) { 1896 case 1: 1897 return MISCREG_IFSR32_EL2; 1898 } 1899 break; 1900 case 1: 1901 switch (op2) { 1902 case 0: 1903 return MISCREG_AFSR0_EL2; 1904 case 1: 1905 return MISCREG_AFSR1_EL2; 1906 } 1907 break; 1908 case 2: 1909 switch (op2) { 1910 case 0: 1911 return MISCREG_ESR_EL2; 1912 case 3: 1913 return MISCREG_VSESR_EL2; 1914 } 1915 break; 1916 case 3: 1917 switch (op2) { 1918 case 0: 1919 return MISCREG_FPEXC32_EL2; 1920 } 1921 break; 1922 } 1923 break; 1924 case 6: 1925 switch (crm) { 1926 case 1: 1927 switch (op2) { 1928 case 0: 1929 return MISCREG_AFSR0_EL3; 1930 case 1: 1931 return MISCREG_AFSR1_EL3; 1932 } 1933 break; 1934 case 2: 1935 switch (op2) { 1936 case 0: 1937 return MISCREG_ESR_EL3; 1938 } 1939 break; 1940 } 1941 break; 1942 } 1943 break; 1944 case 6: 1945 switch (op1) { 1946 case 0: 1947 switch (crm) { 1948 case 0: 1949 switch (op2) { 1950 case 0: 1951 return MISCREG_FAR_EL1; 1952 } 1953 break; 1954 } 1955 break; 1956 case 4: 1957 switch (crm) { 1958 case 0: 1959 switch (op2) { 1960 case 0: 1961 return MISCREG_FAR_EL2; 1962 case 4: 1963 return MISCREG_HPFAR_EL2; 1964 } 1965 break; 1966 } 1967 break; 1968 case 6: 1969 switch (crm) { 1970 case 0: 1971 switch (op2) { 1972 case 0: 1973 return MISCREG_FAR_EL3; 1974 } 1975 break; 1976 } 1977 break; 1978 } 1979 break; 1980 case 7: 1981 switch (op1) { 1982 case 0: 1983 switch (crm) { 1984 case 4: 1985 switch (op2) { 1986 case 0: 1987 return MISCREG_PAR_EL1; 1988 } 1989 break; 1990 } 1991 break; 1992 } 1993 break; 1994 case 9: 1995 switch (op1) { 1996 case 0: 1997 switch (crm) { 1998 case 14: 1999 switch (op2) { 2000 case 1: 2001 return MISCREG_PMINTENSET_EL1; 2002 case 2: 2003 return MISCREG_PMINTENCLR_EL1; 2004 } 2005 break; 2006 } 2007 break; 2008 case 3: 2009 switch (crm) { 2010 case 12: 2011 switch (op2) { 2012 case 0: 2013 return MISCREG_PMCR_EL0; 2014 case 1: 2015 return MISCREG_PMCNTENSET_EL0; 2016 case 2: 2017 return MISCREG_PMCNTENCLR_EL0; 2018 case 3: 2019 return MISCREG_PMOVSCLR_EL0; 2020 case 4: 2021 return MISCREG_PMSWINC_EL0; 2022 case 5: 2023 return MISCREG_PMSELR_EL0; 2024 case 6: 2025 return MISCREG_PMCEID0_EL0; 2026 case 7: 2027 return MISCREG_PMCEID1_EL0; 2028 } 2029 break; 2030 case 13: 2031 switch (op2) { 2032 case 0: 2033 return MISCREG_PMCCNTR_EL0; 2034 case 1: 2035 return MISCREG_PMXEVTYPER_EL0; 2036 case 2: 2037 return MISCREG_PMXEVCNTR_EL0; 2038 } 2039 break; 2040 case 14: 2041 switch (op2) { 2042 case 0: 2043 return MISCREG_PMUSERENR_EL0; 2044 case 3: 2045 return MISCREG_PMOVSSET_EL0; 2046 } 2047 break; 2048 } 2049 break; 2050 } 2051 break; 2052 case 10: 2053 switch (op1) { 2054 case 0: 2055 switch (crm) { 2056 case 2: 2057 switch (op2) { 2058 case 0: 2059 return MISCREG_MAIR_EL1; 2060 } 2061 break; 2062 case 3: 2063 switch (op2) { 2064 case 0: 2065 return MISCREG_AMAIR_EL1; 2066 } 2067 break; 2068 } 2069 break; 2070 case 4: 2071 switch (crm) { 2072 case 2: 2073 switch (op2) { 2074 case 0: 2075 return MISCREG_MAIR_EL2; 2076 } 2077 break; 2078 case 3: 2079 switch (op2) { 2080 case 0: 2081 return MISCREG_AMAIR_EL2; 2082 } 2083 break; 2084 } 2085 break; 2086 case 6: 2087 switch (crm) { 2088 case 2: 2089 switch (op2) { 2090 case 0: 2091 return MISCREG_MAIR_EL3; 2092 } 2093 break; 2094 case 3: 2095 switch (op2) { 2096 case 0: 2097 return MISCREG_AMAIR_EL3; 2098 } 2099 break; 2100 } 2101 break; 2102 } 2103 break; 2104 case 11: 2105 switch (op1) { 2106 case 1: 2107 switch (crm) { 2108 case 0: 2109 switch (op2) { 2110 case 2: 2111 return MISCREG_L2CTLR_EL1; 2112 case 3: 2113 return MISCREG_L2ECTLR_EL1; 2114 } 2115 break; 2116 } 2117 M5_FALLTHROUGH; 2118 default: 2119 // S3_<op1>_11_<Cm>_<op2> 2120 return MISCREG_IMPDEF_UNIMPL; 2121 } 2122 M5_UNREACHABLE; 2123 case 12: 2124 switch (op1) { 2125 case 0: 2126 switch (crm) { 2127 case 0: 2128 switch (op2) { 2129 case 0: 2130 return MISCREG_VBAR_EL1; 2131 case 1: 2132 return MISCREG_RVBAR_EL1; 2133 } 2134 break; 2135 case 1: 2136 switch (op2) { 2137 case 0: 2138 return MISCREG_ISR_EL1; 2139 case 1: 2140 return MISCREG_DISR_EL1; 2141 } 2142 break; 2143 } 2144 break; 2145 case 4: 2146 switch (crm) { 2147 case 0: 2148 switch (op2) { 2149 case 0: 2150 return MISCREG_VBAR_EL2; 2151 case 1: 2152 return MISCREG_RVBAR_EL2; 2153 } 2154 break; 2155 case 1: 2156 switch (op2) { 2157 case 1: 2158 return MISCREG_VDISR_EL2; 2159 } 2160 break; 2161 } 2162 break; 2163 case 6: 2164 switch (crm) { 2165 case 0: 2166 switch (op2) { 2167 case 0: 2168 return MISCREG_VBAR_EL3; 2169 case 1: 2170 return MISCREG_RVBAR_EL3; 2171 case 2: 2172 return MISCREG_RMR_EL3; 2173 } 2174 break; 2175 } 2176 break; 2177 } 2178 break; 2179 case 13: 2180 switch (op1) { 2181 case 0: 2182 switch (crm) { 2183 case 0: 2184 switch (op2) { 2185 case 1: 2186 return MISCREG_CONTEXTIDR_EL1; 2187 case 4: 2188 return MISCREG_TPIDR_EL1; 2189 } 2190 break; 2191 } 2192 break; 2193 case 3: 2194 switch (crm) { 2195 case 0: 2196 switch (op2) { 2197 case 2: 2198 return MISCREG_TPIDR_EL0; 2199 case 3: 2200 return MISCREG_TPIDRRO_EL0; 2201 } 2202 break; 2203 } 2204 break; 2205 case 4: 2206 switch (crm) { 2207 case 0: 2208 switch (op2) { 2209 case 1: 2210 return MISCREG_CONTEXTIDR_EL2; 2211 case 2: 2212 return MISCREG_TPIDR_EL2; 2213 } 2214 break; 2215 } 2216 break; 2217 case 6: 2218 switch (crm) { 2219 case 0: 2220 switch (op2) { 2221 case 2: 2222 return MISCREG_TPIDR_EL3; 2223 } 2224 break; 2225 } 2226 break; 2227 } 2228 break; 2229 case 14: 2230 switch (op1) { 2231 case 0: 2232 switch (crm) { 2233 case 1: 2234 switch (op2) { 2235 case 0: 2236 return MISCREG_CNTKCTL_EL1; 2237 } 2238 break; 2239 } 2240 break; 2241 case 3: 2242 switch (crm) { 2243 case 0: 2244 switch (op2) { 2245 case 0: 2246 return MISCREG_CNTFRQ_EL0; 2247 case 1: 2248 return MISCREG_CNTPCT_EL0; 2249 case 2: 2250 return MISCREG_CNTVCT_EL0; 2251 } 2252 break; 2253 case 2: 2254 switch (op2) { 2255 case 0: 2256 return MISCREG_CNTP_TVAL_EL0; 2257 case 1: 2258 return MISCREG_CNTP_CTL_EL0; 2259 case 2: 2260 return MISCREG_CNTP_CVAL_EL0; 2261 } 2262 break; 2263 case 3: 2264 switch (op2) { 2265 case 0: 2266 return MISCREG_CNTV_TVAL_EL0; 2267 case 1: 2268 return MISCREG_CNTV_CTL_EL0; 2269 case 2: 2270 return MISCREG_CNTV_CVAL_EL0; 2271 } 2272 break; 2273 case 8: 2274 switch (op2) { 2275 case 0: 2276 return MISCREG_PMEVCNTR0_EL0; 2277 case 1: 2278 return MISCREG_PMEVCNTR1_EL0; 2279 case 2: 2280 return MISCREG_PMEVCNTR2_EL0; 2281 case 3: 2282 return MISCREG_PMEVCNTR3_EL0; 2283 case 4: 2284 return MISCREG_PMEVCNTR4_EL0; 2285 case 5: 2286 return MISCREG_PMEVCNTR5_EL0; 2287 } 2288 break; 2289 case 12: 2290 switch (op2) { 2291 case 0: 2292 return MISCREG_PMEVTYPER0_EL0; 2293 case 1: 2294 return MISCREG_PMEVTYPER1_EL0; 2295 case 2: 2296 return MISCREG_PMEVTYPER2_EL0; 2297 case 3: 2298 return MISCREG_PMEVTYPER3_EL0; 2299 case 4: 2300 return MISCREG_PMEVTYPER4_EL0; 2301 case 5: 2302 return MISCREG_PMEVTYPER5_EL0; 2303 } 2304 break; 2305 case 15: 2306 switch (op2) { 2307 case 7: 2308 return MISCREG_PMCCFILTR_EL0; 2309 } 2310 } 2311 break; 2312 case 4: 2313 switch (crm) { 2314 case 0: 2315 switch (op2) { 2316 case 3: 2317 return MISCREG_CNTVOFF_EL2; 2318 } 2319 break; 2320 case 1: 2321 switch (op2) { 2322 case 0: 2323 return MISCREG_CNTHCTL_EL2; 2324 } 2325 break; 2326 case 2: 2327 switch (op2) { 2328 case 0: 2329 return MISCREG_CNTHP_TVAL_EL2; 2330 case 1: 2331 return MISCREG_CNTHP_CTL_EL2; 2332 case 2: 2333 return MISCREG_CNTHP_CVAL_EL2; 2334 } 2335 break; 2336 case 3: 2337 switch (op2) { 2338 case 0: 2339 return MISCREG_CNTHV_TVAL_EL2; 2340 case 1: 2341 return MISCREG_CNTHV_CTL_EL2; 2342 case 2: 2343 return MISCREG_CNTHV_CVAL_EL2; 2344 } 2345 break; 2346 } 2347 break; 2348 case 7: 2349 switch (crm) { 2350 case 2: 2351 switch (op2) { 2352 case 0: 2353 return MISCREG_CNTPS_TVAL_EL1; 2354 case 1: 2355 return MISCREG_CNTPS_CTL_EL1; 2356 case 2: 2357 return MISCREG_CNTPS_CVAL_EL1; 2358 } 2359 break; 2360 } 2361 break; 2362 } 2363 break; 2364 case 15: 2365 switch (op1) { 2366 case 0: 2367 switch (crm) { 2368 case 0: 2369 switch (op2) { 2370 case 0: 2371 return MISCREG_IL1DATA0_EL1; 2372 case 1: 2373 return MISCREG_IL1DATA1_EL1; 2374 case 2: 2375 return MISCREG_IL1DATA2_EL1; 2376 case 3: 2377 return MISCREG_IL1DATA3_EL1; 2378 } 2379 break; 2380 case 1: 2381 switch (op2) { 2382 case 0: 2383 return MISCREG_DL1DATA0_EL1; 2384 case 1: 2385 return MISCREG_DL1DATA1_EL1; 2386 case 2: 2387 return MISCREG_DL1DATA2_EL1; 2388 case 3: 2389 return MISCREG_DL1DATA3_EL1; 2390 case 4: 2391 return MISCREG_DL1DATA4_EL1; 2392 } 2393 break; 2394 } 2395 break; 2396 case 1: 2397 switch (crm) { 2398 case 0: 2399 switch (op2) { 2400 case 0: 2401 return MISCREG_L2ACTLR_EL1; 2402 } 2403 break; 2404 case 2: 2405 switch (op2) { 2406 case 0: 2407 return MISCREG_CPUACTLR_EL1; 2408 case 1: 2409 return MISCREG_CPUECTLR_EL1; 2410 case 2: 2411 return MISCREG_CPUMERRSR_EL1; 2412 case 3: 2413 return MISCREG_L2MERRSR_EL1; 2414 } 2415 break; 2416 case 3: 2417 switch (op2) { 2418 case 0: 2419 return MISCREG_CBAR_EL1; 2420 2421 } 2422 break; 2423 } 2424 break; 2425 } 2426 // S3_<op1>_15_<Cm>_<op2> 2427 return MISCREG_IMPDEF_UNIMPL; 2428 } 2429 break; 2430 } 2431 2432 return MISCREG_UNKNOWN; 2433} 2434 2435bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below 2436 2437void 2438ISA::initializeMiscRegMetadata() 2439{ 2440 // the MiscReg metadata tables are shared across all instances of the 2441 // ISA object, so there's no need to initialize them multiple times. 2442 static bool completed = false; 2443 if (completed) 2444 return; 2445 2446 // This boolean variable specifies if the system is running in aarch32 at 2447 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it 2448 // is running in aarch64 (aarch32EL3 = false) 2449 bool aarch32EL3 = haveSecurity && !highestELIs64; 2450 2451 /** 2452 * Some registers alias with others, and therefore need to be translated. 2453 * When two mapping registers are given, they are the 32b lower and 2454 * upper halves, respectively, of the 64b register being mapped. 2455 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 2456 * 2457 * NAM = "not architecturally mandated", 2458 * from ARM DDI 0487A.i, template text 2459 * "AArch64 System register ___ can be mapped to 2460 * AArch32 System register ___, but this is not 2461 * architecturally mandated." 2462 */ 2463 2464 InitReg(MISCREG_CPSR) 2465 .allPrivileges(); 2466 InitReg(MISCREG_SPSR) 2467 .allPrivileges(); 2468 InitReg(MISCREG_SPSR_FIQ) 2469 .allPrivileges(); 2470 InitReg(MISCREG_SPSR_IRQ) 2471 .allPrivileges(); 2472 InitReg(MISCREG_SPSR_SVC) 2473 .allPrivileges(); 2474 InitReg(MISCREG_SPSR_MON) 2475 .allPrivileges(); 2476 InitReg(MISCREG_SPSR_ABT) 2477 .allPrivileges(); 2478 InitReg(MISCREG_SPSR_HYP) 2479 .allPrivileges(); 2480 InitReg(MISCREG_SPSR_UND) 2481 .allPrivileges(); 2482 InitReg(MISCREG_ELR_HYP) 2483 .allPrivileges(); 2484 InitReg(MISCREG_FPSID) 2485 .allPrivileges(); 2486 InitReg(MISCREG_FPSCR) 2487 .allPrivileges(); 2488 InitReg(MISCREG_MVFR1) 2489 .allPrivileges(); 2490 InitReg(MISCREG_MVFR0) 2491 .allPrivileges(); 2492 InitReg(MISCREG_FPEXC) 2493 .allPrivileges(); 2494 2495 // Helper registers 2496 InitReg(MISCREG_CPSR_MODE) 2497 .allPrivileges(); 2498 InitReg(MISCREG_CPSR_Q) 2499 .allPrivileges(); 2500 InitReg(MISCREG_FPSCR_EXC) 2501 .allPrivileges(); 2502 InitReg(MISCREG_FPSCR_QC) 2503 .allPrivileges(); 2504 InitReg(MISCREG_LOCKADDR) 2505 .allPrivileges(); 2506 InitReg(MISCREG_LOCKFLAG) 2507 .allPrivileges(); 2508 InitReg(MISCREG_PRRR_MAIR0) 2509 .mutex() 2510 .banked(); 2511 InitReg(MISCREG_PRRR_MAIR0_NS) 2512 .mutex() 2513 .privSecure(!aarch32EL3) 2514 .bankedChild(); 2515 InitReg(MISCREG_PRRR_MAIR0_S) 2516 .mutex() 2517 .bankedChild(); 2518 InitReg(MISCREG_NMRR_MAIR1) 2519 .mutex() 2520 .banked(); 2521 InitReg(MISCREG_NMRR_MAIR1_NS) 2522 .mutex() 2523 .privSecure(!aarch32EL3) 2524 .bankedChild(); 2525 InitReg(MISCREG_NMRR_MAIR1_S) 2526 .mutex() 2527 .bankedChild(); 2528 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) 2529 .mutex(); 2530 InitReg(MISCREG_SCTLR_RST) 2531 .allPrivileges(); 2532 InitReg(MISCREG_SEV_MAILBOX) 2533 .allPrivileges(); 2534 2535 // AArch32 CP14 registers 2536 InitReg(MISCREG_DBGDIDR) 2537 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2538 InitReg(MISCREG_DBGDSCRint) 2539 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2540 InitReg(MISCREG_DBGDCCINT) 2541 .unimplemented() 2542 .allPrivileges(); 2543 InitReg(MISCREG_DBGDTRTXint) 2544 .unimplemented() 2545 .allPrivileges(); 2546 InitReg(MISCREG_DBGDTRRXint) 2547 .unimplemented() 2548 .allPrivileges(); 2549 InitReg(MISCREG_DBGWFAR) 2550 .unimplemented() 2551 .allPrivileges(); 2552 InitReg(MISCREG_DBGVCR) 2553 .unimplemented() 2554 .allPrivileges(); 2555 InitReg(MISCREG_DBGDTRRXext) 2556 .unimplemented() 2557 .allPrivileges(); 2558 InitReg(MISCREG_DBGDSCRext) 2559 .unimplemented() 2560 .warnNotFail() 2561 .allPrivileges(); 2562 InitReg(MISCREG_DBGDTRTXext) 2563 .unimplemented() 2564 .allPrivileges(); 2565 InitReg(MISCREG_DBGOSECCR) 2566 .unimplemented() 2567 .allPrivileges(); 2568 InitReg(MISCREG_DBGBVR0) 2569 .unimplemented() 2570 .allPrivileges(); 2571 InitReg(MISCREG_DBGBVR1) 2572 .unimplemented() 2573 .allPrivileges(); 2574 InitReg(MISCREG_DBGBVR2) 2575 .unimplemented() 2576 .allPrivileges(); 2577 InitReg(MISCREG_DBGBVR3) 2578 .unimplemented() 2579 .allPrivileges(); 2580 InitReg(MISCREG_DBGBVR4) 2581 .unimplemented() 2582 .allPrivileges(); 2583 InitReg(MISCREG_DBGBVR5) 2584 .unimplemented() 2585 .allPrivileges(); 2586 InitReg(MISCREG_DBGBCR0) 2587 .unimplemented() 2588 .allPrivileges(); 2589 InitReg(MISCREG_DBGBCR1) 2590 .unimplemented() 2591 .allPrivileges(); 2592 InitReg(MISCREG_DBGBCR2) 2593 .unimplemented() 2594 .allPrivileges(); 2595 InitReg(MISCREG_DBGBCR3) 2596 .unimplemented() 2597 .allPrivileges(); 2598 InitReg(MISCREG_DBGBCR4) 2599 .unimplemented() 2600 .allPrivileges(); 2601 InitReg(MISCREG_DBGBCR5) 2602 .unimplemented() 2603 .allPrivileges(); 2604 InitReg(MISCREG_DBGWVR0) 2605 .unimplemented() 2606 .allPrivileges(); 2607 InitReg(MISCREG_DBGWVR1) 2608 .unimplemented() 2609 .allPrivileges(); 2610 InitReg(MISCREG_DBGWVR2) 2611 .unimplemented() 2612 .allPrivileges(); 2613 InitReg(MISCREG_DBGWVR3) 2614 .unimplemented() 2615 .allPrivileges(); 2616 InitReg(MISCREG_DBGWCR0) 2617 .unimplemented() 2618 .allPrivileges(); 2619 InitReg(MISCREG_DBGWCR1) 2620 .unimplemented() 2621 .allPrivileges(); 2622 InitReg(MISCREG_DBGWCR2) 2623 .unimplemented() 2624 .allPrivileges(); 2625 InitReg(MISCREG_DBGWCR3) 2626 .unimplemented() 2627 .allPrivileges(); 2628 InitReg(MISCREG_DBGDRAR) 2629 .unimplemented() 2630 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2631 InitReg(MISCREG_DBGBXVR4) 2632 .unimplemented() 2633 .allPrivileges(); 2634 InitReg(MISCREG_DBGBXVR5) 2635 .unimplemented() 2636 .allPrivileges(); 2637 InitReg(MISCREG_DBGOSLAR) 2638 .unimplemented() 2639 .allPrivileges().monSecureRead(0).monNonSecureRead(0); 2640 InitReg(MISCREG_DBGOSLSR) 2641 .unimplemented() 2642 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2643 InitReg(MISCREG_DBGOSDLR) 2644 .unimplemented() 2645 .allPrivileges(); 2646 InitReg(MISCREG_DBGPRCR) 2647 .unimplemented() 2648 .allPrivileges(); 2649 InitReg(MISCREG_DBGDSAR) 2650 .unimplemented() 2651 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2652 InitReg(MISCREG_DBGCLAIMSET) 2653 .unimplemented() 2654 .allPrivileges(); 2655 InitReg(MISCREG_DBGCLAIMCLR) 2656 .unimplemented() 2657 .allPrivileges(); 2658 InitReg(MISCREG_DBGAUTHSTATUS) 2659 .unimplemented() 2660 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2661 InitReg(MISCREG_DBGDEVID2) 2662 .unimplemented() 2663 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2664 InitReg(MISCREG_DBGDEVID1) 2665 .unimplemented() 2666 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2667 InitReg(MISCREG_DBGDEVID0) 2668 .unimplemented() 2669 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2670 InitReg(MISCREG_TEECR) 2671 .unimplemented() 2672 .allPrivileges(); 2673 InitReg(MISCREG_JIDR) 2674 .allPrivileges(); 2675 InitReg(MISCREG_TEEHBR) 2676 .allPrivileges(); 2677 InitReg(MISCREG_JOSCR) 2678 .allPrivileges(); 2679 InitReg(MISCREG_JMCR) 2680 .allPrivileges(); 2681 2682 // AArch32 CP15 registers 2683 InitReg(MISCREG_MIDR) 2684 .allPrivileges().exceptUserMode().writes(0); 2685 InitReg(MISCREG_CTR) 2686 .allPrivileges().exceptUserMode().writes(0); 2687 InitReg(MISCREG_TCMTR) 2688 .allPrivileges().exceptUserMode().writes(0); 2689 InitReg(MISCREG_TLBTR) 2690 .allPrivileges().exceptUserMode().writes(0); 2691 InitReg(MISCREG_MPIDR) 2692 .allPrivileges().exceptUserMode().writes(0); 2693 InitReg(MISCREG_REVIDR) 2694 .unimplemented() 2695 .warnNotFail() 2696 .allPrivileges().exceptUserMode().writes(0); 2697 InitReg(MISCREG_ID_PFR0) 2698 .allPrivileges().exceptUserMode().writes(0); 2699 InitReg(MISCREG_ID_PFR1) 2700 .allPrivileges().exceptUserMode().writes(0); 2701 InitReg(MISCREG_ID_DFR0) 2702 .allPrivileges().exceptUserMode().writes(0); 2703 InitReg(MISCREG_ID_AFR0) 2704 .allPrivileges().exceptUserMode().writes(0); 2705 InitReg(MISCREG_ID_MMFR0) 2706 .allPrivileges().exceptUserMode().writes(0); 2707 InitReg(MISCREG_ID_MMFR1) 2708 .allPrivileges().exceptUserMode().writes(0); 2709 InitReg(MISCREG_ID_MMFR2) 2710 .allPrivileges().exceptUserMode().writes(0); 2711 InitReg(MISCREG_ID_MMFR3) 2712 .allPrivileges().exceptUserMode().writes(0); 2713 InitReg(MISCREG_ID_ISAR0) 2714 .allPrivileges().exceptUserMode().writes(0); 2715 InitReg(MISCREG_ID_ISAR1) 2716 .allPrivileges().exceptUserMode().writes(0); 2717 InitReg(MISCREG_ID_ISAR2) 2718 .allPrivileges().exceptUserMode().writes(0); 2719 InitReg(MISCREG_ID_ISAR3) 2720 .allPrivileges().exceptUserMode().writes(0); 2721 InitReg(MISCREG_ID_ISAR4) 2722 .allPrivileges().exceptUserMode().writes(0); 2723 InitReg(MISCREG_ID_ISAR5) 2724 .allPrivileges().exceptUserMode().writes(0); 2725 InitReg(MISCREG_CCSIDR) 2726 .allPrivileges().exceptUserMode().writes(0); 2727 InitReg(MISCREG_CLIDR) 2728 .allPrivileges().exceptUserMode().writes(0); 2729 InitReg(MISCREG_AIDR) 2730 .allPrivileges().exceptUserMode().writes(0); 2731 InitReg(MISCREG_CSSELR) 2732 .banked(); 2733 InitReg(MISCREG_CSSELR_NS) 2734 .bankedChild() 2735 .privSecure(!aarch32EL3) 2736 .nonSecure().exceptUserMode(); 2737 InitReg(MISCREG_CSSELR_S) 2738 .bankedChild() 2739 .secure().exceptUserMode(); 2740 InitReg(MISCREG_VPIDR) 2741 .hyp().monNonSecure(); 2742 InitReg(MISCREG_VMPIDR) 2743 .hyp().monNonSecure(); 2744 InitReg(MISCREG_SCTLR) 2745 .banked(); 2746 InitReg(MISCREG_SCTLR_NS) 2747 .bankedChild() 2748 .privSecure(!aarch32EL3) 2749 .nonSecure().exceptUserMode(); 2750 InitReg(MISCREG_SCTLR_S) 2751 .bankedChild() 2752 .secure().exceptUserMode(); 2753 InitReg(MISCREG_ACTLR) 2754 .banked(); 2755 InitReg(MISCREG_ACTLR_NS) 2756 .bankedChild() 2757 .privSecure(!aarch32EL3) 2758 .nonSecure().exceptUserMode(); 2759 InitReg(MISCREG_ACTLR_S) 2760 .bankedChild() 2761 .secure().exceptUserMode(); 2762 InitReg(MISCREG_CPACR) 2763 .allPrivileges().exceptUserMode(); 2764 InitReg(MISCREG_SCR) 2765 .mon().secure().exceptUserMode() 2766 .res0(0xff40) // [31:16], [6] 2767 .res1(0x0030); // [5:4] 2768 InitReg(MISCREG_SDER) 2769 .mon(); 2770 InitReg(MISCREG_NSACR) 2771 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode(); 2772 InitReg(MISCREG_HSCTLR) 2773 .hyp().monNonSecure(); 2774 InitReg(MISCREG_HACTLR) 2775 .hyp().monNonSecure(); 2776 InitReg(MISCREG_HCR) 2777 .hyp().monNonSecure(); 2778 InitReg(MISCREG_HDCR) 2779 .hyp().monNonSecure(); 2780 InitReg(MISCREG_HCPTR) 2781 .hyp().monNonSecure(); 2782 InitReg(MISCREG_HSTR) 2783 .hyp().monNonSecure(); 2784 InitReg(MISCREG_HACR) 2785 .unimplemented() 2786 .warnNotFail() 2787 .hyp().monNonSecure(); 2788 InitReg(MISCREG_TTBR0) 2789 .banked(); 2790 InitReg(MISCREG_TTBR0_NS) 2791 .bankedChild() 2792 .privSecure(!aarch32EL3) 2793 .nonSecure().exceptUserMode(); 2794 InitReg(MISCREG_TTBR0_S) 2795 .bankedChild() 2796 .secure().exceptUserMode(); 2797 InitReg(MISCREG_TTBR1) 2798 .banked(); 2799 InitReg(MISCREG_TTBR1_NS) 2800 .bankedChild() 2801 .privSecure(!aarch32EL3) 2802 .nonSecure().exceptUserMode(); 2803 InitReg(MISCREG_TTBR1_S) 2804 .bankedChild() 2805 .secure().exceptUserMode(); 2806 InitReg(MISCREG_TTBCR) 2807 .banked(); 2808 InitReg(MISCREG_TTBCR_NS) 2809 .bankedChild() 2810 .privSecure(!aarch32EL3) 2811 .nonSecure().exceptUserMode(); 2812 InitReg(MISCREG_TTBCR_S) 2813 .bankedChild() 2814 .secure().exceptUserMode(); 2815 InitReg(MISCREG_HTCR) 2816 .hyp().monNonSecure(); 2817 InitReg(MISCREG_VTCR) 2818 .hyp().monNonSecure(); 2819 InitReg(MISCREG_DACR) 2820 .banked(); 2821 InitReg(MISCREG_DACR_NS) 2822 .bankedChild() 2823 .privSecure(!aarch32EL3) 2824 .nonSecure().exceptUserMode(); 2825 InitReg(MISCREG_DACR_S) 2826 .bankedChild() 2827 .secure().exceptUserMode(); 2828 InitReg(MISCREG_DFSR) 2829 .banked(); 2830 InitReg(MISCREG_DFSR_NS) 2831 .bankedChild() 2832 .privSecure(!aarch32EL3) 2833 .nonSecure().exceptUserMode(); 2834 InitReg(MISCREG_DFSR_S) 2835 .bankedChild() 2836 .secure().exceptUserMode(); 2837 InitReg(MISCREG_IFSR) 2838 .banked(); 2839 InitReg(MISCREG_IFSR_NS) 2840 .bankedChild() 2841 .privSecure(!aarch32EL3) 2842 .nonSecure().exceptUserMode(); 2843 InitReg(MISCREG_IFSR_S) 2844 .bankedChild() 2845 .secure().exceptUserMode(); 2846 InitReg(MISCREG_ADFSR) 2847 .unimplemented() 2848 .warnNotFail() 2849 .banked(); 2850 InitReg(MISCREG_ADFSR_NS) 2851 .unimplemented() 2852 .warnNotFail() 2853 .bankedChild() 2854 .privSecure(!aarch32EL3) 2855 .nonSecure().exceptUserMode(); 2856 InitReg(MISCREG_ADFSR_S) 2857 .unimplemented() 2858 .warnNotFail() 2859 .bankedChild() 2860 .secure().exceptUserMode(); 2861 InitReg(MISCREG_AIFSR) 2862 .unimplemented() 2863 .warnNotFail() 2864 .banked(); 2865 InitReg(MISCREG_AIFSR_NS) 2866 .unimplemented() 2867 .warnNotFail() 2868 .bankedChild() 2869 .privSecure(!aarch32EL3) 2870 .nonSecure().exceptUserMode(); 2871 InitReg(MISCREG_AIFSR_S) 2872 .unimplemented() 2873 .warnNotFail() 2874 .bankedChild() 2875 .secure().exceptUserMode(); 2876 InitReg(MISCREG_HADFSR) 2877 .hyp().monNonSecure(); 2878 InitReg(MISCREG_HAIFSR) 2879 .hyp().monNonSecure(); 2880 InitReg(MISCREG_HSR) 2881 .hyp().monNonSecure(); 2882 InitReg(MISCREG_DFAR) 2883 .banked(); 2884 InitReg(MISCREG_DFAR_NS) 2885 .bankedChild() 2886 .privSecure(!aarch32EL3) 2887 .nonSecure().exceptUserMode(); 2888 InitReg(MISCREG_DFAR_S) 2889 .bankedChild() 2890 .secure().exceptUserMode(); 2891 InitReg(MISCREG_IFAR) 2892 .banked(); 2893 InitReg(MISCREG_IFAR_NS) 2894 .bankedChild() 2895 .privSecure(!aarch32EL3) 2896 .nonSecure().exceptUserMode(); 2897 InitReg(MISCREG_IFAR_S) 2898 .bankedChild() 2899 .secure().exceptUserMode(); 2900 InitReg(MISCREG_HDFAR) 2901 .hyp().monNonSecure(); 2902 InitReg(MISCREG_HIFAR) 2903 .hyp().monNonSecure(); 2904 InitReg(MISCREG_HPFAR) 2905 .hyp().monNonSecure(); 2906 InitReg(MISCREG_ICIALLUIS) 2907 .unimplemented() 2908 .warnNotFail() 2909 .writes(1).exceptUserMode(); 2910 InitReg(MISCREG_BPIALLIS) 2911 .unimplemented() 2912 .warnNotFail() 2913 .writes(1).exceptUserMode(); 2914 InitReg(MISCREG_PAR) 2915 .banked(); 2916 InitReg(MISCREG_PAR_NS) 2917 .bankedChild() 2918 .privSecure(!aarch32EL3) 2919 .nonSecure().exceptUserMode(); 2920 InitReg(MISCREG_PAR_S) 2921 .bankedChild() 2922 .secure().exceptUserMode(); 2923 InitReg(MISCREG_ICIALLU) 2924 .writes(1).exceptUserMode(); 2925 InitReg(MISCREG_ICIMVAU) 2926 .unimplemented() 2927 .warnNotFail() 2928 .writes(1).exceptUserMode(); 2929 InitReg(MISCREG_CP15ISB) 2930 .writes(1); 2931 InitReg(MISCREG_BPIALL) 2932 .unimplemented() 2933 .warnNotFail() 2934 .writes(1).exceptUserMode(); 2935 InitReg(MISCREG_BPIMVA) 2936 .unimplemented() 2937 .warnNotFail() 2938 .writes(1).exceptUserMode(); 2939 InitReg(MISCREG_DCIMVAC) 2940 .unimplemented() 2941 .warnNotFail() 2942 .writes(1).exceptUserMode(); 2943 InitReg(MISCREG_DCISW) 2944 .unimplemented() 2945 .warnNotFail() 2946 .writes(1).exceptUserMode(); 2947 InitReg(MISCREG_ATS1CPR) 2948 .writes(1).exceptUserMode(); 2949 InitReg(MISCREG_ATS1CPW) 2950 .writes(1).exceptUserMode(); 2951 InitReg(MISCREG_ATS1CUR) 2952 .writes(1).exceptUserMode(); 2953 InitReg(MISCREG_ATS1CUW) 2954 .writes(1).exceptUserMode(); 2955 InitReg(MISCREG_ATS12NSOPR) 2956 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2957 InitReg(MISCREG_ATS12NSOPW) 2958 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2959 InitReg(MISCREG_ATS12NSOUR) 2960 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2961 InitReg(MISCREG_ATS12NSOUW) 2962 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2963 InitReg(MISCREG_DCCMVAC) 2964 .writes(1).exceptUserMode(); 2965 InitReg(MISCREG_DCCSW) 2966 .unimplemented() 2967 .warnNotFail() 2968 .writes(1).exceptUserMode(); 2969 InitReg(MISCREG_CP15DSB) 2970 .writes(1); 2971 InitReg(MISCREG_CP15DMB) 2972 .writes(1); 2973 InitReg(MISCREG_DCCMVAU) 2974 .unimplemented() 2975 .warnNotFail() 2976 .writes(1).exceptUserMode(); 2977 InitReg(MISCREG_DCCIMVAC) 2978 .unimplemented() 2979 .warnNotFail() 2980 .writes(1).exceptUserMode(); 2981 InitReg(MISCREG_DCCISW) 2982 .unimplemented() 2983 .warnNotFail() 2984 .writes(1).exceptUserMode(); 2985 InitReg(MISCREG_ATS1HR) 2986 .monNonSecureWrite().hypWrite(); 2987 InitReg(MISCREG_ATS1HW) 2988 .monNonSecureWrite().hypWrite(); 2989 InitReg(MISCREG_TLBIALLIS) 2990 .writes(1).exceptUserMode(); 2991 InitReg(MISCREG_TLBIMVAIS) 2992 .writes(1).exceptUserMode(); 2993 InitReg(MISCREG_TLBIASIDIS) 2994 .writes(1).exceptUserMode(); 2995 InitReg(MISCREG_TLBIMVAAIS) 2996 .writes(1).exceptUserMode(); 2997 InitReg(MISCREG_TLBIMVALIS) 2998 .writes(1).exceptUserMode(); 2999 InitReg(MISCREG_TLBIMVAALIS) 3000 .writes(1).exceptUserMode(); 3001 InitReg(MISCREG_ITLBIALL) 3002 .writes(1).exceptUserMode(); 3003 InitReg(MISCREG_ITLBIMVA) 3004 .writes(1).exceptUserMode(); 3005 InitReg(MISCREG_ITLBIASID) 3006 .writes(1).exceptUserMode(); 3007 InitReg(MISCREG_DTLBIALL) 3008 .writes(1).exceptUserMode(); 3009 InitReg(MISCREG_DTLBIMVA) 3010 .writes(1).exceptUserMode(); 3011 InitReg(MISCREG_DTLBIASID) 3012 .writes(1).exceptUserMode(); 3013 InitReg(MISCREG_TLBIALL) 3014 .writes(1).exceptUserMode(); 3015 InitReg(MISCREG_TLBIMVA) 3016 .writes(1).exceptUserMode(); 3017 InitReg(MISCREG_TLBIASID) 3018 .writes(1).exceptUserMode(); 3019 InitReg(MISCREG_TLBIMVAA) 3020 .writes(1).exceptUserMode(); 3021 InitReg(MISCREG_TLBIMVAL) 3022 .writes(1).exceptUserMode(); 3023 InitReg(MISCREG_TLBIMVAAL) 3024 .writes(1).exceptUserMode(); 3025 InitReg(MISCREG_TLBIIPAS2IS) 3026 .monNonSecureWrite().hypWrite(); 3027 InitReg(MISCREG_TLBIIPAS2LIS) 3028 .monNonSecureWrite().hypWrite(); 3029 InitReg(MISCREG_TLBIALLHIS) 3030 .monNonSecureWrite().hypWrite(); 3031 InitReg(MISCREG_TLBIMVAHIS) 3032 .monNonSecureWrite().hypWrite(); 3033 InitReg(MISCREG_TLBIALLNSNHIS) 3034 .monNonSecureWrite().hypWrite(); 3035 InitReg(MISCREG_TLBIMVALHIS) 3036 .monNonSecureWrite().hypWrite(); 3037 InitReg(MISCREG_TLBIIPAS2) 3038 .monNonSecureWrite().hypWrite(); 3039 InitReg(MISCREG_TLBIIPAS2L) 3040 .monNonSecureWrite().hypWrite(); 3041 InitReg(MISCREG_TLBIALLH) 3042 .monNonSecureWrite().hypWrite(); 3043 InitReg(MISCREG_TLBIMVAH) 3044 .monNonSecureWrite().hypWrite(); 3045 InitReg(MISCREG_TLBIALLNSNH) 3046 .monNonSecureWrite().hypWrite(); 3047 InitReg(MISCREG_TLBIMVALH) 3048 .monNonSecureWrite().hypWrite(); 3049 InitReg(MISCREG_PMCR) 3050 .allPrivileges(); 3051 InitReg(MISCREG_PMCNTENSET) 3052 .allPrivileges(); 3053 InitReg(MISCREG_PMCNTENCLR) 3054 .allPrivileges(); 3055 InitReg(MISCREG_PMOVSR) 3056 .allPrivileges(); 3057 InitReg(MISCREG_PMSWINC) 3058 .allPrivileges(); 3059 InitReg(MISCREG_PMSELR) 3060 .allPrivileges(); 3061 InitReg(MISCREG_PMCEID0) 3062 .allPrivileges(); 3063 InitReg(MISCREG_PMCEID1) 3064 .allPrivileges(); 3065 InitReg(MISCREG_PMCCNTR) 3066 .allPrivileges(); 3067 InitReg(MISCREG_PMXEVTYPER) 3068 .allPrivileges(); 3069 InitReg(MISCREG_PMCCFILTR) 3070 .allPrivileges(); 3071 InitReg(MISCREG_PMXEVCNTR) 3072 .allPrivileges(); 3073 InitReg(MISCREG_PMUSERENR) 3074 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0); 3075 InitReg(MISCREG_PMINTENSET) 3076 .allPrivileges().exceptUserMode(); 3077 InitReg(MISCREG_PMINTENCLR) 3078 .allPrivileges().exceptUserMode(); 3079 InitReg(MISCREG_PMOVSSET) 3080 .unimplemented() 3081 .allPrivileges(); 3082 InitReg(MISCREG_L2CTLR) 3083 .allPrivileges().exceptUserMode(); 3084 InitReg(MISCREG_L2ECTLR) 3085 .unimplemented() 3086 .allPrivileges().exceptUserMode(); 3087 InitReg(MISCREG_PRRR) 3088 .banked(); 3089 InitReg(MISCREG_PRRR_NS) 3090 .bankedChild() 3091 .privSecure(!aarch32EL3) 3092 .nonSecure().exceptUserMode(); 3093 InitReg(MISCREG_PRRR_S) 3094 .bankedChild() 3095 .secure().exceptUserMode(); 3096 InitReg(MISCREG_MAIR0) 3097 .banked(); 3098 InitReg(MISCREG_MAIR0_NS) 3099 .bankedChild() 3100 .privSecure(!aarch32EL3) 3101 .nonSecure().exceptUserMode(); 3102 InitReg(MISCREG_MAIR0_S) 3103 .bankedChild() 3104 .secure().exceptUserMode(); 3105 InitReg(MISCREG_NMRR) 3106 .banked(); 3107 InitReg(MISCREG_NMRR_NS) 3108 .bankedChild() 3109 .privSecure(!aarch32EL3) 3110 .nonSecure().exceptUserMode(); 3111 InitReg(MISCREG_NMRR_S) 3112 .bankedChild() 3113 .secure().exceptUserMode(); 3114 InitReg(MISCREG_MAIR1) 3115 .banked(); 3116 InitReg(MISCREG_MAIR1_NS) 3117 .bankedChild() 3118 .privSecure(!aarch32EL3) 3119 .nonSecure().exceptUserMode(); 3120 InitReg(MISCREG_MAIR1_S) 3121 .bankedChild() 3122 .secure().exceptUserMode(); 3123 InitReg(MISCREG_AMAIR0) 3124 .banked(); 3125 InitReg(MISCREG_AMAIR0_NS) 3126 .bankedChild() 3127 .privSecure(!aarch32EL3) 3128 .nonSecure().exceptUserMode(); 3129 InitReg(MISCREG_AMAIR0_S) 3130 .bankedChild() 3131 .secure().exceptUserMode(); 3132 InitReg(MISCREG_AMAIR1) 3133 .banked(); 3134 InitReg(MISCREG_AMAIR1_NS) 3135 .bankedChild() 3136 .privSecure(!aarch32EL3) 3137 .nonSecure().exceptUserMode(); 3138 InitReg(MISCREG_AMAIR1_S) 3139 .bankedChild() 3140 .secure().exceptUserMode(); 3141 InitReg(MISCREG_HMAIR0) 3142 .hyp().monNonSecure(); 3143 InitReg(MISCREG_HMAIR1) 3144 .hyp().monNonSecure(); 3145 InitReg(MISCREG_HAMAIR0) 3146 .unimplemented() 3147 .warnNotFail() 3148 .hyp().monNonSecure(); 3149 InitReg(MISCREG_HAMAIR1) 3150 .unimplemented() 3151 .warnNotFail() 3152 .hyp().monNonSecure(); 3153 InitReg(MISCREG_VBAR) 3154 .banked(); 3155 InitReg(MISCREG_VBAR_NS) 3156 .bankedChild() 3157 .privSecure(!aarch32EL3) 3158 .nonSecure().exceptUserMode(); 3159 InitReg(MISCREG_VBAR_S) 3160 .bankedChild() 3161 .secure().exceptUserMode(); 3162 InitReg(MISCREG_MVBAR) 3163 .mon().secure().exceptUserMode(); 3164 InitReg(MISCREG_RMR) 3165 .unimplemented() 3166 .mon().secure().exceptUserMode(); 3167 InitReg(MISCREG_ISR) 3168 .allPrivileges().exceptUserMode().writes(0); 3169 InitReg(MISCREG_HVBAR) 3170 .hyp().monNonSecure(); 3171 InitReg(MISCREG_FCSEIDR) 3172 .unimplemented() 3173 .warnNotFail() 3174 .allPrivileges().exceptUserMode(); 3175 InitReg(MISCREG_CONTEXTIDR) 3176 .banked(); 3177 InitReg(MISCREG_CONTEXTIDR_NS) 3178 .bankedChild() 3179 .privSecure(!aarch32EL3) 3180 .nonSecure().exceptUserMode(); 3181 InitReg(MISCREG_CONTEXTIDR_S) 3182 .bankedChild() 3183 .secure().exceptUserMode(); 3184 InitReg(MISCREG_TPIDRURW) 3185 .banked(); 3186 InitReg(MISCREG_TPIDRURW_NS) 3187 .bankedChild() 3188 .allPrivileges() 3189 .privSecure(!aarch32EL3) 3190 .monSecure(0); 3191 InitReg(MISCREG_TPIDRURW_S) 3192 .bankedChild() 3193 .secure(); 3194 InitReg(MISCREG_TPIDRURO) 3195 .banked(); 3196 InitReg(MISCREG_TPIDRURO_NS) 3197 .bankedChild() 3198 .allPrivileges() 3199 .userNonSecureWrite(0).userSecureRead(1) 3200 .privSecure(!aarch32EL3) 3201 .monSecure(0); 3202 InitReg(MISCREG_TPIDRURO_S) 3203 .bankedChild() 3204 .secure().userSecureWrite(0); 3205 InitReg(MISCREG_TPIDRPRW) 3206 .banked(); 3207 InitReg(MISCREG_TPIDRPRW_NS) 3208 .bankedChild() 3209 .nonSecure().exceptUserMode() 3210 .privSecure(!aarch32EL3); 3211 InitReg(MISCREG_TPIDRPRW_S) 3212 .bankedChild() 3213 .secure().exceptUserMode(); 3214 InitReg(MISCREG_HTPIDR) 3215 .hyp().monNonSecure(); 3216 InitReg(MISCREG_CNTFRQ) 3217 .unverifiable() 3218 .reads(1).mon(); 3219 InitReg(MISCREG_CNTKCTL) 3220 .allPrivileges().exceptUserMode(); 3221 InitReg(MISCREG_CNTP_TVAL) 3222 .banked(); 3223 InitReg(MISCREG_CNTP_TVAL_NS) 3224 .bankedChild() 3225 .allPrivileges() 3226 .privSecure(!aarch32EL3) 3227 .monSecure(0); 3228 InitReg(MISCREG_CNTP_TVAL_S) 3229 .bankedChild() 3230 .secure().user(1); 3231 InitReg(MISCREG_CNTP_CTL) 3232 .banked(); 3233 InitReg(MISCREG_CNTP_CTL_NS) 3234 .bankedChild() 3235 .allPrivileges() 3236 .privSecure(!aarch32EL3) 3237 .monSecure(0); 3238 InitReg(MISCREG_CNTP_CTL_S) 3239 .bankedChild() 3240 .secure().user(1); 3241 InitReg(MISCREG_CNTV_TVAL) 3242 .allPrivileges(); 3243 InitReg(MISCREG_CNTV_CTL) 3244 .allPrivileges(); 3245 InitReg(MISCREG_CNTHCTL) 3246 .hypWrite().monNonSecureRead(); 3247 InitReg(MISCREG_CNTHP_TVAL) 3248 .hypWrite().monNonSecureRead(); 3249 InitReg(MISCREG_CNTHP_CTL) 3250 .hypWrite().monNonSecureRead(); 3251 InitReg(MISCREG_IL1DATA0) 3252 .unimplemented() 3253 .allPrivileges().exceptUserMode(); 3254 InitReg(MISCREG_IL1DATA1) 3255 .unimplemented() 3256 .allPrivileges().exceptUserMode(); 3257 InitReg(MISCREG_IL1DATA2) 3258 .unimplemented() 3259 .allPrivileges().exceptUserMode(); 3260 InitReg(MISCREG_IL1DATA3) 3261 .unimplemented() 3262 .allPrivileges().exceptUserMode(); 3263 InitReg(MISCREG_DL1DATA0) 3264 .unimplemented() 3265 .allPrivileges().exceptUserMode(); 3266 InitReg(MISCREG_DL1DATA1) 3267 .unimplemented() 3268 .allPrivileges().exceptUserMode(); 3269 InitReg(MISCREG_DL1DATA2) 3270 .unimplemented() 3271 .allPrivileges().exceptUserMode(); 3272 InitReg(MISCREG_DL1DATA3) 3273 .unimplemented() 3274 .allPrivileges().exceptUserMode(); 3275 InitReg(MISCREG_DL1DATA4) 3276 .unimplemented() 3277 .allPrivileges().exceptUserMode(); 3278 InitReg(MISCREG_RAMINDEX) 3279 .unimplemented() 3280 .writes(1).exceptUserMode(); 3281 InitReg(MISCREG_L2ACTLR) 3282 .unimplemented() 3283 .allPrivileges().exceptUserMode(); 3284 InitReg(MISCREG_CBAR) 3285 .unimplemented() 3286 .allPrivileges().exceptUserMode().writes(0); 3287 InitReg(MISCREG_HTTBR) 3288 .hyp().monNonSecure(); 3289 InitReg(MISCREG_VTTBR) 3290 .hyp().monNonSecure(); 3291 InitReg(MISCREG_CNTPCT) 3292 .reads(1); 3293 InitReg(MISCREG_CNTVCT) 3294 .unverifiable() 3295 .reads(1); 3296 InitReg(MISCREG_CNTP_CVAL) 3297 .banked(); 3298 InitReg(MISCREG_CNTP_CVAL_NS) 3299 .bankedChild() 3300 .allPrivileges() 3301 .privSecure(!aarch32EL3) 3302 .monSecure(0); 3303 InitReg(MISCREG_CNTP_CVAL_S) 3304 .bankedChild() 3305 .secure().user(1); 3306 InitReg(MISCREG_CNTV_CVAL) 3307 .allPrivileges(); 3308 InitReg(MISCREG_CNTVOFF) 3309 .hyp().monNonSecure(); 3310 InitReg(MISCREG_CNTHP_CVAL) 3311 .hypWrite().monNonSecureRead(); 3312 InitReg(MISCREG_CPUMERRSR) 3313 .unimplemented() 3314 .allPrivileges().exceptUserMode(); 3315 InitReg(MISCREG_L2MERRSR) 3316 .unimplemented() 3317 .warnNotFail() 3318 .allPrivileges().exceptUserMode(); 3319 3320 // AArch64 registers (Op0=2); 3321 InitReg(MISCREG_MDCCINT_EL1) 3322 .allPrivileges(); 3323 InitReg(MISCREG_OSDTRRX_EL1) 3324 .allPrivileges() 3325 .mapsTo(MISCREG_DBGDTRRXext); 3326 InitReg(MISCREG_MDSCR_EL1) 3327 .allPrivileges() 3328 .mapsTo(MISCREG_DBGDSCRext); 3329 InitReg(MISCREG_OSDTRTX_EL1) 3330 .allPrivileges() 3331 .mapsTo(MISCREG_DBGDTRTXext); 3332 InitReg(MISCREG_OSECCR_EL1) 3333 .allPrivileges() 3334 .mapsTo(MISCREG_DBGOSECCR); 3335 InitReg(MISCREG_DBGBVR0_EL1) 3336 .allPrivileges() 3337 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */); 3338 InitReg(MISCREG_DBGBVR1_EL1) 3339 .allPrivileges() 3340 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */); 3341 InitReg(MISCREG_DBGBVR2_EL1) 3342 .allPrivileges() 3343 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */); 3344 InitReg(MISCREG_DBGBVR3_EL1) 3345 .allPrivileges() 3346 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */); 3347 InitReg(MISCREG_DBGBVR4_EL1) 3348 .allPrivileges() 3349 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */); 3350 InitReg(MISCREG_DBGBVR5_EL1) 3351 .allPrivileges() 3352 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */); 3353 InitReg(MISCREG_DBGBCR0_EL1) 3354 .allPrivileges() 3355 .mapsTo(MISCREG_DBGBCR0); 3356 InitReg(MISCREG_DBGBCR1_EL1) 3357 .allPrivileges() 3358 .mapsTo(MISCREG_DBGBCR1); 3359 InitReg(MISCREG_DBGBCR2_EL1) 3360 .allPrivileges() 3361 .mapsTo(MISCREG_DBGBCR2); 3362 InitReg(MISCREG_DBGBCR3_EL1) 3363 .allPrivileges() 3364 .mapsTo(MISCREG_DBGBCR3); 3365 InitReg(MISCREG_DBGBCR4_EL1) 3366 .allPrivileges() 3367 .mapsTo(MISCREG_DBGBCR4); 3368 InitReg(MISCREG_DBGBCR5_EL1) 3369 .allPrivileges() 3370 .mapsTo(MISCREG_DBGBCR5); 3371 InitReg(MISCREG_DBGWVR0_EL1) 3372 .allPrivileges() 3373 .mapsTo(MISCREG_DBGWVR0); 3374 InitReg(MISCREG_DBGWVR1_EL1) 3375 .allPrivileges() 3376 .mapsTo(MISCREG_DBGWVR1); 3377 InitReg(MISCREG_DBGWVR2_EL1) 3378 .allPrivileges() 3379 .mapsTo(MISCREG_DBGWVR2); 3380 InitReg(MISCREG_DBGWVR3_EL1) 3381 .allPrivileges() 3382 .mapsTo(MISCREG_DBGWVR3); 3383 InitReg(MISCREG_DBGWCR0_EL1) 3384 .allPrivileges() 3385 .mapsTo(MISCREG_DBGWCR0); 3386 InitReg(MISCREG_DBGWCR1_EL1) 3387 .allPrivileges() 3388 .mapsTo(MISCREG_DBGWCR1); 3389 InitReg(MISCREG_DBGWCR2_EL1) 3390 .allPrivileges() 3391 .mapsTo(MISCREG_DBGWCR2); 3392 InitReg(MISCREG_DBGWCR3_EL1) 3393 .allPrivileges() 3394 .mapsTo(MISCREG_DBGWCR3); 3395 InitReg(MISCREG_MDCCSR_EL0) 3396 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3397 .mapsTo(MISCREG_DBGDSCRint); 3398 InitReg(MISCREG_MDDTR_EL0) 3399 .allPrivileges(); 3400 InitReg(MISCREG_MDDTRTX_EL0) 3401 .allPrivileges(); 3402 InitReg(MISCREG_MDDTRRX_EL0) 3403 .allPrivileges(); 3404 InitReg(MISCREG_DBGVCR32_EL2) 3405 .allPrivileges() 3406 .mapsTo(MISCREG_DBGVCR); 3407 InitReg(MISCREG_MDRAR_EL1) 3408 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3409 .mapsTo(MISCREG_DBGDRAR); 3410 InitReg(MISCREG_OSLAR_EL1) 3411 .allPrivileges().monSecureRead(0).monNonSecureRead(0) 3412 .mapsTo(MISCREG_DBGOSLAR); 3413 InitReg(MISCREG_OSLSR_EL1) 3414 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3415 .mapsTo(MISCREG_DBGOSLSR); 3416 InitReg(MISCREG_OSDLR_EL1) 3417 .allPrivileges() 3418 .mapsTo(MISCREG_DBGOSDLR); 3419 InitReg(MISCREG_DBGPRCR_EL1) 3420 .allPrivileges() 3421 .mapsTo(MISCREG_DBGPRCR); 3422 InitReg(MISCREG_DBGCLAIMSET_EL1) 3423 .allPrivileges() 3424 .mapsTo(MISCREG_DBGCLAIMSET); 3425 InitReg(MISCREG_DBGCLAIMCLR_EL1) 3426 .allPrivileges() 3427 .mapsTo(MISCREG_DBGCLAIMCLR); 3428 InitReg(MISCREG_DBGAUTHSTATUS_EL1) 3429 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3430 .mapsTo(MISCREG_DBGAUTHSTATUS); 3431 InitReg(MISCREG_TEECR32_EL1); 3432 InitReg(MISCREG_TEEHBR32_EL1); 3433 3434 // AArch64 registers (Op0=1,3); 3435 InitReg(MISCREG_MIDR_EL1) 3436 .allPrivileges().exceptUserMode().writes(0); 3437 InitReg(MISCREG_MPIDR_EL1) 3438 .allPrivileges().exceptUserMode().writes(0); 3439 InitReg(MISCREG_REVIDR_EL1) 3440 .allPrivileges().exceptUserMode().writes(0); 3441 InitReg(MISCREG_ID_PFR0_EL1) 3442 .allPrivileges().exceptUserMode().writes(0) 3443 .mapsTo(MISCREG_ID_PFR0); 3444 InitReg(MISCREG_ID_PFR1_EL1) 3445 .allPrivileges().exceptUserMode().writes(0) 3446 .mapsTo(MISCREG_ID_PFR1); 3447 InitReg(MISCREG_ID_DFR0_EL1) 3448 .allPrivileges().exceptUserMode().writes(0) 3449 .mapsTo(MISCREG_ID_DFR0); 3450 InitReg(MISCREG_ID_AFR0_EL1) 3451 .allPrivileges().exceptUserMode().writes(0) 3452 .mapsTo(MISCREG_ID_AFR0); 3453 InitReg(MISCREG_ID_MMFR0_EL1) 3454 .allPrivileges().exceptUserMode().writes(0) 3455 .mapsTo(MISCREG_ID_MMFR0); 3456 InitReg(MISCREG_ID_MMFR1_EL1) 3457 .allPrivileges().exceptUserMode().writes(0) 3458 .mapsTo(MISCREG_ID_MMFR1); 3459 InitReg(MISCREG_ID_MMFR2_EL1) 3460 .allPrivileges().exceptUserMode().writes(0) 3461 .mapsTo(MISCREG_ID_MMFR2); 3462 InitReg(MISCREG_ID_MMFR3_EL1) 3463 .allPrivileges().exceptUserMode().writes(0) 3464 .mapsTo(MISCREG_ID_MMFR3); 3465 InitReg(MISCREG_ID_ISAR0_EL1) 3466 .allPrivileges().exceptUserMode().writes(0) 3467 .mapsTo(MISCREG_ID_ISAR0); 3468 InitReg(MISCREG_ID_ISAR1_EL1) 3469 .allPrivileges().exceptUserMode().writes(0) 3470 .mapsTo(MISCREG_ID_ISAR1); 3471 InitReg(MISCREG_ID_ISAR2_EL1) 3472 .allPrivileges().exceptUserMode().writes(0) 3473 .mapsTo(MISCREG_ID_ISAR2); 3474 InitReg(MISCREG_ID_ISAR3_EL1) 3475 .allPrivileges().exceptUserMode().writes(0) 3476 .mapsTo(MISCREG_ID_ISAR3); 3477 InitReg(MISCREG_ID_ISAR4_EL1) 3478 .allPrivileges().exceptUserMode().writes(0) 3479 .mapsTo(MISCREG_ID_ISAR4); 3480 InitReg(MISCREG_ID_ISAR5_EL1) 3481 .allPrivileges().exceptUserMode().writes(0) 3482 .mapsTo(MISCREG_ID_ISAR5); 3483 InitReg(MISCREG_MVFR0_EL1) 3484 .allPrivileges().exceptUserMode().writes(0); 3485 InitReg(MISCREG_MVFR1_EL1) 3486 .allPrivileges().exceptUserMode().writes(0); 3487 InitReg(MISCREG_MVFR2_EL1) 3488 .allPrivileges().exceptUserMode().writes(0); 3489 InitReg(MISCREG_ID_AA64PFR0_EL1) 3490 .allPrivileges().exceptUserMode().writes(0); 3491 InitReg(MISCREG_ID_AA64PFR1_EL1) 3492 .allPrivileges().exceptUserMode().writes(0); 3493 InitReg(MISCREG_ID_AA64DFR0_EL1) 3494 .allPrivileges().exceptUserMode().writes(0); 3495 InitReg(MISCREG_ID_AA64DFR1_EL1) 3496 .allPrivileges().exceptUserMode().writes(0); 3497 InitReg(MISCREG_ID_AA64AFR0_EL1) 3498 .allPrivileges().exceptUserMode().writes(0); 3499 InitReg(MISCREG_ID_AA64AFR1_EL1) 3500 .allPrivileges().exceptUserMode().writes(0); 3501 InitReg(MISCREG_ID_AA64ISAR0_EL1) 3502 .allPrivileges().exceptUserMode().writes(0); 3503 InitReg(MISCREG_ID_AA64ISAR1_EL1) 3504 .allPrivileges().exceptUserMode().writes(0); 3505 InitReg(MISCREG_ID_AA64MMFR0_EL1) 3506 .allPrivileges().exceptUserMode().writes(0); 3507 InitReg(MISCREG_ID_AA64MMFR1_EL1) 3508 .allPrivileges().exceptUserMode().writes(0); 3509 InitReg(MISCREG_ID_AA64MMFR2_EL1) 3510 .allPrivileges().exceptUserMode().writes(0); 3511 InitReg(MISCREG_CCSIDR_EL1) 3512 .allPrivileges().exceptUserMode().writes(0); 3513 InitReg(MISCREG_CLIDR_EL1) 3514 .allPrivileges().exceptUserMode().writes(0); 3515 InitReg(MISCREG_AIDR_EL1) 3516 .allPrivileges().exceptUserMode().writes(0); 3517 InitReg(MISCREG_CSSELR_EL1) 3518 .allPrivileges().exceptUserMode() 3519 .mapsTo(MISCREG_CSSELR_NS); 3520 InitReg(MISCREG_CTR_EL0) 3521 .reads(1); 3522 InitReg(MISCREG_DCZID_EL0) 3523 .reads(1); 3524 InitReg(MISCREG_VPIDR_EL2) 3525 .hyp().mon() 3526 .mapsTo(MISCREG_VPIDR); 3527 InitReg(MISCREG_VMPIDR_EL2) 3528 .hyp().mon() 3529 .mapsTo(MISCREG_VMPIDR); 3530 InitReg(MISCREG_SCTLR_EL1) 3531 .allPrivileges().exceptUserMode() 3532 .mapsTo(MISCREG_SCTLR_NS); 3533 InitReg(MISCREG_ACTLR_EL1) 3534 .allPrivileges().exceptUserMode() 3535 .mapsTo(MISCREG_ACTLR_NS); 3536 InitReg(MISCREG_CPACR_EL1) 3537 .allPrivileges().exceptUserMode() 3538 .mapsTo(MISCREG_CPACR); 3539 InitReg(MISCREG_SCTLR_EL2) 3540 .hyp().mon() 3541 .mapsTo(MISCREG_HSCTLR); 3542 InitReg(MISCREG_ACTLR_EL2) 3543 .hyp().mon() 3544 .mapsTo(MISCREG_HACTLR); 3545 InitReg(MISCREG_HCR_EL2) 3546 .hyp().mon() 3547 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/); 3548 InitReg(MISCREG_MDCR_EL2) 3549 .hyp().mon() 3550 .mapsTo(MISCREG_HDCR); 3551 InitReg(MISCREG_CPTR_EL2) 3552 .hyp().mon() 3553 .mapsTo(MISCREG_HCPTR); 3554 InitReg(MISCREG_HSTR_EL2) 3555 .hyp().mon() 3556 .mapsTo(MISCREG_HSTR); 3557 InitReg(MISCREG_HACR_EL2) 3558 .hyp().mon() 3559 .mapsTo(MISCREG_HACR); 3560 InitReg(MISCREG_SCTLR_EL3) 3561 .mon(); 3562 InitReg(MISCREG_ACTLR_EL3) 3563 .mon(); 3564 InitReg(MISCREG_SCR_EL3) 3565 .mon() 3566 .mapsTo(MISCREG_SCR); // NAM D7-2005 3567 InitReg(MISCREG_SDER32_EL3) 3568 .mon() 3569 .mapsTo(MISCREG_SDER); 3570 InitReg(MISCREG_CPTR_EL3) 3571 .mon(); 3572 InitReg(MISCREG_MDCR_EL3) 3573 .mon(); 3574 InitReg(MISCREG_TTBR0_EL1) 3575 .allPrivileges().exceptUserMode() 3576 .mapsTo(MISCREG_TTBR0_NS); 3577 InitReg(MISCREG_TTBR1_EL1) 3578 .allPrivileges().exceptUserMode() 3579 .mapsTo(MISCREG_TTBR1_NS); 3580 InitReg(MISCREG_TCR_EL1) 3581 .allPrivileges().exceptUserMode() 3582 .mapsTo(MISCREG_TTBCR_NS); 3583 InitReg(MISCREG_TTBR0_EL2) 3584 .hyp().mon() 3585 .mapsTo(MISCREG_HTTBR); 3586 InitReg(MISCREG_TTBR1_EL2) 3587 .hyp().mon(); 3588 InitReg(MISCREG_TCR_EL2) 3589 .hyp().mon() 3590 .mapsTo(MISCREG_HTCR); 3591 InitReg(MISCREG_VTTBR_EL2) 3592 .hyp().mon() 3593 .mapsTo(MISCREG_VTTBR); 3594 InitReg(MISCREG_VTCR_EL2) 3595 .hyp().mon() 3596 .mapsTo(MISCREG_VTCR); 3597 InitReg(MISCREG_TTBR0_EL3) 3598 .mon(); 3599 InitReg(MISCREG_TCR_EL3) 3600 .mon(); 3601 InitReg(MISCREG_DACR32_EL2) 3602 .hyp().mon() 3603 .mapsTo(MISCREG_DACR_NS); 3604 InitReg(MISCREG_SPSR_EL1) 3605 .allPrivileges().exceptUserMode() 3606 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1 3607 InitReg(MISCREG_ELR_EL1) 3608 .allPrivileges().exceptUserMode(); 3609 InitReg(MISCREG_SP_EL0) 3610 .allPrivileges().exceptUserMode(); 3611 InitReg(MISCREG_SPSEL) 3612 .allPrivileges().exceptUserMode(); 3613 InitReg(MISCREG_CURRENTEL) 3614 .allPrivileges().exceptUserMode().writes(0); 3615 InitReg(MISCREG_NZCV) 3616 .allPrivileges(); 3617 InitReg(MISCREG_DAIF) 3618 .allPrivileges(); 3619 InitReg(MISCREG_FPCR) 3620 .allPrivileges(); 3621 InitReg(MISCREG_FPSR) 3622 .allPrivileges(); 3623 InitReg(MISCREG_DSPSR_EL0) 3624 .allPrivileges(); 3625 InitReg(MISCREG_DLR_EL0) 3626 .allPrivileges(); 3627 InitReg(MISCREG_SPSR_EL2) 3628 .hyp().mon() 3629 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2 3630 InitReg(MISCREG_ELR_EL2) 3631 .hyp().mon(); 3632 InitReg(MISCREG_SP_EL1) 3633 .hyp().mon(); 3634 InitReg(MISCREG_SPSR_IRQ_AA64) 3635 .hyp().mon(); 3636 InitReg(MISCREG_SPSR_ABT_AA64) 3637 .hyp().mon(); 3638 InitReg(MISCREG_SPSR_UND_AA64) 3639 .hyp().mon(); 3640 InitReg(MISCREG_SPSR_FIQ_AA64) 3641 .hyp().mon(); 3642 InitReg(MISCREG_SPSR_EL3) 3643 .mon() 3644 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3 3645 InitReg(MISCREG_ELR_EL3) 3646 .mon(); 3647 InitReg(MISCREG_SP_EL2) 3648 .mon(); 3649 InitReg(MISCREG_AFSR0_EL1) 3650 .allPrivileges().exceptUserMode() 3651 .mapsTo(MISCREG_ADFSR_NS); 3652 InitReg(MISCREG_AFSR1_EL1) 3653 .allPrivileges().exceptUserMode() 3654 .mapsTo(MISCREG_AIFSR_NS); 3655 InitReg(MISCREG_ESR_EL1) 3656 .allPrivileges().exceptUserMode(); 3657 InitReg(MISCREG_IFSR32_EL2) 3658 .hyp().mon() 3659 .mapsTo(MISCREG_IFSR_NS); 3660 InitReg(MISCREG_AFSR0_EL2) 3661 .hyp().mon() 3662 .mapsTo(MISCREG_HADFSR); 3663 InitReg(MISCREG_AFSR1_EL2) 3664 .hyp().mon() 3665 .mapsTo(MISCREG_HAIFSR); 3666 InitReg(MISCREG_ESR_EL2) 3667 .hyp().mon() 3668 .mapsTo(MISCREG_HSR); 3669 InitReg(MISCREG_FPEXC32_EL2) 3670 .hyp().mon().mapsTo(MISCREG_FPEXC); 3671 InitReg(MISCREG_AFSR0_EL3) 3672 .mon(); 3673 InitReg(MISCREG_AFSR1_EL3) 3674 .mon(); 3675 InitReg(MISCREG_ESR_EL3) 3676 .mon(); 3677 InitReg(MISCREG_FAR_EL1) 3678 .allPrivileges().exceptUserMode() 3679 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS); 3680 InitReg(MISCREG_FAR_EL2) 3681 .hyp().mon() 3682 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR); 3683 InitReg(MISCREG_HPFAR_EL2) 3684 .hyp().mon() 3685 .mapsTo(MISCREG_HPFAR); 3686 InitReg(MISCREG_FAR_EL3) 3687 .mon(); 3688 InitReg(MISCREG_IC_IALLUIS) 3689 .warnNotFail() 3690 .writes(1).exceptUserMode(); 3691 InitReg(MISCREG_PAR_EL1) 3692 .allPrivileges().exceptUserMode() 3693 .mapsTo(MISCREG_PAR_NS); 3694 InitReg(MISCREG_IC_IALLU) 3695 .warnNotFail() 3696 .writes(1).exceptUserMode(); 3697 InitReg(MISCREG_DC_IVAC_Xt) 3698 .warnNotFail() 3699 .writes(1).exceptUserMode(); 3700 InitReg(MISCREG_DC_ISW_Xt) 3701 .warnNotFail() 3702 .writes(1).exceptUserMode(); 3703 InitReg(MISCREG_AT_S1E1R_Xt) 3704 .writes(1).exceptUserMode(); 3705 InitReg(MISCREG_AT_S1E1W_Xt) 3706 .writes(1).exceptUserMode(); 3707 InitReg(MISCREG_AT_S1E0R_Xt) 3708 .writes(1).exceptUserMode(); 3709 InitReg(MISCREG_AT_S1E0W_Xt) 3710 .writes(1).exceptUserMode(); 3711 InitReg(MISCREG_DC_CSW_Xt) 3712 .warnNotFail() 3713 .writes(1).exceptUserMode(); 3714 InitReg(MISCREG_DC_CISW_Xt) 3715 .warnNotFail() 3716 .writes(1).exceptUserMode(); 3717 InitReg(MISCREG_DC_ZVA_Xt) 3718 .warnNotFail() 3719 .writes(1).userSecureWrite(0); 3720 InitReg(MISCREG_IC_IVAU_Xt) 3721 .writes(1); 3722 InitReg(MISCREG_DC_CVAC_Xt) 3723 .warnNotFail() 3724 .writes(1); 3725 InitReg(MISCREG_DC_CVAU_Xt) 3726 .warnNotFail() 3727 .writes(1); 3728 InitReg(MISCREG_DC_CIVAC_Xt) 3729 .warnNotFail() 3730 .writes(1); 3731 InitReg(MISCREG_AT_S1E2R_Xt) 3732 .monNonSecureWrite().hypWrite(); 3733 InitReg(MISCREG_AT_S1E2W_Xt) 3734 .monNonSecureWrite().hypWrite(); 3735 InitReg(MISCREG_AT_S12E1R_Xt) 3736 .hypWrite().monSecureWrite().monNonSecureWrite(); 3737 InitReg(MISCREG_AT_S12E1W_Xt) 3738 .hypWrite().monSecureWrite().monNonSecureWrite(); 3739 InitReg(MISCREG_AT_S12E0R_Xt) 3740 .hypWrite().monSecureWrite().monNonSecureWrite(); 3741 InitReg(MISCREG_AT_S12E0W_Xt) 3742 .hypWrite().monSecureWrite().monNonSecureWrite(); 3743 InitReg(MISCREG_AT_S1E3R_Xt) 3744 .monSecureWrite().monNonSecureWrite(); 3745 InitReg(MISCREG_AT_S1E3W_Xt) 3746 .monSecureWrite().monNonSecureWrite(); 3747 InitReg(MISCREG_TLBI_VMALLE1IS) 3748 .writes(1).exceptUserMode(); 3749 InitReg(MISCREG_TLBI_VAE1IS_Xt) 3750 .writes(1).exceptUserMode(); 3751 InitReg(MISCREG_TLBI_ASIDE1IS_Xt) 3752 .writes(1).exceptUserMode(); 3753 InitReg(MISCREG_TLBI_VAAE1IS_Xt) 3754 .writes(1).exceptUserMode(); 3755 InitReg(MISCREG_TLBI_VALE1IS_Xt) 3756 .writes(1).exceptUserMode(); 3757 InitReg(MISCREG_TLBI_VAALE1IS_Xt) 3758 .writes(1).exceptUserMode(); 3759 InitReg(MISCREG_TLBI_VMALLE1) 3760 .writes(1).exceptUserMode(); 3761 InitReg(MISCREG_TLBI_VAE1_Xt) 3762 .writes(1).exceptUserMode(); 3763 InitReg(MISCREG_TLBI_ASIDE1_Xt) 3764 .writes(1).exceptUserMode(); 3765 InitReg(MISCREG_TLBI_VAAE1_Xt) 3766 .writes(1).exceptUserMode(); 3767 InitReg(MISCREG_TLBI_VALE1_Xt) 3768 .writes(1).exceptUserMode(); 3769 InitReg(MISCREG_TLBI_VAALE1_Xt) 3770 .writes(1).exceptUserMode(); 3771 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt) 3772 .hypWrite().monSecureWrite().monNonSecureWrite(); 3773 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt) 3774 .hypWrite().monSecureWrite().monNonSecureWrite(); 3775 InitReg(MISCREG_TLBI_ALLE2IS) 3776 .monNonSecureWrite().hypWrite(); 3777 InitReg(MISCREG_TLBI_VAE2IS_Xt) 3778 .monNonSecureWrite().hypWrite(); 3779 InitReg(MISCREG_TLBI_ALLE1IS) 3780 .hypWrite().monSecureWrite().monNonSecureWrite(); 3781 InitReg(MISCREG_TLBI_VALE2IS_Xt) 3782 .monNonSecureWrite().hypWrite(); 3783 InitReg(MISCREG_TLBI_VMALLS12E1IS) 3784 .hypWrite().monSecureWrite().monNonSecureWrite(); 3785 InitReg(MISCREG_TLBI_IPAS2E1_Xt) 3786 .hypWrite().monSecureWrite().monNonSecureWrite(); 3787 InitReg(MISCREG_TLBI_IPAS2LE1_Xt) 3788 .hypWrite().monSecureWrite().monNonSecureWrite(); 3789 InitReg(MISCREG_TLBI_ALLE2) 3790 .monNonSecureWrite().hypWrite(); 3791 InitReg(MISCREG_TLBI_VAE2_Xt) 3792 .monNonSecureWrite().hypWrite(); 3793 InitReg(MISCREG_TLBI_ALLE1) 3794 .hypWrite().monSecureWrite().monNonSecureWrite(); 3795 InitReg(MISCREG_TLBI_VALE2_Xt) 3796 .monNonSecureWrite().hypWrite(); 3797 InitReg(MISCREG_TLBI_VMALLS12E1) 3798 .hypWrite().monSecureWrite().monNonSecureWrite(); 3799 InitReg(MISCREG_TLBI_ALLE3IS) 3800 .monSecureWrite().monNonSecureWrite(); 3801 InitReg(MISCREG_TLBI_VAE3IS_Xt) 3802 .monSecureWrite().monNonSecureWrite(); 3803 InitReg(MISCREG_TLBI_VALE3IS_Xt) 3804 .monSecureWrite().monNonSecureWrite(); 3805 InitReg(MISCREG_TLBI_ALLE3) 3806 .monSecureWrite().monNonSecureWrite(); 3807 InitReg(MISCREG_TLBI_VAE3_Xt) 3808 .monSecureWrite().monNonSecureWrite(); 3809 InitReg(MISCREG_TLBI_VALE3_Xt) 3810 .monSecureWrite().monNonSecureWrite(); 3811 InitReg(MISCREG_PMINTENSET_EL1) 3812 .allPrivileges().exceptUserMode() 3813 .mapsTo(MISCREG_PMINTENSET); 3814 InitReg(MISCREG_PMINTENCLR_EL1) 3815 .allPrivileges().exceptUserMode() 3816 .mapsTo(MISCREG_PMINTENCLR); 3817 InitReg(MISCREG_PMCR_EL0) 3818 .allPrivileges() 3819 .mapsTo(MISCREG_PMCR); 3820 InitReg(MISCREG_PMCNTENSET_EL0) 3821 .allPrivileges() 3822 .mapsTo(MISCREG_PMCNTENSET); 3823 InitReg(MISCREG_PMCNTENCLR_EL0) 3824 .allPrivileges() 3825 .mapsTo(MISCREG_PMCNTENCLR); 3826 InitReg(MISCREG_PMOVSCLR_EL0) 3827 .allPrivileges(); 3828// .mapsTo(MISCREG_PMOVSCLR); 3829 InitReg(MISCREG_PMSWINC_EL0) 3830 .writes(1).user() 3831 .mapsTo(MISCREG_PMSWINC); 3832 InitReg(MISCREG_PMSELR_EL0) 3833 .allPrivileges() 3834 .mapsTo(MISCREG_PMSELR); 3835 InitReg(MISCREG_PMCEID0_EL0) 3836 .reads(1).user() 3837 .mapsTo(MISCREG_PMCEID0); 3838 InitReg(MISCREG_PMCEID1_EL0) 3839 .reads(1).user() 3840 .mapsTo(MISCREG_PMCEID1); 3841 InitReg(MISCREG_PMCCNTR_EL0) 3842 .allPrivileges() 3843 .mapsTo(MISCREG_PMCCNTR); 3844 InitReg(MISCREG_PMXEVTYPER_EL0) 3845 .allPrivileges() 3846 .mapsTo(MISCREG_PMXEVTYPER); 3847 InitReg(MISCREG_PMCCFILTR_EL0) 3848 .allPrivileges(); 3849 InitReg(MISCREG_PMXEVCNTR_EL0) 3850 .allPrivileges() 3851 .mapsTo(MISCREG_PMXEVCNTR); 3852 InitReg(MISCREG_PMUSERENR_EL0) 3853 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 3854 .mapsTo(MISCREG_PMUSERENR); 3855 InitReg(MISCREG_PMOVSSET_EL0) 3856 .allPrivileges() 3857 .mapsTo(MISCREG_PMOVSSET); 3858 InitReg(MISCREG_MAIR_EL1) 3859 .allPrivileges().exceptUserMode() 3860 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS); 3861 InitReg(MISCREG_AMAIR_EL1) 3862 .allPrivileges().exceptUserMode() 3863 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS); 3864 InitReg(MISCREG_MAIR_EL2) 3865 .hyp().mon() 3866 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1); 3867 InitReg(MISCREG_AMAIR_EL2) 3868 .hyp().mon() 3869 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1); 3870 InitReg(MISCREG_MAIR_EL3) 3871 .mon(); 3872 InitReg(MISCREG_AMAIR_EL3) 3873 .mon(); 3874 InitReg(MISCREG_L2CTLR_EL1) 3875 .allPrivileges().exceptUserMode(); 3876 InitReg(MISCREG_L2ECTLR_EL1) 3877 .allPrivileges().exceptUserMode(); 3878 InitReg(MISCREG_VBAR_EL1) 3879 .allPrivileges().exceptUserMode() 3880 .mapsTo(MISCREG_VBAR_NS); 3881 InitReg(MISCREG_RVBAR_EL1) 3882 .allPrivileges().exceptUserMode().writes(0); 3883 InitReg(MISCREG_ISR_EL1) 3884 .allPrivileges().exceptUserMode().writes(0); 3885 InitReg(MISCREG_VBAR_EL2) 3886 .hyp().mon() 3887 .mapsTo(MISCREG_HVBAR); 3888 InitReg(MISCREG_RVBAR_EL2) 3889 .mon().hyp().writes(0); 3890 InitReg(MISCREG_VBAR_EL3) 3891 .mon(); 3892 InitReg(MISCREG_RVBAR_EL3) 3893 .mon().writes(0); 3894 InitReg(MISCREG_RMR_EL3) 3895 .mon(); 3896 InitReg(MISCREG_CONTEXTIDR_EL1) 3897 .allPrivileges().exceptUserMode() 3898 .mapsTo(MISCREG_CONTEXTIDR_NS); 3899 InitReg(MISCREG_TPIDR_EL1) 3900 .allPrivileges().exceptUserMode() 3901 .mapsTo(MISCREG_TPIDRPRW_NS); 3902 InitReg(MISCREG_TPIDR_EL0) 3903 .allPrivileges() 3904 .mapsTo(MISCREG_TPIDRURW_NS); 3905 InitReg(MISCREG_TPIDRRO_EL0) 3906 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 3907 .mapsTo(MISCREG_TPIDRURO_NS); 3908 InitReg(MISCREG_TPIDR_EL2) 3909 .hyp().mon() 3910 .mapsTo(MISCREG_HTPIDR); 3911 InitReg(MISCREG_TPIDR_EL3) 3912 .mon(); 3913 InitReg(MISCREG_CNTKCTL_EL1) 3914 .allPrivileges().exceptUserMode() 3915 .mapsTo(MISCREG_CNTKCTL); 3916 InitReg(MISCREG_CNTFRQ_EL0) 3917 .reads(1).mon() 3918 .mapsTo(MISCREG_CNTFRQ); 3919 InitReg(MISCREG_CNTPCT_EL0) 3920 .reads(1) 3921 .mapsTo(MISCREG_CNTPCT); /* 64b */ 3922 InitReg(MISCREG_CNTVCT_EL0) 3923 .unverifiable() 3924 .reads(1) 3925 .mapsTo(MISCREG_CNTVCT); /* 64b */ 3926 InitReg(MISCREG_CNTP_TVAL_EL0) 3927 .allPrivileges() 3928 .mapsTo(MISCREG_CNTP_TVAL_NS); 3929 InitReg(MISCREG_CNTP_CTL_EL0) 3930 .allPrivileges() 3931 .mapsTo(MISCREG_CNTP_CTL_NS); 3932 InitReg(MISCREG_CNTP_CVAL_EL0) 3933 .allPrivileges() 3934 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */ 3935 InitReg(MISCREG_CNTV_TVAL_EL0) 3936 .allPrivileges() 3937 .mapsTo(MISCREG_CNTV_TVAL); 3938 InitReg(MISCREG_CNTV_CTL_EL0) 3939 .allPrivileges() 3940 .mapsTo(MISCREG_CNTV_CTL); 3941 InitReg(MISCREG_CNTV_CVAL_EL0) 3942 .allPrivileges() 3943 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */ 3944 InitReg(MISCREG_PMEVCNTR0_EL0) 3945 .allPrivileges(); 3946// .mapsTo(MISCREG_PMEVCNTR0); 3947 InitReg(MISCREG_PMEVCNTR1_EL0) 3948 .allPrivileges(); 3949// .mapsTo(MISCREG_PMEVCNTR1); 3950 InitReg(MISCREG_PMEVCNTR2_EL0) 3951 .allPrivileges(); 3952// .mapsTo(MISCREG_PMEVCNTR2); 3953 InitReg(MISCREG_PMEVCNTR3_EL0) 3954 .allPrivileges(); 3955// .mapsTo(MISCREG_PMEVCNTR3); 3956 InitReg(MISCREG_PMEVCNTR4_EL0) 3957 .allPrivileges(); 3958// .mapsTo(MISCREG_PMEVCNTR4); 3959 InitReg(MISCREG_PMEVCNTR5_EL0) 3960 .allPrivileges(); 3961// .mapsTo(MISCREG_PMEVCNTR5); 3962 InitReg(MISCREG_PMEVTYPER0_EL0) 3963 .allPrivileges(); 3964// .mapsTo(MISCREG_PMEVTYPER0); 3965 InitReg(MISCREG_PMEVTYPER1_EL0) 3966 .allPrivileges(); 3967// .mapsTo(MISCREG_PMEVTYPER1); 3968 InitReg(MISCREG_PMEVTYPER2_EL0) 3969 .allPrivileges(); 3970// .mapsTo(MISCREG_PMEVTYPER2); 3971 InitReg(MISCREG_PMEVTYPER3_EL0) 3972 .allPrivileges(); 3973// .mapsTo(MISCREG_PMEVTYPER3); 3974 InitReg(MISCREG_PMEVTYPER4_EL0) 3975 .allPrivileges(); 3976// .mapsTo(MISCREG_PMEVTYPER4); 3977 InitReg(MISCREG_PMEVTYPER5_EL0) 3978 .allPrivileges(); 3979// .mapsTo(MISCREG_PMEVTYPER5); 3980 InitReg(MISCREG_CNTVOFF_EL2) 3981 .hyp().mon() 3982 .mapsTo(MISCREG_CNTVOFF); /* 64b */ 3983 InitReg(MISCREG_CNTHCTL_EL2) 3984 .mon().hyp() 3985 .mapsTo(MISCREG_CNTHCTL); 3986 InitReg(MISCREG_CNTHP_TVAL_EL2) 3987 .mon().hyp() 3988 .mapsTo(MISCREG_CNTHP_TVAL); 3989 InitReg(MISCREG_CNTHP_CTL_EL2) 3990 .mon().hyp() 3991 .mapsTo(MISCREG_CNTHP_CTL); 3992 InitReg(MISCREG_CNTHP_CVAL_EL2) 3993 .mon().hyp() 3994 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */ 3995 InitReg(MISCREG_CNTPS_TVAL_EL1) 3996 .mon().privSecure(); 3997 InitReg(MISCREG_CNTPS_CTL_EL1) 3998 .mon().privSecure(); 3999 InitReg(MISCREG_CNTPS_CVAL_EL1) 4000 .mon().privSecure(); 4001 InitReg(MISCREG_IL1DATA0_EL1) 4002 .allPrivileges().exceptUserMode(); 4003 InitReg(MISCREG_IL1DATA1_EL1) 4004 .allPrivileges().exceptUserMode(); 4005 InitReg(MISCREG_IL1DATA2_EL1) 4006 .allPrivileges().exceptUserMode(); 4007 InitReg(MISCREG_IL1DATA3_EL1) 4008 .allPrivileges().exceptUserMode(); 4009 InitReg(MISCREG_DL1DATA0_EL1) 4010 .allPrivileges().exceptUserMode(); 4011 InitReg(MISCREG_DL1DATA1_EL1) 4012 .allPrivileges().exceptUserMode(); 4013 InitReg(MISCREG_DL1DATA2_EL1) 4014 .allPrivileges().exceptUserMode(); 4015 InitReg(MISCREG_DL1DATA3_EL1) 4016 .allPrivileges().exceptUserMode(); 4017 InitReg(MISCREG_DL1DATA4_EL1) 4018 .allPrivileges().exceptUserMode(); 4019 InitReg(MISCREG_L2ACTLR_EL1) 4020 .allPrivileges().exceptUserMode(); 4021 InitReg(MISCREG_CPUACTLR_EL1) 4022 .allPrivileges().exceptUserMode(); 4023 InitReg(MISCREG_CPUECTLR_EL1) 4024 .allPrivileges().exceptUserMode(); 4025 InitReg(MISCREG_CPUMERRSR_EL1) 4026 .allPrivileges().exceptUserMode(); 4027 InitReg(MISCREG_L2MERRSR_EL1) 4028 .unimplemented() 4029 .warnNotFail() 4030 .allPrivileges().exceptUserMode(); 4031 InitReg(MISCREG_CBAR_EL1) 4032 .allPrivileges().exceptUserMode().writes(0); 4033 InitReg(MISCREG_CONTEXTIDR_EL2) 4034 .mon().hyp(); 4035 InitReg(MISCREG_CNTHV_CTL_EL2) 4036 .mon().hyp(); 4037 InitReg(MISCREG_CNTHV_CVAL_EL2) 4038 .mon().hyp(); 4039 InitReg(MISCREG_CNTHV_TVAL_EL2) 4040 .mon().hyp(); 4041 4042 // Dummy registers 4043 InitReg(MISCREG_NOP) 4044 .allPrivileges(); 4045 InitReg(MISCREG_RAZ) 4046 .allPrivileges().exceptUserMode().writes(0); 4047 InitReg(MISCREG_CP14_UNIMPL) 4048 .unimplemented() 4049 .warnNotFail(); 4050 InitReg(MISCREG_CP15_UNIMPL) 4051 .unimplemented() 4052 .warnNotFail(); 4053 InitReg(MISCREG_UNKNOWN); 4054 InitReg(MISCREG_IMPDEF_UNIMPL) 4055 .unimplemented() 4056 .warnNotFail(impdefAsNop); 4057 4058 // RAS extension (unimplemented) 4059 InitReg(MISCREG_ERRIDR_EL1) 4060 .unimplemented() 4061 .warnNotFail(); 4062 InitReg(MISCREG_ERRSELR_EL1) 4063 .unimplemented() 4064 .warnNotFail(); 4065 InitReg(MISCREG_ERXFR_EL1) 4066 .unimplemented() 4067 .warnNotFail(); 4068 InitReg(MISCREG_ERXCTLR_EL1) 4069 .unimplemented() 4070 .warnNotFail(); 4071 InitReg(MISCREG_ERXSTATUS_EL1) 4072 .unimplemented() 4073 .warnNotFail(); 4074 InitReg(MISCREG_ERXADDR_EL1) 4075 .unimplemented() 4076 .warnNotFail(); 4077 InitReg(MISCREG_ERXMISC0_EL1) 4078 .unimplemented() 4079 .warnNotFail(); 4080 InitReg(MISCREG_ERXMISC1_EL1) 4081 .unimplemented() 4082 .warnNotFail(); 4083 InitReg(MISCREG_DISR_EL1) 4084 .unimplemented() 4085 .warnNotFail(); 4086 InitReg(MISCREG_VSESR_EL2) 4087 .unimplemented() 4088 .warnNotFail(); 4089 InitReg(MISCREG_VDISR_EL2) 4090 .unimplemented() 4091 .warnNotFail(); 4092 4093 // Register mappings for some unimplemented registers: 4094 // ESR_EL1 -> DFSR 4095 // RMR_EL1 -> RMR 4096 // RMR_EL2 -> HRMR 4097 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 4098 // DBGDTRRX_EL0 -> DBGDTRRXint 4099 // DBGDTRTX_EL0 -> DBGDTRRXint 4100 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5) 4101 4102 completed = true; 4103} 4104 4105} // namespace ArmISA 4106