miscregs.cc revision 12576:e55d2103ccac 
1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 *          Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57    switch(crn) {
58      case 0:
59        switch (opc1) {
60          case 0:
61            switch (opc2) {
62              case 0:
63                switch (crm) {
64                  case 0:
65                    return MISCREG_DBGDIDR;
66                  case 1:
67                    return MISCREG_DBGDSCRint;
68                }
69                break;
70            }
71            break;
72          case 7:
73            switch (opc2) {
74              case 0:
75                switch (crm) {
76                  case 0:
77                    return MISCREG_JIDR;
78                }
79              break;
80            }
81            break;
82        }
83        break;
84      case 1:
85        switch (opc1) {
86          case 6:
87            switch (crm) {
88              case 0:
89                switch (opc2) {
90                  case 0:
91                    return MISCREG_TEEHBR;
92                }
93                break;
94            }
95            break;
96          case 7:
97            switch (crm) {
98              case 0:
99                switch (opc2) {
100                  case 0:
101                    return MISCREG_JOSCR;
102                }
103                break;
104            }
105            break;
106        }
107        break;
108      case 2:
109        switch (opc1) {
110          case 7:
111            switch (crm) {
112              case 0:
113                switch (opc2) {
114                  case 0:
115                    return MISCREG_JMCR;
116                }
117                break;
118            }
119            break;
120        }
121        break;
122    }
123    // If we get here then it must be a register that we haven't implemented
124    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125         crn, opc1, crm, opc2);
126    return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134    switch (crn) {
135      case 0:
136        switch (opc1) {
137          case 0:
138            switch (crm) {
139              case 0:
140                switch (opc2) {
141                  case 1:
142                    return MISCREG_CTR;
143                  case 2:
144                    return MISCREG_TCMTR;
145                  case 3:
146                    return MISCREG_TLBTR;
147                  case 5:
148                    return MISCREG_MPIDR;
149                  case 6:
150                    return MISCREG_REVIDR;
151                  default:
152                    return MISCREG_MIDR;
153                }
154                break;
155              case 1:
156                switch (opc2) {
157                  case 0:
158                    return MISCREG_ID_PFR0;
159                  case 1:
160                    return MISCREG_ID_PFR1;
161                  case 2:
162                    return MISCREG_ID_DFR0;
163                  case 3:
164                    return MISCREG_ID_AFR0;
165                  case 4:
166                    return MISCREG_ID_MMFR0;
167                  case 5:
168                    return MISCREG_ID_MMFR1;
169                  case 6:
170                    return MISCREG_ID_MMFR2;
171                  case 7:
172                    return MISCREG_ID_MMFR3;
173                }
174                break;
175              case 2:
176                switch (opc2) {
177                  case 0:
178                    return MISCREG_ID_ISAR0;
179                  case 1:
180                    return MISCREG_ID_ISAR1;
181                  case 2:
182                    return MISCREG_ID_ISAR2;
183                  case 3:
184                    return MISCREG_ID_ISAR3;
185                  case 4:
186                    return MISCREG_ID_ISAR4;
187                  case 5:
188                    return MISCREG_ID_ISAR5;
189                  case 6:
190                  case 7:
191                    return MISCREG_RAZ; // read as zero
192                }
193                break;
194              default:
195                return MISCREG_RAZ; // read as zero
196            }
197            break;
198          case 1:
199            if (crm == 0) {
200                switch (opc2) {
201                  case 0:
202                    return MISCREG_CCSIDR;
203                  case 1:
204                    return MISCREG_CLIDR;
205                  case 7:
206                    return MISCREG_AIDR;
207                }
208            }
209            break;
210          case 2:
211            if (crm == 0 && opc2 == 0) {
212                return MISCREG_CSSELR;
213            }
214            break;
215          case 4:
216            if (crm == 0) {
217                if (opc2 == 0)
218                    return MISCREG_VPIDR;
219                else if (opc2 == 5)
220                    return MISCREG_VMPIDR;
221            }
222            break;
223        }
224        break;
225      case 1:
226        if (opc1 == 0) {
227            if (crm == 0) {
228                switch (opc2) {
229                  case 0:
230                    return MISCREG_SCTLR;
231                  case 1:
232                    return MISCREG_ACTLR;
233                  case 0x2:
234                    return MISCREG_CPACR;
235                }
236            } else if (crm == 1) {
237                switch (opc2) {
238                  case 0:
239                    return MISCREG_SCR;
240                  case 1:
241                    return MISCREG_SDER;
242                  case 2:
243                    return MISCREG_NSACR;
244                }
245            }
246        } else if (opc1 == 4) {
247            if (crm == 0) {
248                if (opc2 == 0)
249                    return MISCREG_HSCTLR;
250                else if (opc2 == 1)
251                    return MISCREG_HACTLR;
252            } else if (crm == 1) {
253                switch (opc2) {
254                  case 0:
255                    return MISCREG_HCR;
256                  case 1:
257                    return MISCREG_HDCR;
258                  case 2:
259                    return MISCREG_HCPTR;
260                  case 3:
261                    return MISCREG_HSTR;
262                  case 7:
263                    return MISCREG_HACR;
264                }
265            }
266        }
267        break;
268      case 2:
269        if (opc1 == 0 && crm == 0) {
270            switch (opc2) {
271              case 0:
272                return MISCREG_TTBR0;
273              case 1:
274                return MISCREG_TTBR1;
275              case 2:
276                return MISCREG_TTBCR;
277            }
278        } else if (opc1 == 4) {
279            if (crm == 0 && opc2 == 2)
280                return MISCREG_HTCR;
281            else if (crm == 1 && opc2 == 2)
282                return MISCREG_VTCR;
283        }
284        break;
285      case 3:
286        if (opc1 == 0 && crm == 0 && opc2 == 0) {
287            return MISCREG_DACR;
288        }
289        break;
290      case 5:
291        if (opc1 == 0) {
292            if (crm == 0) {
293                if (opc2 == 0) {
294                    return MISCREG_DFSR;
295                } else if (opc2 == 1) {
296                    return MISCREG_IFSR;
297                }
298            } else if (crm == 1) {
299                if (opc2 == 0) {
300                    return MISCREG_ADFSR;
301                } else if (opc2 == 1) {
302                    return MISCREG_AIFSR;
303                }
304            }
305        } else if (opc1 == 4) {
306            if (crm == 1) {
307                if (opc2 == 0)
308                    return MISCREG_HADFSR;
309                else if (opc2 == 1)
310                    return MISCREG_HAIFSR;
311            } else if (crm == 2 && opc2 == 0) {
312                return MISCREG_HSR;
313            }
314        }
315        break;
316      case 6:
317        if (opc1 == 0 && crm == 0) {
318            switch (opc2) {
319              case 0:
320                return MISCREG_DFAR;
321              case 2:
322                return MISCREG_IFAR;
323            }
324        } else if (opc1 == 4 && crm == 0) {
325            switch (opc2) {
326              case 0:
327                return MISCREG_HDFAR;
328              case 2:
329                return MISCREG_HIFAR;
330              case 4:
331                return MISCREG_HPFAR;
332            }
333        }
334        break;
335      case 7:
336        if (opc1 == 0) {
337            switch (crm) {
338              case 0:
339                if (opc2 == 4) {
340                    return MISCREG_NOP;
341                }
342                break;
343              case 1:
344                switch (opc2) {
345                  case 0:
346                    return MISCREG_ICIALLUIS;
347                  case 6:
348                    return MISCREG_BPIALLIS;
349                }
350                break;
351              case 4:
352                if (opc2 == 0) {
353                    return MISCREG_PAR;
354                }
355                break;
356              case 5:
357                switch (opc2) {
358                  case 0:
359                    return MISCREG_ICIALLU;
360                  case 1:
361                    return MISCREG_ICIMVAU;
362                  case 4:
363                    return MISCREG_CP15ISB;
364                  case 6:
365                    return MISCREG_BPIALL;
366                  case 7:
367                    return MISCREG_BPIMVA;
368                }
369                break;
370              case 6:
371                if (opc2 == 1) {
372                    return MISCREG_DCIMVAC;
373                } else if (opc2 == 2) {
374                    return MISCREG_DCISW;
375                }
376                break;
377              case 8:
378                switch (opc2) {
379                  case 0:
380                    return MISCREG_ATS1CPR;
381                  case 1:
382                    return MISCREG_ATS1CPW;
383                  case 2:
384                    return MISCREG_ATS1CUR;
385                  case 3:
386                    return MISCREG_ATS1CUW;
387                  case 4:
388                    return MISCREG_ATS12NSOPR;
389                  case 5:
390                    return MISCREG_ATS12NSOPW;
391                  case 6:
392                    return MISCREG_ATS12NSOUR;
393                  case 7:
394                    return MISCREG_ATS12NSOUW;
395                }
396                break;
397              case 10:
398                switch (opc2) {
399                  case 1:
400                    return MISCREG_DCCMVAC;
401                  case 2:
402                    return MISCREG_DCCSW;
403                  case 4:
404                    return MISCREG_CP15DSB;
405                  case 5:
406                    return MISCREG_CP15DMB;
407                }
408                break;
409              case 11:
410                if (opc2 == 1) {
411                    return MISCREG_DCCMVAU;
412                }
413                break;
414              case 13:
415                if (opc2 == 1) {
416                    return MISCREG_NOP;
417                }
418                break;
419              case 14:
420                if (opc2 == 1) {
421                    return MISCREG_DCCIMVAC;
422                } else if (opc2 == 2) {
423                    return MISCREG_DCCISW;
424                }
425                break;
426            }
427        } else if (opc1 == 4 && crm == 8) {
428            if (opc2 == 0)
429                return MISCREG_ATS1HR;
430            else if (opc2 == 1)
431                return MISCREG_ATS1HW;
432        }
433        break;
434      case 8:
435        if (opc1 == 0) {
436            switch (crm) {
437              case 3:
438                switch (opc2) {
439                  case 0:
440                    return MISCREG_TLBIALLIS;
441                  case 1:
442                    return MISCREG_TLBIMVAIS;
443                  case 2:
444                    return MISCREG_TLBIASIDIS;
445                  case 3:
446                    return MISCREG_TLBIMVAAIS;
447                  case 5:
448                    return MISCREG_TLBIMVALIS;
449                  case 7:
450                    return MISCREG_TLBIMVAALIS;
451                }
452                break;
453              case 5:
454                switch (opc2) {
455                  case 0:
456                    return MISCREG_ITLBIALL;
457                  case 1:
458                    return MISCREG_ITLBIMVA;
459                  case 2:
460                    return MISCREG_ITLBIASID;
461                }
462                break;
463              case 6:
464                switch (opc2) {
465                  case 0:
466                    return MISCREG_DTLBIALL;
467                  case 1:
468                    return MISCREG_DTLBIMVA;
469                  case 2:
470                    return MISCREG_DTLBIASID;
471                }
472                break;
473              case 7:
474                switch (opc2) {
475                  case 0:
476                    return MISCREG_TLBIALL;
477                  case 1:
478                    return MISCREG_TLBIMVA;
479                  case 2:
480                    return MISCREG_TLBIASID;
481                  case 3:
482                    return MISCREG_TLBIMVAA;
483                  case 5:
484                    return MISCREG_TLBIMVAL;
485                  case 7:
486                    return MISCREG_TLBIMVAAL;
487                }
488                break;
489            }
490        } else if (opc1 == 4) {
491            if (crm == 3) {
492                switch (opc2) {
493                  case 0:
494                    return MISCREG_TLBIALLHIS;
495                  case 1:
496                    return MISCREG_TLBIMVAHIS;
497                  case 4:
498                    return MISCREG_TLBIALLNSNHIS;
499                  case 5:
500                    return MISCREG_TLBIMVALHIS;
501                }
502            } else if (crm == 7) {
503                switch (opc2) {
504                  case 0:
505                    return MISCREG_TLBIALLH;
506                  case 1:
507                    return MISCREG_TLBIMVAH;
508                  case 4:
509                    return MISCREG_TLBIALLNSNH;
510                  case 5:
511                    return MISCREG_TLBIMVALH;
512                }
513            }
514        }
515        break;
516      case 9:
517        // Every cop register with CRn = 9 and CRm in
518        // {0-2}, {5-8} is implementation defined regardless
519        // of opc1 and opc2.
520        switch (crm) {
521          case 0:
522          case 1:
523          case 2:
524          case 5:
525          case 6:
526          case 7:
527          case 8:
528            return MISCREG_IMPDEF_UNIMPL;
529        }
530        if (opc1 == 0) {
531            switch (crm) {
532              case 12:
533                switch (opc2) {
534                  case 0:
535                    return MISCREG_PMCR;
536                  case 1:
537                    return MISCREG_PMCNTENSET;
538                  case 2:
539                    return MISCREG_PMCNTENCLR;
540                  case 3:
541                    return MISCREG_PMOVSR;
542                  case 4:
543                    return MISCREG_PMSWINC;
544                  case 5:
545                    return MISCREG_PMSELR;
546                  case 6:
547                    return MISCREG_PMCEID0;
548                  case 7:
549                    return MISCREG_PMCEID1;
550                }
551                break;
552              case 13:
553                switch (opc2) {
554                  case 0:
555                    return MISCREG_PMCCNTR;
556                  case 1:
557                    // Selector is PMSELR.SEL
558                    return MISCREG_PMXEVTYPER_PMCCFILTR;
559                  case 2:
560                    return MISCREG_PMXEVCNTR;
561                }
562                break;
563              case 14:
564                switch (opc2) {
565                  case 0:
566                    return MISCREG_PMUSERENR;
567                  case 1:
568                    return MISCREG_PMINTENSET;
569                  case 2:
570                    return MISCREG_PMINTENCLR;
571                  case 3:
572                    return MISCREG_PMOVSSET;
573                }
574                break;
575            }
576        } else if (opc1 == 1) {
577            switch (crm) {
578              case 0:
579                switch (opc2) {
580                  case 2: // L2CTLR, L2 Control Register
581                    return MISCREG_L2CTLR;
582                  case 3:
583                    return MISCREG_L2ECTLR;
584                }
585                break;
586                break;
587            }
588        }
589        break;
590      case 10:
591        if (opc1 == 0) {
592            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
593            if (crm < 2) {
594                return MISCREG_IMPDEF_UNIMPL;
595            } else if (crm == 2) { // TEX Remap Registers
596                if (opc2 == 0) {
597                    // Selector is TTBCR.EAE
598                    return MISCREG_PRRR_MAIR0;
599                } else if (opc2 == 1) {
600                    // Selector is TTBCR.EAE
601                    return MISCREG_NMRR_MAIR1;
602                }
603            } else if (crm == 3) {
604                if (opc2 == 0) {
605                    return MISCREG_AMAIR0;
606                } else if (opc2 == 1) {
607                    return MISCREG_AMAIR1;
608                }
609            }
610        } else if (opc1 == 4) {
611            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
612            if (crm == 2) {
613                if (opc2 == 0)
614                    return MISCREG_HMAIR0;
615                else if (opc2 == 1)
616                    return MISCREG_HMAIR1;
617            } else if (crm == 3) {
618                if (opc2 == 0)
619                    return MISCREG_HAMAIR0;
620                else if (opc2 == 1)
621                    return MISCREG_HAMAIR1;
622            }
623        }
624        break;
625      case 11:
626        if (opc1 <=7) {
627            switch (crm) {
628              case 0:
629              case 1:
630              case 2:
631              case 3:
632              case 4:
633              case 5:
634              case 6:
635              case 7:
636              case 8:
637              case 15:
638                // Reserved for DMA operations for TCM access
639                return MISCREG_IMPDEF_UNIMPL;
640              default:
641                break;
642            }
643        }
644        break;
645      case 12:
646        if (opc1 == 0) {
647            if (crm == 0) {
648                if (opc2 == 0) {
649                    return MISCREG_VBAR;
650                } else if (opc2 == 1) {
651                    return MISCREG_MVBAR;
652                }
653            } else if (crm == 1) {
654                if (opc2 == 0) {
655                    return MISCREG_ISR;
656                }
657            }
658        } else if (opc1 == 4) {
659            if (crm == 0 && opc2 == 0)
660                return MISCREG_HVBAR;
661        }
662        break;
663      case 13:
664        if (opc1 == 0) {
665            if (crm == 0) {
666                switch (opc2) {
667                  case 0:
668                    return MISCREG_FCSEIDR;
669                  case 1:
670                    return MISCREG_CONTEXTIDR;
671                  case 2:
672                    return MISCREG_TPIDRURW;
673                  case 3:
674                    return MISCREG_TPIDRURO;
675                  case 4:
676                    return MISCREG_TPIDRPRW;
677                }
678            }
679        } else if (opc1 == 4) {
680            if (crm == 0 && opc2 == 2)
681                return MISCREG_HTPIDR;
682        }
683        break;
684      case 14:
685        if (opc1 == 0) {
686            switch (crm) {
687              case 0:
688                if (opc2 == 0)
689                    return MISCREG_CNTFRQ;
690                break;
691              case 1:
692                if (opc2 == 0)
693                    return MISCREG_CNTKCTL;
694                break;
695              case 2:
696                if (opc2 == 0)
697                    return MISCREG_CNTP_TVAL;
698                else if (opc2 == 1)
699                    return MISCREG_CNTP_CTL;
700                break;
701              case 3:
702                if (opc2 == 0)
703                    return MISCREG_CNTV_TVAL;
704                else if (opc2 == 1)
705                    return MISCREG_CNTV_CTL;
706                break;
707            }
708        } else if (opc1 == 4) {
709            if (crm == 1 && opc2 == 0) {
710                return MISCREG_CNTHCTL;
711            } else if (crm == 2) {
712                if (opc2 == 0)
713                    return MISCREG_CNTHP_TVAL;
714                else if (opc2 == 1)
715                    return MISCREG_CNTHP_CTL;
716            }
717        }
718        break;
719      case 15:
720        // Implementation defined
721        return MISCREG_IMPDEF_UNIMPL;
722    }
723    // Unrecognized register
724    return MISCREG_CP15_UNIMPL;
725}
726
727MiscRegIndex
728decodeCP15Reg64(unsigned crm, unsigned opc1)
729{
730    switch (crm) {
731      case 2:
732        switch (opc1) {
733          case 0:
734            return MISCREG_TTBR0;
735          case 1:
736            return MISCREG_TTBR1;
737          case 4:
738            return MISCREG_HTTBR;
739          case 6:
740            return MISCREG_VTTBR;
741        }
742        break;
743      case 7:
744        if (opc1 == 0)
745            return MISCREG_PAR;
746        break;
747      case 14:
748        switch (opc1) {
749          case 0:
750            return MISCREG_CNTPCT;
751          case 1:
752            return MISCREG_CNTVCT;
753          case 2:
754            return MISCREG_CNTP_CVAL;
755          case 3:
756            return MISCREG_CNTV_CVAL;
757          case 4:
758            return MISCREG_CNTVOFF;
759          case 6:
760            return MISCREG_CNTHP_CVAL;
761        }
762        break;
763      case 15:
764        if (opc1 == 0)
765            return MISCREG_CPUMERRSR;
766        else if (opc1 == 1)
767            return MISCREG_L2MERRSR;
768        break;
769    }
770    // Unrecognized register
771    return MISCREG_CP15_UNIMPL;
772}
773
774std::tuple<bool, bool>
775canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
776{
777    bool secure = !scr.ns;
778    bool canRead = false;
779    bool undefined = false;
780
781    switch (cpsr.mode) {
782      case MODE_USER:
783        canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
784                           miscRegInfo[reg][MISCREG_USR_NS_RD];
785        break;
786      case MODE_FIQ:
787      case MODE_IRQ:
788      case MODE_SVC:
789      case MODE_ABORT:
790      case MODE_UNDEFINED:
791      case MODE_SYSTEM:
792        canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
793                           miscRegInfo[reg][MISCREG_PRI_NS_RD];
794        break;
795      case MODE_MON:
796        canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
797                           miscRegInfo[reg][MISCREG_MON_NS1_RD];
798        break;
799      case MODE_HYP:
800        canRead = miscRegInfo[reg][MISCREG_HYP_RD];
801        break;
802      default:
803        undefined = true;
804    }
805    // can't do permissions checkes on the root of a banked pair of regs
806    assert(!miscRegInfo[reg][MISCREG_BANKED]);
807    return std::make_tuple(canRead, undefined);
808}
809
810std::tuple<bool, bool>
811canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
812{
813    bool secure = !scr.ns;
814    bool canWrite = false;
815    bool undefined = false;
816
817    switch (cpsr.mode) {
818      case MODE_USER:
819        canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
820                            miscRegInfo[reg][MISCREG_USR_NS_WR];
821        break;
822      case MODE_FIQ:
823      case MODE_IRQ:
824      case MODE_SVC:
825      case MODE_ABORT:
826      case MODE_UNDEFINED:
827      case MODE_SYSTEM:
828        canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
829                            miscRegInfo[reg][MISCREG_PRI_NS_WR];
830        break;
831      case MODE_MON:
832        canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
833                            miscRegInfo[reg][MISCREG_MON_NS1_WR];
834        break;
835      case MODE_HYP:
836        canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
837        break;
838      default:
839        undefined = true;
840    }
841    // can't do permissions checkes on the root of a banked pair of regs
842    assert(!miscRegInfo[reg][MISCREG_BANKED]);
843    return std::make_tuple(canWrite, undefined);
844}
845
846int
847snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
848{
849    SCR scr = tc->readMiscReg(MISCREG_SCR);
850    return snsBankedIndex(reg, tc, scr.ns);
851}
852
853int
854snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
855{
856    int reg_as_int = static_cast<int>(reg);
857    if (miscRegInfo[reg][MISCREG_BANKED]) {
858        reg_as_int += (ArmSystem::haveSecurity(tc) &&
859                      !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
860    }
861    return reg_as_int;
862}
863
864
865/**
866 * If the reg is a child reg of a banked set, then the parent is the last
867 * banked one in the list. This is messy, and the wish is to eventually have
868 * the bitmap replaced with a better data structure. the preUnflatten function
869 * initializes a lookup table to speed up the search for these banked
870 * registers.
871 */
872
873int unflattenResultMiscReg[NUM_MISCREGS];
874
875void
876preUnflattenMiscReg()
877{
878    int reg = -1;
879    for (int i = 0 ; i < NUM_MISCREGS; i++){
880        if (miscRegInfo[i][MISCREG_BANKED])
881            reg = i;
882        if (miscRegInfo[i][MISCREG_BANKED_CHILD])
883            unflattenResultMiscReg[i] = reg;
884        else
885            unflattenResultMiscReg[i] = i;
886        // if this assert fails, no parent was found, and something is broken
887        assert(unflattenResultMiscReg[i] > -1);
888    }
889}
890
891int
892unflattenMiscReg(int reg)
893{
894    return unflattenResultMiscReg[reg];
895}
896
897bool
898canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
899{
900    // Check for SP_EL0 access while SPSEL == 0
901    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
902        return false;
903
904    // Check for RVBAR access
905    if (reg == MISCREG_RVBAR_EL1) {
906        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
907        if (highest_el == EL2 || highest_el == EL3)
908            return false;
909    }
910    if (reg == MISCREG_RVBAR_EL2) {
911        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
912        if (highest_el == EL3)
913            return false;
914    }
915
916    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
917
918    switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
919      case EL0:
920        return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
921            miscRegInfo[reg][MISCREG_USR_NS_RD];
922      case EL1:
923        return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
924            miscRegInfo[reg][MISCREG_PRI_NS_RD];
925      case EL2:
926        return miscRegInfo[reg][MISCREG_HYP_RD];
927      case EL3:
928        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
929            miscRegInfo[reg][MISCREG_MON_NS1_RD];
930      default:
931        panic("Invalid exception level");
932    }
933}
934
935bool
936canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
937{
938    // Check for SP_EL0 access while SPSEL == 0
939    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
940        return false;
941    ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
942    if (reg == MISCREG_DAIF) {
943        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
944        if (el == EL0 && !sctlr.uma)
945            return false;
946    }
947    if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
948        // In syscall-emulation mode, this test is skipped and DCZVA is always
949        // allowed at EL0
950        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
951        if (el == EL0 && !sctlr.dze)
952            return false;
953    }
954    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
955        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
956        if (el == EL0 && !sctlr.uci)
957            return false;
958    }
959
960    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
961
962    switch (el) {
963      case EL0:
964        return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
965            miscRegInfo[reg][MISCREG_USR_NS_WR];
966      case EL1:
967        return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
968            miscRegInfo[reg][MISCREG_PRI_NS_WR];
969      case EL2:
970        return miscRegInfo[reg][MISCREG_HYP_WR];
971      case EL3:
972        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
973            miscRegInfo[reg][MISCREG_MON_NS1_WR];
974      default:
975        panic("Invalid exception level");
976    }
977}
978
979MiscRegIndex
980decodeAArch64SysReg(unsigned op0, unsigned op1,
981                    unsigned crn, unsigned crm,
982                    unsigned op2)
983{
984    switch (op0) {
985      case 1:
986        switch (crn) {
987          case 7:
988            switch (op1) {
989              case 0:
990                switch (crm) {
991                  case 1:
992                    switch (op2) {
993                      case 0:
994                        return MISCREG_IC_IALLUIS;
995                    }
996                    break;
997                  case 5:
998                    switch (op2) {
999                      case 0:
1000                        return MISCREG_IC_IALLU;
1001                    }
1002                    break;
1003                  case 6:
1004                    switch (op2) {
1005                      case 1:
1006                        return MISCREG_DC_IVAC_Xt;
1007                      case 2:
1008                        return MISCREG_DC_ISW_Xt;
1009                    }
1010                    break;
1011                  case 8:
1012                    switch (op2) {
1013                      case 0:
1014                        return MISCREG_AT_S1E1R_Xt;
1015                      case 1:
1016                        return MISCREG_AT_S1E1W_Xt;
1017                      case 2:
1018                        return MISCREG_AT_S1E0R_Xt;
1019                      case 3:
1020                        return MISCREG_AT_S1E0W_Xt;
1021                    }
1022                    break;
1023                  case 10:
1024                    switch (op2) {
1025                      case 2:
1026                        return MISCREG_DC_CSW_Xt;
1027                    }
1028                    break;
1029                  case 14:
1030                    switch (op2) {
1031                      case 2:
1032                        return MISCREG_DC_CISW_Xt;
1033                    }
1034                    break;
1035                }
1036                break;
1037              case 3:
1038                switch (crm) {
1039                  case 4:
1040                    switch (op2) {
1041                      case 1:
1042                        return MISCREG_DC_ZVA_Xt;
1043                    }
1044                    break;
1045                  case 5:
1046                    switch (op2) {
1047                      case 1:
1048                        return MISCREG_IC_IVAU_Xt;
1049                    }
1050                    break;
1051                  case 10:
1052                    switch (op2) {
1053                      case 1:
1054                        return MISCREG_DC_CVAC_Xt;
1055                    }
1056                    break;
1057                  case 11:
1058                    switch (op2) {
1059                      case 1:
1060                        return MISCREG_DC_CVAU_Xt;
1061                    }
1062                    break;
1063                  case 14:
1064                    switch (op2) {
1065                      case 1:
1066                        return MISCREG_DC_CIVAC_Xt;
1067                    }
1068                    break;
1069                }
1070                break;
1071              case 4:
1072                switch (crm) {
1073                  case 8:
1074                    switch (op2) {
1075                      case 0:
1076                        return MISCREG_AT_S1E2R_Xt;
1077                      case 1:
1078                        return MISCREG_AT_S1E2W_Xt;
1079                      case 4:
1080                        return MISCREG_AT_S12E1R_Xt;
1081                      case 5:
1082                        return MISCREG_AT_S12E1W_Xt;
1083                      case 6:
1084                        return MISCREG_AT_S12E0R_Xt;
1085                      case 7:
1086                        return MISCREG_AT_S12E0W_Xt;
1087                    }
1088                    break;
1089                }
1090                break;
1091              case 6:
1092                switch (crm) {
1093                  case 8:
1094                    switch (op2) {
1095                      case 0:
1096                        return MISCREG_AT_S1E3R_Xt;
1097                      case 1:
1098                        return MISCREG_AT_S1E3W_Xt;
1099                    }
1100                    break;
1101                }
1102                break;
1103            }
1104            break;
1105          case 8:
1106            switch (op1) {
1107              case 0:
1108                switch (crm) {
1109                  case 3:
1110                    switch (op2) {
1111                      case 0:
1112                        return MISCREG_TLBI_VMALLE1IS;
1113                      case 1:
1114                        return MISCREG_TLBI_VAE1IS_Xt;
1115                      case 2:
1116                        return MISCREG_TLBI_ASIDE1IS_Xt;
1117                      case 3:
1118                        return MISCREG_TLBI_VAAE1IS_Xt;
1119                      case 5:
1120                        return MISCREG_TLBI_VALE1IS_Xt;
1121                      case 7:
1122                        return MISCREG_TLBI_VAALE1IS_Xt;
1123                    }
1124                    break;
1125                  case 7:
1126                    switch (op2) {
1127                      case 0:
1128                        return MISCREG_TLBI_VMALLE1;
1129                      case 1:
1130                        return MISCREG_TLBI_VAE1_Xt;
1131                      case 2:
1132                        return MISCREG_TLBI_ASIDE1_Xt;
1133                      case 3:
1134                        return MISCREG_TLBI_VAAE1_Xt;
1135                      case 5:
1136                        return MISCREG_TLBI_VALE1_Xt;
1137                      case 7:
1138                        return MISCREG_TLBI_VAALE1_Xt;
1139                    }
1140                    break;
1141                }
1142                break;
1143              case 4:
1144                switch (crm) {
1145                  case 0:
1146                    switch (op2) {
1147                      case 1:
1148                        return MISCREG_TLBI_IPAS2E1IS_Xt;
1149                      case 5:
1150                        return MISCREG_TLBI_IPAS2LE1IS_Xt;
1151                    }
1152                    break;
1153                  case 3:
1154                    switch (op2) {
1155                      case 0:
1156                        return MISCREG_TLBI_ALLE2IS;
1157                      case 1:
1158                        return MISCREG_TLBI_VAE2IS_Xt;
1159                      case 4:
1160                        return MISCREG_TLBI_ALLE1IS;
1161                      case 5:
1162                        return MISCREG_TLBI_VALE2IS_Xt;
1163                      case 6:
1164                        return MISCREG_TLBI_VMALLS12E1IS;
1165                    }
1166                    break;
1167                  case 4:
1168                    switch (op2) {
1169                      case 1:
1170                        return MISCREG_TLBI_IPAS2E1_Xt;
1171                      case 5:
1172                        return MISCREG_TLBI_IPAS2LE1_Xt;
1173                    }
1174                    break;
1175                  case 7:
1176                    switch (op2) {
1177                      case 0:
1178                        return MISCREG_TLBI_ALLE2;
1179                      case 1:
1180                        return MISCREG_TLBI_VAE2_Xt;
1181                      case 4:
1182                        return MISCREG_TLBI_ALLE1;
1183                      case 5:
1184                        return MISCREG_TLBI_VALE2_Xt;
1185                      case 6:
1186                        return MISCREG_TLBI_VMALLS12E1;
1187                    }
1188                    break;
1189                }
1190                break;
1191              case 6:
1192                switch (crm) {
1193                  case 3:
1194                    switch (op2) {
1195                      case 0:
1196                        return MISCREG_TLBI_ALLE3IS;
1197                      case 1:
1198                        return MISCREG_TLBI_VAE3IS_Xt;
1199                      case 5:
1200                        return MISCREG_TLBI_VALE3IS_Xt;
1201                    }
1202                    break;
1203                  case 7:
1204                    switch (op2) {
1205                      case 0:
1206                        return MISCREG_TLBI_ALLE3;
1207                      case 1:
1208                        return MISCREG_TLBI_VAE3_Xt;
1209                      case 5:
1210                        return MISCREG_TLBI_VALE3_Xt;
1211                    }
1212                    break;
1213                }
1214                break;
1215            }
1216            break;
1217        }
1218        break;
1219      case 2:
1220        switch (crn) {
1221          case 0:
1222            switch (op1) {
1223              case 0:
1224                switch (crm) {
1225                  case 0:
1226                    switch (op2) {
1227                      case 2:
1228                        return MISCREG_OSDTRRX_EL1;
1229                      case 4:
1230                        return MISCREG_DBGBVR0_EL1;
1231                      case 5:
1232                        return MISCREG_DBGBCR0_EL1;
1233                      case 6:
1234                        return MISCREG_DBGWVR0_EL1;
1235                      case 7:
1236                        return MISCREG_DBGWCR0_EL1;
1237                    }
1238                    break;
1239                  case 1:
1240                    switch (op2) {
1241                      case 4:
1242                        return MISCREG_DBGBVR1_EL1;
1243                      case 5:
1244                        return MISCREG_DBGBCR1_EL1;
1245                      case 6:
1246                        return MISCREG_DBGWVR1_EL1;
1247                      case 7:
1248                        return MISCREG_DBGWCR1_EL1;
1249                    }
1250                    break;
1251                  case 2:
1252                    switch (op2) {
1253                      case 0:
1254                        return MISCREG_MDCCINT_EL1;
1255                      case 2:
1256                        return MISCREG_MDSCR_EL1;
1257                      case 4:
1258                        return MISCREG_DBGBVR2_EL1;
1259                      case 5:
1260                        return MISCREG_DBGBCR2_EL1;
1261                      case 6:
1262                        return MISCREG_DBGWVR2_EL1;
1263                      case 7:
1264                        return MISCREG_DBGWCR2_EL1;
1265                    }
1266                    break;
1267                  case 3:
1268                    switch (op2) {
1269                      case 2:
1270                        return MISCREG_OSDTRTX_EL1;
1271                      case 4:
1272                        return MISCREG_DBGBVR3_EL1;
1273                      case 5:
1274                        return MISCREG_DBGBCR3_EL1;
1275                      case 6:
1276                        return MISCREG_DBGWVR3_EL1;
1277                      case 7:
1278                        return MISCREG_DBGWCR3_EL1;
1279                    }
1280                    break;
1281                  case 4:
1282                    switch (op2) {
1283                      case 4:
1284                        return MISCREG_DBGBVR4_EL1;
1285                      case 5:
1286                        return MISCREG_DBGBCR4_EL1;
1287                    }
1288                    break;
1289                  case 5:
1290                    switch (op2) {
1291                      case 4:
1292                        return MISCREG_DBGBVR5_EL1;
1293                      case 5:
1294                        return MISCREG_DBGBCR5_EL1;
1295                    }
1296                    break;
1297                  case 6:
1298                    switch (op2) {
1299                      case 2:
1300                        return MISCREG_OSECCR_EL1;
1301                    }
1302                    break;
1303                }
1304                break;
1305              case 2:
1306                switch (crm) {
1307                  case 0:
1308                    switch (op2) {
1309                      case 0:
1310                        return MISCREG_TEECR32_EL1;
1311                    }
1312                    break;
1313                }
1314                break;
1315              case 3:
1316                switch (crm) {
1317                  case 1:
1318                    switch (op2) {
1319                      case 0:
1320                        return MISCREG_MDCCSR_EL0;
1321                    }
1322                    break;
1323                  case 4:
1324                    switch (op2) {
1325                      case 0:
1326                        return MISCREG_MDDTR_EL0;
1327                    }
1328                    break;
1329                  case 5:
1330                    switch (op2) {
1331                      case 0:
1332                        return MISCREG_MDDTRRX_EL0;
1333                    }
1334                    break;
1335                }
1336                break;
1337              case 4:
1338                switch (crm) {
1339                  case 7:
1340                    switch (op2) {
1341                      case 0:
1342                        return MISCREG_DBGVCR32_EL2;
1343                    }
1344                    break;
1345                }
1346                break;
1347            }
1348            break;
1349          case 1:
1350            switch (op1) {
1351              case 0:
1352                switch (crm) {
1353                  case 0:
1354                    switch (op2) {
1355                      case 0:
1356                        return MISCREG_MDRAR_EL1;
1357                      case 4:
1358                        return MISCREG_OSLAR_EL1;
1359                    }
1360                    break;
1361                  case 1:
1362                    switch (op2) {
1363                      case 4:
1364                        return MISCREG_OSLSR_EL1;
1365                    }
1366                    break;
1367                  case 3:
1368                    switch (op2) {
1369                      case 4:
1370                        return MISCREG_OSDLR_EL1;
1371                    }
1372                    break;
1373                  case 4:
1374                    switch (op2) {
1375                      case 4:
1376                        return MISCREG_DBGPRCR_EL1;
1377                    }
1378                    break;
1379                }
1380                break;
1381              case 2:
1382                switch (crm) {
1383                  case 0:
1384                    switch (op2) {
1385                      case 0:
1386                        return MISCREG_TEEHBR32_EL1;
1387                    }
1388                    break;
1389                }
1390                break;
1391            }
1392            break;
1393          case 7:
1394            switch (op1) {
1395              case 0:
1396                switch (crm) {
1397                  case 8:
1398                    switch (op2) {
1399                      case 6:
1400                        return MISCREG_DBGCLAIMSET_EL1;
1401                    }
1402                    break;
1403                  case 9:
1404                    switch (op2) {
1405                      case 6:
1406                        return MISCREG_DBGCLAIMCLR_EL1;
1407                    }
1408                    break;
1409                  case 14:
1410                    switch (op2) {
1411                      case 6:
1412                        return MISCREG_DBGAUTHSTATUS_EL1;
1413                    }
1414                    break;
1415                }
1416                break;
1417            }
1418            break;
1419        }
1420        break;
1421      case 3:
1422        switch (crn) {
1423          case 0:
1424            switch (op1) {
1425              case 0:
1426                switch (crm) {
1427                  case 0:
1428                    switch (op2) {
1429                      case 0:
1430                        return MISCREG_MIDR_EL1;
1431                      case 5:
1432                        return MISCREG_MPIDR_EL1;
1433                      case 6:
1434                        return MISCREG_REVIDR_EL1;
1435                    }
1436                    break;
1437                  case 1:
1438                    switch (op2) {
1439                      case 0:
1440                        return MISCREG_ID_PFR0_EL1;
1441                      case 1:
1442                        return MISCREG_ID_PFR1_EL1;
1443                      case 2:
1444                        return MISCREG_ID_DFR0_EL1;
1445                      case 3:
1446                        return MISCREG_ID_AFR0_EL1;
1447                      case 4:
1448                        return MISCREG_ID_MMFR0_EL1;
1449                      case 5:
1450                        return MISCREG_ID_MMFR1_EL1;
1451                      case 6:
1452                        return MISCREG_ID_MMFR2_EL1;
1453                      case 7:
1454                        return MISCREG_ID_MMFR3_EL1;
1455                    }
1456                    break;
1457                  case 2:
1458                    switch (op2) {
1459                      case 0:
1460                        return MISCREG_ID_ISAR0_EL1;
1461                      case 1:
1462                        return MISCREG_ID_ISAR1_EL1;
1463                      case 2:
1464                        return MISCREG_ID_ISAR2_EL1;
1465                      case 3:
1466                        return MISCREG_ID_ISAR3_EL1;
1467                      case 4:
1468                        return MISCREG_ID_ISAR4_EL1;
1469                      case 5:
1470                        return MISCREG_ID_ISAR5_EL1;
1471                    }
1472                    break;
1473                  case 3:
1474                    switch (op2) {
1475                      case 0:
1476                        return MISCREG_MVFR0_EL1;
1477                      case 1:
1478                        return MISCREG_MVFR1_EL1;
1479                      case 2:
1480                        return MISCREG_MVFR2_EL1;
1481                      case 3 ... 7:
1482                        return MISCREG_RAZ;
1483                    }
1484                    break;
1485                  case 4:
1486                    switch (op2) {
1487                      case 0:
1488                        return MISCREG_ID_AA64PFR0_EL1;
1489                      case 1:
1490                        return MISCREG_ID_AA64PFR1_EL1;
1491                      case 2 ... 7:
1492                        return MISCREG_RAZ;
1493                    }
1494                    break;
1495                  case 5:
1496                    switch (op2) {
1497                      case 0:
1498                        return MISCREG_ID_AA64DFR0_EL1;
1499                      case 1:
1500                        return MISCREG_ID_AA64DFR1_EL1;
1501                      case 4:
1502                        return MISCREG_ID_AA64AFR0_EL1;
1503                      case 5:
1504                        return MISCREG_ID_AA64AFR1_EL1;
1505                      case 2:
1506                      case 3:
1507                      case 6:
1508                      case 7:
1509                        return MISCREG_RAZ;
1510                    }
1511                    break;
1512                  case 6:
1513                    switch (op2) {
1514                      case 0:
1515                        return MISCREG_ID_AA64ISAR0_EL1;
1516                      case 1:
1517                        return MISCREG_ID_AA64ISAR1_EL1;
1518                      case 2 ... 7:
1519                        return MISCREG_RAZ;
1520                    }
1521                    break;
1522                  case 7:
1523                    switch (op2) {
1524                      case 0:
1525                        return MISCREG_ID_AA64MMFR0_EL1;
1526                      case 1:
1527                        return MISCREG_ID_AA64MMFR1_EL1;
1528                      case 2 ... 7:
1529                        return MISCREG_RAZ;
1530                    }
1531                    break;
1532                }
1533                break;
1534              case 1:
1535                switch (crm) {
1536                  case 0:
1537                    switch (op2) {
1538                      case 0:
1539                        return MISCREG_CCSIDR_EL1;
1540                      case 1:
1541                        return MISCREG_CLIDR_EL1;
1542                      case 7:
1543                        return MISCREG_AIDR_EL1;
1544                    }
1545                    break;
1546                }
1547                break;
1548              case 2:
1549                switch (crm) {
1550                  case 0:
1551                    switch (op2) {
1552                      case 0:
1553                        return MISCREG_CSSELR_EL1;
1554                    }
1555                    break;
1556                }
1557                break;
1558              case 3:
1559                switch (crm) {
1560                  case 0:
1561                    switch (op2) {
1562                      case 1:
1563                        return MISCREG_CTR_EL0;
1564                      case 7:
1565                        return MISCREG_DCZID_EL0;
1566                    }
1567                    break;
1568                }
1569                break;
1570              case 4:
1571                switch (crm) {
1572                  case 0:
1573                    switch (op2) {
1574                      case 0:
1575                        return MISCREG_VPIDR_EL2;
1576                      case 5:
1577                        return MISCREG_VMPIDR_EL2;
1578                    }
1579                    break;
1580                }
1581                break;
1582            }
1583            break;
1584          case 1:
1585            switch (op1) {
1586              case 0:
1587                switch (crm) {
1588                  case 0:
1589                    switch (op2) {
1590                      case 0:
1591                        return MISCREG_SCTLR_EL1;
1592                      case 1:
1593                        return MISCREG_ACTLR_EL1;
1594                      case 2:
1595                        return MISCREG_CPACR_EL1;
1596                    }
1597                    break;
1598                }
1599                break;
1600              case 4:
1601                switch (crm) {
1602                  case 0:
1603                    switch (op2) {
1604                      case 0:
1605                        return MISCREG_SCTLR_EL2;
1606                      case 1:
1607                        return MISCREG_ACTLR_EL2;
1608                    }
1609                    break;
1610                  case 1:
1611                    switch (op2) {
1612                      case 0:
1613                        return MISCREG_HCR_EL2;
1614                      case 1:
1615                        return MISCREG_MDCR_EL2;
1616                      case 2:
1617                        return MISCREG_CPTR_EL2;
1618                      case 3:
1619                        return MISCREG_HSTR_EL2;
1620                      case 7:
1621                        return MISCREG_HACR_EL2;
1622                    }
1623                    break;
1624                }
1625                break;
1626              case 6:
1627                switch (crm) {
1628                  case 0:
1629                    switch (op2) {
1630                      case 0:
1631                        return MISCREG_SCTLR_EL3;
1632                      case 1:
1633                        return MISCREG_ACTLR_EL3;
1634                    }
1635                    break;
1636                  case 1:
1637                    switch (op2) {
1638                      case 0:
1639                        return MISCREG_SCR_EL3;
1640                      case 1:
1641                        return MISCREG_SDER32_EL3;
1642                      case 2:
1643                        return MISCREG_CPTR_EL3;
1644                    }
1645                    break;
1646                  case 3:
1647                    switch (op2) {
1648                      case 1:
1649                        return MISCREG_MDCR_EL3;
1650                    }
1651                    break;
1652                }
1653                break;
1654            }
1655            break;
1656          case 2:
1657            switch (op1) {
1658              case 0:
1659                switch (crm) {
1660                  case 0:
1661                    switch (op2) {
1662                      case 0:
1663                        return MISCREG_TTBR0_EL1;
1664                      case 1:
1665                        return MISCREG_TTBR1_EL1;
1666                      case 2:
1667                        return MISCREG_TCR_EL1;
1668                    }
1669                    break;
1670                }
1671                break;
1672              case 4:
1673                switch (crm) {
1674                  case 0:
1675                    switch (op2) {
1676                      case 0:
1677                        return MISCREG_TTBR0_EL2;
1678                      case 2:
1679                        return MISCREG_TCR_EL2;
1680                    }
1681                    break;
1682                  case 1:
1683                    switch (op2) {
1684                      case 0:
1685                        return MISCREG_VTTBR_EL2;
1686                      case 2:
1687                        return MISCREG_VTCR_EL2;
1688                    }
1689                    break;
1690                }
1691                break;
1692              case 6:
1693                switch (crm) {
1694                  case 0:
1695                    switch (op2) {
1696                      case 0:
1697                        return MISCREG_TTBR0_EL3;
1698                      case 2:
1699                        return MISCREG_TCR_EL3;
1700                    }
1701                    break;
1702                }
1703                break;
1704            }
1705            break;
1706          case 3:
1707            switch (op1) {
1708              case 4:
1709                switch (crm) {
1710                  case 0:
1711                    switch (op2) {
1712                      case 0:
1713                        return MISCREG_DACR32_EL2;
1714                    }
1715                    break;
1716                }
1717                break;
1718            }
1719            break;
1720          case 4:
1721            switch (op1) {
1722              case 0:
1723                switch (crm) {
1724                  case 0:
1725                    switch (op2) {
1726                      case 0:
1727                        return MISCREG_SPSR_EL1;
1728                      case 1:
1729                        return MISCREG_ELR_EL1;
1730                    }
1731                    break;
1732                  case 1:
1733                    switch (op2) {
1734                      case 0:
1735                        return MISCREG_SP_EL0;
1736                    }
1737                    break;
1738                  case 2:
1739                    switch (op2) {
1740                      case 0:
1741                        return MISCREG_SPSEL;
1742                      case 2:
1743                        return MISCREG_CURRENTEL;
1744                    }
1745                    break;
1746                }
1747                break;
1748              case 3:
1749                switch (crm) {
1750                  case 2:
1751                    switch (op2) {
1752                      case 0:
1753                        return MISCREG_NZCV;
1754                      case 1:
1755                        return MISCREG_DAIF;
1756                    }
1757                    break;
1758                  case 4:
1759                    switch (op2) {
1760                      case 0:
1761                        return MISCREG_FPCR;
1762                      case 1:
1763                        return MISCREG_FPSR;
1764                    }
1765                    break;
1766                  case 5:
1767                    switch (op2) {
1768                      case 0:
1769                        return MISCREG_DSPSR_EL0;
1770                      case 1:
1771                        return MISCREG_DLR_EL0;
1772                    }
1773                    break;
1774                }
1775                break;
1776              case 4:
1777                switch (crm) {
1778                  case 0:
1779                    switch (op2) {
1780                      case 0:
1781                        return MISCREG_SPSR_EL2;
1782                      case 1:
1783                        return MISCREG_ELR_EL2;
1784                    }
1785                    break;
1786                  case 1:
1787                    switch (op2) {
1788                      case 0:
1789                        return MISCREG_SP_EL1;
1790                    }
1791                    break;
1792                  case 3:
1793                    switch (op2) {
1794                      case 0:
1795                        return MISCREG_SPSR_IRQ_AA64;
1796                      case 1:
1797                        return MISCREG_SPSR_ABT_AA64;
1798                      case 2:
1799                        return MISCREG_SPSR_UND_AA64;
1800                      case 3:
1801                        return MISCREG_SPSR_FIQ_AA64;
1802                    }
1803                    break;
1804                }
1805                break;
1806              case 6:
1807                switch (crm) {
1808                  case 0:
1809                    switch (op2) {
1810                      case 0:
1811                        return MISCREG_SPSR_EL3;
1812                      case 1:
1813                        return MISCREG_ELR_EL3;
1814                    }
1815                    break;
1816                  case 1:
1817                    switch (op2) {
1818                      case 0:
1819                        return MISCREG_SP_EL2;
1820                    }
1821                    break;
1822                }
1823                break;
1824            }
1825            break;
1826          case 5:
1827            switch (op1) {
1828              case 0:
1829                switch (crm) {
1830                  case 1:
1831                    switch (op2) {
1832                      case 0:
1833                        return MISCREG_AFSR0_EL1;
1834                      case 1:
1835                        return MISCREG_AFSR1_EL1;
1836                    }
1837                    break;
1838                  case 2:
1839                    switch (op2) {
1840                      case 0:
1841                        return MISCREG_ESR_EL1;
1842                    }
1843                    break;
1844                }
1845                break;
1846              case 4:
1847                switch (crm) {
1848                  case 0:
1849                    switch (op2) {
1850                      case 1:
1851                        return MISCREG_IFSR32_EL2;
1852                    }
1853                    break;
1854                  case 1:
1855                    switch (op2) {
1856                      case 0:
1857                        return MISCREG_AFSR0_EL2;
1858                      case 1:
1859                        return MISCREG_AFSR1_EL2;
1860                    }
1861                    break;
1862                  case 2:
1863                    switch (op2) {
1864                      case 0:
1865                        return MISCREG_ESR_EL2;
1866                    }
1867                    break;
1868                  case 3:
1869                    switch (op2) {
1870                      case 0:
1871                        return MISCREG_FPEXC32_EL2;
1872                    }
1873                    break;
1874                }
1875                break;
1876              case 6:
1877                switch (crm) {
1878                  case 1:
1879                    switch (op2) {
1880                      case 0:
1881                        return MISCREG_AFSR0_EL3;
1882                      case 1:
1883                        return MISCREG_AFSR1_EL3;
1884                    }
1885                    break;
1886                  case 2:
1887                    switch (op2) {
1888                      case 0:
1889                        return MISCREG_ESR_EL3;
1890                    }
1891                    break;
1892                }
1893                break;
1894            }
1895            break;
1896          case 6:
1897            switch (op1) {
1898              case 0:
1899                switch (crm) {
1900                  case 0:
1901                    switch (op2) {
1902                      case 0:
1903                        return MISCREG_FAR_EL1;
1904                    }
1905                    break;
1906                }
1907                break;
1908              case 4:
1909                switch (crm) {
1910                  case 0:
1911                    switch (op2) {
1912                      case 0:
1913                        return MISCREG_FAR_EL2;
1914                      case 4:
1915                        return MISCREG_HPFAR_EL2;
1916                    }
1917                    break;
1918                }
1919                break;
1920              case 6:
1921                switch (crm) {
1922                  case 0:
1923                    switch (op2) {
1924                      case 0:
1925                        return MISCREG_FAR_EL3;
1926                    }
1927                    break;
1928                }
1929                break;
1930            }
1931            break;
1932          case 7:
1933            switch (op1) {
1934              case 0:
1935                switch (crm) {
1936                  case 4:
1937                    switch (op2) {
1938                      case 0:
1939                        return MISCREG_PAR_EL1;
1940                    }
1941                    break;
1942                }
1943                break;
1944            }
1945            break;
1946          case 9:
1947            switch (op1) {
1948              case 0:
1949                switch (crm) {
1950                  case 14:
1951                    switch (op2) {
1952                      case 1:
1953                        return MISCREG_PMINTENSET_EL1;
1954                      case 2:
1955                        return MISCREG_PMINTENCLR_EL1;
1956                    }
1957                    break;
1958                }
1959                break;
1960              case 3:
1961                switch (crm) {
1962                  case 12:
1963                    switch (op2) {
1964                      case 0:
1965                        return MISCREG_PMCR_EL0;
1966                      case 1:
1967                        return MISCREG_PMCNTENSET_EL0;
1968                      case 2:
1969                        return MISCREG_PMCNTENCLR_EL0;
1970                      case 3:
1971                        return MISCREG_PMOVSCLR_EL0;
1972                      case 4:
1973                        return MISCREG_PMSWINC_EL0;
1974                      case 5:
1975                        return MISCREG_PMSELR_EL0;
1976                      case 6:
1977                        return MISCREG_PMCEID0_EL0;
1978                      case 7:
1979                        return MISCREG_PMCEID1_EL0;
1980                    }
1981                    break;
1982                  case 13:
1983                    switch (op2) {
1984                      case 0:
1985                        return MISCREG_PMCCNTR_EL0;
1986                      case 1:
1987                        return MISCREG_PMXEVTYPER_EL0;
1988                      case 2:
1989                        return MISCREG_PMXEVCNTR_EL0;
1990                    }
1991                    break;
1992                  case 14:
1993                    switch (op2) {
1994                      case 0:
1995                        return MISCREG_PMUSERENR_EL0;
1996                      case 3:
1997                        return MISCREG_PMOVSSET_EL0;
1998                    }
1999                    break;
2000                }
2001                break;
2002            }
2003            break;
2004          case 10:
2005            switch (op1) {
2006              case 0:
2007                switch (crm) {
2008                  case 2:
2009                    switch (op2) {
2010                      case 0:
2011                        return MISCREG_MAIR_EL1;
2012                    }
2013                    break;
2014                  case 3:
2015                    switch (op2) {
2016                      case 0:
2017                        return MISCREG_AMAIR_EL1;
2018                    }
2019                    break;
2020                }
2021                break;
2022              case 4:
2023                switch (crm) {
2024                  case 2:
2025                    switch (op2) {
2026                      case 0:
2027                        return MISCREG_MAIR_EL2;
2028                    }
2029                    break;
2030                  case 3:
2031                    switch (op2) {
2032                      case 0:
2033                        return MISCREG_AMAIR_EL2;
2034                    }
2035                    break;
2036                }
2037                break;
2038              case 6:
2039                switch (crm) {
2040                  case 2:
2041                    switch (op2) {
2042                      case 0:
2043                        return MISCREG_MAIR_EL3;
2044                    }
2045                    break;
2046                  case 3:
2047                    switch (op2) {
2048                      case 0:
2049                        return MISCREG_AMAIR_EL3;
2050                    }
2051                    break;
2052                }
2053                break;
2054            }
2055            break;
2056          case 11:
2057            switch (op1) {
2058              case 1:
2059                switch (crm) {
2060                  case 0:
2061                    switch (op2) {
2062                      case 2:
2063                        return MISCREG_L2CTLR_EL1;
2064                      case 3:
2065                        return MISCREG_L2ECTLR_EL1;
2066                    }
2067                    break;
2068                }
2069                break;
2070            }
2071            break;
2072          case 12:
2073            switch (op1) {
2074              case 0:
2075                switch (crm) {
2076                  case 0:
2077                    switch (op2) {
2078                      case 0:
2079                        return MISCREG_VBAR_EL1;
2080                      case 1:
2081                        return MISCREG_RVBAR_EL1;
2082                    }
2083                    break;
2084                  case 1:
2085                    switch (op2) {
2086                      case 0:
2087                        return MISCREG_ISR_EL1;
2088                    }
2089                    break;
2090                }
2091                break;
2092              case 4:
2093                switch (crm) {
2094                  case 0:
2095                    switch (op2) {
2096                      case 0:
2097                        return MISCREG_VBAR_EL2;
2098                      case 1:
2099                        return MISCREG_RVBAR_EL2;
2100                    }
2101                    break;
2102                }
2103                break;
2104              case 6:
2105                switch (crm) {
2106                  case 0:
2107                    switch (op2) {
2108                      case 0:
2109                        return MISCREG_VBAR_EL3;
2110                      case 1:
2111                        return MISCREG_RVBAR_EL3;
2112                      case 2:
2113                        return MISCREG_RMR_EL3;
2114                    }
2115                    break;
2116                }
2117                break;
2118            }
2119            break;
2120          case 13:
2121            switch (op1) {
2122              case 0:
2123                switch (crm) {
2124                  case 0:
2125                    switch (op2) {
2126                      case 1:
2127                        return MISCREG_CONTEXTIDR_EL1;
2128                      case 4:
2129                        return MISCREG_TPIDR_EL1;
2130                    }
2131                    break;
2132                }
2133                break;
2134              case 3:
2135                switch (crm) {
2136                  case 0:
2137                    switch (op2) {
2138                      case 2:
2139                        return MISCREG_TPIDR_EL0;
2140                      case 3:
2141                        return MISCREG_TPIDRRO_EL0;
2142                    }
2143                    break;
2144                }
2145                break;
2146              case 4:
2147                switch (crm) {
2148                  case 0:
2149                    switch (op2) {
2150                      case 1:
2151                        return MISCREG_CONTEXTIDR_EL2;
2152                      case 2:
2153                        return MISCREG_TPIDR_EL2;
2154                    }
2155                    break;
2156                }
2157                break;
2158              case 6:
2159                switch (crm) {
2160                  case 0:
2161                    switch (op2) {
2162                      case 2:
2163                        return MISCREG_TPIDR_EL3;
2164                    }
2165                    break;
2166                }
2167                break;
2168            }
2169            break;
2170          case 14:
2171            switch (op1) {
2172              case 0:
2173                switch (crm) {
2174                  case 1:
2175                    switch (op2) {
2176                      case 0:
2177                        return MISCREG_CNTKCTL_EL1;
2178                    }
2179                    break;
2180                }
2181                break;
2182              case 3:
2183                switch (crm) {
2184                  case 0:
2185                    switch (op2) {
2186                      case 0:
2187                        return MISCREG_CNTFRQ_EL0;
2188                      case 1:
2189                        return MISCREG_CNTPCT_EL0;
2190                      case 2:
2191                        return MISCREG_CNTVCT_EL0;
2192                    }
2193                    break;
2194                  case 2:
2195                    switch (op2) {
2196                      case 0:
2197                        return MISCREG_CNTP_TVAL_EL0;
2198                      case 1:
2199                        return MISCREG_CNTP_CTL_EL0;
2200                      case 2:
2201                        return MISCREG_CNTP_CVAL_EL0;
2202                    }
2203                    break;
2204                  case 3:
2205                    switch (op2) {
2206                      case 0:
2207                        return MISCREG_CNTV_TVAL_EL0;
2208                      case 1:
2209                        return MISCREG_CNTV_CTL_EL0;
2210                      case 2:
2211                        return MISCREG_CNTV_CVAL_EL0;
2212                    }
2213                    break;
2214                  case 8:
2215                    switch (op2) {
2216                      case 0:
2217                        return MISCREG_PMEVCNTR0_EL0;
2218                      case 1:
2219                        return MISCREG_PMEVCNTR1_EL0;
2220                      case 2:
2221                        return MISCREG_PMEVCNTR2_EL0;
2222                      case 3:
2223                        return MISCREG_PMEVCNTR3_EL0;
2224                      case 4:
2225                        return MISCREG_PMEVCNTR4_EL0;
2226                      case 5:
2227                        return MISCREG_PMEVCNTR5_EL0;
2228                    }
2229                    break;
2230                  case 12:
2231                    switch (op2) {
2232                      case 0:
2233                        return MISCREG_PMEVTYPER0_EL0;
2234                      case 1:
2235                        return MISCREG_PMEVTYPER1_EL0;
2236                      case 2:
2237                        return MISCREG_PMEVTYPER2_EL0;
2238                      case 3:
2239                        return MISCREG_PMEVTYPER3_EL0;
2240                      case 4:
2241                        return MISCREG_PMEVTYPER4_EL0;
2242                      case 5:
2243                        return MISCREG_PMEVTYPER5_EL0;
2244                    }
2245                    break;
2246                  case 15:
2247                    switch (op2) {
2248                      case 7:
2249                        return MISCREG_PMCCFILTR_EL0;
2250                    }
2251                }
2252                break;
2253              case 4:
2254                switch (crm) {
2255                  case 0:
2256                    switch (op2) {
2257                      case 3:
2258                        return MISCREG_CNTVOFF_EL2;
2259                    }
2260                    break;
2261                  case 1:
2262                    switch (op2) {
2263                      case 0:
2264                        return MISCREG_CNTHCTL_EL2;
2265                    }
2266                    break;
2267                  case 2:
2268                    switch (op2) {
2269                      case 0:
2270                        return MISCREG_CNTHP_TVAL_EL2;
2271                      case 1:
2272                        return MISCREG_CNTHP_CTL_EL2;
2273                      case 2:
2274                        return MISCREG_CNTHP_CVAL_EL2;
2275                    }
2276                    break;
2277                }
2278                break;
2279              case 7:
2280                switch (crm) {
2281                  case 2:
2282                    switch (op2) {
2283                      case 0:
2284                        return MISCREG_CNTPS_TVAL_EL1;
2285                      case 1:
2286                        return MISCREG_CNTPS_CTL_EL1;
2287                      case 2:
2288                        return MISCREG_CNTPS_CVAL_EL1;
2289                    }
2290                    break;
2291                }
2292                break;
2293            }
2294            break;
2295          case 15:
2296            switch (op1) {
2297              case 0:
2298                switch (crm) {
2299                  case 0:
2300                    switch (op2) {
2301                      case 0:
2302                        return MISCREG_IL1DATA0_EL1;
2303                      case 1:
2304                        return MISCREG_IL1DATA1_EL1;
2305                      case 2:
2306                        return MISCREG_IL1DATA2_EL1;
2307                      case 3:
2308                        return MISCREG_IL1DATA3_EL1;
2309                    }
2310                    break;
2311                  case 1:
2312                    switch (op2) {
2313                      case 0:
2314                        return MISCREG_DL1DATA0_EL1;
2315                      case 1:
2316                        return MISCREG_DL1DATA1_EL1;
2317                      case 2:
2318                        return MISCREG_DL1DATA2_EL1;
2319                      case 3:
2320                        return MISCREG_DL1DATA3_EL1;
2321                      case 4:
2322                        return MISCREG_DL1DATA4_EL1;
2323                    }
2324                    break;
2325                }
2326                break;
2327              case 1:
2328                switch (crm) {
2329                  case 0:
2330                    switch (op2) {
2331                      case 0:
2332                        return MISCREG_L2ACTLR_EL1;
2333                    }
2334                    break;
2335                  case 2:
2336                    switch (op2) {
2337                      case 0:
2338                        return MISCREG_CPUACTLR_EL1;
2339                      case 1:
2340                        return MISCREG_CPUECTLR_EL1;
2341                      case 2:
2342                        return MISCREG_CPUMERRSR_EL1;
2343                      case 3:
2344                        return MISCREG_L2MERRSR_EL1;
2345                    }
2346                    break;
2347                  case 3:
2348                    switch (op2) {
2349                      case 0:
2350                        return MISCREG_CBAR_EL1;
2351
2352                    }
2353                    break;
2354                }
2355                break;
2356            }
2357            break;
2358        }
2359        break;
2360    }
2361
2362    return MISCREG_UNKNOWN;
2363}
2364
2365bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2366
2367void
2368ISA::initializeMiscRegMetadata()
2369{
2370    // the MiscReg metadata tables are shared across all instances of the
2371    // ISA object, so there's no need to initialize them multiple times.
2372    static bool completed = false;
2373    if (completed)
2374        return;
2375
2376    /**
2377     * Some registers alias with others, and therefore need to be translated.
2378     * When two mapping registers are given, they are the 32b lower and
2379     * upper halves, respectively, of the 64b register being mapped.
2380     * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2381     *
2382     * NAM = "not architecturally mandated",
2383     * from ARM DDI 0487A.i, template text
2384     * "AArch64 System register ___ can be mapped to
2385     *  AArch32 System register ___, but this is not
2386     *  architecturally mandated."
2387     */
2388
2389    InitReg(MISCREG_CPSR)
2390      .allPrivileges();
2391    InitReg(MISCREG_SPSR)
2392      .allPrivileges();
2393    InitReg(MISCREG_SPSR_FIQ)
2394      .allPrivileges();
2395    InitReg(MISCREG_SPSR_IRQ)
2396      .allPrivileges();
2397    InitReg(MISCREG_SPSR_SVC)
2398      .allPrivileges();
2399    InitReg(MISCREG_SPSR_MON)
2400      .allPrivileges();
2401    InitReg(MISCREG_SPSR_ABT)
2402      .allPrivileges();
2403    InitReg(MISCREG_SPSR_HYP)
2404      .allPrivileges();
2405    InitReg(MISCREG_SPSR_UND)
2406      .allPrivileges();
2407    InitReg(MISCREG_ELR_HYP)
2408      .allPrivileges();
2409    InitReg(MISCREG_FPSID)
2410      .allPrivileges();
2411    InitReg(MISCREG_FPSCR)
2412      .allPrivileges();
2413    InitReg(MISCREG_MVFR1)
2414      .allPrivileges();
2415    InitReg(MISCREG_MVFR0)
2416      .allPrivileges();
2417    InitReg(MISCREG_FPEXC)
2418      .allPrivileges();
2419
2420    // Helper registers
2421    InitReg(MISCREG_CPSR_MODE)
2422      .allPrivileges();
2423    InitReg(MISCREG_CPSR_Q)
2424      .allPrivileges();
2425    InitReg(MISCREG_FPSCR_EXC)
2426      .allPrivileges();
2427    InitReg(MISCREG_FPSCR_QC)
2428      .allPrivileges();
2429    InitReg(MISCREG_LOCKADDR)
2430      .allPrivileges();
2431    InitReg(MISCREG_LOCKFLAG)
2432      .allPrivileges();
2433    InitReg(MISCREG_PRRR_MAIR0)
2434      .mutex()
2435      .banked();
2436    InitReg(MISCREG_PRRR_MAIR0_NS)
2437      .mutex()
2438      .bankedChild();
2439    InitReg(MISCREG_PRRR_MAIR0_S)
2440      .mutex()
2441      .bankedChild();
2442    InitReg(MISCREG_NMRR_MAIR1)
2443      .mutex()
2444      .banked();
2445    InitReg(MISCREG_NMRR_MAIR1_NS)
2446      .mutex()
2447      .bankedChild();
2448    InitReg(MISCREG_NMRR_MAIR1_S)
2449      .mutex()
2450      .bankedChild();
2451    InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2452      .mutex();
2453    InitReg(MISCREG_SCTLR_RST)
2454      .allPrivileges();
2455    InitReg(MISCREG_SEV_MAILBOX)
2456      .allPrivileges();
2457
2458    // AArch32 CP14 registers
2459    InitReg(MISCREG_DBGDIDR)
2460      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2461    InitReg(MISCREG_DBGDSCRint)
2462      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2463    InitReg(MISCREG_DBGDCCINT)
2464      .unimplemented()
2465      .allPrivileges();
2466    InitReg(MISCREG_DBGDTRTXint)
2467      .unimplemented()
2468      .allPrivileges();
2469    InitReg(MISCREG_DBGDTRRXint)
2470      .unimplemented()
2471      .allPrivileges();
2472    InitReg(MISCREG_DBGWFAR)
2473      .unimplemented()
2474      .allPrivileges();
2475    InitReg(MISCREG_DBGVCR)
2476      .unimplemented()
2477      .allPrivileges();
2478    InitReg(MISCREG_DBGDTRRXext)
2479      .unimplemented()
2480      .allPrivileges();
2481    InitReg(MISCREG_DBGDSCRext)
2482      .unimplemented()
2483      .warnNotFail()
2484      .allPrivileges();
2485    InitReg(MISCREG_DBGDTRTXext)
2486      .unimplemented()
2487      .allPrivileges();
2488    InitReg(MISCREG_DBGOSECCR)
2489      .unimplemented()
2490      .allPrivileges();
2491    InitReg(MISCREG_DBGBVR0)
2492      .unimplemented()
2493      .allPrivileges();
2494    InitReg(MISCREG_DBGBVR1)
2495      .unimplemented()
2496      .allPrivileges();
2497    InitReg(MISCREG_DBGBVR2)
2498      .unimplemented()
2499      .allPrivileges();
2500    InitReg(MISCREG_DBGBVR3)
2501      .unimplemented()
2502      .allPrivileges();
2503    InitReg(MISCREG_DBGBVR4)
2504      .unimplemented()
2505      .allPrivileges();
2506    InitReg(MISCREG_DBGBVR5)
2507      .unimplemented()
2508      .allPrivileges();
2509    InitReg(MISCREG_DBGBCR0)
2510      .unimplemented()
2511      .allPrivileges();
2512    InitReg(MISCREG_DBGBCR1)
2513      .unimplemented()
2514      .allPrivileges();
2515    InitReg(MISCREG_DBGBCR2)
2516      .unimplemented()
2517      .allPrivileges();
2518    InitReg(MISCREG_DBGBCR3)
2519      .unimplemented()
2520      .allPrivileges();
2521    InitReg(MISCREG_DBGBCR4)
2522      .unimplemented()
2523      .allPrivileges();
2524    InitReg(MISCREG_DBGBCR5)
2525      .unimplemented()
2526      .allPrivileges();
2527    InitReg(MISCREG_DBGWVR0)
2528      .unimplemented()
2529      .allPrivileges();
2530    InitReg(MISCREG_DBGWVR1)
2531      .unimplemented()
2532      .allPrivileges();
2533    InitReg(MISCREG_DBGWVR2)
2534      .unimplemented()
2535      .allPrivileges();
2536    InitReg(MISCREG_DBGWVR3)
2537      .unimplemented()
2538      .allPrivileges();
2539    InitReg(MISCREG_DBGWCR0)
2540      .unimplemented()
2541      .allPrivileges();
2542    InitReg(MISCREG_DBGWCR1)
2543      .unimplemented()
2544      .allPrivileges();
2545    InitReg(MISCREG_DBGWCR2)
2546      .unimplemented()
2547      .allPrivileges();
2548    InitReg(MISCREG_DBGWCR3)
2549      .unimplemented()
2550      .allPrivileges();
2551    InitReg(MISCREG_DBGDRAR)
2552      .unimplemented()
2553      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2554    InitReg(MISCREG_DBGBXVR4)
2555      .unimplemented()
2556      .allPrivileges();
2557    InitReg(MISCREG_DBGBXVR5)
2558      .unimplemented()
2559      .allPrivileges();
2560    InitReg(MISCREG_DBGOSLAR)
2561      .unimplemented()
2562      .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2563    InitReg(MISCREG_DBGOSLSR)
2564      .unimplemented()
2565      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2566    InitReg(MISCREG_DBGOSDLR)
2567      .unimplemented()
2568      .allPrivileges();
2569    InitReg(MISCREG_DBGPRCR)
2570      .unimplemented()
2571      .allPrivileges();
2572    InitReg(MISCREG_DBGDSAR)
2573      .unimplemented()
2574      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2575    InitReg(MISCREG_DBGCLAIMSET)
2576      .unimplemented()
2577      .allPrivileges();
2578    InitReg(MISCREG_DBGCLAIMCLR)
2579      .unimplemented()
2580      .allPrivileges();
2581    InitReg(MISCREG_DBGAUTHSTATUS)
2582      .unimplemented()
2583      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2584    InitReg(MISCREG_DBGDEVID2)
2585      .unimplemented()
2586      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2587    InitReg(MISCREG_DBGDEVID1)
2588      .unimplemented()
2589      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2590    InitReg(MISCREG_DBGDEVID0)
2591      .unimplemented()
2592      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2593    InitReg(MISCREG_TEECR)
2594      .unimplemented()
2595      .allPrivileges();
2596    InitReg(MISCREG_JIDR)
2597      .allPrivileges();
2598    InitReg(MISCREG_TEEHBR)
2599      .allPrivileges();
2600    InitReg(MISCREG_JOSCR)
2601      .allPrivileges();
2602    InitReg(MISCREG_JMCR)
2603      .allPrivileges();
2604
2605    // AArch32 CP15 registers
2606    InitReg(MISCREG_MIDR)
2607      .allPrivileges().exceptUserMode().writes(0);
2608    InitReg(MISCREG_CTR)
2609      .allPrivileges().exceptUserMode().writes(0);
2610    InitReg(MISCREG_TCMTR)
2611      .allPrivileges().exceptUserMode().writes(0);
2612    InitReg(MISCREG_TLBTR)
2613      .allPrivileges().exceptUserMode().writes(0);
2614    InitReg(MISCREG_MPIDR)
2615      .allPrivileges().exceptUserMode().writes(0);
2616    InitReg(MISCREG_REVIDR)
2617      .unimplemented()
2618      .warnNotFail()
2619      .allPrivileges().exceptUserMode().writes(0);
2620    InitReg(MISCREG_ID_PFR0)
2621      .allPrivileges().exceptUserMode().writes(0);
2622    InitReg(MISCREG_ID_PFR1)
2623      .allPrivileges().exceptUserMode().writes(0);
2624    InitReg(MISCREG_ID_DFR0)
2625      .allPrivileges().exceptUserMode().writes(0);
2626    InitReg(MISCREG_ID_AFR0)
2627      .allPrivileges().exceptUserMode().writes(0);
2628    InitReg(MISCREG_ID_MMFR0)
2629      .allPrivileges().exceptUserMode().writes(0);
2630    InitReg(MISCREG_ID_MMFR1)
2631      .allPrivileges().exceptUserMode().writes(0);
2632    InitReg(MISCREG_ID_MMFR2)
2633      .allPrivileges().exceptUserMode().writes(0);
2634    InitReg(MISCREG_ID_MMFR3)
2635      .allPrivileges().exceptUserMode().writes(0);
2636    InitReg(MISCREG_ID_ISAR0)
2637      .allPrivileges().exceptUserMode().writes(0);
2638    InitReg(MISCREG_ID_ISAR1)
2639      .allPrivileges().exceptUserMode().writes(0);
2640    InitReg(MISCREG_ID_ISAR2)
2641      .allPrivileges().exceptUserMode().writes(0);
2642    InitReg(MISCREG_ID_ISAR3)
2643      .allPrivileges().exceptUserMode().writes(0);
2644    InitReg(MISCREG_ID_ISAR4)
2645      .allPrivileges().exceptUserMode().writes(0);
2646    InitReg(MISCREG_ID_ISAR5)
2647      .allPrivileges().exceptUserMode().writes(0);
2648    InitReg(MISCREG_CCSIDR)
2649      .allPrivileges().exceptUserMode().writes(0);
2650    InitReg(MISCREG_CLIDR)
2651      .allPrivileges().exceptUserMode().writes(0);
2652    InitReg(MISCREG_AIDR)
2653      .allPrivileges().exceptUserMode().writes(0);
2654    InitReg(MISCREG_CSSELR)
2655      .banked();
2656    InitReg(MISCREG_CSSELR_NS)
2657      .bankedChild()
2658      .nonSecure().exceptUserMode();
2659    InitReg(MISCREG_CSSELR_S)
2660      .bankedChild()
2661      .secure().exceptUserMode();
2662    InitReg(MISCREG_VPIDR)
2663      .hyp().monNonSecure();
2664    InitReg(MISCREG_VMPIDR)
2665      .hyp().monNonSecure();
2666    InitReg(MISCREG_SCTLR)
2667      .banked();
2668    InitReg(MISCREG_SCTLR_NS)
2669      .bankedChild()
2670      .nonSecure().exceptUserMode();
2671    InitReg(MISCREG_SCTLR_S)
2672      .bankedChild()
2673      .secure().exceptUserMode();
2674    InitReg(MISCREG_ACTLR)
2675      .banked();
2676    InitReg(MISCREG_ACTLR_NS)
2677      .bankedChild()
2678      .nonSecure().exceptUserMode();
2679    InitReg(MISCREG_ACTLR_S)
2680      .bankedChild()
2681      .secure().exceptUserMode();
2682    InitReg(MISCREG_CPACR)
2683      .allPrivileges().exceptUserMode();
2684    InitReg(MISCREG_SCR)
2685      .mon().secure().exceptUserMode()
2686      .res0(0xff40)  // [31:16], [6]
2687      .res1(0x0030); // [5:4]
2688    InitReg(MISCREG_SDER)
2689      .mon();
2690    InitReg(MISCREG_NSACR)
2691      .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2692    InitReg(MISCREG_HSCTLR)
2693      .hyp().monNonSecure();
2694    InitReg(MISCREG_HACTLR)
2695      .hyp().monNonSecure();
2696    InitReg(MISCREG_HCR)
2697      .hyp().monNonSecure();
2698    InitReg(MISCREG_HDCR)
2699      .hyp().monNonSecure();
2700    InitReg(MISCREG_HCPTR)
2701      .hyp().monNonSecure();
2702    InitReg(MISCREG_HSTR)
2703      .hyp().monNonSecure();
2704    InitReg(MISCREG_HACR)
2705      .unimplemented()
2706      .warnNotFail()
2707      .hyp().monNonSecure();
2708    InitReg(MISCREG_TTBR0)
2709      .banked();
2710    InitReg(MISCREG_TTBR0_NS)
2711      .bankedChild()
2712      .nonSecure().exceptUserMode();
2713    InitReg(MISCREG_TTBR0_S)
2714      .bankedChild()
2715      .secure().exceptUserMode();
2716    InitReg(MISCREG_TTBR1)
2717      .banked();
2718    InitReg(MISCREG_TTBR1_NS)
2719      .bankedChild()
2720      .nonSecure().exceptUserMode();
2721    InitReg(MISCREG_TTBR1_S)
2722      .bankedChild()
2723      .secure().exceptUserMode();
2724    InitReg(MISCREG_TTBCR)
2725      .banked();
2726    InitReg(MISCREG_TTBCR_NS)
2727      .bankedChild()
2728      .nonSecure().exceptUserMode();
2729    InitReg(MISCREG_TTBCR_S)
2730      .bankedChild()
2731      .secure().exceptUserMode();
2732    InitReg(MISCREG_HTCR)
2733      .hyp().monNonSecure();
2734    InitReg(MISCREG_VTCR)
2735      .hyp().monNonSecure();
2736    InitReg(MISCREG_DACR)
2737      .banked();
2738    InitReg(MISCREG_DACR_NS)
2739      .bankedChild()
2740      .nonSecure().exceptUserMode();
2741    InitReg(MISCREG_DACR_S)
2742      .bankedChild()
2743      .secure().exceptUserMode();
2744    InitReg(MISCREG_DFSR)
2745      .banked();
2746    InitReg(MISCREG_DFSR_NS)
2747      .bankedChild()
2748      .nonSecure().exceptUserMode();
2749    InitReg(MISCREG_DFSR_S)
2750      .bankedChild()
2751      .secure().exceptUserMode();
2752    InitReg(MISCREG_IFSR)
2753      .banked();
2754    InitReg(MISCREG_IFSR_NS)
2755      .bankedChild()
2756      .nonSecure().exceptUserMode();
2757    InitReg(MISCREG_IFSR_S)
2758      .bankedChild()
2759      .secure().exceptUserMode();
2760    InitReg(MISCREG_ADFSR)
2761      .unimplemented()
2762      .warnNotFail()
2763      .banked();
2764    InitReg(MISCREG_ADFSR_NS)
2765      .unimplemented()
2766      .warnNotFail()
2767      .bankedChild()
2768      .nonSecure().exceptUserMode();
2769    InitReg(MISCREG_ADFSR_S)
2770      .unimplemented()
2771      .warnNotFail()
2772      .bankedChild()
2773      .secure().exceptUserMode();
2774    InitReg(MISCREG_AIFSR)
2775      .unimplemented()
2776      .warnNotFail()
2777      .banked();
2778    InitReg(MISCREG_AIFSR_NS)
2779      .unimplemented()
2780      .warnNotFail()
2781      .bankedChild()
2782      .nonSecure().exceptUserMode();
2783    InitReg(MISCREG_AIFSR_S)
2784      .unimplemented()
2785      .warnNotFail()
2786      .bankedChild()
2787      .secure().exceptUserMode();
2788    InitReg(MISCREG_HADFSR)
2789      .hyp().monNonSecure();
2790    InitReg(MISCREG_HAIFSR)
2791      .hyp().monNonSecure();
2792    InitReg(MISCREG_HSR)
2793      .hyp().monNonSecure();
2794    InitReg(MISCREG_DFAR)
2795      .banked();
2796    InitReg(MISCREG_DFAR_NS)
2797      .bankedChild()
2798      .nonSecure().exceptUserMode();
2799    InitReg(MISCREG_DFAR_S)
2800      .bankedChild()
2801      .secure().exceptUserMode();
2802    InitReg(MISCREG_IFAR)
2803      .banked();
2804    InitReg(MISCREG_IFAR_NS)
2805      .bankedChild()
2806      .nonSecure().exceptUserMode();
2807    InitReg(MISCREG_IFAR_S)
2808      .bankedChild()
2809      .secure().exceptUserMode();
2810    InitReg(MISCREG_HDFAR)
2811      .hyp().monNonSecure();
2812    InitReg(MISCREG_HIFAR)
2813      .hyp().monNonSecure();
2814    InitReg(MISCREG_HPFAR)
2815      .hyp().monNonSecure();
2816    InitReg(MISCREG_ICIALLUIS)
2817      .unimplemented()
2818      .warnNotFail()
2819      .writes(1).exceptUserMode();
2820    InitReg(MISCREG_BPIALLIS)
2821      .unimplemented()
2822      .warnNotFail()
2823      .writes(1).exceptUserMode();
2824    InitReg(MISCREG_PAR)
2825      .banked();
2826    InitReg(MISCREG_PAR_NS)
2827      .bankedChild()
2828      .nonSecure().exceptUserMode();
2829    InitReg(MISCREG_PAR_S)
2830      .bankedChild()
2831      .secure().exceptUserMode();
2832    InitReg(MISCREG_ICIALLU)
2833      .writes(1).exceptUserMode();
2834    InitReg(MISCREG_ICIMVAU)
2835      .unimplemented()
2836      .warnNotFail()
2837      .writes(1).exceptUserMode();
2838    InitReg(MISCREG_CP15ISB)
2839      .writes(1);
2840    InitReg(MISCREG_BPIALL)
2841      .unimplemented()
2842      .warnNotFail()
2843      .writes(1).exceptUserMode();
2844    InitReg(MISCREG_BPIMVA)
2845      .unimplemented()
2846      .warnNotFail()
2847      .writes(1).exceptUserMode();
2848    InitReg(MISCREG_DCIMVAC)
2849      .unimplemented()
2850      .warnNotFail()
2851      .writes(1).exceptUserMode();
2852    InitReg(MISCREG_DCISW)
2853      .unimplemented()
2854      .warnNotFail()
2855      .writes(1).exceptUserMode();
2856    InitReg(MISCREG_ATS1CPR)
2857      .writes(1).exceptUserMode();
2858    InitReg(MISCREG_ATS1CPW)
2859      .writes(1).exceptUserMode();
2860    InitReg(MISCREG_ATS1CUR)
2861      .writes(1).exceptUserMode();
2862    InitReg(MISCREG_ATS1CUW)
2863      .writes(1).exceptUserMode();
2864    InitReg(MISCREG_ATS12NSOPR)
2865      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2866    InitReg(MISCREG_ATS12NSOPW)
2867      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2868    InitReg(MISCREG_ATS12NSOUR)
2869      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2870    InitReg(MISCREG_ATS12NSOUW)
2871      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2872    InitReg(MISCREG_DCCMVAC)
2873      .writes(1).exceptUserMode();
2874    InitReg(MISCREG_DCCSW)
2875      .unimplemented()
2876      .warnNotFail()
2877      .writes(1).exceptUserMode();
2878    InitReg(MISCREG_CP15DSB)
2879      .writes(1);
2880    InitReg(MISCREG_CP15DMB)
2881      .writes(1);
2882    InitReg(MISCREG_DCCMVAU)
2883      .unimplemented()
2884      .warnNotFail()
2885      .writes(1).exceptUserMode();
2886    InitReg(MISCREG_DCCIMVAC)
2887      .unimplemented()
2888      .warnNotFail()
2889      .writes(1).exceptUserMode();
2890    InitReg(MISCREG_DCCISW)
2891      .unimplemented()
2892      .warnNotFail()
2893      .writes(1).exceptUserMode();
2894    InitReg(MISCREG_ATS1HR)
2895      .monNonSecureWrite().hypWrite();
2896    InitReg(MISCREG_ATS1HW)
2897      .monNonSecureWrite().hypWrite();
2898    InitReg(MISCREG_TLBIALLIS)
2899      .writes(1).exceptUserMode();
2900    InitReg(MISCREG_TLBIMVAIS)
2901      .writes(1).exceptUserMode();
2902    InitReg(MISCREG_TLBIASIDIS)
2903      .writes(1).exceptUserMode();
2904    InitReg(MISCREG_TLBIMVAAIS)
2905      .writes(1).exceptUserMode();
2906    InitReg(MISCREG_TLBIMVALIS)
2907      .writes(1).exceptUserMode();
2908    InitReg(MISCREG_TLBIMVAALIS)
2909      .writes(1).exceptUserMode();
2910    InitReg(MISCREG_ITLBIALL)
2911      .writes(1).exceptUserMode();
2912    InitReg(MISCREG_ITLBIMVA)
2913      .writes(1).exceptUserMode();
2914    InitReg(MISCREG_ITLBIASID)
2915      .writes(1).exceptUserMode();
2916    InitReg(MISCREG_DTLBIALL)
2917      .writes(1).exceptUserMode();
2918    InitReg(MISCREG_DTLBIMVA)
2919      .writes(1).exceptUserMode();
2920    InitReg(MISCREG_DTLBIASID)
2921      .writes(1).exceptUserMode();
2922    InitReg(MISCREG_TLBIALL)
2923      .writes(1).exceptUserMode();
2924    InitReg(MISCREG_TLBIMVA)
2925      .writes(1).exceptUserMode();
2926    InitReg(MISCREG_TLBIASID)
2927      .writes(1).exceptUserMode();
2928    InitReg(MISCREG_TLBIMVAA)
2929      .writes(1).exceptUserMode();
2930    InitReg(MISCREG_TLBIMVAL)
2931      .writes(1).exceptUserMode();
2932    InitReg(MISCREG_TLBIMVAAL)
2933      .writes(1).exceptUserMode();
2934    InitReg(MISCREG_TLBIIPAS2IS)
2935      .unimplemented()
2936      .monNonSecureWrite().hypWrite();
2937    InitReg(MISCREG_TLBIIPAS2LIS)
2938      .unimplemented()
2939      .monNonSecureWrite().hypWrite();
2940    InitReg(MISCREG_TLBIALLHIS)
2941      .monNonSecureWrite().hypWrite();
2942    InitReg(MISCREG_TLBIMVAHIS)
2943      .monNonSecureWrite().hypWrite();
2944    InitReg(MISCREG_TLBIALLNSNHIS)
2945      .monNonSecureWrite().hypWrite();
2946    InitReg(MISCREG_TLBIMVALHIS)
2947      .monNonSecureWrite().hypWrite();
2948    InitReg(MISCREG_TLBIIPAS2)
2949      .unimplemented()
2950      .monNonSecureWrite().hypWrite();
2951    InitReg(MISCREG_TLBIIPAS2L)
2952      .unimplemented()
2953      .monNonSecureWrite().hypWrite();
2954    InitReg(MISCREG_TLBIALLH)
2955      .monNonSecureWrite().hypWrite();
2956    InitReg(MISCREG_TLBIMVAH)
2957      .monNonSecureWrite().hypWrite();
2958    InitReg(MISCREG_TLBIALLNSNH)
2959      .monNonSecureWrite().hypWrite();
2960    InitReg(MISCREG_TLBIMVALH)
2961      .monNonSecureWrite().hypWrite();
2962    InitReg(MISCREG_PMCR)
2963      .allPrivileges();
2964    InitReg(MISCREG_PMCNTENSET)
2965      .allPrivileges();
2966    InitReg(MISCREG_PMCNTENCLR)
2967      .allPrivileges();
2968    InitReg(MISCREG_PMOVSR)
2969      .allPrivileges();
2970    InitReg(MISCREG_PMSWINC)
2971      .allPrivileges();
2972    InitReg(MISCREG_PMSELR)
2973      .allPrivileges();
2974    InitReg(MISCREG_PMCEID0)
2975      .allPrivileges();
2976    InitReg(MISCREG_PMCEID1)
2977      .allPrivileges();
2978    InitReg(MISCREG_PMCCNTR)
2979      .allPrivileges();
2980    InitReg(MISCREG_PMXEVTYPER)
2981      .allPrivileges();
2982    InitReg(MISCREG_PMCCFILTR)
2983      .allPrivileges();
2984    InitReg(MISCREG_PMXEVCNTR)
2985      .allPrivileges();
2986    InitReg(MISCREG_PMUSERENR)
2987      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
2988    InitReg(MISCREG_PMINTENSET)
2989      .allPrivileges().exceptUserMode();
2990    InitReg(MISCREG_PMINTENCLR)
2991      .allPrivileges().exceptUserMode();
2992    InitReg(MISCREG_PMOVSSET)
2993      .unimplemented()
2994      .allPrivileges();
2995    InitReg(MISCREG_L2CTLR)
2996      .allPrivileges().exceptUserMode();
2997    InitReg(MISCREG_L2ECTLR)
2998      .unimplemented()
2999      .allPrivileges().exceptUserMode();
3000    InitReg(MISCREG_PRRR)
3001      .banked();
3002    InitReg(MISCREG_PRRR_NS)
3003      .bankedChild()
3004      .nonSecure().exceptUserMode();
3005    InitReg(MISCREG_PRRR_S)
3006      .bankedChild()
3007      .secure().exceptUserMode();
3008    InitReg(MISCREG_MAIR0)
3009      .banked();
3010    InitReg(MISCREG_MAIR0_NS)
3011      .bankedChild()
3012      .nonSecure().exceptUserMode();
3013    InitReg(MISCREG_MAIR0_S)
3014      .bankedChild()
3015      .secure().exceptUserMode();
3016    InitReg(MISCREG_NMRR)
3017      .banked();
3018    InitReg(MISCREG_NMRR_NS)
3019      .bankedChild()
3020      .nonSecure().exceptUserMode();
3021    InitReg(MISCREG_NMRR_S)
3022      .bankedChild()
3023      .secure().exceptUserMode();
3024    InitReg(MISCREG_MAIR1)
3025      .banked();
3026    InitReg(MISCREG_MAIR1_NS)
3027      .bankedChild()
3028      .nonSecure().exceptUserMode();
3029    InitReg(MISCREG_MAIR1_S)
3030      .bankedChild()
3031      .secure().exceptUserMode();
3032    InitReg(MISCREG_AMAIR0)
3033      .banked();
3034    InitReg(MISCREG_AMAIR0_NS)
3035      .bankedChild()
3036      .nonSecure().exceptUserMode();
3037    InitReg(MISCREG_AMAIR0_S)
3038      .bankedChild()
3039      .secure().exceptUserMode();
3040    InitReg(MISCREG_AMAIR1)
3041      .banked();
3042    InitReg(MISCREG_AMAIR1_NS)
3043      .bankedChild()
3044      .nonSecure().exceptUserMode();
3045    InitReg(MISCREG_AMAIR1_S)
3046      .bankedChild()
3047      .secure().exceptUserMode();
3048    InitReg(MISCREG_HMAIR0)
3049      .hyp().monNonSecure();
3050    InitReg(MISCREG_HMAIR1)
3051      .hyp().monNonSecure();
3052    InitReg(MISCREG_HAMAIR0)
3053      .unimplemented()
3054      .warnNotFail()
3055      .hyp().monNonSecure();
3056    InitReg(MISCREG_HAMAIR1)
3057      .unimplemented()
3058      .warnNotFail()
3059      .hyp().monNonSecure();
3060    InitReg(MISCREG_VBAR)
3061      .banked();
3062    InitReg(MISCREG_VBAR_NS)
3063      .bankedChild()
3064      .nonSecure().exceptUserMode();
3065    InitReg(MISCREG_VBAR_S)
3066      .bankedChild()
3067      .secure().exceptUserMode();
3068    InitReg(MISCREG_MVBAR)
3069      .mon().secure().exceptUserMode();
3070    InitReg(MISCREG_RMR)
3071      .unimplemented()
3072      .mon().secure().exceptUserMode();
3073    InitReg(MISCREG_ISR)
3074      .allPrivileges().exceptUserMode().writes(0);
3075    InitReg(MISCREG_HVBAR)
3076      .hyp().monNonSecure();
3077    InitReg(MISCREG_FCSEIDR)
3078      .unimplemented()
3079      .warnNotFail()
3080      .allPrivileges().exceptUserMode();
3081    InitReg(MISCREG_CONTEXTIDR)
3082      .banked();
3083    InitReg(MISCREG_CONTEXTIDR_NS)
3084      .bankedChild()
3085      .nonSecure().exceptUserMode();
3086    InitReg(MISCREG_CONTEXTIDR_S)
3087      .bankedChild()
3088      .secure().exceptUserMode();
3089    InitReg(MISCREG_TPIDRURW)
3090      .banked();
3091    InitReg(MISCREG_TPIDRURW_NS)
3092      .bankedChild()
3093      .allPrivileges().monSecure(0).privSecure(0);
3094    InitReg(MISCREG_TPIDRURW_S)
3095      .bankedChild()
3096      .secure();
3097    InitReg(MISCREG_TPIDRURO)
3098      .banked();
3099    InitReg(MISCREG_TPIDRURO_NS)
3100      .bankedChild()
3101      .allPrivileges().secure(0).userNonSecureWrite(0).userSecureRead(1);
3102    InitReg(MISCREG_TPIDRURO_S)
3103      .bankedChild()
3104      .secure().userSecureWrite(0);
3105    InitReg(MISCREG_TPIDRPRW)
3106      .banked();
3107    InitReg(MISCREG_TPIDRPRW_NS)
3108      .bankedChild()
3109      .nonSecure().exceptUserMode();
3110    InitReg(MISCREG_TPIDRPRW_S)
3111      .bankedChild()
3112      .secure().exceptUserMode();
3113    InitReg(MISCREG_HTPIDR)
3114      .hyp().monNonSecure();
3115    InitReg(MISCREG_CNTFRQ)
3116      .unverifiable()
3117      .reads(1).mon();
3118    InitReg(MISCREG_CNTKCTL)
3119      .allPrivileges().exceptUserMode();
3120    InitReg(MISCREG_CNTP_TVAL)
3121      .banked();
3122    InitReg(MISCREG_CNTP_TVAL_NS)
3123      .bankedChild()
3124      .allPrivileges().monSecure(0).privSecure(0);
3125    InitReg(MISCREG_CNTP_TVAL_S)
3126      .unimplemented()
3127      .bankedChild()
3128      .secure().user(1);
3129    InitReg(MISCREG_CNTP_CTL)
3130      .banked();
3131    InitReg(MISCREG_CNTP_CTL_NS)
3132      .bankedChild()
3133      .allPrivileges().monSecure(0).privSecure(0);
3134    InitReg(MISCREG_CNTP_CTL_S)
3135      .unimplemented()
3136      .bankedChild()
3137      .secure().user(1);
3138    InitReg(MISCREG_CNTV_TVAL)
3139      .allPrivileges();
3140    InitReg(MISCREG_CNTV_CTL)
3141      .allPrivileges();
3142    InitReg(MISCREG_CNTHCTL)
3143      .unimplemented()
3144      .hypWrite().monNonSecureRead();
3145    InitReg(MISCREG_CNTHP_TVAL)
3146      .unimplemented()
3147      .hypWrite().monNonSecureRead();
3148    InitReg(MISCREG_CNTHP_CTL)
3149      .unimplemented()
3150      .hypWrite().monNonSecureRead();
3151    InitReg(MISCREG_IL1DATA0)
3152      .unimplemented()
3153      .allPrivileges().exceptUserMode();
3154    InitReg(MISCREG_IL1DATA1)
3155      .unimplemented()
3156      .allPrivileges().exceptUserMode();
3157    InitReg(MISCREG_IL1DATA2)
3158      .unimplemented()
3159      .allPrivileges().exceptUserMode();
3160    InitReg(MISCREG_IL1DATA3)
3161      .unimplemented()
3162      .allPrivileges().exceptUserMode();
3163    InitReg(MISCREG_DL1DATA0)
3164      .unimplemented()
3165      .allPrivileges().exceptUserMode();
3166    InitReg(MISCREG_DL1DATA1)
3167      .unimplemented()
3168      .allPrivileges().exceptUserMode();
3169    InitReg(MISCREG_DL1DATA2)
3170      .unimplemented()
3171      .allPrivileges().exceptUserMode();
3172    InitReg(MISCREG_DL1DATA3)
3173      .unimplemented()
3174      .allPrivileges().exceptUserMode();
3175    InitReg(MISCREG_DL1DATA4)
3176      .unimplemented()
3177      .allPrivileges().exceptUserMode();
3178    InitReg(MISCREG_RAMINDEX)
3179      .unimplemented()
3180      .writes(1).exceptUserMode();
3181    InitReg(MISCREG_L2ACTLR)
3182      .unimplemented()
3183      .allPrivileges().exceptUserMode();
3184    InitReg(MISCREG_CBAR)
3185      .unimplemented()
3186      .allPrivileges().exceptUserMode().writes(0);
3187    InitReg(MISCREG_HTTBR)
3188      .hyp().monNonSecure();
3189    InitReg(MISCREG_VTTBR)
3190      .hyp().monNonSecure();
3191    InitReg(MISCREG_CNTPCT)
3192      .reads(1);
3193    InitReg(MISCREG_CNTVCT)
3194      .unverifiable()
3195      .reads(1);
3196    InitReg(MISCREG_CNTP_CVAL)
3197      .banked();
3198    InitReg(MISCREG_CNTP_CVAL_NS)
3199      .bankedChild()
3200      .allPrivileges().monSecure(0).privSecure(0);
3201    InitReg(MISCREG_CNTP_CVAL_S)
3202      .unimplemented()
3203      .bankedChild()
3204      .secure().user(1);
3205    InitReg(MISCREG_CNTV_CVAL)
3206      .allPrivileges();
3207    InitReg(MISCREG_CNTVOFF)
3208      .hyp().monNonSecure();
3209    InitReg(MISCREG_CNTHP_CVAL)
3210      .unimplemented()
3211      .hypWrite().monNonSecureRead();
3212    InitReg(MISCREG_CPUMERRSR)
3213      .unimplemented()
3214      .allPrivileges().exceptUserMode();
3215    InitReg(MISCREG_L2MERRSR)
3216      .unimplemented()
3217      .warnNotFail()
3218      .allPrivileges().exceptUserMode();
3219
3220    // AArch64 registers (Op0=2);
3221    InitReg(MISCREG_MDCCINT_EL1)
3222      .allPrivileges();
3223    InitReg(MISCREG_OSDTRRX_EL1)
3224      .allPrivileges()
3225      .mapsTo(MISCREG_DBGDTRRXext);
3226    InitReg(MISCREG_MDSCR_EL1)
3227      .allPrivileges()
3228      .mapsTo(MISCREG_DBGDSCRext);
3229    InitReg(MISCREG_OSDTRTX_EL1)
3230      .allPrivileges()
3231      .mapsTo(MISCREG_DBGDTRTXext);
3232    InitReg(MISCREG_OSECCR_EL1)
3233      .allPrivileges()
3234      .mapsTo(MISCREG_DBGOSECCR);
3235    InitReg(MISCREG_DBGBVR0_EL1)
3236      .allPrivileges()
3237      .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3238    InitReg(MISCREG_DBGBVR1_EL1)
3239      .allPrivileges()
3240      .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3241    InitReg(MISCREG_DBGBVR2_EL1)
3242      .allPrivileges()
3243      .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3244    InitReg(MISCREG_DBGBVR3_EL1)
3245      .allPrivileges()
3246      .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3247    InitReg(MISCREG_DBGBVR4_EL1)
3248      .allPrivileges()
3249      .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3250    InitReg(MISCREG_DBGBVR5_EL1)
3251      .allPrivileges()
3252      .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3253    InitReg(MISCREG_DBGBCR0_EL1)
3254      .allPrivileges()
3255      .mapsTo(MISCREG_DBGBCR0);
3256    InitReg(MISCREG_DBGBCR1_EL1)
3257      .allPrivileges()
3258      .mapsTo(MISCREG_DBGBCR1);
3259    InitReg(MISCREG_DBGBCR2_EL1)
3260      .allPrivileges()
3261      .mapsTo(MISCREG_DBGBCR2);
3262    InitReg(MISCREG_DBGBCR3_EL1)
3263      .allPrivileges()
3264      .mapsTo(MISCREG_DBGBCR3);
3265    InitReg(MISCREG_DBGBCR4_EL1)
3266      .allPrivileges()
3267      .mapsTo(MISCREG_DBGBCR4);
3268    InitReg(MISCREG_DBGBCR5_EL1)
3269      .allPrivileges()
3270      .mapsTo(MISCREG_DBGBCR5);
3271    InitReg(MISCREG_DBGWVR0_EL1)
3272      .allPrivileges()
3273      .mapsTo(MISCREG_DBGWVR0);
3274    InitReg(MISCREG_DBGWVR1_EL1)
3275      .allPrivileges()
3276      .mapsTo(MISCREG_DBGWVR1);
3277    InitReg(MISCREG_DBGWVR2_EL1)
3278      .allPrivileges()
3279      .mapsTo(MISCREG_DBGWVR2);
3280    InitReg(MISCREG_DBGWVR3_EL1)
3281      .allPrivileges()
3282      .mapsTo(MISCREG_DBGWVR3);
3283    InitReg(MISCREG_DBGWCR0_EL1)
3284      .allPrivileges()
3285      .mapsTo(MISCREG_DBGWCR0);
3286    InitReg(MISCREG_DBGWCR1_EL1)
3287      .allPrivileges()
3288      .mapsTo(MISCREG_DBGWCR1);
3289    InitReg(MISCREG_DBGWCR2_EL1)
3290      .allPrivileges()
3291      .mapsTo(MISCREG_DBGWCR2);
3292    InitReg(MISCREG_DBGWCR3_EL1)
3293      .allPrivileges()
3294      .mapsTo(MISCREG_DBGWCR3);
3295    InitReg(MISCREG_MDCCSR_EL0)
3296      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3297      .mapsTo(MISCREG_DBGDSCRint);
3298    InitReg(MISCREG_MDDTR_EL0)
3299      .allPrivileges();
3300    InitReg(MISCREG_MDDTRTX_EL0)
3301      .allPrivileges();
3302    InitReg(MISCREG_MDDTRRX_EL0)
3303      .allPrivileges();
3304    InitReg(MISCREG_DBGVCR32_EL2)
3305      .allPrivileges()
3306      .mapsTo(MISCREG_DBGVCR);
3307    InitReg(MISCREG_MDRAR_EL1)
3308      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3309      .mapsTo(MISCREG_DBGDRAR);
3310    InitReg(MISCREG_OSLAR_EL1)
3311      .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3312      .mapsTo(MISCREG_DBGOSLAR);
3313    InitReg(MISCREG_OSLSR_EL1)
3314      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3315      .mapsTo(MISCREG_DBGOSLSR);
3316    InitReg(MISCREG_OSDLR_EL1)
3317      .allPrivileges()
3318      .mapsTo(MISCREG_DBGOSDLR);
3319    InitReg(MISCREG_DBGPRCR_EL1)
3320      .allPrivileges()
3321      .mapsTo(MISCREG_DBGPRCR);
3322    InitReg(MISCREG_DBGCLAIMSET_EL1)
3323      .allPrivileges()
3324      .mapsTo(MISCREG_DBGCLAIMSET);
3325    InitReg(MISCREG_DBGCLAIMCLR_EL1)
3326      .allPrivileges()
3327      .mapsTo(MISCREG_DBGCLAIMCLR);
3328    InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3329      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3330      .mapsTo(MISCREG_DBGAUTHSTATUS);
3331    InitReg(MISCREG_TEECR32_EL1);
3332    InitReg(MISCREG_TEEHBR32_EL1);
3333
3334    // AArch64 registers (Op0=1,3);
3335    InitReg(MISCREG_MIDR_EL1)
3336      .allPrivileges().exceptUserMode().writes(0);
3337    InitReg(MISCREG_MPIDR_EL1)
3338      .allPrivileges().exceptUserMode().writes(0);
3339    InitReg(MISCREG_REVIDR_EL1)
3340      .allPrivileges().exceptUserMode().writes(0);
3341    InitReg(MISCREG_ID_PFR0_EL1)
3342      .allPrivileges().exceptUserMode().writes(0);
3343    InitReg(MISCREG_ID_PFR1_EL1)
3344      .allPrivileges().exceptUserMode().writes(0);
3345    InitReg(MISCREG_ID_DFR0_EL1)
3346      .allPrivileges().exceptUserMode().writes(0)
3347      .mapsTo(MISCREG_ID_DFR0);
3348    InitReg(MISCREG_ID_AFR0_EL1)
3349      .allPrivileges().exceptUserMode().writes(0);
3350    InitReg(MISCREG_ID_MMFR0_EL1)
3351      .allPrivileges().exceptUserMode().writes(0);
3352    InitReg(MISCREG_ID_MMFR1_EL1)
3353      .allPrivileges().exceptUserMode().writes(0);
3354    InitReg(MISCREG_ID_MMFR2_EL1)
3355      .allPrivileges().exceptUserMode().writes(0);
3356    InitReg(MISCREG_ID_MMFR3_EL1)
3357      .allPrivileges().exceptUserMode().writes(0);
3358    InitReg(MISCREG_ID_ISAR0_EL1)
3359      .allPrivileges().exceptUserMode().writes(0);
3360    InitReg(MISCREG_ID_ISAR1_EL1)
3361      .allPrivileges().exceptUserMode().writes(0);
3362    InitReg(MISCREG_ID_ISAR2_EL1)
3363      .allPrivileges().exceptUserMode().writes(0);
3364    InitReg(MISCREG_ID_ISAR3_EL1)
3365      .allPrivileges().exceptUserMode().writes(0);
3366    InitReg(MISCREG_ID_ISAR4_EL1)
3367      .allPrivileges().exceptUserMode().writes(0);
3368    InitReg(MISCREG_ID_ISAR5_EL1)
3369      .allPrivileges().exceptUserMode().writes(0);
3370    InitReg(MISCREG_MVFR0_EL1)
3371      .allPrivileges().exceptUserMode().writes(0);
3372    InitReg(MISCREG_MVFR1_EL1)
3373      .allPrivileges().exceptUserMode().writes(0);
3374    InitReg(MISCREG_MVFR2_EL1)
3375      .allPrivileges().exceptUserMode().writes(0);
3376    InitReg(MISCREG_ID_AA64PFR0_EL1)
3377      .allPrivileges().exceptUserMode().writes(0);
3378    InitReg(MISCREG_ID_AA64PFR1_EL1)
3379      .allPrivileges().exceptUserMode().writes(0);
3380    InitReg(MISCREG_ID_AA64DFR0_EL1)
3381      .allPrivileges().exceptUserMode().writes(0);
3382    InitReg(MISCREG_ID_AA64DFR1_EL1)
3383      .allPrivileges().exceptUserMode().writes(0);
3384    InitReg(MISCREG_ID_AA64AFR0_EL1)
3385      .allPrivileges().exceptUserMode().writes(0);
3386    InitReg(MISCREG_ID_AA64AFR1_EL1)
3387      .allPrivileges().exceptUserMode().writes(0);
3388    InitReg(MISCREG_ID_AA64ISAR0_EL1)
3389      .allPrivileges().exceptUserMode().writes(0);
3390    InitReg(MISCREG_ID_AA64ISAR1_EL1)
3391      .allPrivileges().exceptUserMode().writes(0);
3392    InitReg(MISCREG_ID_AA64MMFR0_EL1)
3393      .allPrivileges().exceptUserMode().writes(0);
3394    InitReg(MISCREG_ID_AA64MMFR1_EL1)
3395      .allPrivileges().exceptUserMode().writes(0);
3396    InitReg(MISCREG_CCSIDR_EL1)
3397      .allPrivileges().exceptUserMode().writes(0);
3398    InitReg(MISCREG_CLIDR_EL1)
3399      .allPrivileges().exceptUserMode().writes(0);
3400    InitReg(MISCREG_AIDR_EL1)
3401      .allPrivileges().exceptUserMode().writes(0);
3402    InitReg(MISCREG_CSSELR_EL1)
3403      .allPrivileges().exceptUserMode()
3404      .mapsTo(MISCREG_CSSELR_NS);
3405    InitReg(MISCREG_CTR_EL0)
3406      .reads(1);
3407    InitReg(MISCREG_DCZID_EL0)
3408      .reads(1);
3409    InitReg(MISCREG_VPIDR_EL2)
3410      .hyp().mon()
3411      .mapsTo(MISCREG_VPIDR);
3412    InitReg(MISCREG_VMPIDR_EL2)
3413      .hyp().mon()
3414      .mapsTo(MISCREG_VMPIDR);
3415    InitReg(MISCREG_SCTLR_EL1)
3416      .allPrivileges().exceptUserMode()
3417      .mapsTo(MISCREG_SCTLR_NS);
3418    InitReg(MISCREG_ACTLR_EL1)
3419      .allPrivileges().exceptUserMode()
3420      .mapsTo(MISCREG_ACTLR_NS);
3421    InitReg(MISCREG_CPACR_EL1)
3422      .allPrivileges().exceptUserMode()
3423      .mapsTo(MISCREG_CPACR);
3424    InitReg(MISCREG_SCTLR_EL2)
3425      .hyp().mon()
3426      .mapsTo(MISCREG_HSCTLR);
3427    InitReg(MISCREG_ACTLR_EL2)
3428      .hyp().mon()
3429      .mapsTo(MISCREG_HACTLR);
3430    InitReg(MISCREG_HCR_EL2)
3431      .hyp().mon()
3432      .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3433    InitReg(MISCREG_MDCR_EL2)
3434      .hyp().mon()
3435      .mapsTo(MISCREG_HDCR);
3436    InitReg(MISCREG_CPTR_EL2)
3437      .hyp().mon()
3438      .mapsTo(MISCREG_HCPTR);
3439    InitReg(MISCREG_HSTR_EL2)
3440      .hyp().mon()
3441      .mapsTo(MISCREG_HSTR);
3442    InitReg(MISCREG_HACR_EL2)
3443      .hyp().mon()
3444      .mapsTo(MISCREG_HACR);
3445    InitReg(MISCREG_SCTLR_EL3)
3446      .mon();
3447    InitReg(MISCREG_ACTLR_EL3)
3448      .mon();
3449    InitReg(MISCREG_SCR_EL3)
3450      .mon()
3451      .mapsTo(MISCREG_SCR); // NAM D7-2005
3452    InitReg(MISCREG_SDER32_EL3)
3453      .mon()
3454      .mapsTo(MISCREG_SDER);
3455    InitReg(MISCREG_CPTR_EL3)
3456      .mon();
3457    InitReg(MISCREG_MDCR_EL3)
3458      .mon();
3459    InitReg(MISCREG_TTBR0_EL1)
3460      .allPrivileges().exceptUserMode()
3461      .mapsTo(MISCREG_TTBR0_NS);
3462    InitReg(MISCREG_TTBR1_EL1)
3463      .allPrivileges().exceptUserMode()
3464      .mapsTo(MISCREG_TTBR1_NS);
3465    InitReg(MISCREG_TCR_EL1)
3466      .allPrivileges().exceptUserMode()
3467      .mapsTo(MISCREG_TTBCR_NS);
3468    InitReg(MISCREG_TTBR0_EL2)
3469      .hyp().mon()
3470      .mapsTo(MISCREG_HTTBR);
3471    InitReg(MISCREG_TCR_EL2)
3472      .hyp().mon()
3473      .mapsTo(MISCREG_HTCR);
3474    InitReg(MISCREG_VTTBR_EL2)
3475      .hyp().mon()
3476      .mapsTo(MISCREG_VTTBR);
3477    InitReg(MISCREG_VTCR_EL2)
3478      .hyp().mon()
3479      .mapsTo(MISCREG_VTCR);
3480    InitReg(MISCREG_TTBR0_EL3)
3481      .mon();
3482    InitReg(MISCREG_TCR_EL3)
3483      .mon();
3484    InitReg(MISCREG_DACR32_EL2)
3485      .hyp().mon()
3486      .mapsTo(MISCREG_DACR_NS);
3487    InitReg(MISCREG_SPSR_EL1)
3488      .allPrivileges().exceptUserMode()
3489      .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3490    InitReg(MISCREG_ELR_EL1)
3491      .allPrivileges().exceptUserMode();
3492    InitReg(MISCREG_SP_EL0)
3493      .allPrivileges().exceptUserMode();
3494    InitReg(MISCREG_SPSEL)
3495      .allPrivileges().exceptUserMode();
3496    InitReg(MISCREG_CURRENTEL)
3497      .allPrivileges().exceptUserMode().writes(0);
3498    InitReg(MISCREG_NZCV)
3499      .allPrivileges();
3500    InitReg(MISCREG_DAIF)
3501      .allPrivileges();
3502    InitReg(MISCREG_FPCR)
3503      .allPrivileges();
3504    InitReg(MISCREG_FPSR)
3505      .allPrivileges();
3506    InitReg(MISCREG_DSPSR_EL0)
3507      .allPrivileges();
3508    InitReg(MISCREG_DLR_EL0)
3509      .allPrivileges();
3510    InitReg(MISCREG_SPSR_EL2)
3511      .hyp().mon()
3512      .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3513    InitReg(MISCREG_ELR_EL2)
3514      .hyp().mon();
3515    InitReg(MISCREG_SP_EL1)
3516      .hyp().mon();
3517    InitReg(MISCREG_SPSR_IRQ_AA64)
3518      .hyp().mon();
3519    InitReg(MISCREG_SPSR_ABT_AA64)
3520      .hyp().mon();
3521    InitReg(MISCREG_SPSR_UND_AA64)
3522      .hyp().mon();
3523    InitReg(MISCREG_SPSR_FIQ_AA64)
3524      .hyp().mon();
3525    InitReg(MISCREG_SPSR_EL3)
3526      .mon()
3527      .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3528    InitReg(MISCREG_ELR_EL3)
3529      .mon();
3530    InitReg(MISCREG_SP_EL2)
3531      .mon();
3532    InitReg(MISCREG_AFSR0_EL1)
3533      .allPrivileges().exceptUserMode()
3534      .mapsTo(MISCREG_ADFSR_NS);
3535    InitReg(MISCREG_AFSR1_EL1)
3536      .allPrivileges().exceptUserMode()
3537      .mapsTo(MISCREG_AIFSR_NS);
3538    InitReg(MISCREG_ESR_EL1)
3539      .allPrivileges().exceptUserMode();
3540    InitReg(MISCREG_IFSR32_EL2)
3541      .hyp().mon()
3542      .mapsTo(MISCREG_IFSR_NS);
3543    InitReg(MISCREG_AFSR0_EL2)
3544      .hyp().mon()
3545      .mapsTo(MISCREG_HADFSR);
3546    InitReg(MISCREG_AFSR1_EL2)
3547      .hyp().mon()
3548      .mapsTo(MISCREG_HAIFSR);
3549    InitReg(MISCREG_ESR_EL2)
3550      .hyp().mon()
3551      .mapsTo(MISCREG_HSR);
3552    InitReg(MISCREG_FPEXC32_EL2)
3553      .hyp().mon();
3554    InitReg(MISCREG_AFSR0_EL3)
3555      .mon();
3556    InitReg(MISCREG_AFSR1_EL3)
3557      .mon();
3558    InitReg(MISCREG_ESR_EL3)
3559      .mon();
3560    InitReg(MISCREG_FAR_EL1)
3561      .allPrivileges().exceptUserMode()
3562      .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3563    InitReg(MISCREG_FAR_EL2)
3564      .hyp().mon()
3565      .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3566    InitReg(MISCREG_HPFAR_EL2)
3567      .hyp().mon()
3568      .mapsTo(MISCREG_HPFAR);
3569    InitReg(MISCREG_FAR_EL3)
3570      .mon();
3571    InitReg(MISCREG_IC_IALLUIS)
3572      .warnNotFail()
3573      .writes(1).exceptUserMode();
3574    InitReg(MISCREG_PAR_EL1)
3575      .allPrivileges().exceptUserMode()
3576      .mapsTo(MISCREG_PAR_NS);
3577    InitReg(MISCREG_IC_IALLU)
3578      .warnNotFail()
3579      .writes(1).exceptUserMode();
3580    InitReg(MISCREG_DC_IVAC_Xt)
3581      .warnNotFail()
3582      .writes(1).exceptUserMode();
3583    InitReg(MISCREG_DC_ISW_Xt)
3584      .warnNotFail()
3585      .writes(1).exceptUserMode();
3586    InitReg(MISCREG_AT_S1E1R_Xt)
3587      .writes(1).exceptUserMode();
3588    InitReg(MISCREG_AT_S1E1W_Xt)
3589      .writes(1).exceptUserMode();
3590    InitReg(MISCREG_AT_S1E0R_Xt)
3591      .writes(1).exceptUserMode();
3592    InitReg(MISCREG_AT_S1E0W_Xt)
3593      .writes(1).exceptUserMode();
3594    InitReg(MISCREG_DC_CSW_Xt)
3595      .warnNotFail()
3596      .writes(1).exceptUserMode();
3597    InitReg(MISCREG_DC_CISW_Xt)
3598      .warnNotFail()
3599      .writes(1).exceptUserMode();
3600    InitReg(MISCREG_DC_ZVA_Xt)
3601      .warnNotFail()
3602      .writes(1).userSecureWrite(0);
3603    InitReg(MISCREG_IC_IVAU_Xt)
3604      .writes(1);
3605    InitReg(MISCREG_DC_CVAC_Xt)
3606      .warnNotFail()
3607      .writes(1);
3608    InitReg(MISCREG_DC_CVAU_Xt)
3609      .warnNotFail()
3610      .writes(1);
3611    InitReg(MISCREG_DC_CIVAC_Xt)
3612      .warnNotFail()
3613      .writes(1);
3614    InitReg(MISCREG_AT_S1E2R_Xt)
3615      .monNonSecureWrite().hypWrite();
3616    InitReg(MISCREG_AT_S1E2W_Xt)
3617      .monNonSecureWrite().hypWrite();
3618    InitReg(MISCREG_AT_S12E1R_Xt)
3619      .hypWrite().monSecureWrite().monNonSecureWrite();
3620    InitReg(MISCREG_AT_S12E1W_Xt)
3621      .hypWrite().monSecureWrite().monNonSecureWrite();
3622    InitReg(MISCREG_AT_S12E0R_Xt)
3623      .hypWrite().monSecureWrite().monNonSecureWrite();
3624    InitReg(MISCREG_AT_S12E0W_Xt)
3625      .hypWrite().monSecureWrite().monNonSecureWrite();
3626    InitReg(MISCREG_AT_S1E3R_Xt)
3627      .monSecureWrite().monNonSecureWrite();
3628    InitReg(MISCREG_AT_S1E3W_Xt)
3629      .monSecureWrite().monNonSecureWrite();
3630    InitReg(MISCREG_TLBI_VMALLE1IS)
3631      .writes(1).exceptUserMode();
3632    InitReg(MISCREG_TLBI_VAE1IS_Xt)
3633      .writes(1).exceptUserMode();
3634    InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3635      .writes(1).exceptUserMode();
3636    InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3637      .writes(1).exceptUserMode();
3638    InitReg(MISCREG_TLBI_VALE1IS_Xt)
3639      .writes(1).exceptUserMode();
3640    InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3641      .writes(1).exceptUserMode();
3642    InitReg(MISCREG_TLBI_VMALLE1)
3643      .writes(1).exceptUserMode();
3644    InitReg(MISCREG_TLBI_VAE1_Xt)
3645      .writes(1).exceptUserMode();
3646    InitReg(MISCREG_TLBI_ASIDE1_Xt)
3647      .writes(1).exceptUserMode();
3648    InitReg(MISCREG_TLBI_VAAE1_Xt)
3649      .writes(1).exceptUserMode();
3650    InitReg(MISCREG_TLBI_VALE1_Xt)
3651      .writes(1).exceptUserMode();
3652    InitReg(MISCREG_TLBI_VAALE1_Xt)
3653      .writes(1).exceptUserMode();
3654    InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3655      .hypWrite().monSecureWrite().monNonSecureWrite();
3656    InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3657      .hypWrite().monSecureWrite().monNonSecureWrite();
3658    InitReg(MISCREG_TLBI_ALLE2IS)
3659      .monNonSecureWrite().hypWrite();
3660    InitReg(MISCREG_TLBI_VAE2IS_Xt)
3661      .monNonSecureWrite().hypWrite();
3662    InitReg(MISCREG_TLBI_ALLE1IS)
3663      .hypWrite().monSecureWrite().monNonSecureWrite();
3664    InitReg(MISCREG_TLBI_VALE2IS_Xt)
3665      .monNonSecureWrite().hypWrite();
3666    InitReg(MISCREG_TLBI_VMALLS12E1IS)
3667      .hypWrite().monSecureWrite().monNonSecureWrite();
3668    InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3669      .hypWrite().monSecureWrite().monNonSecureWrite();
3670    InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3671      .hypWrite().monSecureWrite().monNonSecureWrite();
3672    InitReg(MISCREG_TLBI_ALLE2)
3673      .monNonSecureWrite().hypWrite();
3674    InitReg(MISCREG_TLBI_VAE2_Xt)
3675      .monNonSecureWrite().hypWrite();
3676    InitReg(MISCREG_TLBI_ALLE1)
3677      .hypWrite().monSecureWrite().monNonSecureWrite();
3678    InitReg(MISCREG_TLBI_VALE2_Xt)
3679      .monNonSecureWrite().hypWrite();
3680    InitReg(MISCREG_TLBI_VMALLS12E1)
3681      .hypWrite().monSecureWrite().monNonSecureWrite();
3682    InitReg(MISCREG_TLBI_ALLE3IS)
3683      .monSecureWrite().monNonSecureWrite();
3684    InitReg(MISCREG_TLBI_VAE3IS_Xt)
3685      .monSecureWrite().monNonSecureWrite();
3686    InitReg(MISCREG_TLBI_VALE3IS_Xt)
3687      .monSecureWrite().monNonSecureWrite();
3688    InitReg(MISCREG_TLBI_ALLE3)
3689      .monSecureWrite().monNonSecureWrite();
3690    InitReg(MISCREG_TLBI_VAE3_Xt)
3691      .monSecureWrite().monNonSecureWrite();
3692    InitReg(MISCREG_TLBI_VALE3_Xt)
3693      .monSecureWrite().monNonSecureWrite();
3694    InitReg(MISCREG_PMINTENSET_EL1)
3695      .allPrivileges().exceptUserMode()
3696      .mapsTo(MISCREG_PMINTENSET);
3697    InitReg(MISCREG_PMINTENCLR_EL1)
3698      .allPrivileges().exceptUserMode()
3699      .mapsTo(MISCREG_PMINTENCLR);
3700    InitReg(MISCREG_PMCR_EL0)
3701      .allPrivileges()
3702      .mapsTo(MISCREG_PMCR);
3703    InitReg(MISCREG_PMCNTENSET_EL0)
3704      .allPrivileges()
3705      .mapsTo(MISCREG_PMCNTENSET);
3706    InitReg(MISCREG_PMCNTENCLR_EL0)
3707      .allPrivileges()
3708      .mapsTo(MISCREG_PMCNTENCLR);
3709    InitReg(MISCREG_PMOVSCLR_EL0)
3710      .allPrivileges();
3711//    .mapsTo(MISCREG_PMOVSCLR);
3712    InitReg(MISCREG_PMSWINC_EL0)
3713      .writes(1).user()
3714      .mapsTo(MISCREG_PMSWINC);
3715    InitReg(MISCREG_PMSELR_EL0)
3716      .allPrivileges()
3717      .mapsTo(MISCREG_PMSELR);
3718    InitReg(MISCREG_PMCEID0_EL0)
3719      .reads(1).user()
3720      .mapsTo(MISCREG_PMCEID0);
3721    InitReg(MISCREG_PMCEID1_EL0)
3722      .reads(1).user()
3723      .mapsTo(MISCREG_PMCEID1);
3724    InitReg(MISCREG_PMCCNTR_EL0)
3725      .allPrivileges()
3726      .mapsTo(MISCREG_PMCCNTR);
3727    InitReg(MISCREG_PMXEVTYPER_EL0)
3728      .allPrivileges()
3729      .mapsTo(MISCREG_PMXEVTYPER);
3730    InitReg(MISCREG_PMCCFILTR_EL0)
3731      .allPrivileges();
3732    InitReg(MISCREG_PMXEVCNTR_EL0)
3733      .allPrivileges()
3734      .mapsTo(MISCREG_PMXEVCNTR);
3735    InitReg(MISCREG_PMUSERENR_EL0)
3736      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3737      .mapsTo(MISCREG_PMUSERENR);
3738    InitReg(MISCREG_PMOVSSET_EL0)
3739      .allPrivileges()
3740      .mapsTo(MISCREG_PMOVSSET);
3741    InitReg(MISCREG_MAIR_EL1)
3742      .allPrivileges().exceptUserMode()
3743      .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3744    InitReg(MISCREG_AMAIR_EL1)
3745      .allPrivileges().exceptUserMode()
3746      .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3747    InitReg(MISCREG_MAIR_EL2)
3748      .hyp().mon()
3749      .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3750    InitReg(MISCREG_AMAIR_EL2)
3751      .hyp().mon()
3752      .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3753    InitReg(MISCREG_MAIR_EL3)
3754      .mon();
3755    InitReg(MISCREG_AMAIR_EL3)
3756      .mon();
3757    InitReg(MISCREG_L2CTLR_EL1)
3758      .allPrivileges().exceptUserMode();
3759    InitReg(MISCREG_L2ECTLR_EL1)
3760      .allPrivileges().exceptUserMode();
3761    InitReg(MISCREG_VBAR_EL1)
3762      .allPrivileges().exceptUserMode()
3763      .mapsTo(MISCREG_VBAR_NS);
3764    InitReg(MISCREG_RVBAR_EL1)
3765      .allPrivileges().exceptUserMode().writes(0);
3766    InitReg(MISCREG_ISR_EL1)
3767      .allPrivileges().exceptUserMode().writes(0);
3768    InitReg(MISCREG_VBAR_EL2)
3769      .hyp().mon()
3770      .mapsTo(MISCREG_HVBAR);
3771    InitReg(MISCREG_RVBAR_EL2)
3772      .mon().hyp().writes(0);
3773    InitReg(MISCREG_VBAR_EL3)
3774      .mon();
3775    InitReg(MISCREG_RVBAR_EL3)
3776      .mon().writes(0);
3777    InitReg(MISCREG_RMR_EL3)
3778      .mon();
3779    InitReg(MISCREG_CONTEXTIDR_EL1)
3780      .allPrivileges().exceptUserMode()
3781      .mapsTo(MISCREG_CONTEXTIDR_NS);
3782    InitReg(MISCREG_TPIDR_EL1)
3783      .allPrivileges().exceptUserMode()
3784      .mapsTo(MISCREG_TPIDRPRW_NS);
3785    InitReg(MISCREG_TPIDR_EL0)
3786      .allPrivileges()
3787      .mapsTo(MISCREG_TPIDRURW_NS);
3788    InitReg(MISCREG_TPIDRRO_EL0)
3789      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3790      .mapsTo(MISCREG_TPIDRURO_NS);
3791    InitReg(MISCREG_TPIDR_EL2)
3792      .hyp().mon()
3793      .mapsTo(MISCREG_HTPIDR);
3794    InitReg(MISCREG_TPIDR_EL3)
3795      .mon();
3796    InitReg(MISCREG_CNTKCTL_EL1)
3797      .allPrivileges().exceptUserMode()
3798      .mapsTo(MISCREG_CNTKCTL);
3799    InitReg(MISCREG_CNTFRQ_EL0)
3800      .reads(1).mon()
3801      .mapsTo(MISCREG_CNTFRQ);
3802    InitReg(MISCREG_CNTPCT_EL0)
3803      .reads(1)
3804      .mapsTo(MISCREG_CNTPCT); /* 64b */
3805    InitReg(MISCREG_CNTVCT_EL0)
3806      .unverifiable()
3807      .reads(1)
3808      .mapsTo(MISCREG_CNTVCT); /* 64b */
3809    InitReg(MISCREG_CNTP_TVAL_EL0)
3810      .allPrivileges()
3811      .mapsTo(MISCREG_CNTP_TVAL_NS);
3812    InitReg(MISCREG_CNTP_CTL_EL0)
3813      .allPrivileges()
3814      .mapsTo(MISCREG_CNTP_CTL_NS);
3815    InitReg(MISCREG_CNTP_CVAL_EL0)
3816      .allPrivileges()
3817      .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
3818    InitReg(MISCREG_CNTV_TVAL_EL0)
3819      .allPrivileges()
3820      .mapsTo(MISCREG_CNTV_TVAL);
3821    InitReg(MISCREG_CNTV_CTL_EL0)
3822      .allPrivileges()
3823      .mapsTo(MISCREG_CNTV_CTL);
3824    InitReg(MISCREG_CNTV_CVAL_EL0)
3825      .allPrivileges()
3826      .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
3827    InitReg(MISCREG_PMEVCNTR0_EL0)
3828      .allPrivileges();
3829//    .mapsTo(MISCREG_PMEVCNTR0);
3830    InitReg(MISCREG_PMEVCNTR1_EL0)
3831      .allPrivileges();
3832//    .mapsTo(MISCREG_PMEVCNTR1);
3833    InitReg(MISCREG_PMEVCNTR2_EL0)
3834      .allPrivileges();
3835//    .mapsTo(MISCREG_PMEVCNTR2);
3836    InitReg(MISCREG_PMEVCNTR3_EL0)
3837      .allPrivileges();
3838//    .mapsTo(MISCREG_PMEVCNTR3);
3839    InitReg(MISCREG_PMEVCNTR4_EL0)
3840      .allPrivileges();
3841//    .mapsTo(MISCREG_PMEVCNTR4);
3842    InitReg(MISCREG_PMEVCNTR5_EL0)
3843      .allPrivileges();
3844//    .mapsTo(MISCREG_PMEVCNTR5);
3845    InitReg(MISCREG_PMEVTYPER0_EL0)
3846      .allPrivileges();
3847//    .mapsTo(MISCREG_PMEVTYPER0);
3848    InitReg(MISCREG_PMEVTYPER1_EL0)
3849      .allPrivileges();
3850//    .mapsTo(MISCREG_PMEVTYPER1);
3851    InitReg(MISCREG_PMEVTYPER2_EL0)
3852      .allPrivileges();
3853//    .mapsTo(MISCREG_PMEVTYPER2);
3854    InitReg(MISCREG_PMEVTYPER3_EL0)
3855      .allPrivileges();
3856//    .mapsTo(MISCREG_PMEVTYPER3);
3857    InitReg(MISCREG_PMEVTYPER4_EL0)
3858      .allPrivileges();
3859//    .mapsTo(MISCREG_PMEVTYPER4);
3860    InitReg(MISCREG_PMEVTYPER5_EL0)
3861      .allPrivileges();
3862//    .mapsTo(MISCREG_PMEVTYPER5);
3863    InitReg(MISCREG_CNTVOFF_EL2)
3864      .hyp().mon()
3865      .mapsTo(MISCREG_CNTVOFF); /* 64b */
3866    InitReg(MISCREG_CNTHCTL_EL2)
3867      .unimplemented()
3868      .warnNotFail()
3869      .mon().monNonSecureWrite(0).hypWrite()
3870      .mapsTo(MISCREG_CNTHCTL);
3871    InitReg(MISCREG_CNTHP_TVAL_EL2)
3872      .unimplemented()
3873      .mon().monNonSecureWrite(0).hypWrite()
3874      .mapsTo(MISCREG_CNTHP_TVAL);
3875    InitReg(MISCREG_CNTHP_CTL_EL2)
3876      .unimplemented()
3877      .mon().monNonSecureWrite(0).hypWrite()
3878      .mapsTo(MISCREG_CNTHP_CTL);
3879    InitReg(MISCREG_CNTHP_CVAL_EL2)
3880      .unimplemented()
3881      .mon().monNonSecureWrite(0).hypWrite()
3882      .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
3883    InitReg(MISCREG_CNTPS_TVAL_EL1)
3884      .unimplemented()
3885      .mon().monNonSecureWrite(0).hypWrite();
3886    InitReg(MISCREG_CNTPS_CTL_EL1)
3887      .unimplemented()
3888      .mon().monNonSecureWrite(0).hypWrite();
3889    InitReg(MISCREG_CNTPS_CVAL_EL1)
3890      .unimplemented()
3891      .mon().monNonSecureWrite(0).hypWrite();
3892    InitReg(MISCREG_IL1DATA0_EL1)
3893      .allPrivileges().exceptUserMode();
3894    InitReg(MISCREG_IL1DATA1_EL1)
3895      .allPrivileges().exceptUserMode();
3896    InitReg(MISCREG_IL1DATA2_EL1)
3897      .allPrivileges().exceptUserMode();
3898    InitReg(MISCREG_IL1DATA3_EL1)
3899      .allPrivileges().exceptUserMode();
3900    InitReg(MISCREG_DL1DATA0_EL1)
3901      .allPrivileges().exceptUserMode();
3902    InitReg(MISCREG_DL1DATA1_EL1)
3903      .allPrivileges().exceptUserMode();
3904    InitReg(MISCREG_DL1DATA2_EL1)
3905      .allPrivileges().exceptUserMode();
3906    InitReg(MISCREG_DL1DATA3_EL1)
3907      .allPrivileges().exceptUserMode();
3908    InitReg(MISCREG_DL1DATA4_EL1)
3909      .allPrivileges().exceptUserMode();
3910    InitReg(MISCREG_L2ACTLR_EL1)
3911      .allPrivileges().exceptUserMode();
3912    InitReg(MISCREG_CPUACTLR_EL1)
3913      .allPrivileges().exceptUserMode();
3914    InitReg(MISCREG_CPUECTLR_EL1)
3915      .allPrivileges().exceptUserMode();
3916    InitReg(MISCREG_CPUMERRSR_EL1)
3917      .allPrivileges().exceptUserMode();
3918    InitReg(MISCREG_L2MERRSR_EL1)
3919      .unimplemented()
3920      .warnNotFail()
3921      .allPrivileges().exceptUserMode();
3922    InitReg(MISCREG_CBAR_EL1)
3923      .allPrivileges().exceptUserMode().writes(0);
3924    InitReg(MISCREG_CONTEXTIDR_EL2)
3925      .mon().hyp();
3926
3927    // Dummy registers
3928    InitReg(MISCREG_NOP)
3929      .allPrivileges();
3930    InitReg(MISCREG_RAZ)
3931      .allPrivileges().exceptUserMode().writes(0);
3932    InitReg(MISCREG_CP14_UNIMPL)
3933      .unimplemented()
3934      .warnNotFail();
3935    InitReg(MISCREG_CP15_UNIMPL)
3936      .unimplemented()
3937      .warnNotFail();
3938    InitReg(MISCREG_A64_UNIMPL)
3939      .unimplemented()
3940      .warnNotFail();
3941    InitReg(MISCREG_UNKNOWN);
3942
3943    // Register mappings for some unimplemented registers:
3944    // ESR_EL1 -> DFSR
3945    // RMR_EL1 -> RMR
3946    // RMR_EL2 -> HRMR
3947    // DBGDTR_EL0 -> DBGDTR{R or T}Xint
3948    // DBGDTRRX_EL0 -> DBGDTRRXint
3949    // DBGDTRTX_EL0 -> DBGDTRRXint
3950    // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
3951
3952    completed = true;
3953}
3954
3955} // namespace ArmISA
3956