miscregs.cc revision 12530:ab63172c4fbe 
1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 *          Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57    switch(crn) {
58      case 0:
59        switch (opc1) {
60          case 0:
61            switch (opc2) {
62              case 0:
63                switch (crm) {
64                  case 0:
65                    return MISCREG_DBGDIDR;
66                  case 1:
67                    return MISCREG_DBGDSCRint;
68                }
69                break;
70            }
71            break;
72          case 7:
73            switch (opc2) {
74              case 0:
75                switch (crm) {
76                  case 0:
77                    return MISCREG_JIDR;
78                }
79              break;
80            }
81            break;
82        }
83        break;
84      case 1:
85        switch (opc1) {
86          case 6:
87            switch (crm) {
88              case 0:
89                switch (opc2) {
90                  case 0:
91                    return MISCREG_TEEHBR;
92                }
93                break;
94            }
95            break;
96          case 7:
97            switch (crm) {
98              case 0:
99                switch (opc2) {
100                  case 0:
101                    return MISCREG_JOSCR;
102                }
103                break;
104            }
105            break;
106        }
107        break;
108      case 2:
109        switch (opc1) {
110          case 7:
111            switch (crm) {
112              case 0:
113                switch (opc2) {
114                  case 0:
115                    return MISCREG_JMCR;
116                }
117                break;
118            }
119            break;
120        }
121        break;
122    }
123    // If we get here then it must be a register that we haven't implemented
124    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125         crn, opc1, crm, opc2);
126    return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134    switch (crn) {
135      case 0:
136        switch (opc1) {
137          case 0:
138            switch (crm) {
139              case 0:
140                switch (opc2) {
141                  case 1:
142                    return MISCREG_CTR;
143                  case 2:
144                    return MISCREG_TCMTR;
145                  case 3:
146                    return MISCREG_TLBTR;
147                  case 5:
148                    return MISCREG_MPIDR;
149                  case 6:
150                    return MISCREG_REVIDR;
151                  default:
152                    return MISCREG_MIDR;
153                }
154                break;
155              case 1:
156                switch (opc2) {
157                  case 0:
158                    return MISCREG_ID_PFR0;
159                  case 1:
160                    return MISCREG_ID_PFR1;
161                  case 2:
162                    return MISCREG_ID_DFR0;
163                  case 3:
164                    return MISCREG_ID_AFR0;
165                  case 4:
166                    return MISCREG_ID_MMFR0;
167                  case 5:
168                    return MISCREG_ID_MMFR1;
169                  case 6:
170                    return MISCREG_ID_MMFR2;
171                  case 7:
172                    return MISCREG_ID_MMFR3;
173                }
174                break;
175              case 2:
176                switch (opc2) {
177                  case 0:
178                    return MISCREG_ID_ISAR0;
179                  case 1:
180                    return MISCREG_ID_ISAR1;
181                  case 2:
182                    return MISCREG_ID_ISAR2;
183                  case 3:
184                    return MISCREG_ID_ISAR3;
185                  case 4:
186                    return MISCREG_ID_ISAR4;
187                  case 5:
188                    return MISCREG_ID_ISAR5;
189                  case 6:
190                  case 7:
191                    return MISCREG_RAZ; // read as zero
192                }
193                break;
194              default:
195                return MISCREG_RAZ; // read as zero
196            }
197            break;
198          case 1:
199            if (crm == 0) {
200                switch (opc2) {
201                  case 0:
202                    return MISCREG_CCSIDR;
203                  case 1:
204                    return MISCREG_CLIDR;
205                  case 7:
206                    return MISCREG_AIDR;
207                }
208            }
209            break;
210          case 2:
211            if (crm == 0 && opc2 == 0) {
212                return MISCREG_CSSELR;
213            }
214            break;
215          case 4:
216            if (crm == 0) {
217                if (opc2 == 0)
218                    return MISCREG_VPIDR;
219                else if (opc2 == 5)
220                    return MISCREG_VMPIDR;
221            }
222            break;
223        }
224        break;
225      case 1:
226        if (opc1 == 0) {
227            if (crm == 0) {
228                switch (opc2) {
229                  case 0:
230                    return MISCREG_SCTLR;
231                  case 1:
232                    return MISCREG_ACTLR;
233                  case 0x2:
234                    return MISCREG_CPACR;
235                }
236            } else if (crm == 1) {
237                switch (opc2) {
238                  case 0:
239                    return MISCREG_SCR;
240                  case 1:
241                    return MISCREG_SDER;
242                  case 2:
243                    return MISCREG_NSACR;
244                }
245            }
246        } else if (opc1 == 4) {
247            if (crm == 0) {
248                if (opc2 == 0)
249                    return MISCREG_HSCTLR;
250                else if (opc2 == 1)
251                    return MISCREG_HACTLR;
252            } else if (crm == 1) {
253                switch (opc2) {
254                  case 0:
255                    return MISCREG_HCR;
256                  case 1:
257                    return MISCREG_HDCR;
258                  case 2:
259                    return MISCREG_HCPTR;
260                  case 3:
261                    return MISCREG_HSTR;
262                  case 7:
263                    return MISCREG_HACR;
264                }
265            }
266        }
267        break;
268      case 2:
269        if (opc1 == 0 && crm == 0) {
270            switch (opc2) {
271              case 0:
272                return MISCREG_TTBR0;
273              case 1:
274                return MISCREG_TTBR1;
275              case 2:
276                return MISCREG_TTBCR;
277            }
278        } else if (opc1 == 4) {
279            if (crm == 0 && opc2 == 2)
280                return MISCREG_HTCR;
281            else if (crm == 1 && opc2 == 2)
282                return MISCREG_VTCR;
283        }
284        break;
285      case 3:
286        if (opc1 == 0 && crm == 0 && opc2 == 0) {
287            return MISCREG_DACR;
288        }
289        break;
290      case 5:
291        if (opc1 == 0) {
292            if (crm == 0) {
293                if (opc2 == 0) {
294                    return MISCREG_DFSR;
295                } else if (opc2 == 1) {
296                    return MISCREG_IFSR;
297                }
298            } else if (crm == 1) {
299                if (opc2 == 0) {
300                    return MISCREG_ADFSR;
301                } else if (opc2 == 1) {
302                    return MISCREG_AIFSR;
303                }
304            }
305        } else if (opc1 == 4) {
306            if (crm == 1) {
307                if (opc2 == 0)
308                    return MISCREG_HADFSR;
309                else if (opc2 == 1)
310                    return MISCREG_HAIFSR;
311            } else if (crm == 2 && opc2 == 0) {
312                return MISCREG_HSR;
313            }
314        }
315        break;
316      case 6:
317        if (opc1 == 0 && crm == 0) {
318            switch (opc2) {
319              case 0:
320                return MISCREG_DFAR;
321              case 2:
322                return MISCREG_IFAR;
323            }
324        } else if (opc1 == 4 && crm == 0) {
325            switch (opc2) {
326              case 0:
327                return MISCREG_HDFAR;
328              case 2:
329                return MISCREG_HIFAR;
330              case 4:
331                return MISCREG_HPFAR;
332            }
333        }
334        break;
335      case 7:
336        if (opc1 == 0) {
337            switch (crm) {
338              case 0:
339                if (opc2 == 4) {
340                    return MISCREG_NOP;
341                }
342                break;
343              case 1:
344                switch (opc2) {
345                  case 0:
346                    return MISCREG_ICIALLUIS;
347                  case 6:
348                    return MISCREG_BPIALLIS;
349                }
350                break;
351              case 4:
352                if (opc2 == 0) {
353                    return MISCREG_PAR;
354                }
355                break;
356              case 5:
357                switch (opc2) {
358                  case 0:
359                    return MISCREG_ICIALLU;
360                  case 1:
361                    return MISCREG_ICIMVAU;
362                  case 4:
363                    return MISCREG_CP15ISB;
364                  case 6:
365                    return MISCREG_BPIALL;
366                  case 7:
367                    return MISCREG_BPIMVA;
368                }
369                break;
370              case 6:
371                if (opc2 == 1) {
372                    return MISCREG_DCIMVAC;
373                } else if (opc2 == 2) {
374                    return MISCREG_DCISW;
375                }
376                break;
377              case 8:
378                switch (opc2) {
379                  case 0:
380                    return MISCREG_ATS1CPR;
381                  case 1:
382                    return MISCREG_ATS1CPW;
383                  case 2:
384                    return MISCREG_ATS1CUR;
385                  case 3:
386                    return MISCREG_ATS1CUW;
387                  case 4:
388                    return MISCREG_ATS12NSOPR;
389                  case 5:
390                    return MISCREG_ATS12NSOPW;
391                  case 6:
392                    return MISCREG_ATS12NSOUR;
393                  case 7:
394                    return MISCREG_ATS12NSOUW;
395                }
396                break;
397              case 10:
398                switch (opc2) {
399                  case 1:
400                    return MISCREG_DCCMVAC;
401                  case 2:
402                    return MISCREG_DCCSW;
403                  case 4:
404                    return MISCREG_CP15DSB;
405                  case 5:
406                    return MISCREG_CP15DMB;
407                }
408                break;
409              case 11:
410                if (opc2 == 1) {
411                    return MISCREG_DCCMVAU;
412                }
413                break;
414              case 13:
415                if (opc2 == 1) {
416                    return MISCREG_NOP;
417                }
418                break;
419              case 14:
420                if (opc2 == 1) {
421                    return MISCREG_DCCIMVAC;
422                } else if (opc2 == 2) {
423                    return MISCREG_DCCISW;
424                }
425                break;
426            }
427        } else if (opc1 == 4 && crm == 8) {
428            if (opc2 == 0)
429                return MISCREG_ATS1HR;
430            else if (opc2 == 1)
431                return MISCREG_ATS1HW;
432        }
433        break;
434      case 8:
435        if (opc1 == 0) {
436            switch (crm) {
437              case 3:
438                switch (opc2) {
439                  case 0:
440                    return MISCREG_TLBIALLIS;
441                  case 1:
442                    return MISCREG_TLBIMVAIS;
443                  case 2:
444                    return MISCREG_TLBIASIDIS;
445                  case 3:
446                    return MISCREG_TLBIMVAAIS;
447                }
448                break;
449              case 5:
450                switch (opc2) {
451                  case 0:
452                    return MISCREG_ITLBIALL;
453                  case 1:
454                    return MISCREG_ITLBIMVA;
455                  case 2:
456                    return MISCREG_ITLBIASID;
457                }
458                break;
459              case 6:
460                switch (opc2) {
461                  case 0:
462                    return MISCREG_DTLBIALL;
463                  case 1:
464                    return MISCREG_DTLBIMVA;
465                  case 2:
466                    return MISCREG_DTLBIASID;
467                }
468                break;
469              case 7:
470                switch (opc2) {
471                  case 0:
472                    return MISCREG_TLBIALL;
473                  case 1:
474                    return MISCREG_TLBIMVA;
475                  case 2:
476                    return MISCREG_TLBIASID;
477                  case 3:
478                    return MISCREG_TLBIMVAA;
479                }
480                break;
481            }
482        } else if (opc1 == 4) {
483            if (crm == 3) {
484                switch (opc2) {
485                  case 0:
486                    return MISCREG_TLBIALLHIS;
487                  case 1:
488                    return MISCREG_TLBIMVAHIS;
489                  case 4:
490                    return MISCREG_TLBIALLNSNHIS;
491                }
492            } else if (crm == 7) {
493                switch (opc2) {
494                  case 0:
495                    return MISCREG_TLBIALLH;
496                  case 1:
497                    return MISCREG_TLBIMVAH;
498                  case 4:
499                    return MISCREG_TLBIALLNSNH;
500                }
501            }
502        }
503        break;
504      case 9:
505        // Every cop register with CRn = 9 and CRm in
506        // {0-2}, {5-8} is implementation defined regardless
507        // of opc1 and opc2.
508        switch (crm) {
509          case 0:
510          case 1:
511          case 2:
512          case 5:
513          case 6:
514          case 7:
515          case 8:
516            return MISCREG_IMPDEF_UNIMPL;
517        }
518        if (opc1 == 0) {
519            switch (crm) {
520              case 12:
521                switch (opc2) {
522                  case 0:
523                    return MISCREG_PMCR;
524                  case 1:
525                    return MISCREG_PMCNTENSET;
526                  case 2:
527                    return MISCREG_PMCNTENCLR;
528                  case 3:
529                    return MISCREG_PMOVSR;
530                  case 4:
531                    return MISCREG_PMSWINC;
532                  case 5:
533                    return MISCREG_PMSELR;
534                  case 6:
535                    return MISCREG_PMCEID0;
536                  case 7:
537                    return MISCREG_PMCEID1;
538                }
539                break;
540              case 13:
541                switch (opc2) {
542                  case 0:
543                    return MISCREG_PMCCNTR;
544                  case 1:
545                    // Selector is PMSELR.SEL
546                    return MISCREG_PMXEVTYPER_PMCCFILTR;
547                  case 2:
548                    return MISCREG_PMXEVCNTR;
549                }
550                break;
551              case 14:
552                switch (opc2) {
553                  case 0:
554                    return MISCREG_PMUSERENR;
555                  case 1:
556                    return MISCREG_PMINTENSET;
557                  case 2:
558                    return MISCREG_PMINTENCLR;
559                  case 3:
560                    return MISCREG_PMOVSSET;
561                }
562                break;
563            }
564        } else if (opc1 == 1) {
565            switch (crm) {
566              case 0:
567                switch (opc2) {
568                  case 2: // L2CTLR, L2 Control Register
569                    return MISCREG_L2CTLR;
570                  case 3:
571                    return MISCREG_L2ECTLR;
572                }
573                break;
574                break;
575            }
576        }
577        break;
578      case 10:
579        if (opc1 == 0) {
580            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
581            if (crm < 2) {
582                return MISCREG_IMPDEF_UNIMPL;
583            } else if (crm == 2) { // TEX Remap Registers
584                if (opc2 == 0) {
585                    // Selector is TTBCR.EAE
586                    return MISCREG_PRRR_MAIR0;
587                } else if (opc2 == 1) {
588                    // Selector is TTBCR.EAE
589                    return MISCREG_NMRR_MAIR1;
590                }
591            } else if (crm == 3) {
592                if (opc2 == 0) {
593                    return MISCREG_AMAIR0;
594                } else if (opc2 == 1) {
595                    return MISCREG_AMAIR1;
596                }
597            }
598        } else if (opc1 == 4) {
599            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
600            if (crm == 2) {
601                if (opc2 == 0)
602                    return MISCREG_HMAIR0;
603                else if (opc2 == 1)
604                    return MISCREG_HMAIR1;
605            } else if (crm == 3) {
606                if (opc2 == 0)
607                    return MISCREG_HAMAIR0;
608                else if (opc2 == 1)
609                    return MISCREG_HAMAIR1;
610            }
611        }
612        break;
613      case 11:
614        if (opc1 <=7) {
615            switch (crm) {
616              case 0:
617              case 1:
618              case 2:
619              case 3:
620              case 4:
621              case 5:
622              case 6:
623              case 7:
624              case 8:
625              case 15:
626                // Reserved for DMA operations for TCM access
627                return MISCREG_IMPDEF_UNIMPL;
628              default:
629                break;
630            }
631        }
632        break;
633      case 12:
634        if (opc1 == 0) {
635            if (crm == 0) {
636                if (opc2 == 0) {
637                    return MISCREG_VBAR;
638                } else if (opc2 == 1) {
639                    return MISCREG_MVBAR;
640                }
641            } else if (crm == 1) {
642                if (opc2 == 0) {
643                    return MISCREG_ISR;
644                }
645            }
646        } else if (opc1 == 4) {
647            if (crm == 0 && opc2 == 0)
648                return MISCREG_HVBAR;
649        }
650        break;
651      case 13:
652        if (opc1 == 0) {
653            if (crm == 0) {
654                switch (opc2) {
655                  case 0:
656                    return MISCREG_FCSEIDR;
657                  case 1:
658                    return MISCREG_CONTEXTIDR;
659                  case 2:
660                    return MISCREG_TPIDRURW;
661                  case 3:
662                    return MISCREG_TPIDRURO;
663                  case 4:
664                    return MISCREG_TPIDRPRW;
665                }
666            }
667        } else if (opc1 == 4) {
668            if (crm == 0 && opc2 == 2)
669                return MISCREG_HTPIDR;
670        }
671        break;
672      case 14:
673        if (opc1 == 0) {
674            switch (crm) {
675              case 0:
676                if (opc2 == 0)
677                    return MISCREG_CNTFRQ;
678                break;
679              case 1:
680                if (opc2 == 0)
681                    return MISCREG_CNTKCTL;
682                break;
683              case 2:
684                if (opc2 == 0)
685                    return MISCREG_CNTP_TVAL;
686                else if (opc2 == 1)
687                    return MISCREG_CNTP_CTL;
688                break;
689              case 3:
690                if (opc2 == 0)
691                    return MISCREG_CNTV_TVAL;
692                else if (opc2 == 1)
693                    return MISCREG_CNTV_CTL;
694                break;
695            }
696        } else if (opc1 == 4) {
697            if (crm == 1 && opc2 == 0) {
698                return MISCREG_CNTHCTL;
699            } else if (crm == 2) {
700                if (opc2 == 0)
701                    return MISCREG_CNTHP_TVAL;
702                else if (opc2 == 1)
703                    return MISCREG_CNTHP_CTL;
704            }
705        }
706        break;
707      case 15:
708        // Implementation defined
709        return MISCREG_IMPDEF_UNIMPL;
710    }
711    // Unrecognized register
712    return MISCREG_CP15_UNIMPL;
713}
714
715MiscRegIndex
716decodeCP15Reg64(unsigned crm, unsigned opc1)
717{
718    switch (crm) {
719      case 2:
720        switch (opc1) {
721          case 0:
722            return MISCREG_TTBR0;
723          case 1:
724            return MISCREG_TTBR1;
725          case 4:
726            return MISCREG_HTTBR;
727          case 6:
728            return MISCREG_VTTBR;
729        }
730        break;
731      case 7:
732        if (opc1 == 0)
733            return MISCREG_PAR;
734        break;
735      case 14:
736        switch (opc1) {
737          case 0:
738            return MISCREG_CNTPCT;
739          case 1:
740            return MISCREG_CNTVCT;
741          case 2:
742            return MISCREG_CNTP_CVAL;
743          case 3:
744            return MISCREG_CNTV_CVAL;
745          case 4:
746            return MISCREG_CNTVOFF;
747          case 6:
748            return MISCREG_CNTHP_CVAL;
749        }
750        break;
751      case 15:
752        if (opc1 == 0)
753            return MISCREG_CPUMERRSR;
754        else if (opc1 == 1)
755            return MISCREG_L2MERRSR;
756        break;
757    }
758    // Unrecognized register
759    return MISCREG_CP15_UNIMPL;
760}
761
762std::tuple<bool, bool>
763canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
764{
765    bool secure = !scr.ns;
766    bool canRead = false;
767    bool undefined = false;
768
769    switch (cpsr.mode) {
770      case MODE_USER:
771        canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
772                           miscRegInfo[reg][MISCREG_USR_NS_RD];
773        break;
774      case MODE_FIQ:
775      case MODE_IRQ:
776      case MODE_SVC:
777      case MODE_ABORT:
778      case MODE_UNDEFINED:
779      case MODE_SYSTEM:
780        canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
781                           miscRegInfo[reg][MISCREG_PRI_NS_RD];
782        break;
783      case MODE_MON:
784        canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
785                           miscRegInfo[reg][MISCREG_MON_NS1_RD];
786        break;
787      case MODE_HYP:
788        canRead = miscRegInfo[reg][MISCREG_HYP_RD];
789        break;
790      default:
791        undefined = true;
792    }
793    // can't do permissions checkes on the root of a banked pair of regs
794    assert(!miscRegInfo[reg][MISCREG_BANKED]);
795    return std::make_tuple(canRead, undefined);
796}
797
798std::tuple<bool, bool>
799canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
800{
801    bool secure = !scr.ns;
802    bool canWrite = false;
803    bool undefined = false;
804
805    switch (cpsr.mode) {
806      case MODE_USER:
807        canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
808                            miscRegInfo[reg][MISCREG_USR_NS_WR];
809        break;
810      case MODE_FIQ:
811      case MODE_IRQ:
812      case MODE_SVC:
813      case MODE_ABORT:
814      case MODE_UNDEFINED:
815      case MODE_SYSTEM:
816        canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
817                            miscRegInfo[reg][MISCREG_PRI_NS_WR];
818        break;
819      case MODE_MON:
820        canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
821                            miscRegInfo[reg][MISCREG_MON_NS1_WR];
822        break;
823      case MODE_HYP:
824        canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
825        break;
826      default:
827        undefined = true;
828    }
829    // can't do permissions checkes on the root of a banked pair of regs
830    assert(!miscRegInfo[reg][MISCREG_BANKED]);
831    return std::make_tuple(canWrite, undefined);
832}
833
834int
835snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
836{
837    SCR scr = tc->readMiscReg(MISCREG_SCR);
838    return snsBankedIndex(reg, tc, scr.ns);
839}
840
841int
842snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
843{
844    int reg_as_int = static_cast<int>(reg);
845    if (miscRegInfo[reg][MISCREG_BANKED]) {
846        reg_as_int += (ArmSystem::haveSecurity(tc) &&
847                      !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
848    }
849    return reg_as_int;
850}
851
852
853/**
854 * If the reg is a child reg of a banked set, then the parent is the last
855 * banked one in the list. This is messy, and the wish is to eventually have
856 * the bitmap replaced with a better data structure. the preUnflatten function
857 * initializes a lookup table to speed up the search for these banked
858 * registers.
859 */
860
861int unflattenResultMiscReg[NUM_MISCREGS];
862
863void
864preUnflattenMiscReg()
865{
866    int reg = -1;
867    for (int i = 0 ; i < NUM_MISCREGS; i++){
868        if (miscRegInfo[i][MISCREG_BANKED])
869            reg = i;
870        if (miscRegInfo[i][MISCREG_BANKED_CHILD])
871            unflattenResultMiscReg[i] = reg;
872        else
873            unflattenResultMiscReg[i] = i;
874        // if this assert fails, no parent was found, and something is broken
875        assert(unflattenResultMiscReg[i] > -1);
876    }
877}
878
879int
880unflattenMiscReg(int reg)
881{
882    return unflattenResultMiscReg[reg];
883}
884
885bool
886canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
887{
888    // Check for SP_EL0 access while SPSEL == 0
889    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
890        return false;
891
892    // Check for RVBAR access
893    if (reg == MISCREG_RVBAR_EL1) {
894        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
895        if (highest_el == EL2 || highest_el == EL3)
896            return false;
897    }
898    if (reg == MISCREG_RVBAR_EL2) {
899        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
900        if (highest_el == EL3)
901            return false;
902    }
903
904    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
905
906    switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
907      case EL0:
908        return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
909            miscRegInfo[reg][MISCREG_USR_NS_RD];
910      case EL1:
911        return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
912            miscRegInfo[reg][MISCREG_PRI_NS_RD];
913      case EL2:
914        return miscRegInfo[reg][MISCREG_HYP_RD];
915      case EL3:
916        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
917            miscRegInfo[reg][MISCREG_MON_NS1_RD];
918      default:
919        panic("Invalid exception level");
920    }
921}
922
923bool
924canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
925{
926    // Check for SP_EL0 access while SPSEL == 0
927    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
928        return false;
929    ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
930    if (reg == MISCREG_DAIF) {
931        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
932        if (el == EL0 && !sctlr.uma)
933            return false;
934    }
935    if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
936        // In syscall-emulation mode, this test is skipped and DCZVA is always
937        // allowed at EL0
938        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
939        if (el == EL0 && !sctlr.dze)
940            return false;
941    }
942    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
943        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
944        if (el == EL0 && !sctlr.uci)
945            return false;
946    }
947
948    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
949
950    switch (el) {
951      case EL0:
952        return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
953            miscRegInfo[reg][MISCREG_USR_NS_WR];
954      case EL1:
955        return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
956            miscRegInfo[reg][MISCREG_PRI_NS_WR];
957      case EL2:
958        return miscRegInfo[reg][MISCREG_HYP_WR];
959      case EL3:
960        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
961            miscRegInfo[reg][MISCREG_MON_NS1_WR];
962      default:
963        panic("Invalid exception level");
964    }
965}
966
967MiscRegIndex
968decodeAArch64SysReg(unsigned op0, unsigned op1,
969                    unsigned crn, unsigned crm,
970                    unsigned op2)
971{
972    switch (op0) {
973      case 1:
974        switch (crn) {
975          case 7:
976            switch (op1) {
977              case 0:
978                switch (crm) {
979                  case 1:
980                    switch (op2) {
981                      case 0:
982                        return MISCREG_IC_IALLUIS;
983                    }
984                    break;
985                  case 5:
986                    switch (op2) {
987                      case 0:
988                        return MISCREG_IC_IALLU;
989                    }
990                    break;
991                  case 6:
992                    switch (op2) {
993                      case 1:
994                        return MISCREG_DC_IVAC_Xt;
995                      case 2:
996                        return MISCREG_DC_ISW_Xt;
997                    }
998                    break;
999                  case 8:
1000                    switch (op2) {
1001                      case 0:
1002                        return MISCREG_AT_S1E1R_Xt;
1003                      case 1:
1004                        return MISCREG_AT_S1E1W_Xt;
1005                      case 2:
1006                        return MISCREG_AT_S1E0R_Xt;
1007                      case 3:
1008                        return MISCREG_AT_S1E0W_Xt;
1009                    }
1010                    break;
1011                  case 10:
1012                    switch (op2) {
1013                      case 2:
1014                        return MISCREG_DC_CSW_Xt;
1015                    }
1016                    break;
1017                  case 14:
1018                    switch (op2) {
1019                      case 2:
1020                        return MISCREG_DC_CISW_Xt;
1021                    }
1022                    break;
1023                }
1024                break;
1025              case 3:
1026                switch (crm) {
1027                  case 4:
1028                    switch (op2) {
1029                      case 1:
1030                        return MISCREG_DC_ZVA_Xt;
1031                    }
1032                    break;
1033                  case 5:
1034                    switch (op2) {
1035                      case 1:
1036                        return MISCREG_IC_IVAU_Xt;
1037                    }
1038                    break;
1039                  case 10:
1040                    switch (op2) {
1041                      case 1:
1042                        return MISCREG_DC_CVAC_Xt;
1043                    }
1044                    break;
1045                  case 11:
1046                    switch (op2) {
1047                      case 1:
1048                        return MISCREG_DC_CVAU_Xt;
1049                    }
1050                    break;
1051                  case 14:
1052                    switch (op2) {
1053                      case 1:
1054                        return MISCREG_DC_CIVAC_Xt;
1055                    }
1056                    break;
1057                }
1058                break;
1059              case 4:
1060                switch (crm) {
1061                  case 8:
1062                    switch (op2) {
1063                      case 0:
1064                        return MISCREG_AT_S1E2R_Xt;
1065                      case 1:
1066                        return MISCREG_AT_S1E2W_Xt;
1067                      case 4:
1068                        return MISCREG_AT_S12E1R_Xt;
1069                      case 5:
1070                        return MISCREG_AT_S12E1W_Xt;
1071                      case 6:
1072                        return MISCREG_AT_S12E0R_Xt;
1073                      case 7:
1074                        return MISCREG_AT_S12E0W_Xt;
1075                    }
1076                    break;
1077                }
1078                break;
1079              case 6:
1080                switch (crm) {
1081                  case 8:
1082                    switch (op2) {
1083                      case 0:
1084                        return MISCREG_AT_S1E3R_Xt;
1085                      case 1:
1086                        return MISCREG_AT_S1E3W_Xt;
1087                    }
1088                    break;
1089                }
1090                break;
1091            }
1092            break;
1093          case 8:
1094            switch (op1) {
1095              case 0:
1096                switch (crm) {
1097                  case 3:
1098                    switch (op2) {
1099                      case 0:
1100                        return MISCREG_TLBI_VMALLE1IS;
1101                      case 1:
1102                        return MISCREG_TLBI_VAE1IS_Xt;
1103                      case 2:
1104                        return MISCREG_TLBI_ASIDE1IS_Xt;
1105                      case 3:
1106                        return MISCREG_TLBI_VAAE1IS_Xt;
1107                      case 5:
1108                        return MISCREG_TLBI_VALE1IS_Xt;
1109                      case 7:
1110                        return MISCREG_TLBI_VAALE1IS_Xt;
1111                    }
1112                    break;
1113                  case 7:
1114                    switch (op2) {
1115                      case 0:
1116                        return MISCREG_TLBI_VMALLE1;
1117                      case 1:
1118                        return MISCREG_TLBI_VAE1_Xt;
1119                      case 2:
1120                        return MISCREG_TLBI_ASIDE1_Xt;
1121                      case 3:
1122                        return MISCREG_TLBI_VAAE1_Xt;
1123                      case 5:
1124                        return MISCREG_TLBI_VALE1_Xt;
1125                      case 7:
1126                        return MISCREG_TLBI_VAALE1_Xt;
1127                    }
1128                    break;
1129                }
1130                break;
1131              case 4:
1132                switch (crm) {
1133                  case 0:
1134                    switch (op2) {
1135                      case 1:
1136                        return MISCREG_TLBI_IPAS2E1IS_Xt;
1137                      case 5:
1138                        return MISCREG_TLBI_IPAS2LE1IS_Xt;
1139                    }
1140                    break;
1141                  case 3:
1142                    switch (op2) {
1143                      case 0:
1144                        return MISCREG_TLBI_ALLE2IS;
1145                      case 1:
1146                        return MISCREG_TLBI_VAE2IS_Xt;
1147                      case 4:
1148                        return MISCREG_TLBI_ALLE1IS;
1149                      case 5:
1150                        return MISCREG_TLBI_VALE2IS_Xt;
1151                      case 6:
1152                        return MISCREG_TLBI_VMALLS12E1IS;
1153                    }
1154                    break;
1155                  case 4:
1156                    switch (op2) {
1157                      case 1:
1158                        return MISCREG_TLBI_IPAS2E1_Xt;
1159                      case 5:
1160                        return MISCREG_TLBI_IPAS2LE1_Xt;
1161                    }
1162                    break;
1163                  case 7:
1164                    switch (op2) {
1165                      case 0:
1166                        return MISCREG_TLBI_ALLE2;
1167                      case 1:
1168                        return MISCREG_TLBI_VAE2_Xt;
1169                      case 4:
1170                        return MISCREG_TLBI_ALLE1;
1171                      case 5:
1172                        return MISCREG_TLBI_VALE2_Xt;
1173                      case 6:
1174                        return MISCREG_TLBI_VMALLS12E1;
1175                    }
1176                    break;
1177                }
1178                break;
1179              case 6:
1180                switch (crm) {
1181                  case 3:
1182                    switch (op2) {
1183                      case 0:
1184                        return MISCREG_TLBI_ALLE3IS;
1185                      case 1:
1186                        return MISCREG_TLBI_VAE3IS_Xt;
1187                      case 5:
1188                        return MISCREG_TLBI_VALE3IS_Xt;
1189                    }
1190                    break;
1191                  case 7:
1192                    switch (op2) {
1193                      case 0:
1194                        return MISCREG_TLBI_ALLE3;
1195                      case 1:
1196                        return MISCREG_TLBI_VAE3_Xt;
1197                      case 5:
1198                        return MISCREG_TLBI_VALE3_Xt;
1199                    }
1200                    break;
1201                }
1202                break;
1203            }
1204            break;
1205        }
1206        break;
1207      case 2:
1208        switch (crn) {
1209          case 0:
1210            switch (op1) {
1211              case 0:
1212                switch (crm) {
1213                  case 0:
1214                    switch (op2) {
1215                      case 2:
1216                        return MISCREG_OSDTRRX_EL1;
1217                      case 4:
1218                        return MISCREG_DBGBVR0_EL1;
1219                      case 5:
1220                        return MISCREG_DBGBCR0_EL1;
1221                      case 6:
1222                        return MISCREG_DBGWVR0_EL1;
1223                      case 7:
1224                        return MISCREG_DBGWCR0_EL1;
1225                    }
1226                    break;
1227                  case 1:
1228                    switch (op2) {
1229                      case 4:
1230                        return MISCREG_DBGBVR1_EL1;
1231                      case 5:
1232                        return MISCREG_DBGBCR1_EL1;
1233                      case 6:
1234                        return MISCREG_DBGWVR1_EL1;
1235                      case 7:
1236                        return MISCREG_DBGWCR1_EL1;
1237                    }
1238                    break;
1239                  case 2:
1240                    switch (op2) {
1241                      case 0:
1242                        return MISCREG_MDCCINT_EL1;
1243                      case 2:
1244                        return MISCREG_MDSCR_EL1;
1245                      case 4:
1246                        return MISCREG_DBGBVR2_EL1;
1247                      case 5:
1248                        return MISCREG_DBGBCR2_EL1;
1249                      case 6:
1250                        return MISCREG_DBGWVR2_EL1;
1251                      case 7:
1252                        return MISCREG_DBGWCR2_EL1;
1253                    }
1254                    break;
1255                  case 3:
1256                    switch (op2) {
1257                      case 2:
1258                        return MISCREG_OSDTRTX_EL1;
1259                      case 4:
1260                        return MISCREG_DBGBVR3_EL1;
1261                      case 5:
1262                        return MISCREG_DBGBCR3_EL1;
1263                      case 6:
1264                        return MISCREG_DBGWVR3_EL1;
1265                      case 7:
1266                        return MISCREG_DBGWCR3_EL1;
1267                    }
1268                    break;
1269                  case 4:
1270                    switch (op2) {
1271                      case 4:
1272                        return MISCREG_DBGBVR4_EL1;
1273                      case 5:
1274                        return MISCREG_DBGBCR4_EL1;
1275                    }
1276                    break;
1277                  case 5:
1278                    switch (op2) {
1279                      case 4:
1280                        return MISCREG_DBGBVR5_EL1;
1281                      case 5:
1282                        return MISCREG_DBGBCR5_EL1;
1283                    }
1284                    break;
1285                  case 6:
1286                    switch (op2) {
1287                      case 2:
1288                        return MISCREG_OSECCR_EL1;
1289                    }
1290                    break;
1291                }
1292                break;
1293              case 2:
1294                switch (crm) {
1295                  case 0:
1296                    switch (op2) {
1297                      case 0:
1298                        return MISCREG_TEECR32_EL1;
1299                    }
1300                    break;
1301                }
1302                break;
1303              case 3:
1304                switch (crm) {
1305                  case 1:
1306                    switch (op2) {
1307                      case 0:
1308                        return MISCREG_MDCCSR_EL0;
1309                    }
1310                    break;
1311                  case 4:
1312                    switch (op2) {
1313                      case 0:
1314                        return MISCREG_MDDTR_EL0;
1315                    }
1316                    break;
1317                  case 5:
1318                    switch (op2) {
1319                      case 0:
1320                        return MISCREG_MDDTRRX_EL0;
1321                    }
1322                    break;
1323                }
1324                break;
1325              case 4:
1326                switch (crm) {
1327                  case 7:
1328                    switch (op2) {
1329                      case 0:
1330                        return MISCREG_DBGVCR32_EL2;
1331                    }
1332                    break;
1333                }
1334                break;
1335            }
1336            break;
1337          case 1:
1338            switch (op1) {
1339              case 0:
1340                switch (crm) {
1341                  case 0:
1342                    switch (op2) {
1343                      case 0:
1344                        return MISCREG_MDRAR_EL1;
1345                      case 4:
1346                        return MISCREG_OSLAR_EL1;
1347                    }
1348                    break;
1349                  case 1:
1350                    switch (op2) {
1351                      case 4:
1352                        return MISCREG_OSLSR_EL1;
1353                    }
1354                    break;
1355                  case 3:
1356                    switch (op2) {
1357                      case 4:
1358                        return MISCREG_OSDLR_EL1;
1359                    }
1360                    break;
1361                  case 4:
1362                    switch (op2) {
1363                      case 4:
1364                        return MISCREG_DBGPRCR_EL1;
1365                    }
1366                    break;
1367                }
1368                break;
1369              case 2:
1370                switch (crm) {
1371                  case 0:
1372                    switch (op2) {
1373                      case 0:
1374                        return MISCREG_TEEHBR32_EL1;
1375                    }
1376                    break;
1377                }
1378                break;
1379            }
1380            break;
1381          case 7:
1382            switch (op1) {
1383              case 0:
1384                switch (crm) {
1385                  case 8:
1386                    switch (op2) {
1387                      case 6:
1388                        return MISCREG_DBGCLAIMSET_EL1;
1389                    }
1390                    break;
1391                  case 9:
1392                    switch (op2) {
1393                      case 6:
1394                        return MISCREG_DBGCLAIMCLR_EL1;
1395                    }
1396                    break;
1397                  case 14:
1398                    switch (op2) {
1399                      case 6:
1400                        return MISCREG_DBGAUTHSTATUS_EL1;
1401                    }
1402                    break;
1403                }
1404                break;
1405            }
1406            break;
1407        }
1408        break;
1409      case 3:
1410        switch (crn) {
1411          case 0:
1412            switch (op1) {
1413              case 0:
1414                switch (crm) {
1415                  case 0:
1416                    switch (op2) {
1417                      case 0:
1418                        return MISCREG_MIDR_EL1;
1419                      case 5:
1420                        return MISCREG_MPIDR_EL1;
1421                      case 6:
1422                        return MISCREG_REVIDR_EL1;
1423                    }
1424                    break;
1425                  case 1:
1426                    switch (op2) {
1427                      case 0:
1428                        return MISCREG_ID_PFR0_EL1;
1429                      case 1:
1430                        return MISCREG_ID_PFR1_EL1;
1431                      case 2:
1432                        return MISCREG_ID_DFR0_EL1;
1433                      case 3:
1434                        return MISCREG_ID_AFR0_EL1;
1435                      case 4:
1436                        return MISCREG_ID_MMFR0_EL1;
1437                      case 5:
1438                        return MISCREG_ID_MMFR1_EL1;
1439                      case 6:
1440                        return MISCREG_ID_MMFR2_EL1;
1441                      case 7:
1442                        return MISCREG_ID_MMFR3_EL1;
1443                    }
1444                    break;
1445                  case 2:
1446                    switch (op2) {
1447                      case 0:
1448                        return MISCREG_ID_ISAR0_EL1;
1449                      case 1:
1450                        return MISCREG_ID_ISAR1_EL1;
1451                      case 2:
1452                        return MISCREG_ID_ISAR2_EL1;
1453                      case 3:
1454                        return MISCREG_ID_ISAR3_EL1;
1455                      case 4:
1456                        return MISCREG_ID_ISAR4_EL1;
1457                      case 5:
1458                        return MISCREG_ID_ISAR5_EL1;
1459                    }
1460                    break;
1461                  case 3:
1462                    switch (op2) {
1463                      case 0:
1464                        return MISCREG_MVFR0_EL1;
1465                      case 1:
1466                        return MISCREG_MVFR1_EL1;
1467                      case 2:
1468                        return MISCREG_MVFR2_EL1;
1469                      case 3 ... 7:
1470                        return MISCREG_RAZ;
1471                    }
1472                    break;
1473                  case 4:
1474                    switch (op2) {
1475                      case 0:
1476                        return MISCREG_ID_AA64PFR0_EL1;
1477                      case 1:
1478                        return MISCREG_ID_AA64PFR1_EL1;
1479                      case 2 ... 7:
1480                        return MISCREG_RAZ;
1481                    }
1482                    break;
1483                  case 5:
1484                    switch (op2) {
1485                      case 0:
1486                        return MISCREG_ID_AA64DFR0_EL1;
1487                      case 1:
1488                        return MISCREG_ID_AA64DFR1_EL1;
1489                      case 4:
1490                        return MISCREG_ID_AA64AFR0_EL1;
1491                      case 5:
1492                        return MISCREG_ID_AA64AFR1_EL1;
1493                      case 2:
1494                      case 3:
1495                      case 6:
1496                      case 7:
1497                        return MISCREG_RAZ;
1498                    }
1499                    break;
1500                  case 6:
1501                    switch (op2) {
1502                      case 0:
1503                        return MISCREG_ID_AA64ISAR0_EL1;
1504                      case 1:
1505                        return MISCREG_ID_AA64ISAR1_EL1;
1506                      case 2 ... 7:
1507                        return MISCREG_RAZ;
1508                    }
1509                    break;
1510                  case 7:
1511                    switch (op2) {
1512                      case 0:
1513                        return MISCREG_ID_AA64MMFR0_EL1;
1514                      case 1:
1515                        return MISCREG_ID_AA64MMFR1_EL1;
1516                      case 2 ... 7:
1517                        return MISCREG_RAZ;
1518                    }
1519                    break;
1520                }
1521                break;
1522              case 1:
1523                switch (crm) {
1524                  case 0:
1525                    switch (op2) {
1526                      case 0:
1527                        return MISCREG_CCSIDR_EL1;
1528                      case 1:
1529                        return MISCREG_CLIDR_EL1;
1530                      case 7:
1531                        return MISCREG_AIDR_EL1;
1532                    }
1533                    break;
1534                }
1535                break;
1536              case 2:
1537                switch (crm) {
1538                  case 0:
1539                    switch (op2) {
1540                      case 0:
1541                        return MISCREG_CSSELR_EL1;
1542                    }
1543                    break;
1544                }
1545                break;
1546              case 3:
1547                switch (crm) {
1548                  case 0:
1549                    switch (op2) {
1550                      case 1:
1551                        return MISCREG_CTR_EL0;
1552                      case 7:
1553                        return MISCREG_DCZID_EL0;
1554                    }
1555                    break;
1556                }
1557                break;
1558              case 4:
1559                switch (crm) {
1560                  case 0:
1561                    switch (op2) {
1562                      case 0:
1563                        return MISCREG_VPIDR_EL2;
1564                      case 5:
1565                        return MISCREG_VMPIDR_EL2;
1566                    }
1567                    break;
1568                }
1569                break;
1570            }
1571            break;
1572          case 1:
1573            switch (op1) {
1574              case 0:
1575                switch (crm) {
1576                  case 0:
1577                    switch (op2) {
1578                      case 0:
1579                        return MISCREG_SCTLR_EL1;
1580                      case 1:
1581                        return MISCREG_ACTLR_EL1;
1582                      case 2:
1583                        return MISCREG_CPACR_EL1;
1584                    }
1585                    break;
1586                }
1587                break;
1588              case 4:
1589                switch (crm) {
1590                  case 0:
1591                    switch (op2) {
1592                      case 0:
1593                        return MISCREG_SCTLR_EL2;
1594                      case 1:
1595                        return MISCREG_ACTLR_EL2;
1596                    }
1597                    break;
1598                  case 1:
1599                    switch (op2) {
1600                      case 0:
1601                        return MISCREG_HCR_EL2;
1602                      case 1:
1603                        return MISCREG_MDCR_EL2;
1604                      case 2:
1605                        return MISCREG_CPTR_EL2;
1606                      case 3:
1607                        return MISCREG_HSTR_EL2;
1608                      case 7:
1609                        return MISCREG_HACR_EL2;
1610                    }
1611                    break;
1612                }
1613                break;
1614              case 6:
1615                switch (crm) {
1616                  case 0:
1617                    switch (op2) {
1618                      case 0:
1619                        return MISCREG_SCTLR_EL3;
1620                      case 1:
1621                        return MISCREG_ACTLR_EL3;
1622                    }
1623                    break;
1624                  case 1:
1625                    switch (op2) {
1626                      case 0:
1627                        return MISCREG_SCR_EL3;
1628                      case 1:
1629                        return MISCREG_SDER32_EL3;
1630                      case 2:
1631                        return MISCREG_CPTR_EL3;
1632                    }
1633                    break;
1634                  case 3:
1635                    switch (op2) {
1636                      case 1:
1637                        return MISCREG_MDCR_EL3;
1638                    }
1639                    break;
1640                }
1641                break;
1642            }
1643            break;
1644          case 2:
1645            switch (op1) {
1646              case 0:
1647                switch (crm) {
1648                  case 0:
1649                    switch (op2) {
1650                      case 0:
1651                        return MISCREG_TTBR0_EL1;
1652                      case 1:
1653                        return MISCREG_TTBR1_EL1;
1654                      case 2:
1655                        return MISCREG_TCR_EL1;
1656                    }
1657                    break;
1658                }
1659                break;
1660              case 4:
1661                switch (crm) {
1662                  case 0:
1663                    switch (op2) {
1664                      case 0:
1665                        return MISCREG_TTBR0_EL2;
1666                      case 2:
1667                        return MISCREG_TCR_EL2;
1668                    }
1669                    break;
1670                  case 1:
1671                    switch (op2) {
1672                      case 0:
1673                        return MISCREG_VTTBR_EL2;
1674                      case 2:
1675                        return MISCREG_VTCR_EL2;
1676                    }
1677                    break;
1678                }
1679                break;
1680              case 6:
1681                switch (crm) {
1682                  case 0:
1683                    switch (op2) {
1684                      case 0:
1685                        return MISCREG_TTBR0_EL3;
1686                      case 2:
1687                        return MISCREG_TCR_EL3;
1688                    }
1689                    break;
1690                }
1691                break;
1692            }
1693            break;
1694          case 3:
1695            switch (op1) {
1696              case 4:
1697                switch (crm) {
1698                  case 0:
1699                    switch (op2) {
1700                      case 0:
1701                        return MISCREG_DACR32_EL2;
1702                    }
1703                    break;
1704                }
1705                break;
1706            }
1707            break;
1708          case 4:
1709            switch (op1) {
1710              case 0:
1711                switch (crm) {
1712                  case 0:
1713                    switch (op2) {
1714                      case 0:
1715                        return MISCREG_SPSR_EL1;
1716                      case 1:
1717                        return MISCREG_ELR_EL1;
1718                    }
1719                    break;
1720                  case 1:
1721                    switch (op2) {
1722                      case 0:
1723                        return MISCREG_SP_EL0;
1724                    }
1725                    break;
1726                  case 2:
1727                    switch (op2) {
1728                      case 0:
1729                        return MISCREG_SPSEL;
1730                      case 2:
1731                        return MISCREG_CURRENTEL;
1732                    }
1733                    break;
1734                }
1735                break;
1736              case 3:
1737                switch (crm) {
1738                  case 2:
1739                    switch (op2) {
1740                      case 0:
1741                        return MISCREG_NZCV;
1742                      case 1:
1743                        return MISCREG_DAIF;
1744                    }
1745                    break;
1746                  case 4:
1747                    switch (op2) {
1748                      case 0:
1749                        return MISCREG_FPCR;
1750                      case 1:
1751                        return MISCREG_FPSR;
1752                    }
1753                    break;
1754                  case 5:
1755                    switch (op2) {
1756                      case 0:
1757                        return MISCREG_DSPSR_EL0;
1758                      case 1:
1759                        return MISCREG_DLR_EL0;
1760                    }
1761                    break;
1762                }
1763                break;
1764              case 4:
1765                switch (crm) {
1766                  case 0:
1767                    switch (op2) {
1768                      case 0:
1769                        return MISCREG_SPSR_EL2;
1770                      case 1:
1771                        return MISCREG_ELR_EL2;
1772                    }
1773                    break;
1774                  case 1:
1775                    switch (op2) {
1776                      case 0:
1777                        return MISCREG_SP_EL1;
1778                    }
1779                    break;
1780                  case 3:
1781                    switch (op2) {
1782                      case 0:
1783                        return MISCREG_SPSR_IRQ_AA64;
1784                      case 1:
1785                        return MISCREG_SPSR_ABT_AA64;
1786                      case 2:
1787                        return MISCREG_SPSR_UND_AA64;
1788                      case 3:
1789                        return MISCREG_SPSR_FIQ_AA64;
1790                    }
1791                    break;
1792                }
1793                break;
1794              case 6:
1795                switch (crm) {
1796                  case 0:
1797                    switch (op2) {
1798                      case 0:
1799                        return MISCREG_SPSR_EL3;
1800                      case 1:
1801                        return MISCREG_ELR_EL3;
1802                    }
1803                    break;
1804                  case 1:
1805                    switch (op2) {
1806                      case 0:
1807                        return MISCREG_SP_EL2;
1808                    }
1809                    break;
1810                }
1811                break;
1812            }
1813            break;
1814          case 5:
1815            switch (op1) {
1816              case 0:
1817                switch (crm) {
1818                  case 1:
1819                    switch (op2) {
1820                      case 0:
1821                        return MISCREG_AFSR0_EL1;
1822                      case 1:
1823                        return MISCREG_AFSR1_EL1;
1824                    }
1825                    break;
1826                  case 2:
1827                    switch (op2) {
1828                      case 0:
1829                        return MISCREG_ESR_EL1;
1830                    }
1831                    break;
1832                }
1833                break;
1834              case 4:
1835                switch (crm) {
1836                  case 0:
1837                    switch (op2) {
1838                      case 1:
1839                        return MISCREG_IFSR32_EL2;
1840                    }
1841                    break;
1842                  case 1:
1843                    switch (op2) {
1844                      case 0:
1845                        return MISCREG_AFSR0_EL2;
1846                      case 1:
1847                        return MISCREG_AFSR1_EL2;
1848                    }
1849                    break;
1850                  case 2:
1851                    switch (op2) {
1852                      case 0:
1853                        return MISCREG_ESR_EL2;
1854                    }
1855                    break;
1856                  case 3:
1857                    switch (op2) {
1858                      case 0:
1859                        return MISCREG_FPEXC32_EL2;
1860                    }
1861                    break;
1862                }
1863                break;
1864              case 6:
1865                switch (crm) {
1866                  case 1:
1867                    switch (op2) {
1868                      case 0:
1869                        return MISCREG_AFSR0_EL3;
1870                      case 1:
1871                        return MISCREG_AFSR1_EL3;
1872                    }
1873                    break;
1874                  case 2:
1875                    switch (op2) {
1876                      case 0:
1877                        return MISCREG_ESR_EL3;
1878                    }
1879                    break;
1880                }
1881                break;
1882            }
1883            break;
1884          case 6:
1885            switch (op1) {
1886              case 0:
1887                switch (crm) {
1888                  case 0:
1889                    switch (op2) {
1890                      case 0:
1891                        return MISCREG_FAR_EL1;
1892                    }
1893                    break;
1894                }
1895                break;
1896              case 4:
1897                switch (crm) {
1898                  case 0:
1899                    switch (op2) {
1900                      case 0:
1901                        return MISCREG_FAR_EL2;
1902                      case 4:
1903                        return MISCREG_HPFAR_EL2;
1904                    }
1905                    break;
1906                }
1907                break;
1908              case 6:
1909                switch (crm) {
1910                  case 0:
1911                    switch (op2) {
1912                      case 0:
1913                        return MISCREG_FAR_EL3;
1914                    }
1915                    break;
1916                }
1917                break;
1918            }
1919            break;
1920          case 7:
1921            switch (op1) {
1922              case 0:
1923                switch (crm) {
1924                  case 4:
1925                    switch (op2) {
1926                      case 0:
1927                        return MISCREG_PAR_EL1;
1928                    }
1929                    break;
1930                }
1931                break;
1932            }
1933            break;
1934          case 9:
1935            switch (op1) {
1936              case 0:
1937                switch (crm) {
1938                  case 14:
1939                    switch (op2) {
1940                      case 1:
1941                        return MISCREG_PMINTENSET_EL1;
1942                      case 2:
1943                        return MISCREG_PMINTENCLR_EL1;
1944                    }
1945                    break;
1946                }
1947                break;
1948              case 3:
1949                switch (crm) {
1950                  case 12:
1951                    switch (op2) {
1952                      case 0:
1953                        return MISCREG_PMCR_EL0;
1954                      case 1:
1955                        return MISCREG_PMCNTENSET_EL0;
1956                      case 2:
1957                        return MISCREG_PMCNTENCLR_EL0;
1958                      case 3:
1959                        return MISCREG_PMOVSCLR_EL0;
1960                      case 4:
1961                        return MISCREG_PMSWINC_EL0;
1962                      case 5:
1963                        return MISCREG_PMSELR_EL0;
1964                      case 6:
1965                        return MISCREG_PMCEID0_EL0;
1966                      case 7:
1967                        return MISCREG_PMCEID1_EL0;
1968                    }
1969                    break;
1970                  case 13:
1971                    switch (op2) {
1972                      case 0:
1973                        return MISCREG_PMCCNTR_EL0;
1974                      case 1:
1975                        return MISCREG_PMXEVTYPER_EL0;
1976                      case 2:
1977                        return MISCREG_PMXEVCNTR_EL0;
1978                    }
1979                    break;
1980                  case 14:
1981                    switch (op2) {
1982                      case 0:
1983                        return MISCREG_PMUSERENR_EL0;
1984                      case 3:
1985                        return MISCREG_PMOVSSET_EL0;
1986                    }
1987                    break;
1988                }
1989                break;
1990            }
1991            break;
1992          case 10:
1993            switch (op1) {
1994              case 0:
1995                switch (crm) {
1996                  case 2:
1997                    switch (op2) {
1998                      case 0:
1999                        return MISCREG_MAIR_EL1;
2000                    }
2001                    break;
2002                  case 3:
2003                    switch (op2) {
2004                      case 0:
2005                        return MISCREG_AMAIR_EL1;
2006                    }
2007                    break;
2008                }
2009                break;
2010              case 4:
2011                switch (crm) {
2012                  case 2:
2013                    switch (op2) {
2014                      case 0:
2015                        return MISCREG_MAIR_EL2;
2016                    }
2017                    break;
2018                  case 3:
2019                    switch (op2) {
2020                      case 0:
2021                        return MISCREG_AMAIR_EL2;
2022                    }
2023                    break;
2024                }
2025                break;
2026              case 6:
2027                switch (crm) {
2028                  case 2:
2029                    switch (op2) {
2030                      case 0:
2031                        return MISCREG_MAIR_EL3;
2032                    }
2033                    break;
2034                  case 3:
2035                    switch (op2) {
2036                      case 0:
2037                        return MISCREG_AMAIR_EL3;
2038                    }
2039                    break;
2040                }
2041                break;
2042            }
2043            break;
2044          case 11:
2045            switch (op1) {
2046              case 1:
2047                switch (crm) {
2048                  case 0:
2049                    switch (op2) {
2050                      case 2:
2051                        return MISCREG_L2CTLR_EL1;
2052                      case 3:
2053                        return MISCREG_L2ECTLR_EL1;
2054                    }
2055                    break;
2056                }
2057                break;
2058            }
2059            break;
2060          case 12:
2061            switch (op1) {
2062              case 0:
2063                switch (crm) {
2064                  case 0:
2065                    switch (op2) {
2066                      case 0:
2067                        return MISCREG_VBAR_EL1;
2068                      case 1:
2069                        return MISCREG_RVBAR_EL1;
2070                    }
2071                    break;
2072                  case 1:
2073                    switch (op2) {
2074                      case 0:
2075                        return MISCREG_ISR_EL1;
2076                    }
2077                    break;
2078                }
2079                break;
2080              case 4:
2081                switch (crm) {
2082                  case 0:
2083                    switch (op2) {
2084                      case 0:
2085                        return MISCREG_VBAR_EL2;
2086                      case 1:
2087                        return MISCREG_RVBAR_EL2;
2088                    }
2089                    break;
2090                }
2091                break;
2092              case 6:
2093                switch (crm) {
2094                  case 0:
2095                    switch (op2) {
2096                      case 0:
2097                        return MISCREG_VBAR_EL3;
2098                      case 1:
2099                        return MISCREG_RVBAR_EL3;
2100                      case 2:
2101                        return MISCREG_RMR_EL3;
2102                    }
2103                    break;
2104                }
2105                break;
2106            }
2107            break;
2108          case 13:
2109            switch (op1) {
2110              case 0:
2111                switch (crm) {
2112                  case 0:
2113                    switch (op2) {
2114                      case 1:
2115                        return MISCREG_CONTEXTIDR_EL1;
2116                      case 4:
2117                        return MISCREG_TPIDR_EL1;
2118                    }
2119                    break;
2120                }
2121                break;
2122              case 3:
2123                switch (crm) {
2124                  case 0:
2125                    switch (op2) {
2126                      case 2:
2127                        return MISCREG_TPIDR_EL0;
2128                      case 3:
2129                        return MISCREG_TPIDRRO_EL0;
2130                    }
2131                    break;
2132                }
2133                break;
2134              case 4:
2135                switch (crm) {
2136                  case 0:
2137                    switch (op2) {
2138                      case 1:
2139                        return MISCREG_CONTEXTIDR_EL2;
2140                      case 2:
2141                        return MISCREG_TPIDR_EL2;
2142                    }
2143                    break;
2144                }
2145                break;
2146              case 6:
2147                switch (crm) {
2148                  case 0:
2149                    switch (op2) {
2150                      case 2:
2151                        return MISCREG_TPIDR_EL3;
2152                    }
2153                    break;
2154                }
2155                break;
2156            }
2157            break;
2158          case 14:
2159            switch (op1) {
2160              case 0:
2161                switch (crm) {
2162                  case 1:
2163                    switch (op2) {
2164                      case 0:
2165                        return MISCREG_CNTKCTL_EL1;
2166                    }
2167                    break;
2168                }
2169                break;
2170              case 3:
2171                switch (crm) {
2172                  case 0:
2173                    switch (op2) {
2174                      case 0:
2175                        return MISCREG_CNTFRQ_EL0;
2176                      case 1:
2177                        return MISCREG_CNTPCT_EL0;
2178                      case 2:
2179                        return MISCREG_CNTVCT_EL0;
2180                    }
2181                    break;
2182                  case 2:
2183                    switch (op2) {
2184                      case 0:
2185                        return MISCREG_CNTP_TVAL_EL0;
2186                      case 1:
2187                        return MISCREG_CNTP_CTL_EL0;
2188                      case 2:
2189                        return MISCREG_CNTP_CVAL_EL0;
2190                    }
2191                    break;
2192                  case 3:
2193                    switch (op2) {
2194                      case 0:
2195                        return MISCREG_CNTV_TVAL_EL0;
2196                      case 1:
2197                        return MISCREG_CNTV_CTL_EL0;
2198                      case 2:
2199                        return MISCREG_CNTV_CVAL_EL0;
2200                    }
2201                    break;
2202                  case 8:
2203                    switch (op2) {
2204                      case 0:
2205                        return MISCREG_PMEVCNTR0_EL0;
2206                      case 1:
2207                        return MISCREG_PMEVCNTR1_EL0;
2208                      case 2:
2209                        return MISCREG_PMEVCNTR2_EL0;
2210                      case 3:
2211                        return MISCREG_PMEVCNTR3_EL0;
2212                      case 4:
2213                        return MISCREG_PMEVCNTR4_EL0;
2214                      case 5:
2215                        return MISCREG_PMEVCNTR5_EL0;
2216                    }
2217                    break;
2218                  case 12:
2219                    switch (op2) {
2220                      case 0:
2221                        return MISCREG_PMEVTYPER0_EL0;
2222                      case 1:
2223                        return MISCREG_PMEVTYPER1_EL0;
2224                      case 2:
2225                        return MISCREG_PMEVTYPER2_EL0;
2226                      case 3:
2227                        return MISCREG_PMEVTYPER3_EL0;
2228                      case 4:
2229                        return MISCREG_PMEVTYPER4_EL0;
2230                      case 5:
2231                        return MISCREG_PMEVTYPER5_EL0;
2232                    }
2233                    break;
2234                  case 15:
2235                    switch (op2) {
2236                      case 7:
2237                        return MISCREG_PMCCFILTR_EL0;
2238                    }
2239                }
2240                break;
2241              case 4:
2242                switch (crm) {
2243                  case 0:
2244                    switch (op2) {
2245                      case 3:
2246                        return MISCREG_CNTVOFF_EL2;
2247                    }
2248                    break;
2249                  case 1:
2250                    switch (op2) {
2251                      case 0:
2252                        return MISCREG_CNTHCTL_EL2;
2253                    }
2254                    break;
2255                  case 2:
2256                    switch (op2) {
2257                      case 0:
2258                        return MISCREG_CNTHP_TVAL_EL2;
2259                      case 1:
2260                        return MISCREG_CNTHP_CTL_EL2;
2261                      case 2:
2262                        return MISCREG_CNTHP_CVAL_EL2;
2263                    }
2264                    break;
2265                }
2266                break;
2267              case 7:
2268                switch (crm) {
2269                  case 2:
2270                    switch (op2) {
2271                      case 0:
2272                        return MISCREG_CNTPS_TVAL_EL1;
2273                      case 1:
2274                        return MISCREG_CNTPS_CTL_EL1;
2275                      case 2:
2276                        return MISCREG_CNTPS_CVAL_EL1;
2277                    }
2278                    break;
2279                }
2280                break;
2281            }
2282            break;
2283          case 15:
2284            switch (op1) {
2285              case 0:
2286                switch (crm) {
2287                  case 0:
2288                    switch (op2) {
2289                      case 0:
2290                        return MISCREG_IL1DATA0_EL1;
2291                      case 1:
2292                        return MISCREG_IL1DATA1_EL1;
2293                      case 2:
2294                        return MISCREG_IL1DATA2_EL1;
2295                      case 3:
2296                        return MISCREG_IL1DATA3_EL1;
2297                    }
2298                    break;
2299                  case 1:
2300                    switch (op2) {
2301                      case 0:
2302                        return MISCREG_DL1DATA0_EL1;
2303                      case 1:
2304                        return MISCREG_DL1DATA1_EL1;
2305                      case 2:
2306                        return MISCREG_DL1DATA2_EL1;
2307                      case 3:
2308                        return MISCREG_DL1DATA3_EL1;
2309                      case 4:
2310                        return MISCREG_DL1DATA4_EL1;
2311                    }
2312                    break;
2313                }
2314                break;
2315              case 1:
2316                switch (crm) {
2317                  case 0:
2318                    switch (op2) {
2319                      case 0:
2320                        return MISCREG_L2ACTLR_EL1;
2321                    }
2322                    break;
2323                  case 2:
2324                    switch (op2) {
2325                      case 0:
2326                        return MISCREG_CPUACTLR_EL1;
2327                      case 1:
2328                        return MISCREG_CPUECTLR_EL1;
2329                      case 2:
2330                        return MISCREG_CPUMERRSR_EL1;
2331                      case 3:
2332                        return MISCREG_L2MERRSR_EL1;
2333                    }
2334                    break;
2335                  case 3:
2336                    switch (op2) {
2337                      case 0:
2338                        return MISCREG_CBAR_EL1;
2339
2340                    }
2341                    break;
2342                }
2343                break;
2344            }
2345            break;
2346        }
2347        break;
2348    }
2349
2350    return MISCREG_UNKNOWN;
2351}
2352
2353bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2354
2355void
2356ISA::initializeMiscRegMetadata()
2357{
2358    // the MiscReg metadata tables are shared across all instances of the
2359    // ISA object, so there's no need to initialize them multiple times.
2360    static bool completed = false;
2361    if (completed)
2362        return;
2363
2364    /**
2365     * Some registers alias with others, and therefore need to be translated.
2366     * When two mapping registers are given, they are the 32b lower and
2367     * upper halves, respectively, of the 64b register being mapped.
2368     * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2369     *
2370     * NAM = "not architecturally mandated",
2371     * from ARM DDI 0487A.i, template text
2372     * "AArch64 System register ___ can be mapped to
2373     *  AArch32 System register ___, but this is not
2374     *  architecturally mandated."
2375     */
2376
2377    InitReg(MISCREG_CPSR)
2378      .allPrivileges();
2379    InitReg(MISCREG_SPSR)
2380      .allPrivileges();
2381    InitReg(MISCREG_SPSR_FIQ)
2382      .allPrivileges();
2383    InitReg(MISCREG_SPSR_IRQ)
2384      .allPrivileges();
2385    InitReg(MISCREG_SPSR_SVC)
2386      .allPrivileges();
2387    InitReg(MISCREG_SPSR_MON)
2388      .allPrivileges();
2389    InitReg(MISCREG_SPSR_ABT)
2390      .allPrivileges();
2391    InitReg(MISCREG_SPSR_HYP)
2392      .allPrivileges();
2393    InitReg(MISCREG_SPSR_UND)
2394      .allPrivileges();
2395    InitReg(MISCREG_ELR_HYP)
2396      .allPrivileges();
2397    InitReg(MISCREG_FPSID)
2398      .allPrivileges();
2399    InitReg(MISCREG_FPSCR)
2400      .allPrivileges();
2401    InitReg(MISCREG_MVFR1)
2402      .allPrivileges();
2403    InitReg(MISCREG_MVFR0)
2404      .allPrivileges();
2405    InitReg(MISCREG_FPEXC)
2406      .allPrivileges();
2407
2408    // Helper registers
2409    InitReg(MISCREG_CPSR_MODE)
2410      .allPrivileges();
2411    InitReg(MISCREG_CPSR_Q)
2412      .allPrivileges();
2413    InitReg(MISCREG_FPSCR_EXC)
2414      .allPrivileges();
2415    InitReg(MISCREG_FPSCR_QC)
2416      .allPrivileges();
2417    InitReg(MISCREG_LOCKADDR)
2418      .allPrivileges();
2419    InitReg(MISCREG_LOCKFLAG)
2420      .allPrivileges();
2421    InitReg(MISCREG_PRRR_MAIR0)
2422      .mutex()
2423      .banked();
2424    InitReg(MISCREG_PRRR_MAIR0_NS)
2425      .mutex()
2426      .bankedChild();
2427    InitReg(MISCREG_PRRR_MAIR0_S)
2428      .mutex()
2429      .bankedChild();
2430    InitReg(MISCREG_NMRR_MAIR1)
2431      .mutex()
2432      .banked();
2433    InitReg(MISCREG_NMRR_MAIR1_NS)
2434      .mutex()
2435      .bankedChild();
2436    InitReg(MISCREG_NMRR_MAIR1_S)
2437      .mutex()
2438      .bankedChild();
2439    InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2440      .mutex();
2441    InitReg(MISCREG_SCTLR_RST)
2442      .allPrivileges();
2443    InitReg(MISCREG_SEV_MAILBOX)
2444      .allPrivileges();
2445
2446    // AArch32 CP14 registers
2447    InitReg(MISCREG_DBGDIDR)
2448      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2449    InitReg(MISCREG_DBGDSCRint)
2450      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2451    InitReg(MISCREG_DBGDCCINT)
2452      .unimplemented()
2453      .allPrivileges();
2454    InitReg(MISCREG_DBGDTRTXint)
2455      .unimplemented()
2456      .allPrivileges();
2457    InitReg(MISCREG_DBGDTRRXint)
2458      .unimplemented()
2459      .allPrivileges();
2460    InitReg(MISCREG_DBGWFAR)
2461      .unimplemented()
2462      .allPrivileges();
2463    InitReg(MISCREG_DBGVCR)
2464      .unimplemented()
2465      .allPrivileges();
2466    InitReg(MISCREG_DBGDTRRXext)
2467      .unimplemented()
2468      .allPrivileges();
2469    InitReg(MISCREG_DBGDSCRext)
2470      .unimplemented()
2471      .warnNotFail()
2472      .allPrivileges();
2473    InitReg(MISCREG_DBGDTRTXext)
2474      .unimplemented()
2475      .allPrivileges();
2476    InitReg(MISCREG_DBGOSECCR)
2477      .unimplemented()
2478      .allPrivileges();
2479    InitReg(MISCREG_DBGBVR0)
2480      .unimplemented()
2481      .allPrivileges();
2482    InitReg(MISCREG_DBGBVR1)
2483      .unimplemented()
2484      .allPrivileges();
2485    InitReg(MISCREG_DBGBVR2)
2486      .unimplemented()
2487      .allPrivileges();
2488    InitReg(MISCREG_DBGBVR3)
2489      .unimplemented()
2490      .allPrivileges();
2491    InitReg(MISCREG_DBGBVR4)
2492      .unimplemented()
2493      .allPrivileges();
2494    InitReg(MISCREG_DBGBVR5)
2495      .unimplemented()
2496      .allPrivileges();
2497    InitReg(MISCREG_DBGBCR0)
2498      .unimplemented()
2499      .allPrivileges();
2500    InitReg(MISCREG_DBGBCR1)
2501      .unimplemented()
2502      .allPrivileges();
2503    InitReg(MISCREG_DBGBCR2)
2504      .unimplemented()
2505      .allPrivileges();
2506    InitReg(MISCREG_DBGBCR3)
2507      .unimplemented()
2508      .allPrivileges();
2509    InitReg(MISCREG_DBGBCR4)
2510      .unimplemented()
2511      .allPrivileges();
2512    InitReg(MISCREG_DBGBCR5)
2513      .unimplemented()
2514      .allPrivileges();
2515    InitReg(MISCREG_DBGWVR0)
2516      .unimplemented()
2517      .allPrivileges();
2518    InitReg(MISCREG_DBGWVR1)
2519      .unimplemented()
2520      .allPrivileges();
2521    InitReg(MISCREG_DBGWVR2)
2522      .unimplemented()
2523      .allPrivileges();
2524    InitReg(MISCREG_DBGWVR3)
2525      .unimplemented()
2526      .allPrivileges();
2527    InitReg(MISCREG_DBGWCR0)
2528      .unimplemented()
2529      .allPrivileges();
2530    InitReg(MISCREG_DBGWCR1)
2531      .unimplemented()
2532      .allPrivileges();
2533    InitReg(MISCREG_DBGWCR2)
2534      .unimplemented()
2535      .allPrivileges();
2536    InitReg(MISCREG_DBGWCR3)
2537      .unimplemented()
2538      .allPrivileges();
2539    InitReg(MISCREG_DBGDRAR)
2540      .unimplemented()
2541      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2542    InitReg(MISCREG_DBGBXVR4)
2543      .unimplemented()
2544      .allPrivileges();
2545    InitReg(MISCREG_DBGBXVR5)
2546      .unimplemented()
2547      .allPrivileges();
2548    InitReg(MISCREG_DBGOSLAR)
2549      .unimplemented()
2550      .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2551    InitReg(MISCREG_DBGOSLSR)
2552      .unimplemented()
2553      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2554    InitReg(MISCREG_DBGOSDLR)
2555      .unimplemented()
2556      .allPrivileges();
2557    InitReg(MISCREG_DBGPRCR)
2558      .unimplemented()
2559      .allPrivileges();
2560    InitReg(MISCREG_DBGDSAR)
2561      .unimplemented()
2562      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2563    InitReg(MISCREG_DBGCLAIMSET)
2564      .unimplemented()
2565      .allPrivileges();
2566    InitReg(MISCREG_DBGCLAIMCLR)
2567      .unimplemented()
2568      .allPrivileges();
2569    InitReg(MISCREG_DBGAUTHSTATUS)
2570      .unimplemented()
2571      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2572    InitReg(MISCREG_DBGDEVID2)
2573      .unimplemented()
2574      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2575    InitReg(MISCREG_DBGDEVID1)
2576      .unimplemented()
2577      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2578    InitReg(MISCREG_DBGDEVID0)
2579      .unimplemented()
2580      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2581    InitReg(MISCREG_TEECR)
2582      .unimplemented()
2583      .allPrivileges();
2584    InitReg(MISCREG_JIDR)
2585      .allPrivileges();
2586    InitReg(MISCREG_TEEHBR)
2587      .allPrivileges();
2588    InitReg(MISCREG_JOSCR)
2589      .allPrivileges();
2590    InitReg(MISCREG_JMCR)
2591      .allPrivileges();
2592
2593    // AArch32 CP15 registers
2594    InitReg(MISCREG_MIDR)
2595      .allPrivileges().exceptUserMode().writes(0);
2596    InitReg(MISCREG_CTR)
2597      .allPrivileges().exceptUserMode().writes(0);
2598    InitReg(MISCREG_TCMTR)
2599      .allPrivileges().exceptUserMode().writes(0);
2600    InitReg(MISCREG_TLBTR)
2601      .allPrivileges().exceptUserMode().writes(0);
2602    InitReg(MISCREG_MPIDR)
2603      .allPrivileges().exceptUserMode().writes(0);
2604    InitReg(MISCREG_REVIDR)
2605      .unimplemented()
2606      .warnNotFail()
2607      .allPrivileges().exceptUserMode().writes(0);
2608    InitReg(MISCREG_ID_PFR0)
2609      .allPrivileges().exceptUserMode().writes(0);
2610    InitReg(MISCREG_ID_PFR1)
2611      .allPrivileges().exceptUserMode().writes(0);
2612    InitReg(MISCREG_ID_DFR0)
2613      .allPrivileges().exceptUserMode().writes(0);
2614    InitReg(MISCREG_ID_AFR0)
2615      .allPrivileges().exceptUserMode().writes(0);
2616    InitReg(MISCREG_ID_MMFR0)
2617      .allPrivileges().exceptUserMode().writes(0);
2618    InitReg(MISCREG_ID_MMFR1)
2619      .allPrivileges().exceptUserMode().writes(0);
2620    InitReg(MISCREG_ID_MMFR2)
2621      .allPrivileges().exceptUserMode().writes(0);
2622    InitReg(MISCREG_ID_MMFR3)
2623      .allPrivileges().exceptUserMode().writes(0);
2624    InitReg(MISCREG_ID_ISAR0)
2625      .allPrivileges().exceptUserMode().writes(0);
2626    InitReg(MISCREG_ID_ISAR1)
2627      .allPrivileges().exceptUserMode().writes(0);
2628    InitReg(MISCREG_ID_ISAR2)
2629      .allPrivileges().exceptUserMode().writes(0);
2630    InitReg(MISCREG_ID_ISAR3)
2631      .allPrivileges().exceptUserMode().writes(0);
2632    InitReg(MISCREG_ID_ISAR4)
2633      .allPrivileges().exceptUserMode().writes(0);
2634    InitReg(MISCREG_ID_ISAR5)
2635      .allPrivileges().exceptUserMode().writes(0);
2636    InitReg(MISCREG_CCSIDR)
2637      .allPrivileges().exceptUserMode().writes(0);
2638    InitReg(MISCREG_CLIDR)
2639      .allPrivileges().exceptUserMode().writes(0);
2640    InitReg(MISCREG_AIDR)
2641      .allPrivileges().exceptUserMode().writes(0);
2642    InitReg(MISCREG_CSSELR)
2643      .banked();
2644    InitReg(MISCREG_CSSELR_NS)
2645      .bankedChild()
2646      .nonSecure().exceptUserMode();
2647    InitReg(MISCREG_CSSELR_S)
2648      .bankedChild()
2649      .secure().exceptUserMode();
2650    InitReg(MISCREG_VPIDR)
2651      .hyp().monNonSecure();
2652    InitReg(MISCREG_VMPIDR)
2653      .hyp().monNonSecure();
2654    InitReg(MISCREG_SCTLR)
2655      .banked();
2656    InitReg(MISCREG_SCTLR_NS)
2657      .bankedChild()
2658      .nonSecure().exceptUserMode();
2659    InitReg(MISCREG_SCTLR_S)
2660      .bankedChild()
2661      .secure().exceptUserMode();
2662    InitReg(MISCREG_ACTLR)
2663      .banked();
2664    InitReg(MISCREG_ACTLR_NS)
2665      .bankedChild()
2666      .nonSecure().exceptUserMode();
2667    InitReg(MISCREG_ACTLR_S)
2668      .bankedChild()
2669      .secure().exceptUserMode();
2670    InitReg(MISCREG_CPACR)
2671      .allPrivileges().exceptUserMode();
2672    InitReg(MISCREG_SCR)
2673      .mon().secure().exceptUserMode()
2674      .res0(0xff40)  // [31:16], [6]
2675      .res1(0x0030); // [5:4]
2676    InitReg(MISCREG_SDER)
2677      .mon();
2678    InitReg(MISCREG_NSACR)
2679      .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2680    InitReg(MISCREG_HSCTLR)
2681      .hyp().monNonSecure();
2682    InitReg(MISCREG_HACTLR)
2683      .hyp().monNonSecure();
2684    InitReg(MISCREG_HCR)
2685      .hyp().monNonSecure();
2686    InitReg(MISCREG_HDCR)
2687      .hyp().monNonSecure();
2688    InitReg(MISCREG_HCPTR)
2689      .hyp().monNonSecure();
2690    InitReg(MISCREG_HSTR)
2691      .hyp().monNonSecure();
2692    InitReg(MISCREG_HACR)
2693      .unimplemented()
2694      .warnNotFail()
2695      .hyp().monNonSecure();
2696    InitReg(MISCREG_TTBR0)
2697      .banked();
2698    InitReg(MISCREG_TTBR0_NS)
2699      .bankedChild()
2700      .nonSecure().exceptUserMode();
2701    InitReg(MISCREG_TTBR0_S)
2702      .bankedChild()
2703      .secure().exceptUserMode();
2704    InitReg(MISCREG_TTBR1)
2705      .banked();
2706    InitReg(MISCREG_TTBR1_NS)
2707      .bankedChild()
2708      .nonSecure().exceptUserMode();
2709    InitReg(MISCREG_TTBR1_S)
2710      .bankedChild()
2711      .secure().exceptUserMode();
2712    InitReg(MISCREG_TTBCR)
2713      .banked();
2714    InitReg(MISCREG_TTBCR_NS)
2715      .bankedChild()
2716      .nonSecure().exceptUserMode();
2717    InitReg(MISCREG_TTBCR_S)
2718      .bankedChild()
2719      .secure().exceptUserMode();
2720    InitReg(MISCREG_HTCR)
2721      .hyp().monNonSecure();
2722    InitReg(MISCREG_VTCR)
2723      .hyp().monNonSecure();
2724    InitReg(MISCREG_DACR)
2725      .banked();
2726    InitReg(MISCREG_DACR_NS)
2727      .bankedChild()
2728      .nonSecure().exceptUserMode();
2729    InitReg(MISCREG_DACR_S)
2730      .bankedChild()
2731      .secure().exceptUserMode();
2732    InitReg(MISCREG_DFSR)
2733      .banked();
2734    InitReg(MISCREG_DFSR_NS)
2735      .bankedChild()
2736      .nonSecure().exceptUserMode();
2737    InitReg(MISCREG_DFSR_S)
2738      .bankedChild()
2739      .secure().exceptUserMode();
2740    InitReg(MISCREG_IFSR)
2741      .banked();
2742    InitReg(MISCREG_IFSR_NS)
2743      .bankedChild()
2744      .nonSecure().exceptUserMode();
2745    InitReg(MISCREG_IFSR_S)
2746      .bankedChild()
2747      .secure().exceptUserMode();
2748    InitReg(MISCREG_ADFSR)
2749      .unimplemented()
2750      .warnNotFail()
2751      .banked();
2752    InitReg(MISCREG_ADFSR_NS)
2753      .unimplemented()
2754      .warnNotFail()
2755      .bankedChild()
2756      .nonSecure().exceptUserMode();
2757    InitReg(MISCREG_ADFSR_S)
2758      .unimplemented()
2759      .warnNotFail()
2760      .bankedChild()
2761      .secure().exceptUserMode();
2762    InitReg(MISCREG_AIFSR)
2763      .unimplemented()
2764      .warnNotFail()
2765      .banked();
2766    InitReg(MISCREG_AIFSR_NS)
2767      .unimplemented()
2768      .warnNotFail()
2769      .bankedChild()
2770      .nonSecure().exceptUserMode();
2771    InitReg(MISCREG_AIFSR_S)
2772      .unimplemented()
2773      .warnNotFail()
2774      .bankedChild()
2775      .secure().exceptUserMode();
2776    InitReg(MISCREG_HADFSR)
2777      .hyp().monNonSecure();
2778    InitReg(MISCREG_HAIFSR)
2779      .hyp().monNonSecure();
2780    InitReg(MISCREG_HSR)
2781      .hyp().monNonSecure();
2782    InitReg(MISCREG_DFAR)
2783      .banked();
2784    InitReg(MISCREG_DFAR_NS)
2785      .bankedChild()
2786      .nonSecure().exceptUserMode();
2787    InitReg(MISCREG_DFAR_S)
2788      .bankedChild()
2789      .secure().exceptUserMode();
2790    InitReg(MISCREG_IFAR)
2791      .banked();
2792    InitReg(MISCREG_IFAR_NS)
2793      .bankedChild()
2794      .nonSecure().exceptUserMode();
2795    InitReg(MISCREG_IFAR_S)
2796      .bankedChild()
2797      .secure().exceptUserMode();
2798    InitReg(MISCREG_HDFAR)
2799      .hyp().monNonSecure();
2800    InitReg(MISCREG_HIFAR)
2801      .hyp().monNonSecure();
2802    InitReg(MISCREG_HPFAR)
2803      .hyp().monNonSecure();
2804    InitReg(MISCREG_ICIALLUIS)
2805      .unimplemented()
2806      .warnNotFail()
2807      .writes(1).exceptUserMode();
2808    InitReg(MISCREG_BPIALLIS)
2809      .unimplemented()
2810      .warnNotFail()
2811      .writes(1).exceptUserMode();
2812    InitReg(MISCREG_PAR)
2813      .banked();
2814    InitReg(MISCREG_PAR_NS)
2815      .bankedChild()
2816      .nonSecure().exceptUserMode();
2817    InitReg(MISCREG_PAR_S)
2818      .bankedChild()
2819      .secure().exceptUserMode();
2820    InitReg(MISCREG_ICIALLU)
2821      .writes(1).exceptUserMode();
2822    InitReg(MISCREG_ICIMVAU)
2823      .unimplemented()
2824      .warnNotFail()
2825      .writes(1).exceptUserMode();
2826    InitReg(MISCREG_CP15ISB)
2827      .writes(1);
2828    InitReg(MISCREG_BPIALL)
2829      .unimplemented()
2830      .warnNotFail()
2831      .writes(1).exceptUserMode();
2832    InitReg(MISCREG_BPIMVA)
2833      .unimplemented()
2834      .warnNotFail()
2835      .writes(1).exceptUserMode();
2836    InitReg(MISCREG_DCIMVAC)
2837      .unimplemented()
2838      .warnNotFail()
2839      .writes(1).exceptUserMode();
2840    InitReg(MISCREG_DCISW)
2841      .unimplemented()
2842      .warnNotFail()
2843      .writes(1).exceptUserMode();
2844    InitReg(MISCREG_ATS1CPR)
2845      .writes(1).exceptUserMode();
2846    InitReg(MISCREG_ATS1CPW)
2847      .writes(1).exceptUserMode();
2848    InitReg(MISCREG_ATS1CUR)
2849      .writes(1).exceptUserMode();
2850    InitReg(MISCREG_ATS1CUW)
2851      .writes(1).exceptUserMode();
2852    InitReg(MISCREG_ATS12NSOPR)
2853      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2854    InitReg(MISCREG_ATS12NSOPW)
2855      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2856    InitReg(MISCREG_ATS12NSOUR)
2857      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2858    InitReg(MISCREG_ATS12NSOUW)
2859      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2860    InitReg(MISCREG_DCCMVAC)
2861      .writes(1).exceptUserMode();
2862    InitReg(MISCREG_DCCSW)
2863      .unimplemented()
2864      .warnNotFail()
2865      .writes(1).exceptUserMode();
2866    InitReg(MISCREG_CP15DSB)
2867      .writes(1);
2868    InitReg(MISCREG_CP15DMB)
2869      .writes(1);
2870    InitReg(MISCREG_DCCMVAU)
2871      .unimplemented()
2872      .warnNotFail()
2873      .writes(1).exceptUserMode();
2874    InitReg(MISCREG_DCCIMVAC)
2875      .unimplemented()
2876      .warnNotFail()
2877      .writes(1).exceptUserMode();
2878    InitReg(MISCREG_DCCISW)
2879      .unimplemented()
2880      .warnNotFail()
2881      .writes(1).exceptUserMode();
2882    InitReg(MISCREG_ATS1HR)
2883      .monNonSecureWrite().hypWrite();
2884    InitReg(MISCREG_ATS1HW)
2885      .monNonSecureWrite().hypWrite();
2886    InitReg(MISCREG_TLBIALLIS)
2887      .writes(1).exceptUserMode();
2888    InitReg(MISCREG_TLBIMVAIS)
2889      .writes(1).exceptUserMode();
2890    InitReg(MISCREG_TLBIASIDIS)
2891      .writes(1).exceptUserMode();
2892    InitReg(MISCREG_TLBIMVAAIS)
2893      .writes(1).exceptUserMode();
2894    InitReg(MISCREG_TLBIMVALIS)
2895      .unimplemented()
2896      .writes(1).exceptUserMode();
2897    InitReg(MISCREG_TLBIMVAALIS)
2898      .unimplemented()
2899      .writes(1).exceptUserMode();
2900    InitReg(MISCREG_ITLBIALL)
2901      .writes(1).exceptUserMode();
2902    InitReg(MISCREG_ITLBIMVA)
2903      .writes(1).exceptUserMode();
2904    InitReg(MISCREG_ITLBIASID)
2905      .writes(1).exceptUserMode();
2906    InitReg(MISCREG_DTLBIALL)
2907      .writes(1).exceptUserMode();
2908    InitReg(MISCREG_DTLBIMVA)
2909      .writes(1).exceptUserMode();
2910    InitReg(MISCREG_DTLBIASID)
2911      .writes(1).exceptUserMode();
2912    InitReg(MISCREG_TLBIALL)
2913      .writes(1).exceptUserMode();
2914    InitReg(MISCREG_TLBIMVA)
2915      .writes(1).exceptUserMode();
2916    InitReg(MISCREG_TLBIASID)
2917      .writes(1).exceptUserMode();
2918    InitReg(MISCREG_TLBIMVAA)
2919      .writes(1).exceptUserMode();
2920    InitReg(MISCREG_TLBIMVAL)
2921      .unimplemented()
2922      .writes(1).exceptUserMode();
2923    InitReg(MISCREG_TLBIMVAAL)
2924      .unimplemented()
2925      .writes(1).exceptUserMode();
2926    InitReg(MISCREG_TLBIIPAS2IS)
2927      .unimplemented()
2928      .monNonSecureWrite().hypWrite();
2929    InitReg(MISCREG_TLBIIPAS2LIS)
2930      .unimplemented()
2931      .monNonSecureWrite().hypWrite();
2932    InitReg(MISCREG_TLBIALLHIS)
2933      .monNonSecureWrite().hypWrite();
2934    InitReg(MISCREG_TLBIMVAHIS)
2935      .monNonSecureWrite().hypWrite();
2936    InitReg(MISCREG_TLBIALLNSNHIS)
2937      .monNonSecureWrite().hypWrite();
2938    InitReg(MISCREG_TLBIMVALHIS)
2939      .unimplemented()
2940      .monNonSecureWrite().hypWrite();
2941    InitReg(MISCREG_TLBIIPAS2)
2942      .unimplemented()
2943      .monNonSecureWrite().hypWrite();
2944    InitReg(MISCREG_TLBIIPAS2L)
2945      .unimplemented()
2946      .monNonSecureWrite().hypWrite();
2947    InitReg(MISCREG_TLBIALLH)
2948      .monNonSecureWrite().hypWrite();
2949    InitReg(MISCREG_TLBIMVAH)
2950      .monNonSecureWrite().hypWrite();
2951    InitReg(MISCREG_TLBIALLNSNH)
2952      .monNonSecureWrite().hypWrite();
2953    InitReg(MISCREG_TLBIMVALH)
2954      .unimplemented()
2955      .monNonSecureWrite().hypWrite();
2956    InitReg(MISCREG_PMCR)
2957      .allPrivileges();
2958    InitReg(MISCREG_PMCNTENSET)
2959      .allPrivileges();
2960    InitReg(MISCREG_PMCNTENCLR)
2961      .allPrivileges();
2962    InitReg(MISCREG_PMOVSR)
2963      .allPrivileges();
2964    InitReg(MISCREG_PMSWINC)
2965      .allPrivileges();
2966    InitReg(MISCREG_PMSELR)
2967      .allPrivileges();
2968    InitReg(MISCREG_PMCEID0)
2969      .allPrivileges();
2970    InitReg(MISCREG_PMCEID1)
2971      .allPrivileges();
2972    InitReg(MISCREG_PMCCNTR)
2973      .allPrivileges();
2974    InitReg(MISCREG_PMXEVTYPER)
2975      .allPrivileges();
2976    InitReg(MISCREG_PMCCFILTR)
2977      .allPrivileges();
2978    InitReg(MISCREG_PMXEVCNTR)
2979      .allPrivileges();
2980    InitReg(MISCREG_PMUSERENR)
2981      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
2982    InitReg(MISCREG_PMINTENSET)
2983      .allPrivileges().exceptUserMode();
2984    InitReg(MISCREG_PMINTENCLR)
2985      .allPrivileges().exceptUserMode();
2986    InitReg(MISCREG_PMOVSSET)
2987      .unimplemented()
2988      .allPrivileges();
2989    InitReg(MISCREG_L2CTLR)
2990      .allPrivileges().exceptUserMode();
2991    InitReg(MISCREG_L2ECTLR)
2992      .unimplemented()
2993      .allPrivileges().exceptUserMode();
2994    InitReg(MISCREG_PRRR)
2995      .banked();
2996    InitReg(MISCREG_PRRR_NS)
2997      .bankedChild()
2998      .nonSecure().exceptUserMode();
2999    InitReg(MISCREG_PRRR_S)
3000      .bankedChild()
3001      .secure().exceptUserMode();
3002    InitReg(MISCREG_MAIR0)
3003      .banked();
3004    InitReg(MISCREG_MAIR0_NS)
3005      .bankedChild()
3006      .nonSecure().exceptUserMode();
3007    InitReg(MISCREG_MAIR0_S)
3008      .bankedChild()
3009      .secure().exceptUserMode();
3010    InitReg(MISCREG_NMRR)
3011      .banked();
3012    InitReg(MISCREG_NMRR_NS)
3013      .bankedChild()
3014      .nonSecure().exceptUserMode();
3015    InitReg(MISCREG_NMRR_S)
3016      .bankedChild()
3017      .secure().exceptUserMode();
3018    InitReg(MISCREG_MAIR1)
3019      .banked();
3020    InitReg(MISCREG_MAIR1_NS)
3021      .bankedChild()
3022      .nonSecure().exceptUserMode();
3023    InitReg(MISCREG_MAIR1_S)
3024      .bankedChild()
3025      .secure().exceptUserMode();
3026    InitReg(MISCREG_AMAIR0)
3027      .banked();
3028    InitReg(MISCREG_AMAIR0_NS)
3029      .bankedChild()
3030      .nonSecure().exceptUserMode();
3031    InitReg(MISCREG_AMAIR0_S)
3032      .bankedChild()
3033      .secure().exceptUserMode();
3034    InitReg(MISCREG_AMAIR1)
3035      .banked();
3036    InitReg(MISCREG_AMAIR1_NS)
3037      .bankedChild()
3038      .nonSecure().exceptUserMode();
3039    InitReg(MISCREG_AMAIR1_S)
3040      .bankedChild()
3041      .secure().exceptUserMode();
3042    InitReg(MISCREG_HMAIR0)
3043      .hyp().monNonSecure();
3044    InitReg(MISCREG_HMAIR1)
3045      .hyp().monNonSecure();
3046    InitReg(MISCREG_HAMAIR0)
3047      .unimplemented()
3048      .warnNotFail()
3049      .hyp().monNonSecure();
3050    InitReg(MISCREG_HAMAIR1)
3051      .unimplemented()
3052      .warnNotFail()
3053      .hyp().monNonSecure();
3054    InitReg(MISCREG_VBAR)
3055      .banked();
3056    InitReg(MISCREG_VBAR_NS)
3057      .bankedChild()
3058      .nonSecure().exceptUserMode();
3059    InitReg(MISCREG_VBAR_S)
3060      .bankedChild()
3061      .secure().exceptUserMode();
3062    InitReg(MISCREG_MVBAR)
3063      .mon().secure().exceptUserMode();
3064    InitReg(MISCREG_RMR)
3065      .unimplemented()
3066      .mon().secure().exceptUserMode();
3067    InitReg(MISCREG_ISR)
3068      .allPrivileges().exceptUserMode().writes(0);
3069    InitReg(MISCREG_HVBAR)
3070      .hyp().monNonSecure();
3071    InitReg(MISCREG_FCSEIDR)
3072      .unimplemented()
3073      .warnNotFail()
3074      .allPrivileges().exceptUserMode();
3075    InitReg(MISCREG_CONTEXTIDR)
3076      .banked();
3077    InitReg(MISCREG_CONTEXTIDR_NS)
3078      .bankedChild()
3079      .nonSecure().exceptUserMode();
3080    InitReg(MISCREG_CONTEXTIDR_S)
3081      .bankedChild()
3082      .secure().exceptUserMode();
3083    InitReg(MISCREG_TPIDRURW)
3084      .banked();
3085    InitReg(MISCREG_TPIDRURW_NS)
3086      .bankedChild()
3087      .allPrivileges().monSecure(0).privSecure(0);
3088    InitReg(MISCREG_TPIDRURW_S)
3089      .bankedChild()
3090      .secure();
3091    InitReg(MISCREG_TPIDRURO)
3092      .banked();
3093    InitReg(MISCREG_TPIDRURO_NS)
3094      .bankedChild()
3095      .allPrivileges().secure(0).userNonSecureWrite(0).userSecureRead(1);
3096    InitReg(MISCREG_TPIDRURO_S)
3097      .bankedChild()
3098      .secure().userSecureWrite(0);
3099    InitReg(MISCREG_TPIDRPRW)
3100      .banked();
3101    InitReg(MISCREG_TPIDRPRW_NS)
3102      .bankedChild()
3103      .nonSecure().exceptUserMode();
3104    InitReg(MISCREG_TPIDRPRW_S)
3105      .bankedChild()
3106      .secure().exceptUserMode();
3107    InitReg(MISCREG_HTPIDR)
3108      .hyp().monNonSecure();
3109    InitReg(MISCREG_CNTFRQ)
3110      .unverifiable()
3111      .reads(1).mon();
3112    InitReg(MISCREG_CNTKCTL)
3113      .allPrivileges().exceptUserMode();
3114    InitReg(MISCREG_CNTP_TVAL)
3115      .banked();
3116    InitReg(MISCREG_CNTP_TVAL_NS)
3117      .bankedChild()
3118      .allPrivileges().monSecure(0).privSecure(0);
3119    InitReg(MISCREG_CNTP_TVAL_S)
3120      .unimplemented()
3121      .bankedChild()
3122      .secure().user(1);
3123    InitReg(MISCREG_CNTP_CTL)
3124      .banked();
3125    InitReg(MISCREG_CNTP_CTL_NS)
3126      .bankedChild()
3127      .allPrivileges().monSecure(0).privSecure(0);
3128    InitReg(MISCREG_CNTP_CTL_S)
3129      .unimplemented()
3130      .bankedChild()
3131      .secure().user(1);
3132    InitReg(MISCREG_CNTV_TVAL)
3133      .allPrivileges();
3134    InitReg(MISCREG_CNTV_CTL)
3135      .allPrivileges();
3136    InitReg(MISCREG_CNTHCTL)
3137      .unimplemented()
3138      .hypWrite().monNonSecureRead();
3139    InitReg(MISCREG_CNTHP_TVAL)
3140      .unimplemented()
3141      .hypWrite().monNonSecureRead();
3142    InitReg(MISCREG_CNTHP_CTL)
3143      .unimplemented()
3144      .hypWrite().monNonSecureRead();
3145    InitReg(MISCREG_IL1DATA0)
3146      .unimplemented()
3147      .allPrivileges().exceptUserMode();
3148    InitReg(MISCREG_IL1DATA1)
3149      .unimplemented()
3150      .allPrivileges().exceptUserMode();
3151    InitReg(MISCREG_IL1DATA2)
3152      .unimplemented()
3153      .allPrivileges().exceptUserMode();
3154    InitReg(MISCREG_IL1DATA3)
3155      .unimplemented()
3156      .allPrivileges().exceptUserMode();
3157    InitReg(MISCREG_DL1DATA0)
3158      .unimplemented()
3159      .allPrivileges().exceptUserMode();
3160    InitReg(MISCREG_DL1DATA1)
3161      .unimplemented()
3162      .allPrivileges().exceptUserMode();
3163    InitReg(MISCREG_DL1DATA2)
3164      .unimplemented()
3165      .allPrivileges().exceptUserMode();
3166    InitReg(MISCREG_DL1DATA3)
3167      .unimplemented()
3168      .allPrivileges().exceptUserMode();
3169    InitReg(MISCREG_DL1DATA4)
3170      .unimplemented()
3171      .allPrivileges().exceptUserMode();
3172    InitReg(MISCREG_RAMINDEX)
3173      .unimplemented()
3174      .writes(1).exceptUserMode();
3175    InitReg(MISCREG_L2ACTLR)
3176      .unimplemented()
3177      .allPrivileges().exceptUserMode();
3178    InitReg(MISCREG_CBAR)
3179      .unimplemented()
3180      .allPrivileges().exceptUserMode().writes(0);
3181    InitReg(MISCREG_HTTBR)
3182      .hyp().monNonSecure();
3183    InitReg(MISCREG_VTTBR)
3184      .hyp().monNonSecure();
3185    InitReg(MISCREG_CNTPCT)
3186      .reads(1);
3187    InitReg(MISCREG_CNTVCT)
3188      .unverifiable()
3189      .reads(1);
3190    InitReg(MISCREG_CNTP_CVAL)
3191      .banked();
3192    InitReg(MISCREG_CNTP_CVAL_NS)
3193      .bankedChild()
3194      .allPrivileges().monSecure(0).privSecure(0);
3195    InitReg(MISCREG_CNTP_CVAL_S)
3196      .unimplemented()
3197      .bankedChild()
3198      .secure().user(1);
3199    InitReg(MISCREG_CNTV_CVAL)
3200      .allPrivileges();
3201    InitReg(MISCREG_CNTVOFF)
3202      .hyp().monNonSecure();
3203    InitReg(MISCREG_CNTHP_CVAL)
3204      .unimplemented()
3205      .hypWrite().monNonSecureRead();
3206    InitReg(MISCREG_CPUMERRSR)
3207      .unimplemented()
3208      .allPrivileges().exceptUserMode();
3209    InitReg(MISCREG_L2MERRSR)
3210      .unimplemented()
3211      .warnNotFail()
3212      .allPrivileges().exceptUserMode();
3213
3214    // AArch64 registers (Op0=2);
3215    InitReg(MISCREG_MDCCINT_EL1)
3216      .allPrivileges();
3217    InitReg(MISCREG_OSDTRRX_EL1)
3218      .allPrivileges()
3219      .mapsTo(MISCREG_DBGDTRRXext);
3220    InitReg(MISCREG_MDSCR_EL1)
3221      .allPrivileges()
3222      .mapsTo(MISCREG_DBGDSCRext);
3223    InitReg(MISCREG_OSDTRTX_EL1)
3224      .allPrivileges()
3225      .mapsTo(MISCREG_DBGDTRTXext);
3226    InitReg(MISCREG_OSECCR_EL1)
3227      .allPrivileges()
3228      .mapsTo(MISCREG_DBGOSECCR);
3229    InitReg(MISCREG_DBGBVR0_EL1)
3230      .allPrivileges()
3231      .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3232    InitReg(MISCREG_DBGBVR1_EL1)
3233      .allPrivileges()
3234      .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3235    InitReg(MISCREG_DBGBVR2_EL1)
3236      .allPrivileges()
3237      .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3238    InitReg(MISCREG_DBGBVR3_EL1)
3239      .allPrivileges()
3240      .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3241    InitReg(MISCREG_DBGBVR4_EL1)
3242      .allPrivileges()
3243      .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3244    InitReg(MISCREG_DBGBVR5_EL1)
3245      .allPrivileges()
3246      .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3247    InitReg(MISCREG_DBGBCR0_EL1)
3248      .allPrivileges()
3249      .mapsTo(MISCREG_DBGBCR0);
3250    InitReg(MISCREG_DBGBCR1_EL1)
3251      .allPrivileges()
3252      .mapsTo(MISCREG_DBGBCR1);
3253    InitReg(MISCREG_DBGBCR2_EL1)
3254      .allPrivileges()
3255      .mapsTo(MISCREG_DBGBCR2);
3256    InitReg(MISCREG_DBGBCR3_EL1)
3257      .allPrivileges()
3258      .mapsTo(MISCREG_DBGBCR3);
3259    InitReg(MISCREG_DBGBCR4_EL1)
3260      .allPrivileges()
3261      .mapsTo(MISCREG_DBGBCR4);
3262    InitReg(MISCREG_DBGBCR5_EL1)
3263      .allPrivileges()
3264      .mapsTo(MISCREG_DBGBCR5);
3265    InitReg(MISCREG_DBGWVR0_EL1)
3266      .allPrivileges()
3267      .mapsTo(MISCREG_DBGWVR0);
3268    InitReg(MISCREG_DBGWVR1_EL1)
3269      .allPrivileges()
3270      .mapsTo(MISCREG_DBGWVR1);
3271    InitReg(MISCREG_DBGWVR2_EL1)
3272      .allPrivileges()
3273      .mapsTo(MISCREG_DBGWVR2);
3274    InitReg(MISCREG_DBGWVR3_EL1)
3275      .allPrivileges()
3276      .mapsTo(MISCREG_DBGWVR3);
3277    InitReg(MISCREG_DBGWCR0_EL1)
3278      .allPrivileges()
3279      .mapsTo(MISCREG_DBGWCR0);
3280    InitReg(MISCREG_DBGWCR1_EL1)
3281      .allPrivileges()
3282      .mapsTo(MISCREG_DBGWCR1);
3283    InitReg(MISCREG_DBGWCR2_EL1)
3284      .allPrivileges()
3285      .mapsTo(MISCREG_DBGWCR2);
3286    InitReg(MISCREG_DBGWCR3_EL1)
3287      .allPrivileges()
3288      .mapsTo(MISCREG_DBGWCR3);
3289    InitReg(MISCREG_MDCCSR_EL0)
3290      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3291      .mapsTo(MISCREG_DBGDSCRint);
3292    InitReg(MISCREG_MDDTR_EL0)
3293      .allPrivileges();
3294    InitReg(MISCREG_MDDTRTX_EL0)
3295      .allPrivileges();
3296    InitReg(MISCREG_MDDTRRX_EL0)
3297      .allPrivileges();
3298    InitReg(MISCREG_DBGVCR32_EL2)
3299      .allPrivileges()
3300      .mapsTo(MISCREG_DBGVCR);
3301    InitReg(MISCREG_MDRAR_EL1)
3302      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3303      .mapsTo(MISCREG_DBGDRAR);
3304    InitReg(MISCREG_OSLAR_EL1)
3305      .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3306      .mapsTo(MISCREG_DBGOSLAR);
3307    InitReg(MISCREG_OSLSR_EL1)
3308      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3309      .mapsTo(MISCREG_DBGOSLSR);
3310    InitReg(MISCREG_OSDLR_EL1)
3311      .allPrivileges()
3312      .mapsTo(MISCREG_DBGOSDLR);
3313    InitReg(MISCREG_DBGPRCR_EL1)
3314      .allPrivileges()
3315      .mapsTo(MISCREG_DBGPRCR);
3316    InitReg(MISCREG_DBGCLAIMSET_EL1)
3317      .allPrivileges()
3318      .mapsTo(MISCREG_DBGCLAIMSET);
3319    InitReg(MISCREG_DBGCLAIMCLR_EL1)
3320      .allPrivileges()
3321      .mapsTo(MISCREG_DBGCLAIMCLR);
3322    InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3323      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3324      .mapsTo(MISCREG_DBGAUTHSTATUS);
3325    InitReg(MISCREG_TEECR32_EL1);
3326    InitReg(MISCREG_TEEHBR32_EL1);
3327
3328    // AArch64 registers (Op0=1,3);
3329    InitReg(MISCREG_MIDR_EL1)
3330      .allPrivileges().exceptUserMode().writes(0);
3331    InitReg(MISCREG_MPIDR_EL1)
3332      .allPrivileges().exceptUserMode().writes(0);
3333    InitReg(MISCREG_REVIDR_EL1)
3334      .allPrivileges().exceptUserMode().writes(0);
3335    InitReg(MISCREG_ID_PFR0_EL1)
3336      .allPrivileges().exceptUserMode().writes(0);
3337    InitReg(MISCREG_ID_PFR1_EL1)
3338      .allPrivileges().exceptUserMode().writes(0);
3339    InitReg(MISCREG_ID_DFR0_EL1)
3340      .allPrivileges().exceptUserMode().writes(0)
3341      .mapsTo(MISCREG_ID_DFR0);
3342    InitReg(MISCREG_ID_AFR0_EL1)
3343      .allPrivileges().exceptUserMode().writes(0);
3344    InitReg(MISCREG_ID_MMFR0_EL1)
3345      .allPrivileges().exceptUserMode().writes(0);
3346    InitReg(MISCREG_ID_MMFR1_EL1)
3347      .allPrivileges().exceptUserMode().writes(0);
3348    InitReg(MISCREG_ID_MMFR2_EL1)
3349      .allPrivileges().exceptUserMode().writes(0);
3350    InitReg(MISCREG_ID_MMFR3_EL1)
3351      .allPrivileges().exceptUserMode().writes(0);
3352    InitReg(MISCREG_ID_ISAR0_EL1)
3353      .allPrivileges().exceptUserMode().writes(0);
3354    InitReg(MISCREG_ID_ISAR1_EL1)
3355      .allPrivileges().exceptUserMode().writes(0);
3356    InitReg(MISCREG_ID_ISAR2_EL1)
3357      .allPrivileges().exceptUserMode().writes(0);
3358    InitReg(MISCREG_ID_ISAR3_EL1)
3359      .allPrivileges().exceptUserMode().writes(0);
3360    InitReg(MISCREG_ID_ISAR4_EL1)
3361      .allPrivileges().exceptUserMode().writes(0);
3362    InitReg(MISCREG_ID_ISAR5_EL1)
3363      .allPrivileges().exceptUserMode().writes(0);
3364    InitReg(MISCREG_MVFR0_EL1)
3365      .allPrivileges().exceptUserMode().writes(0);
3366    InitReg(MISCREG_MVFR1_EL1)
3367      .allPrivileges().exceptUserMode().writes(0);
3368    InitReg(MISCREG_MVFR2_EL1)
3369      .allPrivileges().exceptUserMode().writes(0);
3370    InitReg(MISCREG_ID_AA64PFR0_EL1)
3371      .allPrivileges().exceptUserMode().writes(0);
3372    InitReg(MISCREG_ID_AA64PFR1_EL1)
3373      .allPrivileges().exceptUserMode().writes(0);
3374    InitReg(MISCREG_ID_AA64DFR0_EL1)
3375      .allPrivileges().exceptUserMode().writes(0);
3376    InitReg(MISCREG_ID_AA64DFR1_EL1)
3377      .allPrivileges().exceptUserMode().writes(0);
3378    InitReg(MISCREG_ID_AA64AFR0_EL1)
3379      .allPrivileges().exceptUserMode().writes(0);
3380    InitReg(MISCREG_ID_AA64AFR1_EL1)
3381      .allPrivileges().exceptUserMode().writes(0);
3382    InitReg(MISCREG_ID_AA64ISAR0_EL1)
3383      .allPrivileges().exceptUserMode().writes(0);
3384    InitReg(MISCREG_ID_AA64ISAR1_EL1)
3385      .allPrivileges().exceptUserMode().writes(0);
3386    InitReg(MISCREG_ID_AA64MMFR0_EL1)
3387      .allPrivileges().exceptUserMode().writes(0);
3388    InitReg(MISCREG_ID_AA64MMFR1_EL1)
3389      .allPrivileges().exceptUserMode().writes(0);
3390    InitReg(MISCREG_CCSIDR_EL1)
3391      .allPrivileges().exceptUserMode().writes(0);
3392    InitReg(MISCREG_CLIDR_EL1)
3393      .allPrivileges().exceptUserMode().writes(0);
3394    InitReg(MISCREG_AIDR_EL1)
3395      .allPrivileges().exceptUserMode().writes(0);
3396    InitReg(MISCREG_CSSELR_EL1)
3397      .allPrivileges().exceptUserMode()
3398      .mapsTo(MISCREG_CSSELR_NS);
3399    InitReg(MISCREG_CTR_EL0)
3400      .reads(1);
3401    InitReg(MISCREG_DCZID_EL0)
3402      .reads(1);
3403    InitReg(MISCREG_VPIDR_EL2)
3404      .hyp().mon()
3405      .mapsTo(MISCREG_VPIDR);
3406    InitReg(MISCREG_VMPIDR_EL2)
3407      .hyp().mon()
3408      .mapsTo(MISCREG_VMPIDR);
3409    InitReg(MISCREG_SCTLR_EL1)
3410      .allPrivileges().exceptUserMode()
3411      .mapsTo(MISCREG_SCTLR_NS);
3412    InitReg(MISCREG_ACTLR_EL1)
3413      .allPrivileges().exceptUserMode()
3414      .mapsTo(MISCREG_ACTLR_NS);
3415    InitReg(MISCREG_CPACR_EL1)
3416      .allPrivileges().exceptUserMode()
3417      .mapsTo(MISCREG_CPACR);
3418    InitReg(MISCREG_SCTLR_EL2)
3419      .hyp().mon()
3420      .mapsTo(MISCREG_HSCTLR);
3421    InitReg(MISCREG_ACTLR_EL2)
3422      .hyp().mon()
3423      .mapsTo(MISCREG_HACTLR);
3424    InitReg(MISCREG_HCR_EL2)
3425      .hyp().mon()
3426      .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3427    InitReg(MISCREG_MDCR_EL2)
3428      .hyp().mon()
3429      .mapsTo(MISCREG_HDCR);
3430    InitReg(MISCREG_CPTR_EL2)
3431      .hyp().mon()
3432      .mapsTo(MISCREG_HCPTR);
3433    InitReg(MISCREG_HSTR_EL2)
3434      .hyp().mon()
3435      .mapsTo(MISCREG_HSTR);
3436    InitReg(MISCREG_HACR_EL2)
3437      .hyp().mon()
3438      .mapsTo(MISCREG_HACR);
3439    InitReg(MISCREG_SCTLR_EL3)
3440      .mon();
3441    InitReg(MISCREG_ACTLR_EL3)
3442      .mon();
3443    InitReg(MISCREG_SCR_EL3)
3444      .mon()
3445      .mapsTo(MISCREG_SCR); // NAM D7-2005
3446    InitReg(MISCREG_SDER32_EL3)
3447      .mon()
3448      .mapsTo(MISCREG_SDER);
3449    InitReg(MISCREG_CPTR_EL3)
3450      .mon();
3451    InitReg(MISCREG_MDCR_EL3)
3452      .mon();
3453    InitReg(MISCREG_TTBR0_EL1)
3454      .allPrivileges().exceptUserMode()
3455      .mapsTo(MISCREG_TTBR0_NS);
3456    InitReg(MISCREG_TTBR1_EL1)
3457      .allPrivileges().exceptUserMode()
3458      .mapsTo(MISCREG_TTBR1_NS);
3459    InitReg(MISCREG_TCR_EL1)
3460      .allPrivileges().exceptUserMode()
3461      .mapsTo(MISCREG_TTBCR_NS);
3462    InitReg(MISCREG_TTBR0_EL2)
3463      .hyp().mon()
3464      .mapsTo(MISCREG_HTTBR);
3465    InitReg(MISCREG_TCR_EL2)
3466      .hyp().mon()
3467      .mapsTo(MISCREG_HTCR);
3468    InitReg(MISCREG_VTTBR_EL2)
3469      .hyp().mon()
3470      .mapsTo(MISCREG_VTTBR);
3471    InitReg(MISCREG_VTCR_EL2)
3472      .hyp().mon()
3473      .mapsTo(MISCREG_VTCR);
3474    InitReg(MISCREG_TTBR0_EL3)
3475      .mon();
3476    InitReg(MISCREG_TCR_EL3)
3477      .mon();
3478    InitReg(MISCREG_DACR32_EL2)
3479      .hyp().mon()
3480      .mapsTo(MISCREG_DACR_NS);
3481    InitReg(MISCREG_SPSR_EL1)
3482      .allPrivileges().exceptUserMode()
3483      .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3484    InitReg(MISCREG_ELR_EL1)
3485      .allPrivileges().exceptUserMode();
3486    InitReg(MISCREG_SP_EL0)
3487      .allPrivileges().exceptUserMode();
3488    InitReg(MISCREG_SPSEL)
3489      .allPrivileges().exceptUserMode();
3490    InitReg(MISCREG_CURRENTEL)
3491      .allPrivileges().exceptUserMode().writes(0);
3492    InitReg(MISCREG_NZCV)
3493      .allPrivileges();
3494    InitReg(MISCREG_DAIF)
3495      .allPrivileges();
3496    InitReg(MISCREG_FPCR)
3497      .allPrivileges();
3498    InitReg(MISCREG_FPSR)
3499      .allPrivileges();
3500    InitReg(MISCREG_DSPSR_EL0)
3501      .allPrivileges();
3502    InitReg(MISCREG_DLR_EL0)
3503      .allPrivileges();
3504    InitReg(MISCREG_SPSR_EL2)
3505      .hyp().mon()
3506      .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3507    InitReg(MISCREG_ELR_EL2)
3508      .hyp().mon();
3509    InitReg(MISCREG_SP_EL1)
3510      .hyp().mon();
3511    InitReg(MISCREG_SPSR_IRQ_AA64)
3512      .hyp().mon();
3513    InitReg(MISCREG_SPSR_ABT_AA64)
3514      .hyp().mon();
3515    InitReg(MISCREG_SPSR_UND_AA64)
3516      .hyp().mon();
3517    InitReg(MISCREG_SPSR_FIQ_AA64)
3518      .hyp().mon();
3519    InitReg(MISCREG_SPSR_EL3)
3520      .mon()
3521      .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3522    InitReg(MISCREG_ELR_EL3)
3523      .mon();
3524    InitReg(MISCREG_SP_EL2)
3525      .mon();
3526    InitReg(MISCREG_AFSR0_EL1)
3527      .allPrivileges().exceptUserMode()
3528      .mapsTo(MISCREG_ADFSR_NS);
3529    InitReg(MISCREG_AFSR1_EL1)
3530      .allPrivileges().exceptUserMode()
3531      .mapsTo(MISCREG_AIFSR_NS);
3532    InitReg(MISCREG_ESR_EL1)
3533      .allPrivileges().exceptUserMode();
3534    InitReg(MISCREG_IFSR32_EL2)
3535      .hyp().mon()
3536      .mapsTo(MISCREG_IFSR_NS);
3537    InitReg(MISCREG_AFSR0_EL2)
3538      .hyp().mon()
3539      .mapsTo(MISCREG_HADFSR);
3540    InitReg(MISCREG_AFSR1_EL2)
3541      .hyp().mon()
3542      .mapsTo(MISCREG_HAIFSR);
3543    InitReg(MISCREG_ESR_EL2)
3544      .hyp().mon()
3545      .mapsTo(MISCREG_HSR);
3546    InitReg(MISCREG_FPEXC32_EL2)
3547      .hyp().mon();
3548    InitReg(MISCREG_AFSR0_EL3)
3549      .mon();
3550    InitReg(MISCREG_AFSR1_EL3)
3551      .mon();
3552    InitReg(MISCREG_ESR_EL3)
3553      .mon();
3554    InitReg(MISCREG_FAR_EL1)
3555      .allPrivileges().exceptUserMode()
3556      .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3557    InitReg(MISCREG_FAR_EL2)
3558      .hyp().mon()
3559      .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3560    InitReg(MISCREG_HPFAR_EL2)
3561      .hyp().mon()
3562      .mapsTo(MISCREG_HPFAR);
3563    InitReg(MISCREG_FAR_EL3)
3564      .mon();
3565    InitReg(MISCREG_IC_IALLUIS)
3566      .warnNotFail()
3567      .writes(1).exceptUserMode();
3568    InitReg(MISCREG_PAR_EL1)
3569      .allPrivileges().exceptUserMode()
3570      .mapsTo(MISCREG_PAR_NS);
3571    InitReg(MISCREG_IC_IALLU)
3572      .warnNotFail()
3573      .writes(1).exceptUserMode();
3574    InitReg(MISCREG_DC_IVAC_Xt)
3575      .warnNotFail()
3576      .writes(1).exceptUserMode();
3577    InitReg(MISCREG_DC_ISW_Xt)
3578      .warnNotFail()
3579      .writes(1).exceptUserMode();
3580    InitReg(MISCREG_AT_S1E1R_Xt)
3581      .writes(1).exceptUserMode();
3582    InitReg(MISCREG_AT_S1E1W_Xt)
3583      .writes(1).exceptUserMode();
3584    InitReg(MISCREG_AT_S1E0R_Xt)
3585      .writes(1).exceptUserMode();
3586    InitReg(MISCREG_AT_S1E0W_Xt)
3587      .writes(1).exceptUserMode();
3588    InitReg(MISCREG_DC_CSW_Xt)
3589      .warnNotFail()
3590      .writes(1).exceptUserMode();
3591    InitReg(MISCREG_DC_CISW_Xt)
3592      .warnNotFail()
3593      .writes(1).exceptUserMode();
3594    InitReg(MISCREG_DC_ZVA_Xt)
3595      .warnNotFail()
3596      .writes(1).userSecureWrite(0);
3597    InitReg(MISCREG_IC_IVAU_Xt)
3598      .writes(1);
3599    InitReg(MISCREG_DC_CVAC_Xt)
3600      .warnNotFail()
3601      .writes(1);
3602    InitReg(MISCREG_DC_CVAU_Xt)
3603      .warnNotFail()
3604      .writes(1);
3605    InitReg(MISCREG_DC_CIVAC_Xt)
3606      .warnNotFail()
3607      .writes(1);
3608    InitReg(MISCREG_AT_S1E2R_Xt)
3609      .monNonSecureWrite().hypWrite();
3610    InitReg(MISCREG_AT_S1E2W_Xt)
3611      .monNonSecureWrite().hypWrite();
3612    InitReg(MISCREG_AT_S12E1R_Xt)
3613      .hypWrite().monSecureWrite().monNonSecureWrite();
3614    InitReg(MISCREG_AT_S12E1W_Xt)
3615      .hypWrite().monSecureWrite().monNonSecureWrite();
3616    InitReg(MISCREG_AT_S12E0R_Xt)
3617      .hypWrite().monSecureWrite().monNonSecureWrite();
3618    InitReg(MISCREG_AT_S12E0W_Xt)
3619      .hypWrite().monSecureWrite().monNonSecureWrite();
3620    InitReg(MISCREG_AT_S1E3R_Xt)
3621      .monSecureWrite().monNonSecureWrite();
3622    InitReg(MISCREG_AT_S1E3W_Xt)
3623      .monSecureWrite().monNonSecureWrite();
3624    InitReg(MISCREG_TLBI_VMALLE1IS)
3625      .writes(1).exceptUserMode();
3626    InitReg(MISCREG_TLBI_VAE1IS_Xt)
3627      .writes(1).exceptUserMode();
3628    InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3629      .writes(1).exceptUserMode();
3630    InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3631      .writes(1).exceptUserMode();
3632    InitReg(MISCREG_TLBI_VALE1IS_Xt)
3633      .writes(1).exceptUserMode();
3634    InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3635      .writes(1).exceptUserMode();
3636    InitReg(MISCREG_TLBI_VMALLE1)
3637      .writes(1).exceptUserMode();
3638    InitReg(MISCREG_TLBI_VAE1_Xt)
3639      .writes(1).exceptUserMode();
3640    InitReg(MISCREG_TLBI_ASIDE1_Xt)
3641      .writes(1).exceptUserMode();
3642    InitReg(MISCREG_TLBI_VAAE1_Xt)
3643      .writes(1).exceptUserMode();
3644    InitReg(MISCREG_TLBI_VALE1_Xt)
3645      .writes(1).exceptUserMode();
3646    InitReg(MISCREG_TLBI_VAALE1_Xt)
3647      .writes(1).exceptUserMode();
3648    InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3649      .hypWrite().monSecureWrite().monNonSecureWrite();
3650    InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3651      .hypWrite().monSecureWrite().monNonSecureWrite();
3652    InitReg(MISCREG_TLBI_ALLE2IS)
3653      .monNonSecureWrite().hypWrite();
3654    InitReg(MISCREG_TLBI_VAE2IS_Xt)
3655      .monNonSecureWrite().hypWrite();
3656    InitReg(MISCREG_TLBI_ALLE1IS)
3657      .hypWrite().monSecureWrite().monNonSecureWrite();
3658    InitReg(MISCREG_TLBI_VALE2IS_Xt)
3659      .monNonSecureWrite().hypWrite();
3660    InitReg(MISCREG_TLBI_VMALLS12E1IS)
3661      .hypWrite().monSecureWrite().monNonSecureWrite();
3662    InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3663      .hypWrite().monSecureWrite().monNonSecureWrite();
3664    InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3665      .hypWrite().monSecureWrite().monNonSecureWrite();
3666    InitReg(MISCREG_TLBI_ALLE2)
3667      .monNonSecureWrite().hypWrite();
3668    InitReg(MISCREG_TLBI_VAE2_Xt)
3669      .monNonSecureWrite().hypWrite();
3670    InitReg(MISCREG_TLBI_ALLE1)
3671      .hypWrite().monSecureWrite().monNonSecureWrite();
3672    InitReg(MISCREG_TLBI_VALE2_Xt)
3673      .monNonSecureWrite().hypWrite();
3674    InitReg(MISCREG_TLBI_VMALLS12E1)
3675      .hypWrite().monSecureWrite().monNonSecureWrite();
3676    InitReg(MISCREG_TLBI_ALLE3IS)
3677      .monSecureWrite().monNonSecureWrite();
3678    InitReg(MISCREG_TLBI_VAE3IS_Xt)
3679      .monSecureWrite().monNonSecureWrite();
3680    InitReg(MISCREG_TLBI_VALE3IS_Xt)
3681      .monSecureWrite().monNonSecureWrite();
3682    InitReg(MISCREG_TLBI_ALLE3)
3683      .monSecureWrite().monNonSecureWrite();
3684    InitReg(MISCREG_TLBI_VAE3_Xt)
3685      .monSecureWrite().monNonSecureWrite();
3686    InitReg(MISCREG_TLBI_VALE3_Xt)
3687      .monSecureWrite().monNonSecureWrite();
3688    InitReg(MISCREG_PMINTENSET_EL1)
3689      .allPrivileges().exceptUserMode()
3690      .mapsTo(MISCREG_PMINTENSET);
3691    InitReg(MISCREG_PMINTENCLR_EL1)
3692      .allPrivileges().exceptUserMode()
3693      .mapsTo(MISCREG_PMINTENCLR);
3694    InitReg(MISCREG_PMCR_EL0)
3695      .allPrivileges()
3696      .mapsTo(MISCREG_PMCR);
3697    InitReg(MISCREG_PMCNTENSET_EL0)
3698      .allPrivileges()
3699      .mapsTo(MISCREG_PMCNTENSET);
3700    InitReg(MISCREG_PMCNTENCLR_EL0)
3701      .allPrivileges()
3702      .mapsTo(MISCREG_PMCNTENCLR);
3703    InitReg(MISCREG_PMOVSCLR_EL0)
3704      .allPrivileges();
3705//    .mapsTo(MISCREG_PMOVSCLR);
3706    InitReg(MISCREG_PMSWINC_EL0)
3707      .writes(1).user()
3708      .mapsTo(MISCREG_PMSWINC);
3709    InitReg(MISCREG_PMSELR_EL0)
3710      .allPrivileges()
3711      .mapsTo(MISCREG_PMSELR);
3712    InitReg(MISCREG_PMCEID0_EL0)
3713      .reads(1).user()
3714      .mapsTo(MISCREG_PMCEID0);
3715    InitReg(MISCREG_PMCEID1_EL0)
3716      .reads(1).user()
3717      .mapsTo(MISCREG_PMCEID1);
3718    InitReg(MISCREG_PMCCNTR_EL0)
3719      .allPrivileges()
3720      .mapsTo(MISCREG_PMCCNTR);
3721    InitReg(MISCREG_PMXEVTYPER_EL0)
3722      .allPrivileges()
3723      .mapsTo(MISCREG_PMXEVTYPER);
3724    InitReg(MISCREG_PMCCFILTR_EL0)
3725      .allPrivileges();
3726    InitReg(MISCREG_PMXEVCNTR_EL0)
3727      .allPrivileges()
3728      .mapsTo(MISCREG_PMXEVCNTR);
3729    InitReg(MISCREG_PMUSERENR_EL0)
3730      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3731      .mapsTo(MISCREG_PMUSERENR);
3732    InitReg(MISCREG_PMOVSSET_EL0)
3733      .allPrivileges()
3734      .mapsTo(MISCREG_PMOVSSET);
3735    InitReg(MISCREG_MAIR_EL1)
3736      .allPrivileges().exceptUserMode()
3737      .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3738    InitReg(MISCREG_AMAIR_EL1)
3739      .allPrivileges().exceptUserMode()
3740      .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3741    InitReg(MISCREG_MAIR_EL2)
3742      .hyp().mon()
3743      .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3744    InitReg(MISCREG_AMAIR_EL2)
3745      .hyp().mon()
3746      .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3747    InitReg(MISCREG_MAIR_EL3)
3748      .mon();
3749    InitReg(MISCREG_AMAIR_EL3)
3750      .mon();
3751    InitReg(MISCREG_L2CTLR_EL1)
3752      .allPrivileges().exceptUserMode();
3753    InitReg(MISCREG_L2ECTLR_EL1)
3754      .allPrivileges().exceptUserMode();
3755    InitReg(MISCREG_VBAR_EL1)
3756      .allPrivileges().exceptUserMode()
3757      .mapsTo(MISCREG_VBAR_NS);
3758    InitReg(MISCREG_RVBAR_EL1)
3759      .allPrivileges().exceptUserMode().writes(0);
3760    InitReg(MISCREG_ISR_EL1)
3761      .allPrivileges().exceptUserMode().writes(0);
3762    InitReg(MISCREG_VBAR_EL2)
3763      .hyp().mon()
3764      .mapsTo(MISCREG_HVBAR);
3765    InitReg(MISCREG_RVBAR_EL2)
3766      .mon().hyp().writes(0);
3767    InitReg(MISCREG_VBAR_EL3)
3768      .mon();
3769    InitReg(MISCREG_RVBAR_EL3)
3770      .mon().writes(0);
3771    InitReg(MISCREG_RMR_EL3)
3772      .mon();
3773    InitReg(MISCREG_CONTEXTIDR_EL1)
3774      .allPrivileges().exceptUserMode()
3775      .mapsTo(MISCREG_CONTEXTIDR_NS);
3776    InitReg(MISCREG_TPIDR_EL1)
3777      .allPrivileges().exceptUserMode()
3778      .mapsTo(MISCREG_TPIDRPRW_NS);
3779    InitReg(MISCREG_TPIDR_EL0)
3780      .allPrivileges()
3781      .mapsTo(MISCREG_TPIDRURW_NS);
3782    InitReg(MISCREG_TPIDRRO_EL0)
3783      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3784      .mapsTo(MISCREG_TPIDRURO_NS);
3785    InitReg(MISCREG_TPIDR_EL2)
3786      .hyp().mon()
3787      .mapsTo(MISCREG_HTPIDR);
3788    InitReg(MISCREG_TPIDR_EL3)
3789      .mon();
3790    InitReg(MISCREG_CNTKCTL_EL1)
3791      .allPrivileges().exceptUserMode()
3792      .mapsTo(MISCREG_CNTKCTL);
3793    InitReg(MISCREG_CNTFRQ_EL0)
3794      .reads(1).mon()
3795      .mapsTo(MISCREG_CNTFRQ);
3796    InitReg(MISCREG_CNTPCT_EL0)
3797      .reads(1)
3798      .mapsTo(MISCREG_CNTPCT); /* 64b */
3799    InitReg(MISCREG_CNTVCT_EL0)
3800      .unverifiable()
3801      .reads(1)
3802      .mapsTo(MISCREG_CNTVCT); /* 64b */
3803    InitReg(MISCREG_CNTP_TVAL_EL0)
3804      .allPrivileges()
3805      .mapsTo(MISCREG_CNTP_TVAL_NS);
3806    InitReg(MISCREG_CNTP_CTL_EL0)
3807      .allPrivileges()
3808      .mapsTo(MISCREG_CNTP_CTL_NS);
3809    InitReg(MISCREG_CNTP_CVAL_EL0)
3810      .allPrivileges()
3811      .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
3812    InitReg(MISCREG_CNTV_TVAL_EL0)
3813      .allPrivileges()
3814      .mapsTo(MISCREG_CNTV_TVAL);
3815    InitReg(MISCREG_CNTV_CTL_EL0)
3816      .allPrivileges()
3817      .mapsTo(MISCREG_CNTV_CTL);
3818    InitReg(MISCREG_CNTV_CVAL_EL0)
3819      .allPrivileges()
3820      .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
3821    InitReg(MISCREG_PMEVCNTR0_EL0)
3822      .allPrivileges();
3823//    .mapsTo(MISCREG_PMEVCNTR0);
3824    InitReg(MISCREG_PMEVCNTR1_EL0)
3825      .allPrivileges();
3826//    .mapsTo(MISCREG_PMEVCNTR1);
3827    InitReg(MISCREG_PMEVCNTR2_EL0)
3828      .allPrivileges();
3829//    .mapsTo(MISCREG_PMEVCNTR2);
3830    InitReg(MISCREG_PMEVCNTR3_EL0)
3831      .allPrivileges();
3832//    .mapsTo(MISCREG_PMEVCNTR3);
3833    InitReg(MISCREG_PMEVCNTR4_EL0)
3834      .allPrivileges();
3835//    .mapsTo(MISCREG_PMEVCNTR4);
3836    InitReg(MISCREG_PMEVCNTR5_EL0)
3837      .allPrivileges();
3838//    .mapsTo(MISCREG_PMEVCNTR5);
3839    InitReg(MISCREG_PMEVTYPER0_EL0)
3840      .allPrivileges();
3841//    .mapsTo(MISCREG_PMEVTYPER0);
3842    InitReg(MISCREG_PMEVTYPER1_EL0)
3843      .allPrivileges();
3844//    .mapsTo(MISCREG_PMEVTYPER1);
3845    InitReg(MISCREG_PMEVTYPER2_EL0)
3846      .allPrivileges();
3847//    .mapsTo(MISCREG_PMEVTYPER2);
3848    InitReg(MISCREG_PMEVTYPER3_EL0)
3849      .allPrivileges();
3850//    .mapsTo(MISCREG_PMEVTYPER3);
3851    InitReg(MISCREG_PMEVTYPER4_EL0)
3852      .allPrivileges();
3853//    .mapsTo(MISCREG_PMEVTYPER4);
3854    InitReg(MISCREG_PMEVTYPER5_EL0)
3855      .allPrivileges();
3856//    .mapsTo(MISCREG_PMEVTYPER5);
3857    InitReg(MISCREG_CNTVOFF_EL2)
3858      .hyp().mon()
3859      .mapsTo(MISCREG_CNTVOFF); /* 64b */
3860    InitReg(MISCREG_CNTHCTL_EL2)
3861      .unimplemented()
3862      .warnNotFail()
3863      .mon().monNonSecureWrite(0).hypWrite()
3864      .mapsTo(MISCREG_CNTHCTL);
3865    InitReg(MISCREG_CNTHP_TVAL_EL2)
3866      .unimplemented()
3867      .mon().monNonSecureWrite(0).hypWrite()
3868      .mapsTo(MISCREG_CNTHP_TVAL);
3869    InitReg(MISCREG_CNTHP_CTL_EL2)
3870      .unimplemented()
3871      .mon().monNonSecureWrite(0).hypWrite()
3872      .mapsTo(MISCREG_CNTHP_CTL);
3873    InitReg(MISCREG_CNTHP_CVAL_EL2)
3874      .unimplemented()
3875      .mon().monNonSecureWrite(0).hypWrite()
3876      .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
3877    InitReg(MISCREG_CNTPS_TVAL_EL1)
3878      .unimplemented()
3879      .mon().monNonSecureWrite(0).hypWrite();
3880    InitReg(MISCREG_CNTPS_CTL_EL1)
3881      .unimplemented()
3882      .mon().monNonSecureWrite(0).hypWrite();
3883    InitReg(MISCREG_CNTPS_CVAL_EL1)
3884      .unimplemented()
3885      .mon().monNonSecureWrite(0).hypWrite();
3886    InitReg(MISCREG_IL1DATA0_EL1)
3887      .allPrivileges().exceptUserMode();
3888    InitReg(MISCREG_IL1DATA1_EL1)
3889      .allPrivileges().exceptUserMode();
3890    InitReg(MISCREG_IL1DATA2_EL1)
3891      .allPrivileges().exceptUserMode();
3892    InitReg(MISCREG_IL1DATA3_EL1)
3893      .allPrivileges().exceptUserMode();
3894    InitReg(MISCREG_DL1DATA0_EL1)
3895      .allPrivileges().exceptUserMode();
3896    InitReg(MISCREG_DL1DATA1_EL1)
3897      .allPrivileges().exceptUserMode();
3898    InitReg(MISCREG_DL1DATA2_EL1)
3899      .allPrivileges().exceptUserMode();
3900    InitReg(MISCREG_DL1DATA3_EL1)
3901      .allPrivileges().exceptUserMode();
3902    InitReg(MISCREG_DL1DATA4_EL1)
3903      .allPrivileges().exceptUserMode();
3904    InitReg(MISCREG_L2ACTLR_EL1)
3905      .allPrivileges().exceptUserMode();
3906    InitReg(MISCREG_CPUACTLR_EL1)
3907      .allPrivileges().exceptUserMode();
3908    InitReg(MISCREG_CPUECTLR_EL1)
3909      .allPrivileges().exceptUserMode();
3910    InitReg(MISCREG_CPUMERRSR_EL1)
3911      .allPrivileges().exceptUserMode();
3912    InitReg(MISCREG_L2MERRSR_EL1)
3913      .unimplemented()
3914      .warnNotFail()
3915      .allPrivileges().exceptUserMode();
3916    InitReg(MISCREG_CBAR_EL1)
3917      .allPrivileges().exceptUserMode().writes(0);
3918    InitReg(MISCREG_CONTEXTIDR_EL2)
3919      .mon().hyp();
3920
3921    // Dummy registers
3922    InitReg(MISCREG_NOP)
3923      .allPrivileges();
3924    InitReg(MISCREG_RAZ)
3925      .allPrivileges().exceptUserMode().writes(0);
3926    InitReg(MISCREG_CP14_UNIMPL)
3927      .unimplemented()
3928      .warnNotFail();
3929    InitReg(MISCREG_CP15_UNIMPL)
3930      .unimplemented()
3931      .warnNotFail();
3932    InitReg(MISCREG_A64_UNIMPL)
3933      .unimplemented()
3934      .warnNotFail();
3935    InitReg(MISCREG_UNKNOWN);
3936
3937    // Register mappings for some unimplemented registers:
3938    // ESR_EL1 -> DFSR
3939    // RMR_EL1 -> RMR
3940    // RMR_EL2 -> HRMR
3941    // DBGDTR_EL0 -> DBGDTR{R or T}Xint
3942    // DBGDTRRX_EL0 -> DBGDTRRXint
3943    // DBGDTRTX_EL0 -> DBGDTRRXint
3944    // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
3945
3946    completed = true;
3947}
3948
3949} // namespace ArmISA
3950