miscregs.cc revision 12502:ba8a94a77482
1/* 2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 * Giacomo Gabrielli 40 */ 41 42#include "arch/arm/miscregs.hh" 43 44#include <tuple> 45 46#include "arch/arm/isa.hh" 47#include "base/logging.hh" 48#include "cpu/thread_context.hh" 49#include "sim/full_system.hh" 50 51namespace ArmISA 52{ 53 54MiscRegIndex 55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 56{ 57 switch(crn) { 58 case 0: 59 switch (opc1) { 60 case 0: 61 switch (opc2) { 62 case 0: 63 switch (crm) { 64 case 0: 65 return MISCREG_DBGDIDR; 66 case 1: 67 return MISCREG_DBGDSCRint; 68 } 69 break; 70 } 71 break; 72 case 7: 73 switch (opc2) { 74 case 0: 75 switch (crm) { 76 case 0: 77 return MISCREG_JIDR; 78 } 79 break; 80 } 81 break; 82 } 83 break; 84 case 1: 85 switch (opc1) { 86 case 6: 87 switch (crm) { 88 case 0: 89 switch (opc2) { 90 case 0: 91 return MISCREG_TEEHBR; 92 } 93 break; 94 } 95 break; 96 case 7: 97 switch (crm) { 98 case 0: 99 switch (opc2) { 100 case 0: 101 return MISCREG_JOSCR; 102 } 103 break; 104 } 105 break; 106 } 107 break; 108 case 2: 109 switch (opc1) { 110 case 7: 111 switch (crm) { 112 case 0: 113 switch (opc2) { 114 case 0: 115 return MISCREG_JMCR; 116 } 117 break; 118 } 119 break; 120 } 121 break; 122 } 123 // If we get here then it must be a register that we haven't implemented 124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 125 crn, opc1, crm, opc2); 126 return MISCREG_CP14_UNIMPL; 127} 128 129using namespace std; 130 131MiscRegIndex 132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 133{ 134 switch (crn) { 135 case 0: 136 switch (opc1) { 137 case 0: 138 switch (crm) { 139 case 0: 140 switch (opc2) { 141 case 1: 142 return MISCREG_CTR; 143 case 2: 144 return MISCREG_TCMTR; 145 case 3: 146 return MISCREG_TLBTR; 147 case 5: 148 return MISCREG_MPIDR; 149 case 6: 150 return MISCREG_REVIDR; 151 default: 152 return MISCREG_MIDR; 153 } 154 break; 155 case 1: 156 switch (opc2) { 157 case 0: 158 return MISCREG_ID_PFR0; 159 case 1: 160 return MISCREG_ID_PFR1; 161 case 2: 162 return MISCREG_ID_DFR0; 163 case 3: 164 return MISCREG_ID_AFR0; 165 case 4: 166 return MISCREG_ID_MMFR0; 167 case 5: 168 return MISCREG_ID_MMFR1; 169 case 6: 170 return MISCREG_ID_MMFR2; 171 case 7: 172 return MISCREG_ID_MMFR3; 173 } 174 break; 175 case 2: 176 switch (opc2) { 177 case 0: 178 return MISCREG_ID_ISAR0; 179 case 1: 180 return MISCREG_ID_ISAR1; 181 case 2: 182 return MISCREG_ID_ISAR2; 183 case 3: 184 return MISCREG_ID_ISAR3; 185 case 4: 186 return MISCREG_ID_ISAR4; 187 case 5: 188 return MISCREG_ID_ISAR5; 189 case 6: 190 case 7: 191 return MISCREG_RAZ; // read as zero 192 } 193 break; 194 default: 195 return MISCREG_RAZ; // read as zero 196 } 197 break; 198 case 1: 199 if (crm == 0) { 200 switch (opc2) { 201 case 0: 202 return MISCREG_CCSIDR; 203 case 1: 204 return MISCREG_CLIDR; 205 case 7: 206 return MISCREG_AIDR; 207 } 208 } 209 break; 210 case 2: 211 if (crm == 0 && opc2 == 0) { 212 return MISCREG_CSSELR; 213 } 214 break; 215 case 4: 216 if (crm == 0) { 217 if (opc2 == 0) 218 return MISCREG_VPIDR; 219 else if (opc2 == 5) 220 return MISCREG_VMPIDR; 221 } 222 break; 223 } 224 break; 225 case 1: 226 if (opc1 == 0) { 227 if (crm == 0) { 228 switch (opc2) { 229 case 0: 230 return MISCREG_SCTLR; 231 case 1: 232 return MISCREG_ACTLR; 233 case 0x2: 234 return MISCREG_CPACR; 235 } 236 } else if (crm == 1) { 237 switch (opc2) { 238 case 0: 239 return MISCREG_SCR; 240 case 1: 241 return MISCREG_SDER; 242 case 2: 243 return MISCREG_NSACR; 244 } 245 } 246 } else if (opc1 == 4) { 247 if (crm == 0) { 248 if (opc2 == 0) 249 return MISCREG_HSCTLR; 250 else if (opc2 == 1) 251 return MISCREG_HACTLR; 252 } else if (crm == 1) { 253 switch (opc2) { 254 case 0: 255 return MISCREG_HCR; 256 case 1: 257 return MISCREG_HDCR; 258 case 2: 259 return MISCREG_HCPTR; 260 case 3: 261 return MISCREG_HSTR; 262 case 7: 263 return MISCREG_HACR; 264 } 265 } 266 } 267 break; 268 case 2: 269 if (opc1 == 0 && crm == 0) { 270 switch (opc2) { 271 case 0: 272 return MISCREG_TTBR0; 273 case 1: 274 return MISCREG_TTBR1; 275 case 2: 276 return MISCREG_TTBCR; 277 } 278 } else if (opc1 == 4) { 279 if (crm == 0 && opc2 == 2) 280 return MISCREG_HTCR; 281 else if (crm == 1 && opc2 == 2) 282 return MISCREG_VTCR; 283 } 284 break; 285 case 3: 286 if (opc1 == 0 && crm == 0 && opc2 == 0) { 287 return MISCREG_DACR; 288 } 289 break; 290 case 5: 291 if (opc1 == 0) { 292 if (crm == 0) { 293 if (opc2 == 0) { 294 return MISCREG_DFSR; 295 } else if (opc2 == 1) { 296 return MISCREG_IFSR; 297 } 298 } else if (crm == 1) { 299 if (opc2 == 0) { 300 return MISCREG_ADFSR; 301 } else if (opc2 == 1) { 302 return MISCREG_AIFSR; 303 } 304 } 305 } else if (opc1 == 4) { 306 if (crm == 1) { 307 if (opc2 == 0) 308 return MISCREG_HADFSR; 309 else if (opc2 == 1) 310 return MISCREG_HAIFSR; 311 } else if (crm == 2 && opc2 == 0) { 312 return MISCREG_HSR; 313 } 314 } 315 break; 316 case 6: 317 if (opc1 == 0 && crm == 0) { 318 switch (opc2) { 319 case 0: 320 return MISCREG_DFAR; 321 case 2: 322 return MISCREG_IFAR; 323 } 324 } else if (opc1 == 4 && crm == 0) { 325 switch (opc2) { 326 case 0: 327 return MISCREG_HDFAR; 328 case 2: 329 return MISCREG_HIFAR; 330 case 4: 331 return MISCREG_HPFAR; 332 } 333 } 334 break; 335 case 7: 336 if (opc1 == 0) { 337 switch (crm) { 338 case 0: 339 if (opc2 == 4) { 340 return MISCREG_NOP; 341 } 342 break; 343 case 1: 344 switch (opc2) { 345 case 0: 346 return MISCREG_ICIALLUIS; 347 case 6: 348 return MISCREG_BPIALLIS; 349 } 350 break; 351 case 4: 352 if (opc2 == 0) { 353 return MISCREG_PAR; 354 } 355 break; 356 case 5: 357 switch (opc2) { 358 case 0: 359 return MISCREG_ICIALLU; 360 case 1: 361 return MISCREG_ICIMVAU; 362 case 4: 363 return MISCREG_CP15ISB; 364 case 6: 365 return MISCREG_BPIALL; 366 case 7: 367 return MISCREG_BPIMVA; 368 } 369 break; 370 case 6: 371 if (opc2 == 1) { 372 return MISCREG_DCIMVAC; 373 } else if (opc2 == 2) { 374 return MISCREG_DCISW; 375 } 376 break; 377 case 8: 378 switch (opc2) { 379 case 0: 380 return MISCREG_ATS1CPR; 381 case 1: 382 return MISCREG_ATS1CPW; 383 case 2: 384 return MISCREG_ATS1CUR; 385 case 3: 386 return MISCREG_ATS1CUW; 387 case 4: 388 return MISCREG_ATS12NSOPR; 389 case 5: 390 return MISCREG_ATS12NSOPW; 391 case 6: 392 return MISCREG_ATS12NSOUR; 393 case 7: 394 return MISCREG_ATS12NSOUW; 395 } 396 break; 397 case 10: 398 switch (opc2) { 399 case 1: 400 return MISCREG_DCCMVAC; 401 case 2: 402 return MISCREG_DCCSW; 403 case 4: 404 return MISCREG_CP15DSB; 405 case 5: 406 return MISCREG_CP15DMB; 407 } 408 break; 409 case 11: 410 if (opc2 == 1) { 411 return MISCREG_DCCMVAU; 412 } 413 break; 414 case 13: 415 if (opc2 == 1) { 416 return MISCREG_NOP; 417 } 418 break; 419 case 14: 420 if (opc2 == 1) { 421 return MISCREG_DCCIMVAC; 422 } else if (opc2 == 2) { 423 return MISCREG_DCCISW; 424 } 425 break; 426 } 427 } else if (opc1 == 4 && crm == 8) { 428 if (opc2 == 0) 429 return MISCREG_ATS1HR; 430 else if (opc2 == 1) 431 return MISCREG_ATS1HW; 432 } 433 break; 434 case 8: 435 if (opc1 == 0) { 436 switch (crm) { 437 case 3: 438 switch (opc2) { 439 case 0: 440 return MISCREG_TLBIALLIS; 441 case 1: 442 return MISCREG_TLBIMVAIS; 443 case 2: 444 return MISCREG_TLBIASIDIS; 445 case 3: 446 return MISCREG_TLBIMVAAIS; 447 } 448 break; 449 case 5: 450 switch (opc2) { 451 case 0: 452 return MISCREG_ITLBIALL; 453 case 1: 454 return MISCREG_ITLBIMVA; 455 case 2: 456 return MISCREG_ITLBIASID; 457 } 458 break; 459 case 6: 460 switch (opc2) { 461 case 0: 462 return MISCREG_DTLBIALL; 463 case 1: 464 return MISCREG_DTLBIMVA; 465 case 2: 466 return MISCREG_DTLBIASID; 467 } 468 break; 469 case 7: 470 switch (opc2) { 471 case 0: 472 return MISCREG_TLBIALL; 473 case 1: 474 return MISCREG_TLBIMVA; 475 case 2: 476 return MISCREG_TLBIASID; 477 case 3: 478 return MISCREG_TLBIMVAA; 479 } 480 break; 481 } 482 } else if (opc1 == 4) { 483 if (crm == 3) { 484 switch (opc2) { 485 case 0: 486 return MISCREG_TLBIALLHIS; 487 case 1: 488 return MISCREG_TLBIMVAHIS; 489 case 4: 490 return MISCREG_TLBIALLNSNHIS; 491 } 492 } else if (crm == 7) { 493 switch (opc2) { 494 case 0: 495 return MISCREG_TLBIALLH; 496 case 1: 497 return MISCREG_TLBIMVAH; 498 case 4: 499 return MISCREG_TLBIALLNSNH; 500 } 501 } 502 } 503 break; 504 case 9: 505 if (opc1 == 0) { 506 switch (crm) { 507 case 12: 508 switch (opc2) { 509 case 0: 510 return MISCREG_PMCR; 511 case 1: 512 return MISCREG_PMCNTENSET; 513 case 2: 514 return MISCREG_PMCNTENCLR; 515 case 3: 516 return MISCREG_PMOVSR; 517 case 4: 518 return MISCREG_PMSWINC; 519 case 5: 520 return MISCREG_PMSELR; 521 case 6: 522 return MISCREG_PMCEID0; 523 case 7: 524 return MISCREG_PMCEID1; 525 } 526 break; 527 case 13: 528 switch (opc2) { 529 case 0: 530 return MISCREG_PMCCNTR; 531 case 1: 532 // Selector is PMSELR.SEL 533 return MISCREG_PMXEVTYPER_PMCCFILTR; 534 case 2: 535 return MISCREG_PMXEVCNTR; 536 } 537 break; 538 case 14: 539 switch (opc2) { 540 case 0: 541 return MISCREG_PMUSERENR; 542 case 1: 543 return MISCREG_PMINTENSET; 544 case 2: 545 return MISCREG_PMINTENCLR; 546 case 3: 547 return MISCREG_PMOVSSET; 548 } 549 break; 550 } 551 } else if (opc1 == 1) { 552 switch (crm) { 553 case 0: 554 switch (opc2) { 555 case 2: // L2CTLR, L2 Control Register 556 return MISCREG_L2CTLR; 557 case 3: 558 return MISCREG_L2ECTLR; 559 } 560 break; 561 break; 562 } 563 } 564 break; 565 case 10: 566 if (opc1 == 0) { 567 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 568 if (crm == 2) { // TEX Remap Registers 569 if (opc2 == 0) { 570 // Selector is TTBCR.EAE 571 return MISCREG_PRRR_MAIR0; 572 } else if (opc2 == 1) { 573 // Selector is TTBCR.EAE 574 return MISCREG_NMRR_MAIR1; 575 } 576 } else if (crm == 3) { 577 if (opc2 == 0) { 578 return MISCREG_AMAIR0; 579 } else if (opc2 == 1) { 580 return MISCREG_AMAIR1; 581 } 582 } 583 } else if (opc1 == 4) { 584 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 585 if (crm == 2) { 586 if (opc2 == 0) 587 return MISCREG_HMAIR0; 588 else if (opc2 == 1) 589 return MISCREG_HMAIR1; 590 } else if (crm == 3) { 591 if (opc2 == 0) 592 return MISCREG_HAMAIR0; 593 else if (opc2 == 1) 594 return MISCREG_HAMAIR1; 595 } 596 } 597 break; 598 case 11: 599 if (opc1 <=7) { 600 switch (crm) { 601 case 0: 602 case 1: 603 case 2: 604 case 3: 605 case 4: 606 case 5: 607 case 6: 608 case 7: 609 case 8: 610 case 15: 611 // Reserved for DMA operations for TCM access 612 break; 613 } 614 } 615 break; 616 case 12: 617 if (opc1 == 0) { 618 if (crm == 0) { 619 if (opc2 == 0) { 620 return MISCREG_VBAR; 621 } else if (opc2 == 1) { 622 return MISCREG_MVBAR; 623 } 624 } else if (crm == 1) { 625 if (opc2 == 0) { 626 return MISCREG_ISR; 627 } 628 } 629 } else if (opc1 == 4) { 630 if (crm == 0 && opc2 == 0) 631 return MISCREG_HVBAR; 632 } 633 break; 634 case 13: 635 if (opc1 == 0) { 636 if (crm == 0) { 637 switch (opc2) { 638 case 0: 639 return MISCREG_FCSEIDR; 640 case 1: 641 return MISCREG_CONTEXTIDR; 642 case 2: 643 return MISCREG_TPIDRURW; 644 case 3: 645 return MISCREG_TPIDRURO; 646 case 4: 647 return MISCREG_TPIDRPRW; 648 } 649 } 650 } else if (opc1 == 4) { 651 if (crm == 0 && opc2 == 2) 652 return MISCREG_HTPIDR; 653 } 654 break; 655 case 14: 656 if (opc1 == 0) { 657 switch (crm) { 658 case 0: 659 if (opc2 == 0) 660 return MISCREG_CNTFRQ; 661 break; 662 case 1: 663 if (opc2 == 0) 664 return MISCREG_CNTKCTL; 665 break; 666 case 2: 667 if (opc2 == 0) 668 return MISCREG_CNTP_TVAL; 669 else if (opc2 == 1) 670 return MISCREG_CNTP_CTL; 671 break; 672 case 3: 673 if (opc2 == 0) 674 return MISCREG_CNTV_TVAL; 675 else if (opc2 == 1) 676 return MISCREG_CNTV_CTL; 677 break; 678 } 679 } else if (opc1 == 4) { 680 if (crm == 1 && opc2 == 0) { 681 return MISCREG_CNTHCTL; 682 } else if (crm == 2) { 683 if (opc2 == 0) 684 return MISCREG_CNTHP_TVAL; 685 else if (opc2 == 1) 686 return MISCREG_CNTHP_CTL; 687 } 688 } 689 break; 690 case 15: 691 // Implementation defined 692 return MISCREG_CP15_UNIMPL; 693 } 694 // Unrecognized register 695 return MISCREG_CP15_UNIMPL; 696} 697 698MiscRegIndex 699decodeCP15Reg64(unsigned crm, unsigned opc1) 700{ 701 switch (crm) { 702 case 2: 703 switch (opc1) { 704 case 0: 705 return MISCREG_TTBR0; 706 case 1: 707 return MISCREG_TTBR1; 708 case 4: 709 return MISCREG_HTTBR; 710 case 6: 711 return MISCREG_VTTBR; 712 } 713 break; 714 case 7: 715 if (opc1 == 0) 716 return MISCREG_PAR; 717 break; 718 case 14: 719 switch (opc1) { 720 case 0: 721 return MISCREG_CNTPCT; 722 case 1: 723 return MISCREG_CNTVCT; 724 case 2: 725 return MISCREG_CNTP_CVAL; 726 case 3: 727 return MISCREG_CNTV_CVAL; 728 case 4: 729 return MISCREG_CNTVOFF; 730 case 6: 731 return MISCREG_CNTHP_CVAL; 732 } 733 break; 734 case 15: 735 if (opc1 == 0) 736 return MISCREG_CPUMERRSR; 737 else if (opc1 == 1) 738 return MISCREG_L2MERRSR; 739 break; 740 } 741 // Unrecognized register 742 return MISCREG_CP15_UNIMPL; 743} 744 745std::tuple<bool, bool> 746canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 747{ 748 bool secure = !scr.ns; 749 bool canRead = false; 750 bool undefined = false; 751 752 switch (cpsr.mode) { 753 case MODE_USER: 754 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 755 miscRegInfo[reg][MISCREG_USR_NS_RD]; 756 break; 757 case MODE_FIQ: 758 case MODE_IRQ: 759 case MODE_SVC: 760 case MODE_ABORT: 761 case MODE_UNDEFINED: 762 case MODE_SYSTEM: 763 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 764 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 765 break; 766 case MODE_MON: 767 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 768 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 769 break; 770 case MODE_HYP: 771 canRead = miscRegInfo[reg][MISCREG_HYP_RD]; 772 break; 773 default: 774 undefined = true; 775 } 776 // can't do permissions checkes on the root of a banked pair of regs 777 assert(!miscRegInfo[reg][MISCREG_BANKED]); 778 return std::make_tuple(canRead, undefined); 779} 780 781std::tuple<bool, bool> 782canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 783{ 784 bool secure = !scr.ns; 785 bool canWrite = false; 786 bool undefined = false; 787 788 switch (cpsr.mode) { 789 case MODE_USER: 790 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 791 miscRegInfo[reg][MISCREG_USR_NS_WR]; 792 break; 793 case MODE_FIQ: 794 case MODE_IRQ: 795 case MODE_SVC: 796 case MODE_ABORT: 797 case MODE_UNDEFINED: 798 case MODE_SYSTEM: 799 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 800 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 801 break; 802 case MODE_MON: 803 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 804 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 805 break; 806 case MODE_HYP: 807 canWrite = miscRegInfo[reg][MISCREG_HYP_WR]; 808 break; 809 default: 810 undefined = true; 811 } 812 // can't do permissions checkes on the root of a banked pair of regs 813 assert(!miscRegInfo[reg][MISCREG_BANKED]); 814 return std::make_tuple(canWrite, undefined); 815} 816 817int 818snsBankedIndex(MiscRegIndex reg, ThreadContext *tc) 819{ 820 SCR scr = tc->readMiscReg(MISCREG_SCR); 821 return snsBankedIndex(reg, tc, scr.ns); 822} 823 824int 825snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns) 826{ 827 int reg_as_int = static_cast<int>(reg); 828 if (miscRegInfo[reg][MISCREG_BANKED]) { 829 reg_as_int += (ArmSystem::haveSecurity(tc) && 830 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1; 831 } 832 return reg_as_int; 833} 834 835 836/** 837 * If the reg is a child reg of a banked set, then the parent is the last 838 * banked one in the list. This is messy, and the wish is to eventually have 839 * the bitmap replaced with a better data structure. the preUnflatten function 840 * initializes a lookup table to speed up the search for these banked 841 * registers. 842 */ 843 844int unflattenResultMiscReg[NUM_MISCREGS]; 845 846void 847preUnflattenMiscReg() 848{ 849 int reg = -1; 850 for (int i = 0 ; i < NUM_MISCREGS; i++){ 851 if (miscRegInfo[i][MISCREG_BANKED]) 852 reg = i; 853 if (miscRegInfo[i][MISCREG_BANKED_CHILD]) 854 unflattenResultMiscReg[i] = reg; 855 else 856 unflattenResultMiscReg[i] = i; 857 // if this assert fails, no parent was found, and something is broken 858 assert(unflattenResultMiscReg[i] > -1); 859 } 860} 861 862int 863unflattenMiscReg(int reg) 864{ 865 return unflattenResultMiscReg[reg]; 866} 867 868bool 869canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 870{ 871 // Check for SP_EL0 access while SPSEL == 0 872 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 873 return false; 874 875 // Check for RVBAR access 876 if (reg == MISCREG_RVBAR_EL1) { 877 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 878 if (highest_el == EL2 || highest_el == EL3) 879 return false; 880 } 881 if (reg == MISCREG_RVBAR_EL2) { 882 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 883 if (highest_el == EL3) 884 return false; 885 } 886 887 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 888 889 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) { 890 case EL0: 891 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 892 miscRegInfo[reg][MISCREG_USR_NS_RD]; 893 case EL1: 894 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 895 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 896 case EL2: 897 return miscRegInfo[reg][MISCREG_HYP_RD]; 898 case EL3: 899 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 900 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 901 default: 902 panic("Invalid exception level"); 903 } 904} 905 906bool 907canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 908{ 909 // Check for SP_EL0 access while SPSEL == 0 910 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 911 return false; 912 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode); 913 if (reg == MISCREG_DAIF) { 914 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 915 if (el == EL0 && !sctlr.uma) 916 return false; 917 } 918 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) { 919 // In syscall-emulation mode, this test is skipped and DCZVA is always 920 // allowed at EL0 921 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 922 if (el == EL0 && !sctlr.dze) 923 return false; 924 } 925 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) { 926 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 927 if (el == EL0 && !sctlr.uci) 928 return false; 929 } 930 931 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 932 933 switch (el) { 934 case EL0: 935 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 936 miscRegInfo[reg][MISCREG_USR_NS_WR]; 937 case EL1: 938 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 939 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 940 case EL2: 941 return miscRegInfo[reg][MISCREG_HYP_WR]; 942 case EL3: 943 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 944 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 945 default: 946 panic("Invalid exception level"); 947 } 948} 949 950MiscRegIndex 951decodeAArch64SysReg(unsigned op0, unsigned op1, 952 unsigned crn, unsigned crm, 953 unsigned op2) 954{ 955 switch (op0) { 956 case 1: 957 switch (crn) { 958 case 7: 959 switch (op1) { 960 case 0: 961 switch (crm) { 962 case 1: 963 switch (op2) { 964 case 0: 965 return MISCREG_IC_IALLUIS; 966 } 967 break; 968 case 5: 969 switch (op2) { 970 case 0: 971 return MISCREG_IC_IALLU; 972 } 973 break; 974 case 6: 975 switch (op2) { 976 case 1: 977 return MISCREG_DC_IVAC_Xt; 978 case 2: 979 return MISCREG_DC_ISW_Xt; 980 } 981 break; 982 case 8: 983 switch (op2) { 984 case 0: 985 return MISCREG_AT_S1E1R_Xt; 986 case 1: 987 return MISCREG_AT_S1E1W_Xt; 988 case 2: 989 return MISCREG_AT_S1E0R_Xt; 990 case 3: 991 return MISCREG_AT_S1E0W_Xt; 992 } 993 break; 994 case 10: 995 switch (op2) { 996 case 2: 997 return MISCREG_DC_CSW_Xt; 998 } 999 break; 1000 case 14: 1001 switch (op2) { 1002 case 2: 1003 return MISCREG_DC_CISW_Xt; 1004 } 1005 break; 1006 } 1007 break; 1008 case 3: 1009 switch (crm) { 1010 case 4: 1011 switch (op2) { 1012 case 1: 1013 return MISCREG_DC_ZVA_Xt; 1014 } 1015 break; 1016 case 5: 1017 switch (op2) { 1018 case 1: 1019 return MISCREG_IC_IVAU_Xt; 1020 } 1021 break; 1022 case 10: 1023 switch (op2) { 1024 case 1: 1025 return MISCREG_DC_CVAC_Xt; 1026 } 1027 break; 1028 case 11: 1029 switch (op2) { 1030 case 1: 1031 return MISCREG_DC_CVAU_Xt; 1032 } 1033 break; 1034 case 14: 1035 switch (op2) { 1036 case 1: 1037 return MISCREG_DC_CIVAC_Xt; 1038 } 1039 break; 1040 } 1041 break; 1042 case 4: 1043 switch (crm) { 1044 case 8: 1045 switch (op2) { 1046 case 0: 1047 return MISCREG_AT_S1E2R_Xt; 1048 case 1: 1049 return MISCREG_AT_S1E2W_Xt; 1050 case 4: 1051 return MISCREG_AT_S12E1R_Xt; 1052 case 5: 1053 return MISCREG_AT_S12E1W_Xt; 1054 case 6: 1055 return MISCREG_AT_S12E0R_Xt; 1056 case 7: 1057 return MISCREG_AT_S12E0W_Xt; 1058 } 1059 break; 1060 } 1061 break; 1062 case 6: 1063 switch (crm) { 1064 case 8: 1065 switch (op2) { 1066 case 0: 1067 return MISCREG_AT_S1E3R_Xt; 1068 case 1: 1069 return MISCREG_AT_S1E3W_Xt; 1070 } 1071 break; 1072 } 1073 break; 1074 } 1075 break; 1076 case 8: 1077 switch (op1) { 1078 case 0: 1079 switch (crm) { 1080 case 3: 1081 switch (op2) { 1082 case 0: 1083 return MISCREG_TLBI_VMALLE1IS; 1084 case 1: 1085 return MISCREG_TLBI_VAE1IS_Xt; 1086 case 2: 1087 return MISCREG_TLBI_ASIDE1IS_Xt; 1088 case 3: 1089 return MISCREG_TLBI_VAAE1IS_Xt; 1090 case 5: 1091 return MISCREG_TLBI_VALE1IS_Xt; 1092 case 7: 1093 return MISCREG_TLBI_VAALE1IS_Xt; 1094 } 1095 break; 1096 case 7: 1097 switch (op2) { 1098 case 0: 1099 return MISCREG_TLBI_VMALLE1; 1100 case 1: 1101 return MISCREG_TLBI_VAE1_Xt; 1102 case 2: 1103 return MISCREG_TLBI_ASIDE1_Xt; 1104 case 3: 1105 return MISCREG_TLBI_VAAE1_Xt; 1106 case 5: 1107 return MISCREG_TLBI_VALE1_Xt; 1108 case 7: 1109 return MISCREG_TLBI_VAALE1_Xt; 1110 } 1111 break; 1112 } 1113 break; 1114 case 4: 1115 switch (crm) { 1116 case 0: 1117 switch (op2) { 1118 case 1: 1119 return MISCREG_TLBI_IPAS2E1IS_Xt; 1120 case 5: 1121 return MISCREG_TLBI_IPAS2LE1IS_Xt; 1122 } 1123 break; 1124 case 3: 1125 switch (op2) { 1126 case 0: 1127 return MISCREG_TLBI_ALLE2IS; 1128 case 1: 1129 return MISCREG_TLBI_VAE2IS_Xt; 1130 case 4: 1131 return MISCREG_TLBI_ALLE1IS; 1132 case 5: 1133 return MISCREG_TLBI_VALE2IS_Xt; 1134 case 6: 1135 return MISCREG_TLBI_VMALLS12E1IS; 1136 } 1137 break; 1138 case 4: 1139 switch (op2) { 1140 case 1: 1141 return MISCREG_TLBI_IPAS2E1_Xt; 1142 case 5: 1143 return MISCREG_TLBI_IPAS2LE1_Xt; 1144 } 1145 break; 1146 case 7: 1147 switch (op2) { 1148 case 0: 1149 return MISCREG_TLBI_ALLE2; 1150 case 1: 1151 return MISCREG_TLBI_VAE2_Xt; 1152 case 4: 1153 return MISCREG_TLBI_ALLE1; 1154 case 5: 1155 return MISCREG_TLBI_VALE2_Xt; 1156 case 6: 1157 return MISCREG_TLBI_VMALLS12E1; 1158 } 1159 break; 1160 } 1161 break; 1162 case 6: 1163 switch (crm) { 1164 case 3: 1165 switch (op2) { 1166 case 0: 1167 return MISCREG_TLBI_ALLE3IS; 1168 case 1: 1169 return MISCREG_TLBI_VAE3IS_Xt; 1170 case 5: 1171 return MISCREG_TLBI_VALE3IS_Xt; 1172 } 1173 break; 1174 case 7: 1175 switch (op2) { 1176 case 0: 1177 return MISCREG_TLBI_ALLE3; 1178 case 1: 1179 return MISCREG_TLBI_VAE3_Xt; 1180 case 5: 1181 return MISCREG_TLBI_VALE3_Xt; 1182 } 1183 break; 1184 } 1185 break; 1186 } 1187 break; 1188 } 1189 break; 1190 case 2: 1191 switch (crn) { 1192 case 0: 1193 switch (op1) { 1194 case 0: 1195 switch (crm) { 1196 case 0: 1197 switch (op2) { 1198 case 2: 1199 return MISCREG_OSDTRRX_EL1; 1200 case 4: 1201 return MISCREG_DBGBVR0_EL1; 1202 case 5: 1203 return MISCREG_DBGBCR0_EL1; 1204 case 6: 1205 return MISCREG_DBGWVR0_EL1; 1206 case 7: 1207 return MISCREG_DBGWCR0_EL1; 1208 } 1209 break; 1210 case 1: 1211 switch (op2) { 1212 case 4: 1213 return MISCREG_DBGBVR1_EL1; 1214 case 5: 1215 return MISCREG_DBGBCR1_EL1; 1216 case 6: 1217 return MISCREG_DBGWVR1_EL1; 1218 case 7: 1219 return MISCREG_DBGWCR1_EL1; 1220 } 1221 break; 1222 case 2: 1223 switch (op2) { 1224 case 0: 1225 return MISCREG_MDCCINT_EL1; 1226 case 2: 1227 return MISCREG_MDSCR_EL1; 1228 case 4: 1229 return MISCREG_DBGBVR2_EL1; 1230 case 5: 1231 return MISCREG_DBGBCR2_EL1; 1232 case 6: 1233 return MISCREG_DBGWVR2_EL1; 1234 case 7: 1235 return MISCREG_DBGWCR2_EL1; 1236 } 1237 break; 1238 case 3: 1239 switch (op2) { 1240 case 2: 1241 return MISCREG_OSDTRTX_EL1; 1242 case 4: 1243 return MISCREG_DBGBVR3_EL1; 1244 case 5: 1245 return MISCREG_DBGBCR3_EL1; 1246 case 6: 1247 return MISCREG_DBGWVR3_EL1; 1248 case 7: 1249 return MISCREG_DBGWCR3_EL1; 1250 } 1251 break; 1252 case 4: 1253 switch (op2) { 1254 case 4: 1255 return MISCREG_DBGBVR4_EL1; 1256 case 5: 1257 return MISCREG_DBGBCR4_EL1; 1258 } 1259 break; 1260 case 5: 1261 switch (op2) { 1262 case 4: 1263 return MISCREG_DBGBVR5_EL1; 1264 case 5: 1265 return MISCREG_DBGBCR5_EL1; 1266 } 1267 break; 1268 case 6: 1269 switch (op2) { 1270 case 2: 1271 return MISCREG_OSECCR_EL1; 1272 } 1273 break; 1274 } 1275 break; 1276 case 2: 1277 switch (crm) { 1278 case 0: 1279 switch (op2) { 1280 case 0: 1281 return MISCREG_TEECR32_EL1; 1282 } 1283 break; 1284 } 1285 break; 1286 case 3: 1287 switch (crm) { 1288 case 1: 1289 switch (op2) { 1290 case 0: 1291 return MISCREG_MDCCSR_EL0; 1292 } 1293 break; 1294 case 4: 1295 switch (op2) { 1296 case 0: 1297 return MISCREG_MDDTR_EL0; 1298 } 1299 break; 1300 case 5: 1301 switch (op2) { 1302 case 0: 1303 return MISCREG_MDDTRRX_EL0; 1304 } 1305 break; 1306 } 1307 break; 1308 case 4: 1309 switch (crm) { 1310 case 7: 1311 switch (op2) { 1312 case 0: 1313 return MISCREG_DBGVCR32_EL2; 1314 } 1315 break; 1316 } 1317 break; 1318 } 1319 break; 1320 case 1: 1321 switch (op1) { 1322 case 0: 1323 switch (crm) { 1324 case 0: 1325 switch (op2) { 1326 case 0: 1327 return MISCREG_MDRAR_EL1; 1328 case 4: 1329 return MISCREG_OSLAR_EL1; 1330 } 1331 break; 1332 case 1: 1333 switch (op2) { 1334 case 4: 1335 return MISCREG_OSLSR_EL1; 1336 } 1337 break; 1338 case 3: 1339 switch (op2) { 1340 case 4: 1341 return MISCREG_OSDLR_EL1; 1342 } 1343 break; 1344 case 4: 1345 switch (op2) { 1346 case 4: 1347 return MISCREG_DBGPRCR_EL1; 1348 } 1349 break; 1350 } 1351 break; 1352 case 2: 1353 switch (crm) { 1354 case 0: 1355 switch (op2) { 1356 case 0: 1357 return MISCREG_TEEHBR32_EL1; 1358 } 1359 break; 1360 } 1361 break; 1362 } 1363 break; 1364 case 7: 1365 switch (op1) { 1366 case 0: 1367 switch (crm) { 1368 case 8: 1369 switch (op2) { 1370 case 6: 1371 return MISCREG_DBGCLAIMSET_EL1; 1372 } 1373 break; 1374 case 9: 1375 switch (op2) { 1376 case 6: 1377 return MISCREG_DBGCLAIMCLR_EL1; 1378 } 1379 break; 1380 case 14: 1381 switch (op2) { 1382 case 6: 1383 return MISCREG_DBGAUTHSTATUS_EL1; 1384 } 1385 break; 1386 } 1387 break; 1388 } 1389 break; 1390 } 1391 break; 1392 case 3: 1393 switch (crn) { 1394 case 0: 1395 switch (op1) { 1396 case 0: 1397 switch (crm) { 1398 case 0: 1399 switch (op2) { 1400 case 0: 1401 return MISCREG_MIDR_EL1; 1402 case 5: 1403 return MISCREG_MPIDR_EL1; 1404 case 6: 1405 return MISCREG_REVIDR_EL1; 1406 } 1407 break; 1408 case 1: 1409 switch (op2) { 1410 case 0: 1411 return MISCREG_ID_PFR0_EL1; 1412 case 1: 1413 return MISCREG_ID_PFR1_EL1; 1414 case 2: 1415 return MISCREG_ID_DFR0_EL1; 1416 case 3: 1417 return MISCREG_ID_AFR0_EL1; 1418 case 4: 1419 return MISCREG_ID_MMFR0_EL1; 1420 case 5: 1421 return MISCREG_ID_MMFR1_EL1; 1422 case 6: 1423 return MISCREG_ID_MMFR2_EL1; 1424 case 7: 1425 return MISCREG_ID_MMFR3_EL1; 1426 } 1427 break; 1428 case 2: 1429 switch (op2) { 1430 case 0: 1431 return MISCREG_ID_ISAR0_EL1; 1432 case 1: 1433 return MISCREG_ID_ISAR1_EL1; 1434 case 2: 1435 return MISCREG_ID_ISAR2_EL1; 1436 case 3: 1437 return MISCREG_ID_ISAR3_EL1; 1438 case 4: 1439 return MISCREG_ID_ISAR4_EL1; 1440 case 5: 1441 return MISCREG_ID_ISAR5_EL1; 1442 } 1443 break; 1444 case 3: 1445 switch (op2) { 1446 case 0: 1447 return MISCREG_MVFR0_EL1; 1448 case 1: 1449 return MISCREG_MVFR1_EL1; 1450 case 2: 1451 return MISCREG_MVFR2_EL1; 1452 case 3 ... 7: 1453 return MISCREG_RAZ; 1454 } 1455 break; 1456 case 4: 1457 switch (op2) { 1458 case 0: 1459 return MISCREG_ID_AA64PFR0_EL1; 1460 case 1: 1461 return MISCREG_ID_AA64PFR1_EL1; 1462 case 2 ... 7: 1463 return MISCREG_RAZ; 1464 } 1465 break; 1466 case 5: 1467 switch (op2) { 1468 case 0: 1469 return MISCREG_ID_AA64DFR0_EL1; 1470 case 1: 1471 return MISCREG_ID_AA64DFR1_EL1; 1472 case 4: 1473 return MISCREG_ID_AA64AFR0_EL1; 1474 case 5: 1475 return MISCREG_ID_AA64AFR1_EL1; 1476 case 2: 1477 case 3: 1478 case 6: 1479 case 7: 1480 return MISCREG_RAZ; 1481 } 1482 break; 1483 case 6: 1484 switch (op2) { 1485 case 0: 1486 return MISCREG_ID_AA64ISAR0_EL1; 1487 case 1: 1488 return MISCREG_ID_AA64ISAR1_EL1; 1489 case 2 ... 7: 1490 return MISCREG_RAZ; 1491 } 1492 break; 1493 case 7: 1494 switch (op2) { 1495 case 0: 1496 return MISCREG_ID_AA64MMFR0_EL1; 1497 case 1: 1498 return MISCREG_ID_AA64MMFR1_EL1; 1499 case 2 ... 7: 1500 return MISCREG_RAZ; 1501 } 1502 break; 1503 } 1504 break; 1505 case 1: 1506 switch (crm) { 1507 case 0: 1508 switch (op2) { 1509 case 0: 1510 return MISCREG_CCSIDR_EL1; 1511 case 1: 1512 return MISCREG_CLIDR_EL1; 1513 case 7: 1514 return MISCREG_AIDR_EL1; 1515 } 1516 break; 1517 } 1518 break; 1519 case 2: 1520 switch (crm) { 1521 case 0: 1522 switch (op2) { 1523 case 0: 1524 return MISCREG_CSSELR_EL1; 1525 } 1526 break; 1527 } 1528 break; 1529 case 3: 1530 switch (crm) { 1531 case 0: 1532 switch (op2) { 1533 case 1: 1534 return MISCREG_CTR_EL0; 1535 case 7: 1536 return MISCREG_DCZID_EL0; 1537 } 1538 break; 1539 } 1540 break; 1541 case 4: 1542 switch (crm) { 1543 case 0: 1544 switch (op2) { 1545 case 0: 1546 return MISCREG_VPIDR_EL2; 1547 case 5: 1548 return MISCREG_VMPIDR_EL2; 1549 } 1550 break; 1551 } 1552 break; 1553 } 1554 break; 1555 case 1: 1556 switch (op1) { 1557 case 0: 1558 switch (crm) { 1559 case 0: 1560 switch (op2) { 1561 case 0: 1562 return MISCREG_SCTLR_EL1; 1563 case 1: 1564 return MISCREG_ACTLR_EL1; 1565 case 2: 1566 return MISCREG_CPACR_EL1; 1567 } 1568 break; 1569 } 1570 break; 1571 case 4: 1572 switch (crm) { 1573 case 0: 1574 switch (op2) { 1575 case 0: 1576 return MISCREG_SCTLR_EL2; 1577 case 1: 1578 return MISCREG_ACTLR_EL2; 1579 } 1580 break; 1581 case 1: 1582 switch (op2) { 1583 case 0: 1584 return MISCREG_HCR_EL2; 1585 case 1: 1586 return MISCREG_MDCR_EL2; 1587 case 2: 1588 return MISCREG_CPTR_EL2; 1589 case 3: 1590 return MISCREG_HSTR_EL2; 1591 case 7: 1592 return MISCREG_HACR_EL2; 1593 } 1594 break; 1595 } 1596 break; 1597 case 6: 1598 switch (crm) { 1599 case 0: 1600 switch (op2) { 1601 case 0: 1602 return MISCREG_SCTLR_EL3; 1603 case 1: 1604 return MISCREG_ACTLR_EL3; 1605 } 1606 break; 1607 case 1: 1608 switch (op2) { 1609 case 0: 1610 return MISCREG_SCR_EL3; 1611 case 1: 1612 return MISCREG_SDER32_EL3; 1613 case 2: 1614 return MISCREG_CPTR_EL3; 1615 } 1616 break; 1617 case 3: 1618 switch (op2) { 1619 case 1: 1620 return MISCREG_MDCR_EL3; 1621 } 1622 break; 1623 } 1624 break; 1625 } 1626 break; 1627 case 2: 1628 switch (op1) { 1629 case 0: 1630 switch (crm) { 1631 case 0: 1632 switch (op2) { 1633 case 0: 1634 return MISCREG_TTBR0_EL1; 1635 case 1: 1636 return MISCREG_TTBR1_EL1; 1637 case 2: 1638 return MISCREG_TCR_EL1; 1639 } 1640 break; 1641 } 1642 break; 1643 case 4: 1644 switch (crm) { 1645 case 0: 1646 switch (op2) { 1647 case 0: 1648 return MISCREG_TTBR0_EL2; 1649 case 2: 1650 return MISCREG_TCR_EL2; 1651 } 1652 break; 1653 case 1: 1654 switch (op2) { 1655 case 0: 1656 return MISCREG_VTTBR_EL2; 1657 case 2: 1658 return MISCREG_VTCR_EL2; 1659 } 1660 break; 1661 } 1662 break; 1663 case 6: 1664 switch (crm) { 1665 case 0: 1666 switch (op2) { 1667 case 0: 1668 return MISCREG_TTBR0_EL3; 1669 case 2: 1670 return MISCREG_TCR_EL3; 1671 } 1672 break; 1673 } 1674 break; 1675 } 1676 break; 1677 case 3: 1678 switch (op1) { 1679 case 4: 1680 switch (crm) { 1681 case 0: 1682 switch (op2) { 1683 case 0: 1684 return MISCREG_DACR32_EL2; 1685 } 1686 break; 1687 } 1688 break; 1689 } 1690 break; 1691 case 4: 1692 switch (op1) { 1693 case 0: 1694 switch (crm) { 1695 case 0: 1696 switch (op2) { 1697 case 0: 1698 return MISCREG_SPSR_EL1; 1699 case 1: 1700 return MISCREG_ELR_EL1; 1701 } 1702 break; 1703 case 1: 1704 switch (op2) { 1705 case 0: 1706 return MISCREG_SP_EL0; 1707 } 1708 break; 1709 case 2: 1710 switch (op2) { 1711 case 0: 1712 return MISCREG_SPSEL; 1713 case 2: 1714 return MISCREG_CURRENTEL; 1715 } 1716 break; 1717 } 1718 break; 1719 case 3: 1720 switch (crm) { 1721 case 2: 1722 switch (op2) { 1723 case 0: 1724 return MISCREG_NZCV; 1725 case 1: 1726 return MISCREG_DAIF; 1727 } 1728 break; 1729 case 4: 1730 switch (op2) { 1731 case 0: 1732 return MISCREG_FPCR; 1733 case 1: 1734 return MISCREG_FPSR; 1735 } 1736 break; 1737 case 5: 1738 switch (op2) { 1739 case 0: 1740 return MISCREG_DSPSR_EL0; 1741 case 1: 1742 return MISCREG_DLR_EL0; 1743 } 1744 break; 1745 } 1746 break; 1747 case 4: 1748 switch (crm) { 1749 case 0: 1750 switch (op2) { 1751 case 0: 1752 return MISCREG_SPSR_EL2; 1753 case 1: 1754 return MISCREG_ELR_EL2; 1755 } 1756 break; 1757 case 1: 1758 switch (op2) { 1759 case 0: 1760 return MISCREG_SP_EL1; 1761 } 1762 break; 1763 case 3: 1764 switch (op2) { 1765 case 0: 1766 return MISCREG_SPSR_IRQ_AA64; 1767 case 1: 1768 return MISCREG_SPSR_ABT_AA64; 1769 case 2: 1770 return MISCREG_SPSR_UND_AA64; 1771 case 3: 1772 return MISCREG_SPSR_FIQ_AA64; 1773 } 1774 break; 1775 } 1776 break; 1777 case 6: 1778 switch (crm) { 1779 case 0: 1780 switch (op2) { 1781 case 0: 1782 return MISCREG_SPSR_EL3; 1783 case 1: 1784 return MISCREG_ELR_EL3; 1785 } 1786 break; 1787 case 1: 1788 switch (op2) { 1789 case 0: 1790 return MISCREG_SP_EL2; 1791 } 1792 break; 1793 } 1794 break; 1795 } 1796 break; 1797 case 5: 1798 switch (op1) { 1799 case 0: 1800 switch (crm) { 1801 case 1: 1802 switch (op2) { 1803 case 0: 1804 return MISCREG_AFSR0_EL1; 1805 case 1: 1806 return MISCREG_AFSR1_EL1; 1807 } 1808 break; 1809 case 2: 1810 switch (op2) { 1811 case 0: 1812 return MISCREG_ESR_EL1; 1813 } 1814 break; 1815 } 1816 break; 1817 case 4: 1818 switch (crm) { 1819 case 0: 1820 switch (op2) { 1821 case 1: 1822 return MISCREG_IFSR32_EL2; 1823 } 1824 break; 1825 case 1: 1826 switch (op2) { 1827 case 0: 1828 return MISCREG_AFSR0_EL2; 1829 case 1: 1830 return MISCREG_AFSR1_EL2; 1831 } 1832 break; 1833 case 2: 1834 switch (op2) { 1835 case 0: 1836 return MISCREG_ESR_EL2; 1837 } 1838 break; 1839 case 3: 1840 switch (op2) { 1841 case 0: 1842 return MISCREG_FPEXC32_EL2; 1843 } 1844 break; 1845 } 1846 break; 1847 case 6: 1848 switch (crm) { 1849 case 1: 1850 switch (op2) { 1851 case 0: 1852 return MISCREG_AFSR0_EL3; 1853 case 1: 1854 return MISCREG_AFSR1_EL3; 1855 } 1856 break; 1857 case 2: 1858 switch (op2) { 1859 case 0: 1860 return MISCREG_ESR_EL3; 1861 } 1862 break; 1863 } 1864 break; 1865 } 1866 break; 1867 case 6: 1868 switch (op1) { 1869 case 0: 1870 switch (crm) { 1871 case 0: 1872 switch (op2) { 1873 case 0: 1874 return MISCREG_FAR_EL1; 1875 } 1876 break; 1877 } 1878 break; 1879 case 4: 1880 switch (crm) { 1881 case 0: 1882 switch (op2) { 1883 case 0: 1884 return MISCREG_FAR_EL2; 1885 case 4: 1886 return MISCREG_HPFAR_EL2; 1887 } 1888 break; 1889 } 1890 break; 1891 case 6: 1892 switch (crm) { 1893 case 0: 1894 switch (op2) { 1895 case 0: 1896 return MISCREG_FAR_EL3; 1897 } 1898 break; 1899 } 1900 break; 1901 } 1902 break; 1903 case 7: 1904 switch (op1) { 1905 case 0: 1906 switch (crm) { 1907 case 4: 1908 switch (op2) { 1909 case 0: 1910 return MISCREG_PAR_EL1; 1911 } 1912 break; 1913 } 1914 break; 1915 } 1916 break; 1917 case 9: 1918 switch (op1) { 1919 case 0: 1920 switch (crm) { 1921 case 14: 1922 switch (op2) { 1923 case 1: 1924 return MISCREG_PMINTENSET_EL1; 1925 case 2: 1926 return MISCREG_PMINTENCLR_EL1; 1927 } 1928 break; 1929 } 1930 break; 1931 case 3: 1932 switch (crm) { 1933 case 12: 1934 switch (op2) { 1935 case 0: 1936 return MISCREG_PMCR_EL0; 1937 case 1: 1938 return MISCREG_PMCNTENSET_EL0; 1939 case 2: 1940 return MISCREG_PMCNTENCLR_EL0; 1941 case 3: 1942 return MISCREG_PMOVSCLR_EL0; 1943 case 4: 1944 return MISCREG_PMSWINC_EL0; 1945 case 5: 1946 return MISCREG_PMSELR_EL0; 1947 case 6: 1948 return MISCREG_PMCEID0_EL0; 1949 case 7: 1950 return MISCREG_PMCEID1_EL0; 1951 } 1952 break; 1953 case 13: 1954 switch (op2) { 1955 case 0: 1956 return MISCREG_PMCCNTR_EL0; 1957 case 1: 1958 return MISCREG_PMXEVTYPER_EL0; 1959 case 2: 1960 return MISCREG_PMXEVCNTR_EL0; 1961 } 1962 break; 1963 case 14: 1964 switch (op2) { 1965 case 0: 1966 return MISCREG_PMUSERENR_EL0; 1967 case 3: 1968 return MISCREG_PMOVSSET_EL0; 1969 } 1970 break; 1971 } 1972 break; 1973 } 1974 break; 1975 case 10: 1976 switch (op1) { 1977 case 0: 1978 switch (crm) { 1979 case 2: 1980 switch (op2) { 1981 case 0: 1982 return MISCREG_MAIR_EL1; 1983 } 1984 break; 1985 case 3: 1986 switch (op2) { 1987 case 0: 1988 return MISCREG_AMAIR_EL1; 1989 } 1990 break; 1991 } 1992 break; 1993 case 4: 1994 switch (crm) { 1995 case 2: 1996 switch (op2) { 1997 case 0: 1998 return MISCREG_MAIR_EL2; 1999 } 2000 break; 2001 case 3: 2002 switch (op2) { 2003 case 0: 2004 return MISCREG_AMAIR_EL2; 2005 } 2006 break; 2007 } 2008 break; 2009 case 6: 2010 switch (crm) { 2011 case 2: 2012 switch (op2) { 2013 case 0: 2014 return MISCREG_MAIR_EL3; 2015 } 2016 break; 2017 case 3: 2018 switch (op2) { 2019 case 0: 2020 return MISCREG_AMAIR_EL3; 2021 } 2022 break; 2023 } 2024 break; 2025 } 2026 break; 2027 case 11: 2028 switch (op1) { 2029 case 1: 2030 switch (crm) { 2031 case 0: 2032 switch (op2) { 2033 case 2: 2034 return MISCREG_L2CTLR_EL1; 2035 case 3: 2036 return MISCREG_L2ECTLR_EL1; 2037 } 2038 break; 2039 } 2040 break; 2041 } 2042 break; 2043 case 12: 2044 switch (op1) { 2045 case 0: 2046 switch (crm) { 2047 case 0: 2048 switch (op2) { 2049 case 0: 2050 return MISCREG_VBAR_EL1; 2051 case 1: 2052 return MISCREG_RVBAR_EL1; 2053 } 2054 break; 2055 case 1: 2056 switch (op2) { 2057 case 0: 2058 return MISCREG_ISR_EL1; 2059 } 2060 break; 2061 } 2062 break; 2063 case 4: 2064 switch (crm) { 2065 case 0: 2066 switch (op2) { 2067 case 0: 2068 return MISCREG_VBAR_EL2; 2069 case 1: 2070 return MISCREG_RVBAR_EL2; 2071 } 2072 break; 2073 } 2074 break; 2075 case 6: 2076 switch (crm) { 2077 case 0: 2078 switch (op2) { 2079 case 0: 2080 return MISCREG_VBAR_EL3; 2081 case 1: 2082 return MISCREG_RVBAR_EL3; 2083 case 2: 2084 return MISCREG_RMR_EL3; 2085 } 2086 break; 2087 } 2088 break; 2089 } 2090 break; 2091 case 13: 2092 switch (op1) { 2093 case 0: 2094 switch (crm) { 2095 case 0: 2096 switch (op2) { 2097 case 1: 2098 return MISCREG_CONTEXTIDR_EL1; 2099 case 4: 2100 return MISCREG_TPIDR_EL1; 2101 } 2102 break; 2103 } 2104 break; 2105 case 3: 2106 switch (crm) { 2107 case 0: 2108 switch (op2) { 2109 case 2: 2110 return MISCREG_TPIDR_EL0; 2111 case 3: 2112 return MISCREG_TPIDRRO_EL0; 2113 } 2114 break; 2115 } 2116 break; 2117 case 4: 2118 switch (crm) { 2119 case 0: 2120 switch (op2) { 2121 case 1: 2122 return MISCREG_CONTEXTIDR_EL2; 2123 case 2: 2124 return MISCREG_TPIDR_EL2; 2125 } 2126 break; 2127 } 2128 break; 2129 case 6: 2130 switch (crm) { 2131 case 0: 2132 switch (op2) { 2133 case 2: 2134 return MISCREG_TPIDR_EL3; 2135 } 2136 break; 2137 } 2138 break; 2139 } 2140 break; 2141 case 14: 2142 switch (op1) { 2143 case 0: 2144 switch (crm) { 2145 case 1: 2146 switch (op2) { 2147 case 0: 2148 return MISCREG_CNTKCTL_EL1; 2149 } 2150 break; 2151 } 2152 break; 2153 case 3: 2154 switch (crm) { 2155 case 0: 2156 switch (op2) { 2157 case 0: 2158 return MISCREG_CNTFRQ_EL0; 2159 case 1: 2160 return MISCREG_CNTPCT_EL0; 2161 case 2: 2162 return MISCREG_CNTVCT_EL0; 2163 } 2164 break; 2165 case 2: 2166 switch (op2) { 2167 case 0: 2168 return MISCREG_CNTP_TVAL_EL0; 2169 case 1: 2170 return MISCREG_CNTP_CTL_EL0; 2171 case 2: 2172 return MISCREG_CNTP_CVAL_EL0; 2173 } 2174 break; 2175 case 3: 2176 switch (op2) { 2177 case 0: 2178 return MISCREG_CNTV_TVAL_EL0; 2179 case 1: 2180 return MISCREG_CNTV_CTL_EL0; 2181 case 2: 2182 return MISCREG_CNTV_CVAL_EL0; 2183 } 2184 break; 2185 case 8: 2186 switch (op2) { 2187 case 0: 2188 return MISCREG_PMEVCNTR0_EL0; 2189 case 1: 2190 return MISCREG_PMEVCNTR1_EL0; 2191 case 2: 2192 return MISCREG_PMEVCNTR2_EL0; 2193 case 3: 2194 return MISCREG_PMEVCNTR3_EL0; 2195 case 4: 2196 return MISCREG_PMEVCNTR4_EL0; 2197 case 5: 2198 return MISCREG_PMEVCNTR5_EL0; 2199 } 2200 break; 2201 case 12: 2202 switch (op2) { 2203 case 0: 2204 return MISCREG_PMEVTYPER0_EL0; 2205 case 1: 2206 return MISCREG_PMEVTYPER1_EL0; 2207 case 2: 2208 return MISCREG_PMEVTYPER2_EL0; 2209 case 3: 2210 return MISCREG_PMEVTYPER3_EL0; 2211 case 4: 2212 return MISCREG_PMEVTYPER4_EL0; 2213 case 5: 2214 return MISCREG_PMEVTYPER5_EL0; 2215 } 2216 break; 2217 case 15: 2218 switch (op2) { 2219 case 7: 2220 return MISCREG_PMCCFILTR_EL0; 2221 } 2222 } 2223 break; 2224 case 4: 2225 switch (crm) { 2226 case 0: 2227 switch (op2) { 2228 case 3: 2229 return MISCREG_CNTVOFF_EL2; 2230 } 2231 break; 2232 case 1: 2233 switch (op2) { 2234 case 0: 2235 return MISCREG_CNTHCTL_EL2; 2236 } 2237 break; 2238 case 2: 2239 switch (op2) { 2240 case 0: 2241 return MISCREG_CNTHP_TVAL_EL2; 2242 case 1: 2243 return MISCREG_CNTHP_CTL_EL2; 2244 case 2: 2245 return MISCREG_CNTHP_CVAL_EL2; 2246 } 2247 break; 2248 } 2249 break; 2250 case 7: 2251 switch (crm) { 2252 case 2: 2253 switch (op2) { 2254 case 0: 2255 return MISCREG_CNTPS_TVAL_EL1; 2256 case 1: 2257 return MISCREG_CNTPS_CTL_EL1; 2258 case 2: 2259 return MISCREG_CNTPS_CVAL_EL1; 2260 } 2261 break; 2262 } 2263 break; 2264 } 2265 break; 2266 case 15: 2267 switch (op1) { 2268 case 0: 2269 switch (crm) { 2270 case 0: 2271 switch (op2) { 2272 case 0: 2273 return MISCREG_IL1DATA0_EL1; 2274 case 1: 2275 return MISCREG_IL1DATA1_EL1; 2276 case 2: 2277 return MISCREG_IL1DATA2_EL1; 2278 case 3: 2279 return MISCREG_IL1DATA3_EL1; 2280 } 2281 break; 2282 case 1: 2283 switch (op2) { 2284 case 0: 2285 return MISCREG_DL1DATA0_EL1; 2286 case 1: 2287 return MISCREG_DL1DATA1_EL1; 2288 case 2: 2289 return MISCREG_DL1DATA2_EL1; 2290 case 3: 2291 return MISCREG_DL1DATA3_EL1; 2292 case 4: 2293 return MISCREG_DL1DATA4_EL1; 2294 } 2295 break; 2296 } 2297 break; 2298 case 1: 2299 switch (crm) { 2300 case 0: 2301 switch (op2) { 2302 case 0: 2303 return MISCREG_L2ACTLR_EL1; 2304 } 2305 break; 2306 case 2: 2307 switch (op2) { 2308 case 0: 2309 return MISCREG_CPUACTLR_EL1; 2310 case 1: 2311 return MISCREG_CPUECTLR_EL1; 2312 case 2: 2313 return MISCREG_CPUMERRSR_EL1; 2314 case 3: 2315 return MISCREG_L2MERRSR_EL1; 2316 } 2317 break; 2318 case 3: 2319 switch (op2) { 2320 case 0: 2321 return MISCREG_CBAR_EL1; 2322 2323 } 2324 break; 2325 } 2326 break; 2327 } 2328 break; 2329 } 2330 break; 2331 } 2332 2333 return MISCREG_UNKNOWN; 2334} 2335 2336bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below 2337 2338void 2339ISA::initializeMiscRegMetadata() 2340{ 2341 // the MiscReg metadata tables are shared across all instances of the 2342 // ISA object, so there's no need to initialize them multiple times. 2343 static bool completed = false; 2344 if (completed) 2345 return; 2346 2347 /** 2348 * Some registers alias with others, and therefore need to be translated. 2349 * When two mapping registers are given, they are the 32b lower and 2350 * upper halves, respectively, of the 64b register being mapped. 2351 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 2352 * 2353 * NAM = "not architecturally mandated", 2354 * from ARM DDI 0487A.i, template text 2355 * "AArch64 System register ___ can be mapped to 2356 * AArch32 System register ___, but this is not 2357 * architecturally mandated." 2358 */ 2359 2360 InitReg(MISCREG_CPSR) 2361 .allPrivileges(); 2362 InitReg(MISCREG_SPSR) 2363 .allPrivileges(); 2364 InitReg(MISCREG_SPSR_FIQ) 2365 .allPrivileges(); 2366 InitReg(MISCREG_SPSR_IRQ) 2367 .allPrivileges(); 2368 InitReg(MISCREG_SPSR_SVC) 2369 .allPrivileges(); 2370 InitReg(MISCREG_SPSR_MON) 2371 .allPrivileges(); 2372 InitReg(MISCREG_SPSR_ABT) 2373 .allPrivileges(); 2374 InitReg(MISCREG_SPSR_HYP) 2375 .allPrivileges(); 2376 InitReg(MISCREG_SPSR_UND) 2377 .allPrivileges(); 2378 InitReg(MISCREG_ELR_HYP) 2379 .allPrivileges(); 2380 InitReg(MISCREG_FPSID) 2381 .allPrivileges(); 2382 InitReg(MISCREG_FPSCR) 2383 .allPrivileges(); 2384 InitReg(MISCREG_MVFR1) 2385 .allPrivileges(); 2386 InitReg(MISCREG_MVFR0) 2387 .allPrivileges(); 2388 InitReg(MISCREG_FPEXC) 2389 .allPrivileges(); 2390 2391 // Helper registers 2392 InitReg(MISCREG_CPSR_MODE) 2393 .allPrivileges(); 2394 InitReg(MISCREG_CPSR_Q) 2395 .allPrivileges(); 2396 InitReg(MISCREG_FPSCR_EXC) 2397 .allPrivileges(); 2398 InitReg(MISCREG_FPSCR_QC) 2399 .allPrivileges(); 2400 InitReg(MISCREG_LOCKADDR) 2401 .allPrivileges(); 2402 InitReg(MISCREG_LOCKFLAG) 2403 .allPrivileges(); 2404 InitReg(MISCREG_PRRR_MAIR0) 2405 .mutex() 2406 .banked(); 2407 InitReg(MISCREG_PRRR_MAIR0_NS) 2408 .mutex() 2409 .bankedChild(); 2410 InitReg(MISCREG_PRRR_MAIR0_S) 2411 .mutex() 2412 .bankedChild(); 2413 InitReg(MISCREG_NMRR_MAIR1) 2414 .mutex() 2415 .banked(); 2416 InitReg(MISCREG_NMRR_MAIR1_NS) 2417 .mutex() 2418 .bankedChild(); 2419 InitReg(MISCREG_NMRR_MAIR1_S) 2420 .mutex() 2421 .bankedChild(); 2422 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) 2423 .mutex(); 2424 InitReg(MISCREG_SCTLR_RST) 2425 .allPrivileges(); 2426 InitReg(MISCREG_SEV_MAILBOX) 2427 .allPrivileges(); 2428 2429 // AArch32 CP14 registers 2430 InitReg(MISCREG_DBGDIDR) 2431 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2432 InitReg(MISCREG_DBGDSCRint) 2433 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2434 InitReg(MISCREG_DBGDCCINT) 2435 .unimplemented() 2436 .allPrivileges(); 2437 InitReg(MISCREG_DBGDTRTXint) 2438 .unimplemented() 2439 .allPrivileges(); 2440 InitReg(MISCREG_DBGDTRRXint) 2441 .unimplemented() 2442 .allPrivileges(); 2443 InitReg(MISCREG_DBGWFAR) 2444 .unimplemented() 2445 .allPrivileges(); 2446 InitReg(MISCREG_DBGVCR) 2447 .unimplemented() 2448 .allPrivileges(); 2449 InitReg(MISCREG_DBGDTRRXext) 2450 .unimplemented() 2451 .allPrivileges(); 2452 InitReg(MISCREG_DBGDSCRext) 2453 .unimplemented() 2454 .warnNotFail() 2455 .allPrivileges(); 2456 InitReg(MISCREG_DBGDTRTXext) 2457 .unimplemented() 2458 .allPrivileges(); 2459 InitReg(MISCREG_DBGOSECCR) 2460 .unimplemented() 2461 .allPrivileges(); 2462 InitReg(MISCREG_DBGBVR0) 2463 .unimplemented() 2464 .allPrivileges(); 2465 InitReg(MISCREG_DBGBVR1) 2466 .unimplemented() 2467 .allPrivileges(); 2468 InitReg(MISCREG_DBGBVR2) 2469 .unimplemented() 2470 .allPrivileges(); 2471 InitReg(MISCREG_DBGBVR3) 2472 .unimplemented() 2473 .allPrivileges(); 2474 InitReg(MISCREG_DBGBVR4) 2475 .unimplemented() 2476 .allPrivileges(); 2477 InitReg(MISCREG_DBGBVR5) 2478 .unimplemented() 2479 .allPrivileges(); 2480 InitReg(MISCREG_DBGBCR0) 2481 .unimplemented() 2482 .allPrivileges(); 2483 InitReg(MISCREG_DBGBCR1) 2484 .unimplemented() 2485 .allPrivileges(); 2486 InitReg(MISCREG_DBGBCR2) 2487 .unimplemented() 2488 .allPrivileges(); 2489 InitReg(MISCREG_DBGBCR3) 2490 .unimplemented() 2491 .allPrivileges(); 2492 InitReg(MISCREG_DBGBCR4) 2493 .unimplemented() 2494 .allPrivileges(); 2495 InitReg(MISCREG_DBGBCR5) 2496 .unimplemented() 2497 .allPrivileges(); 2498 InitReg(MISCREG_DBGWVR0) 2499 .unimplemented() 2500 .allPrivileges(); 2501 InitReg(MISCREG_DBGWVR1) 2502 .unimplemented() 2503 .allPrivileges(); 2504 InitReg(MISCREG_DBGWVR2) 2505 .unimplemented() 2506 .allPrivileges(); 2507 InitReg(MISCREG_DBGWVR3) 2508 .unimplemented() 2509 .allPrivileges(); 2510 InitReg(MISCREG_DBGWCR0) 2511 .unimplemented() 2512 .allPrivileges(); 2513 InitReg(MISCREG_DBGWCR1) 2514 .unimplemented() 2515 .allPrivileges(); 2516 InitReg(MISCREG_DBGWCR2) 2517 .unimplemented() 2518 .allPrivileges(); 2519 InitReg(MISCREG_DBGWCR3) 2520 .unimplemented() 2521 .allPrivileges(); 2522 InitReg(MISCREG_DBGDRAR) 2523 .unimplemented() 2524 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2525 InitReg(MISCREG_DBGBXVR4) 2526 .unimplemented() 2527 .allPrivileges(); 2528 InitReg(MISCREG_DBGBXVR5) 2529 .unimplemented() 2530 .allPrivileges(); 2531 InitReg(MISCREG_DBGOSLAR) 2532 .unimplemented() 2533 .allPrivileges().monSecureRead(0).monNonSecureRead(0); 2534 InitReg(MISCREG_DBGOSLSR) 2535 .unimplemented() 2536 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2537 InitReg(MISCREG_DBGOSDLR) 2538 .unimplemented() 2539 .allPrivileges(); 2540 InitReg(MISCREG_DBGPRCR) 2541 .unimplemented() 2542 .allPrivileges(); 2543 InitReg(MISCREG_DBGDSAR) 2544 .unimplemented() 2545 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2546 InitReg(MISCREG_DBGCLAIMSET) 2547 .unimplemented() 2548 .allPrivileges(); 2549 InitReg(MISCREG_DBGCLAIMCLR) 2550 .unimplemented() 2551 .allPrivileges(); 2552 InitReg(MISCREG_DBGAUTHSTATUS) 2553 .unimplemented() 2554 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2555 InitReg(MISCREG_DBGDEVID2) 2556 .unimplemented() 2557 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2558 InitReg(MISCREG_DBGDEVID1) 2559 .unimplemented() 2560 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2561 InitReg(MISCREG_DBGDEVID0) 2562 .unimplemented() 2563 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2564 InitReg(MISCREG_TEECR) 2565 .unimplemented() 2566 .allPrivileges(); 2567 InitReg(MISCREG_JIDR) 2568 .allPrivileges(); 2569 InitReg(MISCREG_TEEHBR) 2570 .allPrivileges(); 2571 InitReg(MISCREG_JOSCR) 2572 .allPrivileges(); 2573 InitReg(MISCREG_JMCR) 2574 .allPrivileges(); 2575 2576 // AArch32 CP15 registers 2577 InitReg(MISCREG_MIDR) 2578 .allPrivileges().exceptUserMode().writes(0); 2579 InitReg(MISCREG_CTR) 2580 .allPrivileges().exceptUserMode().writes(0); 2581 InitReg(MISCREG_TCMTR) 2582 .allPrivileges().exceptUserMode().writes(0); 2583 InitReg(MISCREG_TLBTR) 2584 .allPrivileges().exceptUserMode().writes(0); 2585 InitReg(MISCREG_MPIDR) 2586 .allPrivileges().exceptUserMode().writes(0); 2587 InitReg(MISCREG_REVIDR) 2588 .unimplemented() 2589 .warnNotFail() 2590 .allPrivileges().exceptUserMode().writes(0); 2591 InitReg(MISCREG_ID_PFR0) 2592 .allPrivileges().exceptUserMode().writes(0); 2593 InitReg(MISCREG_ID_PFR1) 2594 .allPrivileges().exceptUserMode().writes(0); 2595 InitReg(MISCREG_ID_DFR0) 2596 .allPrivileges().exceptUserMode().writes(0); 2597 InitReg(MISCREG_ID_AFR0) 2598 .allPrivileges().exceptUserMode().writes(0); 2599 InitReg(MISCREG_ID_MMFR0) 2600 .allPrivileges().exceptUserMode().writes(0); 2601 InitReg(MISCREG_ID_MMFR1) 2602 .allPrivileges().exceptUserMode().writes(0); 2603 InitReg(MISCREG_ID_MMFR2) 2604 .allPrivileges().exceptUserMode().writes(0); 2605 InitReg(MISCREG_ID_MMFR3) 2606 .allPrivileges().exceptUserMode().writes(0); 2607 InitReg(MISCREG_ID_ISAR0) 2608 .allPrivileges().exceptUserMode().writes(0); 2609 InitReg(MISCREG_ID_ISAR1) 2610 .allPrivileges().exceptUserMode().writes(0); 2611 InitReg(MISCREG_ID_ISAR2) 2612 .allPrivileges().exceptUserMode().writes(0); 2613 InitReg(MISCREG_ID_ISAR3) 2614 .allPrivileges().exceptUserMode().writes(0); 2615 InitReg(MISCREG_ID_ISAR4) 2616 .allPrivileges().exceptUserMode().writes(0); 2617 InitReg(MISCREG_ID_ISAR5) 2618 .allPrivileges().exceptUserMode().writes(0); 2619 InitReg(MISCREG_CCSIDR) 2620 .allPrivileges().exceptUserMode().writes(0); 2621 InitReg(MISCREG_CLIDR) 2622 .allPrivileges().exceptUserMode().writes(0); 2623 InitReg(MISCREG_AIDR) 2624 .allPrivileges().exceptUserMode().writes(0); 2625 InitReg(MISCREG_CSSELR) 2626 .banked(); 2627 InitReg(MISCREG_CSSELR_NS) 2628 .bankedChild() 2629 .nonSecure().exceptUserMode(); 2630 InitReg(MISCREG_CSSELR_S) 2631 .bankedChild() 2632 .secure().exceptUserMode(); 2633 InitReg(MISCREG_VPIDR) 2634 .hyp().monNonSecure(); 2635 InitReg(MISCREG_VMPIDR) 2636 .hyp().monNonSecure(); 2637 InitReg(MISCREG_SCTLR) 2638 .banked(); 2639 InitReg(MISCREG_SCTLR_NS) 2640 .bankedChild() 2641 .nonSecure().exceptUserMode(); 2642 InitReg(MISCREG_SCTLR_S) 2643 .bankedChild() 2644 .secure().exceptUserMode(); 2645 InitReg(MISCREG_ACTLR) 2646 .banked(); 2647 InitReg(MISCREG_ACTLR_NS) 2648 .bankedChild() 2649 .nonSecure().exceptUserMode(); 2650 InitReg(MISCREG_ACTLR_S) 2651 .bankedChild() 2652 .secure().exceptUserMode(); 2653 InitReg(MISCREG_CPACR) 2654 .allPrivileges().exceptUserMode(); 2655 InitReg(MISCREG_SCR) 2656 .mon().secure().exceptUserMode() 2657 .res0(0xff40) // [31:16], [6] 2658 .res1(0x0030); // [5:4] 2659 InitReg(MISCREG_SDER) 2660 .mon(); 2661 InitReg(MISCREG_NSACR) 2662 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode(); 2663 InitReg(MISCREG_HSCTLR) 2664 .hyp().monNonSecure(); 2665 InitReg(MISCREG_HACTLR) 2666 .hyp().monNonSecure(); 2667 InitReg(MISCREG_HCR) 2668 .hyp().monNonSecure(); 2669 InitReg(MISCREG_HDCR) 2670 .hyp().monNonSecure(); 2671 InitReg(MISCREG_HCPTR) 2672 .hyp().monNonSecure(); 2673 InitReg(MISCREG_HSTR) 2674 .hyp().monNonSecure(); 2675 InitReg(MISCREG_HACR) 2676 .unimplemented() 2677 .warnNotFail() 2678 .hyp().monNonSecure(); 2679 InitReg(MISCREG_TTBR0) 2680 .banked(); 2681 InitReg(MISCREG_TTBR0_NS) 2682 .bankedChild() 2683 .nonSecure().exceptUserMode(); 2684 InitReg(MISCREG_TTBR0_S) 2685 .bankedChild() 2686 .secure().exceptUserMode(); 2687 InitReg(MISCREG_TTBR1) 2688 .banked(); 2689 InitReg(MISCREG_TTBR1_NS) 2690 .bankedChild() 2691 .nonSecure().exceptUserMode(); 2692 InitReg(MISCREG_TTBR1_S) 2693 .bankedChild() 2694 .secure().exceptUserMode(); 2695 InitReg(MISCREG_TTBCR) 2696 .banked(); 2697 InitReg(MISCREG_TTBCR_NS) 2698 .bankedChild() 2699 .nonSecure().exceptUserMode(); 2700 InitReg(MISCREG_TTBCR_S) 2701 .bankedChild() 2702 .secure().exceptUserMode(); 2703 InitReg(MISCREG_HTCR) 2704 .hyp().monNonSecure(); 2705 InitReg(MISCREG_VTCR) 2706 .hyp().monNonSecure(); 2707 InitReg(MISCREG_DACR) 2708 .banked(); 2709 InitReg(MISCREG_DACR_NS) 2710 .bankedChild() 2711 .nonSecure().exceptUserMode(); 2712 InitReg(MISCREG_DACR_S) 2713 .bankedChild() 2714 .secure().exceptUserMode(); 2715 InitReg(MISCREG_DFSR) 2716 .banked(); 2717 InitReg(MISCREG_DFSR_NS) 2718 .bankedChild() 2719 .nonSecure().exceptUserMode(); 2720 InitReg(MISCREG_DFSR_S) 2721 .bankedChild() 2722 .secure().exceptUserMode(); 2723 InitReg(MISCREG_IFSR) 2724 .banked(); 2725 InitReg(MISCREG_IFSR_NS) 2726 .bankedChild() 2727 .nonSecure().exceptUserMode(); 2728 InitReg(MISCREG_IFSR_S) 2729 .bankedChild() 2730 .secure().exceptUserMode(); 2731 InitReg(MISCREG_ADFSR) 2732 .unimplemented() 2733 .warnNotFail() 2734 .banked(); 2735 InitReg(MISCREG_ADFSR_NS) 2736 .unimplemented() 2737 .warnNotFail() 2738 .bankedChild() 2739 .nonSecure().exceptUserMode(); 2740 InitReg(MISCREG_ADFSR_S) 2741 .unimplemented() 2742 .warnNotFail() 2743 .bankedChild() 2744 .secure().exceptUserMode(); 2745 InitReg(MISCREG_AIFSR) 2746 .unimplemented() 2747 .warnNotFail() 2748 .banked(); 2749 InitReg(MISCREG_AIFSR_NS) 2750 .unimplemented() 2751 .warnNotFail() 2752 .bankedChild() 2753 .nonSecure().exceptUserMode(); 2754 InitReg(MISCREG_AIFSR_S) 2755 .unimplemented() 2756 .warnNotFail() 2757 .bankedChild() 2758 .secure().exceptUserMode(); 2759 InitReg(MISCREG_HADFSR) 2760 .hyp().monNonSecure(); 2761 InitReg(MISCREG_HAIFSR) 2762 .hyp().monNonSecure(); 2763 InitReg(MISCREG_HSR) 2764 .hyp().monNonSecure(); 2765 InitReg(MISCREG_DFAR) 2766 .banked(); 2767 InitReg(MISCREG_DFAR_NS) 2768 .bankedChild() 2769 .nonSecure().exceptUserMode(); 2770 InitReg(MISCREG_DFAR_S) 2771 .bankedChild() 2772 .secure().exceptUserMode(); 2773 InitReg(MISCREG_IFAR) 2774 .banked(); 2775 InitReg(MISCREG_IFAR_NS) 2776 .bankedChild() 2777 .nonSecure().exceptUserMode(); 2778 InitReg(MISCREG_IFAR_S) 2779 .bankedChild() 2780 .secure().exceptUserMode(); 2781 InitReg(MISCREG_HDFAR) 2782 .hyp().monNonSecure(); 2783 InitReg(MISCREG_HIFAR) 2784 .hyp().monNonSecure(); 2785 InitReg(MISCREG_HPFAR) 2786 .hyp().monNonSecure(); 2787 InitReg(MISCREG_ICIALLUIS) 2788 .unimplemented() 2789 .warnNotFail() 2790 .writes(1).exceptUserMode(); 2791 InitReg(MISCREG_BPIALLIS) 2792 .unimplemented() 2793 .warnNotFail() 2794 .writes(1).exceptUserMode(); 2795 InitReg(MISCREG_PAR) 2796 .banked(); 2797 InitReg(MISCREG_PAR_NS) 2798 .bankedChild() 2799 .nonSecure().exceptUserMode(); 2800 InitReg(MISCREG_PAR_S) 2801 .bankedChild() 2802 .secure().exceptUserMode(); 2803 InitReg(MISCREG_ICIALLU) 2804 .writes(1).exceptUserMode(); 2805 InitReg(MISCREG_ICIMVAU) 2806 .unimplemented() 2807 .warnNotFail() 2808 .writes(1).exceptUserMode(); 2809 InitReg(MISCREG_CP15ISB) 2810 .writes(1); 2811 InitReg(MISCREG_BPIALL) 2812 .unimplemented() 2813 .warnNotFail() 2814 .writes(1).exceptUserMode(); 2815 InitReg(MISCREG_BPIMVA) 2816 .unimplemented() 2817 .warnNotFail() 2818 .writes(1).exceptUserMode(); 2819 InitReg(MISCREG_DCIMVAC) 2820 .unimplemented() 2821 .warnNotFail() 2822 .writes(1).exceptUserMode(); 2823 InitReg(MISCREG_DCISW) 2824 .unimplemented() 2825 .warnNotFail() 2826 .writes(1).exceptUserMode(); 2827 InitReg(MISCREG_ATS1CPR) 2828 .writes(1).exceptUserMode(); 2829 InitReg(MISCREG_ATS1CPW) 2830 .writes(1).exceptUserMode(); 2831 InitReg(MISCREG_ATS1CUR) 2832 .writes(1).exceptUserMode(); 2833 InitReg(MISCREG_ATS1CUW) 2834 .writes(1).exceptUserMode(); 2835 InitReg(MISCREG_ATS12NSOPR) 2836 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2837 InitReg(MISCREG_ATS12NSOPW) 2838 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2839 InitReg(MISCREG_ATS12NSOUR) 2840 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2841 InitReg(MISCREG_ATS12NSOUW) 2842 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2843 InitReg(MISCREG_DCCMVAC) 2844 .writes(1).exceptUserMode(); 2845 InitReg(MISCREG_DCCSW) 2846 .unimplemented() 2847 .warnNotFail() 2848 .writes(1).exceptUserMode(); 2849 InitReg(MISCREG_CP15DSB) 2850 .writes(1); 2851 InitReg(MISCREG_CP15DMB) 2852 .writes(1); 2853 InitReg(MISCREG_DCCMVAU) 2854 .unimplemented() 2855 .warnNotFail() 2856 .writes(1).exceptUserMode(); 2857 InitReg(MISCREG_DCCIMVAC) 2858 .unimplemented() 2859 .warnNotFail() 2860 .writes(1).exceptUserMode(); 2861 InitReg(MISCREG_DCCISW) 2862 .unimplemented() 2863 .warnNotFail() 2864 .writes(1).exceptUserMode(); 2865 InitReg(MISCREG_ATS1HR) 2866 .monNonSecureWrite().hypWrite(); 2867 InitReg(MISCREG_ATS1HW) 2868 .monNonSecureWrite().hypWrite(); 2869 InitReg(MISCREG_TLBIALLIS) 2870 .writes(1).exceptUserMode(); 2871 InitReg(MISCREG_TLBIMVAIS) 2872 .writes(1).exceptUserMode(); 2873 InitReg(MISCREG_TLBIASIDIS) 2874 .writes(1).exceptUserMode(); 2875 InitReg(MISCREG_TLBIMVAAIS) 2876 .writes(1).exceptUserMode(); 2877 InitReg(MISCREG_TLBIMVALIS) 2878 .unimplemented() 2879 .writes(1).exceptUserMode(); 2880 InitReg(MISCREG_TLBIMVAALIS) 2881 .unimplemented() 2882 .writes(1).exceptUserMode(); 2883 InitReg(MISCREG_ITLBIALL) 2884 .writes(1).exceptUserMode(); 2885 InitReg(MISCREG_ITLBIMVA) 2886 .writes(1).exceptUserMode(); 2887 InitReg(MISCREG_ITLBIASID) 2888 .writes(1).exceptUserMode(); 2889 InitReg(MISCREG_DTLBIALL) 2890 .writes(1).exceptUserMode(); 2891 InitReg(MISCREG_DTLBIMVA) 2892 .writes(1).exceptUserMode(); 2893 InitReg(MISCREG_DTLBIASID) 2894 .writes(1).exceptUserMode(); 2895 InitReg(MISCREG_TLBIALL) 2896 .writes(1).exceptUserMode(); 2897 InitReg(MISCREG_TLBIMVA) 2898 .writes(1).exceptUserMode(); 2899 InitReg(MISCREG_TLBIASID) 2900 .writes(1).exceptUserMode(); 2901 InitReg(MISCREG_TLBIMVAA) 2902 .writes(1).exceptUserMode(); 2903 InitReg(MISCREG_TLBIMVAL) 2904 .unimplemented() 2905 .writes(1).exceptUserMode(); 2906 InitReg(MISCREG_TLBIMVAAL) 2907 .unimplemented() 2908 .writes(1).exceptUserMode(); 2909 InitReg(MISCREG_TLBIIPAS2IS) 2910 .unimplemented() 2911 .monNonSecureWrite().hypWrite(); 2912 InitReg(MISCREG_TLBIIPAS2LIS) 2913 .unimplemented() 2914 .monNonSecureWrite().hypWrite(); 2915 InitReg(MISCREG_TLBIALLHIS) 2916 .monNonSecureWrite().hypWrite(); 2917 InitReg(MISCREG_TLBIMVAHIS) 2918 .monNonSecureWrite().hypWrite(); 2919 InitReg(MISCREG_TLBIALLNSNHIS) 2920 .monNonSecureWrite().hypWrite(); 2921 InitReg(MISCREG_TLBIMVALHIS) 2922 .unimplemented() 2923 .monNonSecureWrite().hypWrite(); 2924 InitReg(MISCREG_TLBIIPAS2) 2925 .unimplemented() 2926 .monNonSecureWrite().hypWrite(); 2927 InitReg(MISCREG_TLBIIPAS2L) 2928 .unimplemented() 2929 .monNonSecureWrite().hypWrite(); 2930 InitReg(MISCREG_TLBIALLH) 2931 .monNonSecureWrite().hypWrite(); 2932 InitReg(MISCREG_TLBIMVAH) 2933 .monNonSecureWrite().hypWrite(); 2934 InitReg(MISCREG_TLBIALLNSNH) 2935 .monNonSecureWrite().hypWrite(); 2936 InitReg(MISCREG_TLBIMVALH) 2937 .unimplemented() 2938 .monNonSecureWrite().hypWrite(); 2939 InitReg(MISCREG_PMCR) 2940 .allPrivileges(); 2941 InitReg(MISCREG_PMCNTENSET) 2942 .allPrivileges(); 2943 InitReg(MISCREG_PMCNTENCLR) 2944 .allPrivileges(); 2945 InitReg(MISCREG_PMOVSR) 2946 .allPrivileges(); 2947 InitReg(MISCREG_PMSWINC) 2948 .allPrivileges(); 2949 InitReg(MISCREG_PMSELR) 2950 .allPrivileges(); 2951 InitReg(MISCREG_PMCEID0) 2952 .allPrivileges(); 2953 InitReg(MISCREG_PMCEID1) 2954 .allPrivileges(); 2955 InitReg(MISCREG_PMCCNTR) 2956 .allPrivileges(); 2957 InitReg(MISCREG_PMXEVTYPER) 2958 .allPrivileges(); 2959 InitReg(MISCREG_PMCCFILTR) 2960 .allPrivileges(); 2961 InitReg(MISCREG_PMXEVCNTR) 2962 .allPrivileges(); 2963 InitReg(MISCREG_PMUSERENR) 2964 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0); 2965 InitReg(MISCREG_PMINTENSET) 2966 .allPrivileges().exceptUserMode(); 2967 InitReg(MISCREG_PMINTENCLR) 2968 .allPrivileges().exceptUserMode(); 2969 InitReg(MISCREG_PMOVSSET) 2970 .unimplemented() 2971 .allPrivileges(); 2972 InitReg(MISCREG_L2CTLR) 2973 .allPrivileges().exceptUserMode(); 2974 InitReg(MISCREG_L2ECTLR) 2975 .unimplemented() 2976 .allPrivileges().exceptUserMode(); 2977 InitReg(MISCREG_PRRR) 2978 .banked(); 2979 InitReg(MISCREG_PRRR_NS) 2980 .bankedChild() 2981 .nonSecure().exceptUserMode(); 2982 InitReg(MISCREG_PRRR_S) 2983 .bankedChild() 2984 .secure().exceptUserMode(); 2985 InitReg(MISCREG_MAIR0) 2986 .banked(); 2987 InitReg(MISCREG_MAIR0_NS) 2988 .bankedChild() 2989 .nonSecure().exceptUserMode(); 2990 InitReg(MISCREG_MAIR0_S) 2991 .bankedChild() 2992 .secure().exceptUserMode(); 2993 InitReg(MISCREG_NMRR) 2994 .banked(); 2995 InitReg(MISCREG_NMRR_NS) 2996 .bankedChild() 2997 .nonSecure().exceptUserMode(); 2998 InitReg(MISCREG_NMRR_S) 2999 .bankedChild() 3000 .secure().exceptUserMode(); 3001 InitReg(MISCREG_MAIR1) 3002 .banked(); 3003 InitReg(MISCREG_MAIR1_NS) 3004 .bankedChild() 3005 .nonSecure().exceptUserMode(); 3006 InitReg(MISCREG_MAIR1_S) 3007 .bankedChild() 3008 .secure().exceptUserMode(); 3009 InitReg(MISCREG_AMAIR0) 3010 .banked(); 3011 InitReg(MISCREG_AMAIR0_NS) 3012 .bankedChild() 3013 .nonSecure().exceptUserMode(); 3014 InitReg(MISCREG_AMAIR0_S) 3015 .bankedChild() 3016 .secure().exceptUserMode(); 3017 InitReg(MISCREG_AMAIR1) 3018 .banked(); 3019 InitReg(MISCREG_AMAIR1_NS) 3020 .bankedChild() 3021 .nonSecure().exceptUserMode(); 3022 InitReg(MISCREG_AMAIR1_S) 3023 .bankedChild() 3024 .secure().exceptUserMode(); 3025 InitReg(MISCREG_HMAIR0) 3026 .hyp().monNonSecure(); 3027 InitReg(MISCREG_HMAIR1) 3028 .hyp().monNonSecure(); 3029 InitReg(MISCREG_HAMAIR0) 3030 .unimplemented() 3031 .warnNotFail() 3032 .hyp().monNonSecure(); 3033 InitReg(MISCREG_HAMAIR1) 3034 .unimplemented() 3035 .warnNotFail() 3036 .hyp().monNonSecure(); 3037 InitReg(MISCREG_VBAR) 3038 .banked(); 3039 InitReg(MISCREG_VBAR_NS) 3040 .bankedChild() 3041 .nonSecure().exceptUserMode(); 3042 InitReg(MISCREG_VBAR_S) 3043 .bankedChild() 3044 .secure().exceptUserMode(); 3045 InitReg(MISCREG_MVBAR) 3046 .mon().secure().exceptUserMode(); 3047 InitReg(MISCREG_RMR) 3048 .unimplemented() 3049 .mon().secure().exceptUserMode(); 3050 InitReg(MISCREG_ISR) 3051 .allPrivileges().exceptUserMode().writes(0); 3052 InitReg(MISCREG_HVBAR) 3053 .hyp().monNonSecure(); 3054 InitReg(MISCREG_FCSEIDR) 3055 .unimplemented() 3056 .warnNotFail() 3057 .allPrivileges().exceptUserMode(); 3058 InitReg(MISCREG_CONTEXTIDR) 3059 .banked(); 3060 InitReg(MISCREG_CONTEXTIDR_NS) 3061 .bankedChild() 3062 .nonSecure().exceptUserMode(); 3063 InitReg(MISCREG_CONTEXTIDR_S) 3064 .bankedChild() 3065 .secure().exceptUserMode(); 3066 InitReg(MISCREG_TPIDRURW) 3067 .banked(); 3068 InitReg(MISCREG_TPIDRURW_NS) 3069 .bankedChild() 3070 .allPrivileges().monSecure(0).privSecure(0); 3071 InitReg(MISCREG_TPIDRURW_S) 3072 .bankedChild() 3073 .secure(); 3074 InitReg(MISCREG_TPIDRURO) 3075 .banked(); 3076 InitReg(MISCREG_TPIDRURO_NS) 3077 .bankedChild() 3078 .allPrivileges().secure(0).userNonSecureWrite(0).userSecureRead(1); 3079 InitReg(MISCREG_TPIDRURO_S) 3080 .bankedChild() 3081 .secure().userSecureWrite(0); 3082 InitReg(MISCREG_TPIDRPRW) 3083 .banked(); 3084 InitReg(MISCREG_TPIDRPRW_NS) 3085 .bankedChild() 3086 .nonSecure().exceptUserMode(); 3087 InitReg(MISCREG_TPIDRPRW_S) 3088 .bankedChild() 3089 .secure().exceptUserMode(); 3090 InitReg(MISCREG_HTPIDR) 3091 .hyp().monNonSecure(); 3092 InitReg(MISCREG_CNTFRQ) 3093 .unverifiable() 3094 .reads(1).mon(); 3095 InitReg(MISCREG_CNTKCTL) 3096 .allPrivileges().exceptUserMode(); 3097 InitReg(MISCREG_CNTP_TVAL) 3098 .banked(); 3099 InitReg(MISCREG_CNTP_TVAL_NS) 3100 .bankedChild() 3101 .allPrivileges().monSecure(0).privSecure(0); 3102 InitReg(MISCREG_CNTP_TVAL_S) 3103 .unimplemented() 3104 .bankedChild() 3105 .secure().user(1); 3106 InitReg(MISCREG_CNTP_CTL) 3107 .banked(); 3108 InitReg(MISCREG_CNTP_CTL_NS) 3109 .bankedChild() 3110 .allPrivileges().monSecure(0).privSecure(0); 3111 InitReg(MISCREG_CNTP_CTL_S) 3112 .unimplemented() 3113 .bankedChild() 3114 .secure().user(1); 3115 InitReg(MISCREG_CNTV_TVAL) 3116 .allPrivileges(); 3117 InitReg(MISCREG_CNTV_CTL) 3118 .allPrivileges(); 3119 InitReg(MISCREG_CNTHCTL) 3120 .unimplemented() 3121 .hypWrite().monNonSecureRead(); 3122 InitReg(MISCREG_CNTHP_TVAL) 3123 .unimplemented() 3124 .hypWrite().monNonSecureRead(); 3125 InitReg(MISCREG_CNTHP_CTL) 3126 .unimplemented() 3127 .hypWrite().monNonSecureRead(); 3128 InitReg(MISCREG_IL1DATA0) 3129 .unimplemented() 3130 .allPrivileges().exceptUserMode(); 3131 InitReg(MISCREG_IL1DATA1) 3132 .unimplemented() 3133 .allPrivileges().exceptUserMode(); 3134 InitReg(MISCREG_IL1DATA2) 3135 .unimplemented() 3136 .allPrivileges().exceptUserMode(); 3137 InitReg(MISCREG_IL1DATA3) 3138 .unimplemented() 3139 .allPrivileges().exceptUserMode(); 3140 InitReg(MISCREG_DL1DATA0) 3141 .unimplemented() 3142 .allPrivileges().exceptUserMode(); 3143 InitReg(MISCREG_DL1DATA1) 3144 .unimplemented() 3145 .allPrivileges().exceptUserMode(); 3146 InitReg(MISCREG_DL1DATA2) 3147 .unimplemented() 3148 .allPrivileges().exceptUserMode(); 3149 InitReg(MISCREG_DL1DATA3) 3150 .unimplemented() 3151 .allPrivileges().exceptUserMode(); 3152 InitReg(MISCREG_DL1DATA4) 3153 .unimplemented() 3154 .allPrivileges().exceptUserMode(); 3155 InitReg(MISCREG_RAMINDEX) 3156 .unimplemented() 3157 .writes(1).exceptUserMode(); 3158 InitReg(MISCREG_L2ACTLR) 3159 .unimplemented() 3160 .allPrivileges().exceptUserMode(); 3161 InitReg(MISCREG_CBAR) 3162 .unimplemented() 3163 .allPrivileges().exceptUserMode().writes(0); 3164 InitReg(MISCREG_HTTBR) 3165 .hyp().monNonSecure(); 3166 InitReg(MISCREG_VTTBR) 3167 .hyp().monNonSecure(); 3168 InitReg(MISCREG_CNTPCT) 3169 .reads(1); 3170 InitReg(MISCREG_CNTVCT) 3171 .unverifiable() 3172 .reads(1); 3173 InitReg(MISCREG_CNTP_CVAL) 3174 .banked(); 3175 InitReg(MISCREG_CNTP_CVAL_NS) 3176 .bankedChild() 3177 .allPrivileges().monSecure(0).privSecure(0); 3178 InitReg(MISCREG_CNTP_CVAL_S) 3179 .unimplemented() 3180 .bankedChild() 3181 .secure().user(1); 3182 InitReg(MISCREG_CNTV_CVAL) 3183 .allPrivileges(); 3184 InitReg(MISCREG_CNTVOFF) 3185 .hyp().monNonSecure(); 3186 InitReg(MISCREG_CNTHP_CVAL) 3187 .unimplemented() 3188 .hypWrite().monNonSecureRead(); 3189 InitReg(MISCREG_CPUMERRSR) 3190 .unimplemented() 3191 .allPrivileges().exceptUserMode(); 3192 InitReg(MISCREG_L2MERRSR) 3193 .unimplemented() 3194 .warnNotFail() 3195 .allPrivileges().exceptUserMode(); 3196 3197 // AArch64 registers (Op0=2); 3198 InitReg(MISCREG_MDCCINT_EL1) 3199 .allPrivileges(); 3200 InitReg(MISCREG_OSDTRRX_EL1) 3201 .allPrivileges() 3202 .mapsTo(MISCREG_DBGDTRRXext); 3203 InitReg(MISCREG_MDSCR_EL1) 3204 .allPrivileges() 3205 .mapsTo(MISCREG_DBGDSCRext); 3206 InitReg(MISCREG_OSDTRTX_EL1) 3207 .allPrivileges() 3208 .mapsTo(MISCREG_DBGDTRTXext); 3209 InitReg(MISCREG_OSECCR_EL1) 3210 .allPrivileges() 3211 .mapsTo(MISCREG_DBGOSECCR); 3212 InitReg(MISCREG_DBGBVR0_EL1) 3213 .allPrivileges() 3214 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */); 3215 InitReg(MISCREG_DBGBVR1_EL1) 3216 .allPrivileges() 3217 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */); 3218 InitReg(MISCREG_DBGBVR2_EL1) 3219 .allPrivileges() 3220 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */); 3221 InitReg(MISCREG_DBGBVR3_EL1) 3222 .allPrivileges() 3223 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */); 3224 InitReg(MISCREG_DBGBVR4_EL1) 3225 .allPrivileges() 3226 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */); 3227 InitReg(MISCREG_DBGBVR5_EL1) 3228 .allPrivileges() 3229 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */); 3230 InitReg(MISCREG_DBGBCR0_EL1) 3231 .allPrivileges() 3232 .mapsTo(MISCREG_DBGBCR0); 3233 InitReg(MISCREG_DBGBCR1_EL1) 3234 .allPrivileges() 3235 .mapsTo(MISCREG_DBGBCR1); 3236 InitReg(MISCREG_DBGBCR2_EL1) 3237 .allPrivileges() 3238 .mapsTo(MISCREG_DBGBCR2); 3239 InitReg(MISCREG_DBGBCR3_EL1) 3240 .allPrivileges() 3241 .mapsTo(MISCREG_DBGBCR3); 3242 InitReg(MISCREG_DBGBCR4_EL1) 3243 .allPrivileges() 3244 .mapsTo(MISCREG_DBGBCR4); 3245 InitReg(MISCREG_DBGBCR5_EL1) 3246 .allPrivileges() 3247 .mapsTo(MISCREG_DBGBCR5); 3248 InitReg(MISCREG_DBGWVR0_EL1) 3249 .allPrivileges() 3250 .mapsTo(MISCREG_DBGWVR0); 3251 InitReg(MISCREG_DBGWVR1_EL1) 3252 .allPrivileges() 3253 .mapsTo(MISCREG_DBGWVR1); 3254 InitReg(MISCREG_DBGWVR2_EL1) 3255 .allPrivileges() 3256 .mapsTo(MISCREG_DBGWVR2); 3257 InitReg(MISCREG_DBGWVR3_EL1) 3258 .allPrivileges() 3259 .mapsTo(MISCREG_DBGWVR3); 3260 InitReg(MISCREG_DBGWCR0_EL1) 3261 .allPrivileges() 3262 .mapsTo(MISCREG_DBGWCR0); 3263 InitReg(MISCREG_DBGWCR1_EL1) 3264 .allPrivileges() 3265 .mapsTo(MISCREG_DBGWCR1); 3266 InitReg(MISCREG_DBGWCR2_EL1) 3267 .allPrivileges() 3268 .mapsTo(MISCREG_DBGWCR2); 3269 InitReg(MISCREG_DBGWCR3_EL1) 3270 .allPrivileges() 3271 .mapsTo(MISCREG_DBGWCR3); 3272 InitReg(MISCREG_MDCCSR_EL0) 3273 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3274 .mapsTo(MISCREG_DBGDSCRint); 3275 InitReg(MISCREG_MDDTR_EL0) 3276 .allPrivileges(); 3277 InitReg(MISCREG_MDDTRTX_EL0) 3278 .allPrivileges(); 3279 InitReg(MISCREG_MDDTRRX_EL0) 3280 .allPrivileges(); 3281 InitReg(MISCREG_DBGVCR32_EL2) 3282 .allPrivileges() 3283 .mapsTo(MISCREG_DBGVCR); 3284 InitReg(MISCREG_MDRAR_EL1) 3285 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3286 .mapsTo(MISCREG_DBGDRAR); 3287 InitReg(MISCREG_OSLAR_EL1) 3288 .allPrivileges().monSecureRead(0).monNonSecureRead(0) 3289 .mapsTo(MISCREG_DBGOSLAR); 3290 InitReg(MISCREG_OSLSR_EL1) 3291 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3292 .mapsTo(MISCREG_DBGOSLSR); 3293 InitReg(MISCREG_OSDLR_EL1) 3294 .allPrivileges() 3295 .mapsTo(MISCREG_DBGOSDLR); 3296 InitReg(MISCREG_DBGPRCR_EL1) 3297 .allPrivileges() 3298 .mapsTo(MISCREG_DBGPRCR); 3299 InitReg(MISCREG_DBGCLAIMSET_EL1) 3300 .allPrivileges() 3301 .mapsTo(MISCREG_DBGCLAIMSET); 3302 InitReg(MISCREG_DBGCLAIMCLR_EL1) 3303 .allPrivileges() 3304 .mapsTo(MISCREG_DBGCLAIMCLR); 3305 InitReg(MISCREG_DBGAUTHSTATUS_EL1) 3306 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3307 .mapsTo(MISCREG_DBGAUTHSTATUS); 3308 InitReg(MISCREG_TEECR32_EL1); 3309 InitReg(MISCREG_TEEHBR32_EL1); 3310 3311 // AArch64 registers (Op0=1,3); 3312 InitReg(MISCREG_MIDR_EL1) 3313 .allPrivileges().exceptUserMode().writes(0); 3314 InitReg(MISCREG_MPIDR_EL1) 3315 .allPrivileges().exceptUserMode().writes(0); 3316 InitReg(MISCREG_REVIDR_EL1) 3317 .allPrivileges().exceptUserMode().writes(0); 3318 InitReg(MISCREG_ID_PFR0_EL1) 3319 .allPrivileges().exceptUserMode().writes(0); 3320 InitReg(MISCREG_ID_PFR1_EL1) 3321 .allPrivileges().exceptUserMode().writes(0); 3322 InitReg(MISCREG_ID_DFR0_EL1) 3323 .allPrivileges().exceptUserMode().writes(0) 3324 .mapsTo(MISCREG_ID_DFR0); 3325 InitReg(MISCREG_ID_AFR0_EL1) 3326 .allPrivileges().exceptUserMode().writes(0); 3327 InitReg(MISCREG_ID_MMFR0_EL1) 3328 .allPrivileges().exceptUserMode().writes(0); 3329 InitReg(MISCREG_ID_MMFR1_EL1) 3330 .allPrivileges().exceptUserMode().writes(0); 3331 InitReg(MISCREG_ID_MMFR2_EL1) 3332 .allPrivileges().exceptUserMode().writes(0); 3333 InitReg(MISCREG_ID_MMFR3_EL1) 3334 .allPrivileges().exceptUserMode().writes(0); 3335 InitReg(MISCREG_ID_ISAR0_EL1) 3336 .allPrivileges().exceptUserMode().writes(0); 3337 InitReg(MISCREG_ID_ISAR1_EL1) 3338 .allPrivileges().exceptUserMode().writes(0); 3339 InitReg(MISCREG_ID_ISAR2_EL1) 3340 .allPrivileges().exceptUserMode().writes(0); 3341 InitReg(MISCREG_ID_ISAR3_EL1) 3342 .allPrivileges().exceptUserMode().writes(0); 3343 InitReg(MISCREG_ID_ISAR4_EL1) 3344 .allPrivileges().exceptUserMode().writes(0); 3345 InitReg(MISCREG_ID_ISAR5_EL1) 3346 .allPrivileges().exceptUserMode().writes(0); 3347 InitReg(MISCREG_MVFR0_EL1) 3348 .allPrivileges().exceptUserMode().writes(0); 3349 InitReg(MISCREG_MVFR1_EL1) 3350 .allPrivileges().exceptUserMode().writes(0); 3351 InitReg(MISCREG_MVFR2_EL1) 3352 .allPrivileges().exceptUserMode().writes(0); 3353 InitReg(MISCREG_ID_AA64PFR0_EL1) 3354 .allPrivileges().exceptUserMode().writes(0); 3355 InitReg(MISCREG_ID_AA64PFR1_EL1) 3356 .allPrivileges().exceptUserMode().writes(0); 3357 InitReg(MISCREG_ID_AA64DFR0_EL1) 3358 .allPrivileges().exceptUserMode().writes(0); 3359 InitReg(MISCREG_ID_AA64DFR1_EL1) 3360 .allPrivileges().exceptUserMode().writes(0); 3361 InitReg(MISCREG_ID_AA64AFR0_EL1) 3362 .allPrivileges().exceptUserMode().writes(0); 3363 InitReg(MISCREG_ID_AA64AFR1_EL1) 3364 .allPrivileges().exceptUserMode().writes(0); 3365 InitReg(MISCREG_ID_AA64ISAR0_EL1) 3366 .allPrivileges().exceptUserMode().writes(0); 3367 InitReg(MISCREG_ID_AA64ISAR1_EL1) 3368 .allPrivileges().exceptUserMode().writes(0); 3369 InitReg(MISCREG_ID_AA64MMFR0_EL1) 3370 .allPrivileges().exceptUserMode().writes(0); 3371 InitReg(MISCREG_ID_AA64MMFR1_EL1) 3372 .allPrivileges().exceptUserMode().writes(0); 3373 InitReg(MISCREG_CCSIDR_EL1) 3374 .allPrivileges().exceptUserMode().writes(0); 3375 InitReg(MISCREG_CLIDR_EL1) 3376 .allPrivileges().exceptUserMode().writes(0); 3377 InitReg(MISCREG_AIDR_EL1) 3378 .allPrivileges().exceptUserMode().writes(0); 3379 InitReg(MISCREG_CSSELR_EL1) 3380 .allPrivileges().exceptUserMode() 3381 .mapsTo(MISCREG_CSSELR_NS); 3382 InitReg(MISCREG_CTR_EL0) 3383 .reads(1); 3384 InitReg(MISCREG_DCZID_EL0) 3385 .reads(1); 3386 InitReg(MISCREG_VPIDR_EL2) 3387 .hyp().mon() 3388 .mapsTo(MISCREG_VPIDR); 3389 InitReg(MISCREG_VMPIDR_EL2) 3390 .hyp().mon() 3391 .mapsTo(MISCREG_VMPIDR); 3392 InitReg(MISCREG_SCTLR_EL1) 3393 .allPrivileges().exceptUserMode() 3394 .mapsTo(MISCREG_SCTLR_NS); 3395 InitReg(MISCREG_ACTLR_EL1) 3396 .allPrivileges().exceptUserMode() 3397 .mapsTo(MISCREG_ACTLR_NS); 3398 InitReg(MISCREG_CPACR_EL1) 3399 .allPrivileges().exceptUserMode() 3400 .mapsTo(MISCREG_CPACR); 3401 InitReg(MISCREG_SCTLR_EL2) 3402 .hyp().mon() 3403 .mapsTo(MISCREG_HSCTLR); 3404 InitReg(MISCREG_ACTLR_EL2) 3405 .hyp().mon() 3406 .mapsTo(MISCREG_HACTLR); 3407 InitReg(MISCREG_HCR_EL2) 3408 .hyp().mon() 3409 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/); 3410 InitReg(MISCREG_MDCR_EL2) 3411 .hyp().mon() 3412 .mapsTo(MISCREG_HDCR); 3413 InitReg(MISCREG_CPTR_EL2) 3414 .hyp().mon() 3415 .mapsTo(MISCREG_HCPTR); 3416 InitReg(MISCREG_HSTR_EL2) 3417 .hyp().mon() 3418 .mapsTo(MISCREG_HSTR); 3419 InitReg(MISCREG_HACR_EL2) 3420 .hyp().mon() 3421 .mapsTo(MISCREG_HACR); 3422 InitReg(MISCREG_SCTLR_EL3) 3423 .mon(); 3424 InitReg(MISCREG_ACTLR_EL3) 3425 .mon(); 3426 InitReg(MISCREG_SCR_EL3) 3427 .mon() 3428 .mapsTo(MISCREG_SCR); // NAM D7-2005 3429 InitReg(MISCREG_SDER32_EL3) 3430 .mon() 3431 .mapsTo(MISCREG_SDER); 3432 InitReg(MISCREG_CPTR_EL3) 3433 .mon(); 3434 InitReg(MISCREG_MDCR_EL3) 3435 .mon(); 3436 InitReg(MISCREG_TTBR0_EL1) 3437 .allPrivileges().exceptUserMode() 3438 .mapsTo(MISCREG_TTBR0_NS); 3439 InitReg(MISCREG_TTBR1_EL1) 3440 .allPrivileges().exceptUserMode() 3441 .mapsTo(MISCREG_TTBR1_NS); 3442 InitReg(MISCREG_TCR_EL1) 3443 .allPrivileges().exceptUserMode() 3444 .mapsTo(MISCREG_TTBCR_NS); 3445 InitReg(MISCREG_TTBR0_EL2) 3446 .hyp().mon() 3447 .mapsTo(MISCREG_HTTBR); 3448 InitReg(MISCREG_TCR_EL2) 3449 .hyp().mon() 3450 .mapsTo(MISCREG_HTCR); 3451 InitReg(MISCREG_VTTBR_EL2) 3452 .hyp().mon() 3453 .mapsTo(MISCREG_VTTBR); 3454 InitReg(MISCREG_VTCR_EL2) 3455 .hyp().mon() 3456 .mapsTo(MISCREG_VTCR); 3457 InitReg(MISCREG_TTBR0_EL3) 3458 .mon(); 3459 InitReg(MISCREG_TCR_EL3) 3460 .mon(); 3461 InitReg(MISCREG_DACR32_EL2) 3462 .hyp().mon() 3463 .mapsTo(MISCREG_DACR_NS); 3464 InitReg(MISCREG_SPSR_EL1) 3465 .allPrivileges().exceptUserMode() 3466 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1 3467 InitReg(MISCREG_ELR_EL1) 3468 .allPrivileges().exceptUserMode(); 3469 InitReg(MISCREG_SP_EL0) 3470 .allPrivileges().exceptUserMode(); 3471 InitReg(MISCREG_SPSEL) 3472 .allPrivileges().exceptUserMode(); 3473 InitReg(MISCREG_CURRENTEL) 3474 .allPrivileges().exceptUserMode().writes(0); 3475 InitReg(MISCREG_NZCV) 3476 .allPrivileges(); 3477 InitReg(MISCREG_DAIF) 3478 .allPrivileges(); 3479 InitReg(MISCREG_FPCR) 3480 .allPrivileges(); 3481 InitReg(MISCREG_FPSR) 3482 .allPrivileges(); 3483 InitReg(MISCREG_DSPSR_EL0) 3484 .allPrivileges(); 3485 InitReg(MISCREG_DLR_EL0) 3486 .allPrivileges(); 3487 InitReg(MISCREG_SPSR_EL2) 3488 .hyp().mon() 3489 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2 3490 InitReg(MISCREG_ELR_EL2) 3491 .hyp().mon(); 3492 InitReg(MISCREG_SP_EL1) 3493 .hyp().mon(); 3494 InitReg(MISCREG_SPSR_IRQ_AA64) 3495 .hyp().mon(); 3496 InitReg(MISCREG_SPSR_ABT_AA64) 3497 .hyp().mon(); 3498 InitReg(MISCREG_SPSR_UND_AA64) 3499 .hyp().mon(); 3500 InitReg(MISCREG_SPSR_FIQ_AA64) 3501 .hyp().mon(); 3502 InitReg(MISCREG_SPSR_EL3) 3503 .mon() 3504 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3 3505 InitReg(MISCREG_ELR_EL3) 3506 .mon(); 3507 InitReg(MISCREG_SP_EL2) 3508 .mon(); 3509 InitReg(MISCREG_AFSR0_EL1) 3510 .allPrivileges().exceptUserMode() 3511 .mapsTo(MISCREG_ADFSR_NS); 3512 InitReg(MISCREG_AFSR1_EL1) 3513 .allPrivileges().exceptUserMode() 3514 .mapsTo(MISCREG_AIFSR_NS); 3515 InitReg(MISCREG_ESR_EL1) 3516 .allPrivileges().exceptUserMode(); 3517 InitReg(MISCREG_IFSR32_EL2) 3518 .hyp().mon() 3519 .mapsTo(MISCREG_IFSR_NS); 3520 InitReg(MISCREG_AFSR0_EL2) 3521 .hyp().mon() 3522 .mapsTo(MISCREG_HADFSR); 3523 InitReg(MISCREG_AFSR1_EL2) 3524 .hyp().mon() 3525 .mapsTo(MISCREG_HAIFSR); 3526 InitReg(MISCREG_ESR_EL2) 3527 .hyp().mon() 3528 .mapsTo(MISCREG_HSR); 3529 InitReg(MISCREG_FPEXC32_EL2) 3530 .hyp().mon(); 3531 InitReg(MISCREG_AFSR0_EL3) 3532 .mon(); 3533 InitReg(MISCREG_AFSR1_EL3) 3534 .mon(); 3535 InitReg(MISCREG_ESR_EL3) 3536 .mon(); 3537 InitReg(MISCREG_FAR_EL1) 3538 .allPrivileges().exceptUserMode() 3539 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS); 3540 InitReg(MISCREG_FAR_EL2) 3541 .hyp().mon() 3542 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR); 3543 InitReg(MISCREG_HPFAR_EL2) 3544 .hyp().mon() 3545 .mapsTo(MISCREG_HPFAR); 3546 InitReg(MISCREG_FAR_EL3) 3547 .mon(); 3548 InitReg(MISCREG_IC_IALLUIS) 3549 .warnNotFail() 3550 .writes(1).exceptUserMode(); 3551 InitReg(MISCREG_PAR_EL1) 3552 .allPrivileges().exceptUserMode() 3553 .mapsTo(MISCREG_PAR_NS); 3554 InitReg(MISCREG_IC_IALLU) 3555 .warnNotFail() 3556 .writes(1).exceptUserMode(); 3557 InitReg(MISCREG_DC_IVAC_Xt) 3558 .warnNotFail() 3559 .writes(1).exceptUserMode(); 3560 InitReg(MISCREG_DC_ISW_Xt) 3561 .warnNotFail() 3562 .writes(1).exceptUserMode(); 3563 InitReg(MISCREG_AT_S1E1R_Xt) 3564 .writes(1).exceptUserMode(); 3565 InitReg(MISCREG_AT_S1E1W_Xt) 3566 .writes(1).exceptUserMode(); 3567 InitReg(MISCREG_AT_S1E0R_Xt) 3568 .writes(1).exceptUserMode(); 3569 InitReg(MISCREG_AT_S1E0W_Xt) 3570 .writes(1).exceptUserMode(); 3571 InitReg(MISCREG_DC_CSW_Xt) 3572 .warnNotFail() 3573 .writes(1).exceptUserMode(); 3574 InitReg(MISCREG_DC_CISW_Xt) 3575 .warnNotFail() 3576 .writes(1).exceptUserMode(); 3577 InitReg(MISCREG_DC_ZVA_Xt) 3578 .warnNotFail() 3579 .writes(1).userSecureWrite(0); 3580 InitReg(MISCREG_IC_IVAU_Xt) 3581 .writes(1); 3582 InitReg(MISCREG_DC_CVAC_Xt) 3583 .warnNotFail() 3584 .writes(1); 3585 InitReg(MISCREG_DC_CVAU_Xt) 3586 .warnNotFail() 3587 .writes(1); 3588 InitReg(MISCREG_DC_CIVAC_Xt) 3589 .warnNotFail() 3590 .writes(1); 3591 InitReg(MISCREG_AT_S1E2R_Xt) 3592 .monNonSecureWrite().hypWrite(); 3593 InitReg(MISCREG_AT_S1E2W_Xt) 3594 .monNonSecureWrite().hypWrite(); 3595 InitReg(MISCREG_AT_S12E1R_Xt) 3596 .hypWrite().monSecureWrite().monNonSecureWrite(); 3597 InitReg(MISCREG_AT_S12E1W_Xt) 3598 .hypWrite().monSecureWrite().monNonSecureWrite(); 3599 InitReg(MISCREG_AT_S12E0R_Xt) 3600 .hypWrite().monSecureWrite().monNonSecureWrite(); 3601 InitReg(MISCREG_AT_S12E0W_Xt) 3602 .hypWrite().monSecureWrite().monNonSecureWrite(); 3603 InitReg(MISCREG_AT_S1E3R_Xt) 3604 .monSecureWrite().monNonSecureWrite(); 3605 InitReg(MISCREG_AT_S1E3W_Xt) 3606 .monSecureWrite().monNonSecureWrite(); 3607 InitReg(MISCREG_TLBI_VMALLE1IS) 3608 .writes(1).exceptUserMode(); 3609 InitReg(MISCREG_TLBI_VAE1IS_Xt) 3610 .writes(1).exceptUserMode(); 3611 InitReg(MISCREG_TLBI_ASIDE1IS_Xt) 3612 .writes(1).exceptUserMode(); 3613 InitReg(MISCREG_TLBI_VAAE1IS_Xt) 3614 .writes(1).exceptUserMode(); 3615 InitReg(MISCREG_TLBI_VALE1IS_Xt) 3616 .writes(1).exceptUserMode(); 3617 InitReg(MISCREG_TLBI_VAALE1IS_Xt) 3618 .writes(1).exceptUserMode(); 3619 InitReg(MISCREG_TLBI_VMALLE1) 3620 .writes(1).exceptUserMode(); 3621 InitReg(MISCREG_TLBI_VAE1_Xt) 3622 .writes(1).exceptUserMode(); 3623 InitReg(MISCREG_TLBI_ASIDE1_Xt) 3624 .writes(1).exceptUserMode(); 3625 InitReg(MISCREG_TLBI_VAAE1_Xt) 3626 .writes(1).exceptUserMode(); 3627 InitReg(MISCREG_TLBI_VALE1_Xt) 3628 .writes(1).exceptUserMode(); 3629 InitReg(MISCREG_TLBI_VAALE1_Xt) 3630 .writes(1).exceptUserMode(); 3631 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt) 3632 .hypWrite().monSecureWrite().monNonSecureWrite(); 3633 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt) 3634 .hypWrite().monSecureWrite().monNonSecureWrite(); 3635 InitReg(MISCREG_TLBI_ALLE2IS) 3636 .monNonSecureWrite().hypWrite(); 3637 InitReg(MISCREG_TLBI_VAE2IS_Xt) 3638 .monNonSecureWrite().hypWrite(); 3639 InitReg(MISCREG_TLBI_ALLE1IS) 3640 .hypWrite().monSecureWrite().monNonSecureWrite(); 3641 InitReg(MISCREG_TLBI_VALE2IS_Xt) 3642 .monNonSecureWrite().hypWrite(); 3643 InitReg(MISCREG_TLBI_VMALLS12E1IS) 3644 .hypWrite().monSecureWrite().monNonSecureWrite(); 3645 InitReg(MISCREG_TLBI_IPAS2E1_Xt) 3646 .hypWrite().monSecureWrite().monNonSecureWrite(); 3647 InitReg(MISCREG_TLBI_IPAS2LE1_Xt) 3648 .hypWrite().monSecureWrite().monNonSecureWrite(); 3649 InitReg(MISCREG_TLBI_ALLE2) 3650 .monNonSecureWrite().hypWrite(); 3651 InitReg(MISCREG_TLBI_VAE2_Xt) 3652 .monNonSecureWrite().hypWrite(); 3653 InitReg(MISCREG_TLBI_ALLE1) 3654 .hypWrite().monSecureWrite().monNonSecureWrite(); 3655 InitReg(MISCREG_TLBI_VALE2_Xt) 3656 .monNonSecureWrite().hypWrite(); 3657 InitReg(MISCREG_TLBI_VMALLS12E1) 3658 .hypWrite().monSecureWrite().monNonSecureWrite(); 3659 InitReg(MISCREG_TLBI_ALLE3IS) 3660 .monSecureWrite().monNonSecureWrite(); 3661 InitReg(MISCREG_TLBI_VAE3IS_Xt) 3662 .monSecureWrite().monNonSecureWrite(); 3663 InitReg(MISCREG_TLBI_VALE3IS_Xt) 3664 .monSecureWrite().monNonSecureWrite(); 3665 InitReg(MISCREG_TLBI_ALLE3) 3666 .monSecureWrite().monNonSecureWrite(); 3667 InitReg(MISCREG_TLBI_VAE3_Xt) 3668 .monSecureWrite().monNonSecureWrite(); 3669 InitReg(MISCREG_TLBI_VALE3_Xt) 3670 .monSecureWrite().monNonSecureWrite(); 3671 InitReg(MISCREG_PMINTENSET_EL1) 3672 .allPrivileges().exceptUserMode() 3673 .mapsTo(MISCREG_PMINTENSET); 3674 InitReg(MISCREG_PMINTENCLR_EL1) 3675 .allPrivileges().exceptUserMode() 3676 .mapsTo(MISCREG_PMINTENCLR); 3677 InitReg(MISCREG_PMCR_EL0) 3678 .allPrivileges() 3679 .mapsTo(MISCREG_PMCR); 3680 InitReg(MISCREG_PMCNTENSET_EL0) 3681 .allPrivileges() 3682 .mapsTo(MISCREG_PMCNTENSET); 3683 InitReg(MISCREG_PMCNTENCLR_EL0) 3684 .allPrivileges() 3685 .mapsTo(MISCREG_PMCNTENCLR); 3686 InitReg(MISCREG_PMOVSCLR_EL0) 3687 .allPrivileges(); 3688// .mapsTo(MISCREG_PMOVSCLR); 3689 InitReg(MISCREG_PMSWINC_EL0) 3690 .writes(1).user() 3691 .mapsTo(MISCREG_PMSWINC); 3692 InitReg(MISCREG_PMSELR_EL0) 3693 .allPrivileges() 3694 .mapsTo(MISCREG_PMSELR); 3695 InitReg(MISCREG_PMCEID0_EL0) 3696 .reads(1).user() 3697 .mapsTo(MISCREG_PMCEID0); 3698 InitReg(MISCREG_PMCEID1_EL0) 3699 .reads(1).user() 3700 .mapsTo(MISCREG_PMCEID1); 3701 InitReg(MISCREG_PMCCNTR_EL0) 3702 .allPrivileges() 3703 .mapsTo(MISCREG_PMCCNTR); 3704 InitReg(MISCREG_PMXEVTYPER_EL0) 3705 .allPrivileges() 3706 .mapsTo(MISCREG_PMXEVTYPER); 3707 InitReg(MISCREG_PMCCFILTR_EL0) 3708 .allPrivileges(); 3709 InitReg(MISCREG_PMXEVCNTR_EL0) 3710 .allPrivileges() 3711 .mapsTo(MISCREG_PMXEVCNTR); 3712 InitReg(MISCREG_PMUSERENR_EL0) 3713 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 3714 .mapsTo(MISCREG_PMUSERENR); 3715 InitReg(MISCREG_PMOVSSET_EL0) 3716 .allPrivileges() 3717 .mapsTo(MISCREG_PMOVSSET); 3718 InitReg(MISCREG_MAIR_EL1) 3719 .allPrivileges().exceptUserMode() 3720 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS); 3721 InitReg(MISCREG_AMAIR_EL1) 3722 .allPrivileges().exceptUserMode() 3723 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS); 3724 InitReg(MISCREG_MAIR_EL2) 3725 .hyp().mon() 3726 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1); 3727 InitReg(MISCREG_AMAIR_EL2) 3728 .hyp().mon() 3729 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1); 3730 InitReg(MISCREG_MAIR_EL3) 3731 .mon(); 3732 InitReg(MISCREG_AMAIR_EL3) 3733 .mon(); 3734 InitReg(MISCREG_L2CTLR_EL1) 3735 .allPrivileges().exceptUserMode(); 3736 InitReg(MISCREG_L2ECTLR_EL1) 3737 .allPrivileges().exceptUserMode(); 3738 InitReg(MISCREG_VBAR_EL1) 3739 .allPrivileges().exceptUserMode() 3740 .mapsTo(MISCREG_VBAR_NS); 3741 InitReg(MISCREG_RVBAR_EL1) 3742 .allPrivileges().exceptUserMode().writes(0); 3743 InitReg(MISCREG_ISR_EL1) 3744 .allPrivileges().exceptUserMode().writes(0); 3745 InitReg(MISCREG_VBAR_EL2) 3746 .hyp().mon() 3747 .mapsTo(MISCREG_HVBAR); 3748 InitReg(MISCREG_RVBAR_EL2) 3749 .mon().hyp().writes(0); 3750 InitReg(MISCREG_VBAR_EL3) 3751 .mon(); 3752 InitReg(MISCREG_RVBAR_EL3) 3753 .mon().writes(0); 3754 InitReg(MISCREG_RMR_EL3) 3755 .mon(); 3756 InitReg(MISCREG_CONTEXTIDR_EL1) 3757 .allPrivileges().exceptUserMode() 3758 .mapsTo(MISCREG_CONTEXTIDR_NS); 3759 InitReg(MISCREG_TPIDR_EL1) 3760 .allPrivileges().exceptUserMode() 3761 .mapsTo(MISCREG_TPIDRPRW_NS); 3762 InitReg(MISCREG_TPIDR_EL0) 3763 .allPrivileges() 3764 .mapsTo(MISCREG_TPIDRURW_NS); 3765 InitReg(MISCREG_TPIDRRO_EL0) 3766 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 3767 .mapsTo(MISCREG_TPIDRURO_NS); 3768 InitReg(MISCREG_TPIDR_EL2) 3769 .hyp().mon() 3770 .mapsTo(MISCREG_HTPIDR); 3771 InitReg(MISCREG_TPIDR_EL3) 3772 .mon(); 3773 InitReg(MISCREG_CNTKCTL_EL1) 3774 .allPrivileges().exceptUserMode() 3775 .mapsTo(MISCREG_CNTKCTL); 3776 InitReg(MISCREG_CNTFRQ_EL0) 3777 .reads(1).mon() 3778 .mapsTo(MISCREG_CNTFRQ); 3779 InitReg(MISCREG_CNTPCT_EL0) 3780 .reads(1) 3781 .mapsTo(MISCREG_CNTPCT); /* 64b */ 3782 InitReg(MISCREG_CNTVCT_EL0) 3783 .unverifiable() 3784 .reads(1) 3785 .mapsTo(MISCREG_CNTVCT); /* 64b */ 3786 InitReg(MISCREG_CNTP_TVAL_EL0) 3787 .allPrivileges() 3788 .mapsTo(MISCREG_CNTP_TVAL_NS); 3789 InitReg(MISCREG_CNTP_CTL_EL0) 3790 .allPrivileges() 3791 .mapsTo(MISCREG_CNTP_CTL_NS); 3792 InitReg(MISCREG_CNTP_CVAL_EL0) 3793 .allPrivileges() 3794 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */ 3795 InitReg(MISCREG_CNTV_TVAL_EL0) 3796 .allPrivileges() 3797 .mapsTo(MISCREG_CNTV_TVAL); 3798 InitReg(MISCREG_CNTV_CTL_EL0) 3799 .allPrivileges() 3800 .mapsTo(MISCREG_CNTV_CTL); 3801 InitReg(MISCREG_CNTV_CVAL_EL0) 3802 .allPrivileges() 3803 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */ 3804 InitReg(MISCREG_PMEVCNTR0_EL0) 3805 .allPrivileges(); 3806// .mapsTo(MISCREG_PMEVCNTR0); 3807 InitReg(MISCREG_PMEVCNTR1_EL0) 3808 .allPrivileges(); 3809// .mapsTo(MISCREG_PMEVCNTR1); 3810 InitReg(MISCREG_PMEVCNTR2_EL0) 3811 .allPrivileges(); 3812// .mapsTo(MISCREG_PMEVCNTR2); 3813 InitReg(MISCREG_PMEVCNTR3_EL0) 3814 .allPrivileges(); 3815// .mapsTo(MISCREG_PMEVCNTR3); 3816 InitReg(MISCREG_PMEVCNTR4_EL0) 3817 .allPrivileges(); 3818// .mapsTo(MISCREG_PMEVCNTR4); 3819 InitReg(MISCREG_PMEVCNTR5_EL0) 3820 .allPrivileges(); 3821// .mapsTo(MISCREG_PMEVCNTR5); 3822 InitReg(MISCREG_PMEVTYPER0_EL0) 3823 .allPrivileges(); 3824// .mapsTo(MISCREG_PMEVTYPER0); 3825 InitReg(MISCREG_PMEVTYPER1_EL0) 3826 .allPrivileges(); 3827// .mapsTo(MISCREG_PMEVTYPER1); 3828 InitReg(MISCREG_PMEVTYPER2_EL0) 3829 .allPrivileges(); 3830// .mapsTo(MISCREG_PMEVTYPER2); 3831 InitReg(MISCREG_PMEVTYPER3_EL0) 3832 .allPrivileges(); 3833// .mapsTo(MISCREG_PMEVTYPER3); 3834 InitReg(MISCREG_PMEVTYPER4_EL0) 3835 .allPrivileges(); 3836// .mapsTo(MISCREG_PMEVTYPER4); 3837 InitReg(MISCREG_PMEVTYPER5_EL0) 3838 .allPrivileges(); 3839// .mapsTo(MISCREG_PMEVTYPER5); 3840 InitReg(MISCREG_CNTVOFF_EL2) 3841 .hyp().mon() 3842 .mapsTo(MISCREG_CNTVOFF); /* 64b */ 3843 InitReg(MISCREG_CNTHCTL_EL2) 3844 .unimplemented() 3845 .warnNotFail() 3846 .mon().monNonSecureWrite(0).hypWrite() 3847 .mapsTo(MISCREG_CNTHCTL); 3848 InitReg(MISCREG_CNTHP_TVAL_EL2) 3849 .unimplemented() 3850 .mon().monNonSecureWrite(0).hypWrite() 3851 .mapsTo(MISCREG_CNTHP_TVAL); 3852 InitReg(MISCREG_CNTHP_CTL_EL2) 3853 .unimplemented() 3854 .mon().monNonSecureWrite(0).hypWrite() 3855 .mapsTo(MISCREG_CNTHP_CTL); 3856 InitReg(MISCREG_CNTHP_CVAL_EL2) 3857 .unimplemented() 3858 .mon().monNonSecureWrite(0).hypWrite() 3859 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */ 3860 InitReg(MISCREG_CNTPS_TVAL_EL1) 3861 .unimplemented() 3862 .mon().monNonSecureWrite(0).hypWrite(); 3863 InitReg(MISCREG_CNTPS_CTL_EL1) 3864 .unimplemented() 3865 .mon().monNonSecureWrite(0).hypWrite(); 3866 InitReg(MISCREG_CNTPS_CVAL_EL1) 3867 .unimplemented() 3868 .mon().monNonSecureWrite(0).hypWrite(); 3869 InitReg(MISCREG_IL1DATA0_EL1) 3870 .allPrivileges().exceptUserMode(); 3871 InitReg(MISCREG_IL1DATA1_EL1) 3872 .allPrivileges().exceptUserMode(); 3873 InitReg(MISCREG_IL1DATA2_EL1) 3874 .allPrivileges().exceptUserMode(); 3875 InitReg(MISCREG_IL1DATA3_EL1) 3876 .allPrivileges().exceptUserMode(); 3877 InitReg(MISCREG_DL1DATA0_EL1) 3878 .allPrivileges().exceptUserMode(); 3879 InitReg(MISCREG_DL1DATA1_EL1) 3880 .allPrivileges().exceptUserMode(); 3881 InitReg(MISCREG_DL1DATA2_EL1) 3882 .allPrivileges().exceptUserMode(); 3883 InitReg(MISCREG_DL1DATA3_EL1) 3884 .allPrivileges().exceptUserMode(); 3885 InitReg(MISCREG_DL1DATA4_EL1) 3886 .allPrivileges().exceptUserMode(); 3887 InitReg(MISCREG_L2ACTLR_EL1) 3888 .allPrivileges().exceptUserMode(); 3889 InitReg(MISCREG_CPUACTLR_EL1) 3890 .allPrivileges().exceptUserMode(); 3891 InitReg(MISCREG_CPUECTLR_EL1) 3892 .allPrivileges().exceptUserMode(); 3893 InitReg(MISCREG_CPUMERRSR_EL1) 3894 .allPrivileges().exceptUserMode(); 3895 InitReg(MISCREG_L2MERRSR_EL1) 3896 .unimplemented() 3897 .warnNotFail() 3898 .allPrivileges().exceptUserMode(); 3899 InitReg(MISCREG_CBAR_EL1) 3900 .allPrivileges().exceptUserMode().writes(0); 3901 InitReg(MISCREG_CONTEXTIDR_EL2) 3902 .mon().hyp(); 3903 3904 // Dummy registers 3905 InitReg(MISCREG_NOP) 3906 .allPrivileges(); 3907 InitReg(MISCREG_RAZ) 3908 .allPrivileges().exceptUserMode().writes(0); 3909 InitReg(MISCREG_CP14_UNIMPL) 3910 .unimplemented() 3911 .warnNotFail(); 3912 InitReg(MISCREG_CP15_UNIMPL) 3913 .unimplemented() 3914 .warnNotFail(); 3915 InitReg(MISCREG_A64_UNIMPL) 3916 .unimplemented() 3917 .warnNotFail(); 3918 InitReg(MISCREG_UNKNOWN); 3919 3920 // Register mappings for some unimplemented registers: 3921 // ESR_EL1 -> DFSR 3922 // RMR_EL1 -> RMR 3923 // RMR_EL2 -> HRMR 3924 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 3925 // DBGDTRRX_EL0 -> DBGDTRRXint 3926 // DBGDTRTX_EL0 -> DBGDTRRXint 3927 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5) 3928 3929 completed = true; 3930} 3931 3932} // namespace ArmISA 3933