miscregs.cc revision 12334:e0ab29a34764
1/* 2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 * Giacomo Gabrielli 40 */ 41 42#include "arch/arm/miscregs.hh" 43 44#include <tuple> 45 46#include "arch/arm/isa.hh" 47#include "base/logging.hh" 48#include "cpu/thread_context.hh" 49#include "sim/full_system.hh" 50 51namespace ArmISA 52{ 53 54MiscRegIndex 55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 56{ 57 switch(crn) { 58 case 0: 59 switch (opc1) { 60 case 0: 61 switch (opc2) { 62 case 0: 63 switch (crm) { 64 case 0: 65 return MISCREG_DBGDIDR; 66 case 1: 67 return MISCREG_DBGDSCRint; 68 } 69 break; 70 } 71 break; 72 case 7: 73 switch (opc2) { 74 case 0: 75 switch (crm) { 76 case 0: 77 return MISCREG_JIDR; 78 } 79 break; 80 } 81 break; 82 } 83 break; 84 case 1: 85 switch (opc1) { 86 case 6: 87 switch (crm) { 88 case 0: 89 switch (opc2) { 90 case 0: 91 return MISCREG_TEEHBR; 92 } 93 break; 94 } 95 break; 96 case 7: 97 switch (crm) { 98 case 0: 99 switch (opc2) { 100 case 0: 101 return MISCREG_JOSCR; 102 } 103 break; 104 } 105 break; 106 } 107 break; 108 case 2: 109 switch (opc1) { 110 case 7: 111 switch (crm) { 112 case 0: 113 switch (opc2) { 114 case 0: 115 return MISCREG_JMCR; 116 } 117 break; 118 } 119 break; 120 } 121 break; 122 } 123 // If we get here then it must be a register that we haven't implemented 124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 125 crn, opc1, crm, opc2); 126 return MISCREG_CP14_UNIMPL; 127} 128 129using namespace std; 130 131bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = { 132 // MISCREG_CPSR 133 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 134 // MISCREG_SPSR 135 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 136 // MISCREG_SPSR_FIQ 137 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 138 // MISCREG_SPSR_IRQ 139 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 140 // MISCREG_SPSR_SVC 141 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 142 // MISCREG_SPSR_MON 143 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 144 // MISCREG_SPSR_ABT 145 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 146 // MISCREG_SPSR_HYP 147 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 148 // MISCREG_SPSR_UND 149 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 150 // MISCREG_ELR_HYP 151 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 152 // MISCREG_FPSID 153 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 154 // MISCREG_FPSCR 155 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 156 // MISCREG_MVFR1 157 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 158 // MISCREG_MVFR0 159 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 160 // MISCREG_FPEXC 161 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 162 163 // Helper registers 164 // MISCREG_CPSR_MODE 165 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 166 // MISCREG_CPSR_Q 167 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 168 // MISCREG_FPSCR_Q 169 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 170 // MISCREG_FPSCR_EXC 171 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 172 // MISCREG_LOCKADDR 173 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 174 // MISCREG_LOCKFLAG 175 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 176 // MISCREG_PRRR_MAIR0 177 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")), 178 // MISCREG_PRRR_MAIR0_NS 179 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 180 // MISCREG_PRRR_MAIR0_S 181 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 182 // MISCREG_NMRR_MAIR1 183 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")), 184 // MISCREG_NMRR_MAIR1_NS 185 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 186 // MISCREG_NMRR_MAIR1_S 187 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 188 // MISCREG_PMXEVTYPER_PMCCFILTR 189 bitset<NUM_MISCREG_INFOS>(string("00000000000000001001")), 190 // MISCREG_SCTLR_RST 191 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 192 // MISCREG_SEV_MAILBOX 193 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 194 195 // AArch32 CP14 registers 196 // MISCREG_DBGDIDR 197 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 198 // MISCREG_DBGDSCRint 199 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 200 // MISCREG_DBGDCCINT 201 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 202 // MISCREG_DBGDTRTXint 203 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 204 // MISCREG_DBGDTRRXint 205 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 206 // MISCREG_DBGWFAR 207 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 208 // MISCREG_DBGVCR 209 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 210 // MISCREG_DBGDTRRXext 211 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 212 // MISCREG_DBGDSCRext 213 bitset<NUM_MISCREG_INFOS>(string("11111111111111000100")), 214 // MISCREG_DBGDTRTXext 215 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 216 // MISCREG_DBGOSECCR 217 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 218 // MISCREG_DBGBVR0 219 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 220 // MISCREG_DBGBVR1 221 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 222 // MISCREG_DBGBVR2 223 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 224 // MISCREG_DBGBVR3 225 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 226 // MISCREG_DBGBVR4 227 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 228 // MISCREG_DBGBVR5 229 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 230 // MISCREG_DBGBCR0 231 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 232 // MISCREG_DBGBCR1 233 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 234 // MISCREG_DBGBCR2 235 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 236 // MISCREG_DBGBCR3 237 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 238 // MISCREG_DBGBCR4 239 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 240 // MISCREG_DBGBCR5 241 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 242 // MISCREG_DBGWVR0 243 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 244 // MISCREG_DBGWVR1 245 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 246 // MISCREG_DBGWVR2 247 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 248 // MISCREG_DBGWVR3 249 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 250 // MISCREG_DBGWCR0 251 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 252 // MISCREG_DBGWCR1 253 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 254 // MISCREG_DBGWCR2 255 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 256 // MISCREG_DBGWCR3 257 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 258 // MISCREG_DBGDRAR 259 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 260 // MISCREG_DBGBXVR4 261 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 262 // MISCREG_DBGBXVR5 263 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 264 // MISCREG_DBGOSLAR 265 bitset<NUM_MISCREG_INFOS>(string("10101111111111000000")), 266 // MISCREG_DBGOSLSR 267 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 268 // MISCREG_DBGOSDLR 269 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 270 // MISCREG_DBGPRCR 271 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 272 // MISCREG_DBGDSAR 273 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 274 // MISCREG_DBGCLAIMSET 275 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 276 // MISCREG_DBGCLAIMCLR 277 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 278 // MISCREG_DBGAUTHSTATUS 279 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 280 // MISCREG_DBGDEVID2 281 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 282 // MISCREG_DBGDEVID1 283 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 284 // MISCREG_DBGDEVID0 285 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 286 // MISCREG_TEECR 287 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 288 // MISCREG_JIDR 289 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 290 // MISCREG_TEEHBR 291 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 292 // MISCREG_JOSCR 293 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 294 // MISCREG_JMCR 295 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 296 297 // AArch32 CP15 registers 298 // MISCREG_MIDR 299 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 300 // MISCREG_CTR 301 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 302 // MISCREG_TCMTR 303 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 304 // MISCREG_TLBTR 305 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 306 // MISCREG_MPIDR 307 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 308 // MISCREG_REVIDR 309 bitset<NUM_MISCREG_INFOS>(string("01010101010000000100")), 310 // MISCREG_ID_PFR0 311 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 312 // MISCREG_ID_PFR1 313 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 314 // MISCREG_ID_DFR0 315 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 316 // MISCREG_ID_AFR0 317 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 318 // MISCREG_ID_MMFR0 319 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 320 // MISCREG_ID_MMFR1 321 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 322 // MISCREG_ID_MMFR2 323 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 324 // MISCREG_ID_MMFR3 325 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 326 // MISCREG_ID_ISAR0 327 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 328 // MISCREG_ID_ISAR1 329 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 330 // MISCREG_ID_ISAR2 331 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 332 // MISCREG_ID_ISAR3 333 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 334 // MISCREG_ID_ISAR4 335 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 336 // MISCREG_ID_ISAR5 337 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 338 // MISCREG_CCSIDR 339 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 340 // MISCREG_CLIDR 341 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 342 // MISCREG_AIDR 343 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 344 // MISCREG_CSSELR 345 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 346 // MISCREG_CSSELR_NS 347 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 348 // MISCREG_CSSELR_S 349 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 350 // MISCREG_VPIDR 351 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 352 // MISCREG_VMPIDR 353 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 354 // MISCREG_SCTLR 355 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 356 // MISCREG_SCTLR_NS 357 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 358 // MISCREG_SCTLR_S 359 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 360 // MISCREG_ACTLR 361 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 362 // MISCREG_ACTLR_NS 363 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 364 // MISCREG_ACTLR_S 365 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 366 // MISCREG_CPACR 367 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 368 // MISCREG_SCR 369 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")), 370 // MISCREG_SDER 371 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 372 // MISCREG_NSACR 373 bitset<NUM_MISCREG_INFOS>(string("11110111010000000001")), 374 // MISCREG_HSCTLR 375 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 376 // MISCREG_HACTLR 377 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 378 // MISCREG_HCR 379 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 380 // MISCREG_HDCR 381 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 382 // MISCREG_HCPTR 383 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 384 // MISCREG_HSTR 385 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 386 // MISCREG_HACR 387 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")), 388 // MISCREG_TTBR0 389 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 390 // MISCREG_TTBR0_NS 391 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 392 // MISCREG_TTBR0_S 393 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 394 // MISCREG_TTBR1 395 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 396 // MISCREG_TTBR1_NS 397 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 398 // MISCREG_TTBR1_S 399 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 400 // MISCREG_TTBCR 401 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 402 // MISCREG_TTBCR_NS 403 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 404 // MISCREG_TTBCR_S 405 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 406 // MISCREG_HTCR 407 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 408 // MISCREG_VTCR 409 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 410 // MISCREG_DACR 411 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 412 // MISCREG_DACR_NS 413 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 414 // MISCREG_DACR_S 415 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 416 // MISCREG_DFSR 417 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 418 // MISCREG_DFSR_NS 419 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 420 // MISCREG_DFSR_S 421 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 422 // MISCREG_IFSR 423 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 424 // MISCREG_IFSR_NS 425 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 426 // MISCREG_IFSR_S 427 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 428 // MISCREG_ADFSR 429 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")), 430 // MISCREG_ADFSR_NS 431 bitset<NUM_MISCREG_INFOS>(string("11001111110000100100")), 432 // MISCREG_ADFSR_S 433 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")), 434 // MISCREG_AIFSR 435 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")), 436 // MISCREG_AIFSR_NS 437 bitset<NUM_MISCREG_INFOS>(string("11001111110000100100")), 438 // MISCREG_AIFSR_S 439 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")), 440 // MISCREG_HADFSR 441 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 442 // MISCREG_HAIFSR 443 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 444 // MISCREG_HSR 445 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 446 // MISCREG_DFAR 447 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 448 // MISCREG_DFAR_NS 449 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 450 // MISCREG_DFAR_S 451 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 452 // MISCREG_IFAR 453 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 454 // MISCREG_IFAR_NS 455 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 456 // MISCREG_IFAR_S 457 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 458 // MISCREG_HDFAR 459 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 460 // MISCREG_HIFAR 461 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 462 // MISCREG_HPFAR 463 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 464 // MISCREG_ICIALLUIS 465 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 466 // MISCREG_BPIALLIS 467 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 468 // MISCREG_PAR 469 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 470 // MISCREG_PAR_NS 471 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 472 // MISCREG_PAR_S 473 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 474 // MISCREG_ICIALLU 475 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 476 // MISCREG_ICIMVAU 477 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 478 // MISCREG_CP15ISB 479 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 480 // MISCREG_BPIALL 481 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 482 // MISCREG_BPIMVA 483 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 484 // MISCREG_DCIMVAC 485 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 486 // MISCREG_DCISW 487 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 488 // MISCREG_ATS1CPR 489 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 490 // MISCREG_ATS1CPW 491 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 492 // MISCREG_ATS1CUR 493 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 494 // MISCREG_ATS1CUW 495 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 496 // MISCREG_ATS12NSOPR 497 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 498 // MISCREG_ATS12NSOPW 499 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 500 // MISCREG_ATS12NSOUR 501 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 502 // MISCREG_ATS12NSOUW 503 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 504 // MISCREG_DCCMVAC 505 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 506 // MISCREG_DCCSW 507 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 508 // MISCREG_CP15DSB 509 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 510 // MISCREG_CP15DMB 511 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 512 // MISCREG_DCCMVAU 513 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 514 // MISCREG_DCCIMVAC 515 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 516 // MISCREG_DCCISW 517 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 518 // MISCREG_ATS1HR 519 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 520 // MISCREG_ATS1HW 521 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 522 // MISCREG_TLBIALLIS 523 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 524 // MISCREG_TLBIMVAIS 525 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 526 // MISCREG_TLBIASIDIS 527 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 528 // MISCREG_TLBIMVAAIS 529 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 530 // MISCREG_TLBIMVALIS 531 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 532 // MISCREG_TLBIMVAALIS 533 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 534 // MISCREG_ITLBIALL 535 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 536 // MISCREG_ITLBIMVA 537 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 538 // MISCREG_ITLBIASID 539 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 540 // MISCREG_DTLBIALL 541 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 542 // MISCREG_DTLBIMVA 543 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 544 // MISCREG_DTLBIASID 545 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 546 // MISCREG_TLBIALL 547 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 548 // MISCREG_TLBIMVA 549 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 550 // MISCREG_TLBIASID 551 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 552 // MISCREG_TLBIMVAA 553 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 554 // MISCREG_TLBIMVAL 555 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 556 // MISCREG_TLBIMVAAL 557 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 558 // MISCREG_TLBIIPAS2IS 559 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 560 // MISCREG_TLBIIPAS2LIS 561 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 562 // MISCREG_TLBIALLHIS 563 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 564 // MISCREG_TLBIMVAHIS 565 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 566 // MISCREG_TLBIALLNSNHIS 567 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 568 // MISCREG_TLBIMVALHIS 569 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 570 // MISCREG_TLBIIPAS2 571 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 572 // MISCREG_TLBIIPAS2L 573 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 574 // MISCREG_TLBIALLH 575 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 576 // MISCREG_TLBIMVAH 577 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 578 // MISCREG_TLBIALLNSNH 579 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 580 // MISCREG_TLBIMVALH 581 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 582 // MISCREG_PMCR 583 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 584 // MISCREG_PMCNTENSET 585 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 586 // MISCREG_PMCNTENCLR 587 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 588 // MISCREG_PMOVSR 589 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 590 // MISCREG_PMSWINC 591 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 592 // MISCREG_PMSELR 593 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 594 // MISCREG_PMCEID0 595 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 596 // MISCREG_PMCEID1 597 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 598 // MISCREG_PMCCNTR 599 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 600 // MISCREG_PMXEVTYPER 601 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 602 // MISCREG_PMCCFILTR 603 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 604 // MISCREG_PMXEVCNTR 605 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 606 // MISCREG_PMUSERENR 607 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")), 608 // MISCREG_PMINTENSET 609 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 610 // MISCREG_PMINTENCLR 611 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 612 // MISCREG_PMOVSSET 613 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 614 // MISCREG_L2CTLR 615 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 616 // MISCREG_L2ECTLR 617 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 618 // MISCREG_PRRR 619 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 620 // MISCREG_PRRR_NS 621 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 622 // MISCREG_PRRR_S 623 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 624 // MISCREG_MAIR0 625 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 626 // MISCREG_MAIR0_NS 627 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 628 // MISCREG_MAIR0_S 629 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 630 // MISCREG_NMRR 631 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 632 // MISCREG_NMRR_NS 633 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 634 // MISCREG_NMRR_S 635 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 636 // MISCREG_MAIR1 637 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 638 // MISCREG_MAIR1_NS 639 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 640 // MISCREG_MAIR1_S 641 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 642 // MISCREG_AMAIR0 643 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 644 // MISCREG_AMAIR0_NS 645 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 646 // MISCREG_AMAIR0_S 647 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 648 // MISCREG_AMAIR1 649 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 650 // MISCREG_AMAIR1_NS 651 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 652 // MISCREG_AMAIR1_S 653 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 654 // MISCREG_HMAIR0 655 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 656 // MISCREG_HMAIR1 657 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 658 // MISCREG_HAMAIR0 659 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")), 660 // MISCREG_HAMAIR1 661 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")), 662 // MISCREG_VBAR 663 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 664 // MISCREG_VBAR_NS 665 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 666 // MISCREG_VBAR_S 667 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 668 // MISCREG_MVBAR 669 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")), 670 // MISCREG_RMR 671 bitset<NUM_MISCREG_INFOS>(string("11110011000000000000")), 672 // MISCREG_ISR 673 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 674 // MISCREG_HVBAR 675 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 676 // MISCREG_FCSEIDR 677 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), 678 // MISCREG_CONTEXTIDR 679 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 680 // MISCREG_CONTEXTIDR_NS 681 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 682 // MISCREG_CONTEXTIDR_S 683 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 684 // MISCREG_TPIDRURW 685 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 686 // MISCREG_TPIDRURW_NS 687 bitset<NUM_MISCREG_INFOS>(string("11001111111111100001")), 688 // MISCREG_TPIDRURW_S 689 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 690 // MISCREG_TPIDRURO 691 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 692 // MISCREG_TPIDRURO_NS 693 bitset<NUM_MISCREG_INFOS>(string("11001111110101100001")), 694 // MISCREG_TPIDRURO_S 695 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 696 // MISCREG_TPIDRPRW 697 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 698 // MISCREG_TPIDRPRW_NS 699 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 700 // MISCREG_TPIDRPRW_S 701 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 702 // MISCREG_HTPIDR 703 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 704 // MISCREG_CNTFRQ 705 bitset<NUM_MISCREG_INFOS>(string("11110101010101000011")), 706 // MISCREG_CNTKCTL 707 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 708 // MISCREG_CNTP_TVAL 709 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 710 // MISCREG_CNTP_TVAL_NS 711 bitset<NUM_MISCREG_INFOS>(string("11001111111111100001")), 712 // MISCREG_CNTP_TVAL_S 713 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")), 714 // MISCREG_CNTP_CTL 715 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 716 // MISCREG_CNTP_CTL_NS 717 bitset<NUM_MISCREG_INFOS>(string("11001111111111100001")), 718 // MISCREG_CNTP_CTL_S 719 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")), 720 // MISCREG_CNTV_TVAL 721 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 722 // MISCREG_CNTV_CTL 723 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 724 // MISCREG_CNTHCTL 725 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 726 // MISCREG_CNTHP_TVAL 727 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 728 // MISCREG_CNTHP_CTL 729 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 730 // MISCREG_IL1DATA0 731 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 732 // MISCREG_IL1DATA1 733 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 734 // MISCREG_IL1DATA2 735 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 736 // MISCREG_IL1DATA3 737 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 738 // MISCREG_DL1DATA0 739 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 740 // MISCREG_DL1DATA1 741 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 742 // MISCREG_DL1DATA2 743 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 744 // MISCREG_DL1DATA3 745 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 746 // MISCREG_DL1DATA4 747 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 748 // MISCREG_RAMINDEX 749 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 750 // MISCREG_L2ACTLR 751 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 752 // MISCREG_CBAR 753 bitset<NUM_MISCREG_INFOS>(string("01010101010000000000")), 754 // MISCREG_HTTBR 755 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 756 // MISCREG_VTTBR 757 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 758 // MISCREG_CNTPCT 759 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 760 // MISCREG_CNTVCT 761 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")), 762 // MISCREG_CNTP_CVAL 763 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 764 // MISCREG_CNTP_CVAL_NS 765 bitset<NUM_MISCREG_INFOS>(string("11001111111111100001")), 766 // MISCREG_CNTP_CVAL_S 767 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")), 768 // MISCREG_CNTV_CVAL 769 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 770 // MISCREG_CNTVOFF 771 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 772 // MISCREG_CNTHP_CVAL 773 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 774 // MISCREG_CPUMERRSR 775 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 776 // MISCREG_L2MERRSR 777 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), 778 779 // AArch64 registers (Op0=2) 780 // MISCREG_MDCCINT_EL1 781 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 782 // MISCREG_OSDTRRX_EL1 783 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 784 // MISCREG_MDSCR_EL1 785 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 786 // MISCREG_OSDTRTX_EL1 787 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 788 // MISCREG_OSECCR_EL1 789 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 790 // MISCREG_DBGBVR0_EL1 791 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 792 // MISCREG_DBGBVR1_EL1 793 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 794 // MISCREG_DBGBVR2_EL1 795 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 796 // MISCREG_DBGBVR3_EL1 797 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 798 // MISCREG_DBGBVR4_EL1 799 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 800 // MISCREG_DBGBVR5_EL1 801 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 802 // MISCREG_DBGBCR0_EL1 803 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 804 // MISCREG_DBGBCR1_EL1 805 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 806 // MISCREG_DBGBCR2_EL1 807 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 808 // MISCREG_DBGBCR3_EL1 809 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 810 // MISCREG_DBGBCR4_EL1 811 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 812 // MISCREG_DBGBCR5_EL1 813 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 814 // MISCREG_DBGWVR0_EL1 815 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 816 // MISCREG_DBGWVR1_EL1 817 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 818 // MISCREG_DBGWVR2_EL1 819 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 820 // MISCREG_DBGWVR3_EL1 821 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 822 // MISCREG_DBGWCR0_EL1 823 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 824 // MISCREG_DBGWCR1_EL1 825 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 826 // MISCREG_DBGWCR2_EL1 827 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 828 // MISCREG_DBGWCR3_EL1 829 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 830 // MISCREG_MDCCSR_EL0 831 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 832 // MISCREG_MDDTR_EL0 833 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 834 // MISCREG_MDDTRTX_EL0 835 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 836 // MISCREG_MDDTRRX_EL0 837 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 838 // MISCREG_DBGVCR32_EL2 839 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 840 // MISCREG_MDRAR_EL1 841 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 842 // MISCREG_OSLAR_EL1 843 bitset<NUM_MISCREG_INFOS>(string("10101111111111000001")), 844 // MISCREG_OSLSR_EL1 845 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 846 // MISCREG_OSDLR_EL1 847 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 848 // MISCREG_DBGPRCR_EL1 849 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 850 // MISCREG_DBGCLAIMSET_EL1 851 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 852 // MISCREG_DBGCLAIMCLR_EL1 853 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 854 // MISCREG_DBGAUTHSTATUS_EL1 855 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 856 // MISCREG_TEECR32_EL1 857 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")), 858 // MISCREG_TEEHBR32_EL1 859 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")), 860 861 // AArch64 registers (Op0=1,3) 862 // MISCREG_MIDR_EL1 863 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 864 // MISCREG_MPIDR_EL1 865 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 866 // MISCREG_REVIDR_EL1 867 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 868 // MISCREG_ID_PFR0_EL1 869 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 870 // MISCREG_ID_PFR1_EL1 871 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 872 // MISCREG_ID_DFR0_EL1 873 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 874 // MISCREG_ID_AFR0_EL1 875 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 876 // MISCREG_ID_MMFR0_EL1 877 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 878 // MISCREG_ID_MMFR1_EL1 879 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 880 // MISCREG_ID_MMFR2_EL1 881 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 882 // MISCREG_ID_MMFR3_EL1 883 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 884 // MISCREG_ID_ISAR0_EL1 885 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 886 // MISCREG_ID_ISAR1_EL1 887 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 888 // MISCREG_ID_ISAR2_EL1 889 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 890 // MISCREG_ID_ISAR3_EL1 891 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 892 // MISCREG_ID_ISAR4_EL1 893 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 894 // MISCREG_ID_ISAR5_EL1 895 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 896 // MISCREG_MVFR0_EL1 897 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 898 // MISCREG_MVFR1_EL1 899 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 900 // MISCREG_MVFR2_EL1 901 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 902 // MISCREG_ID_AA64PFR0_EL1 903 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 904 // MISCREG_ID_AA64PFR1_EL1 905 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 906 // MISCREG_ID_AA64DFR0_EL1 907 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 908 // MISCREG_ID_AA64DFR1_EL1 909 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 910 // MISCREG_ID_AA64AFR0_EL1 911 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 912 // MISCREG_ID_AA64AFR1_EL1 913 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 914 // MISCREG_ID_AA64ISAR0_EL1 915 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 916 // MISCREG_ID_AA64ISAR1_EL1 917 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 918 // MISCREG_ID_AA64MMFR0_EL1 919 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 920 // MISCREG_ID_AA64MMFR1_EL1 921 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 922 // MISCREG_CCSIDR_EL1 923 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 924 // MISCREG_CLIDR_EL1 925 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 926 // MISCREG_AIDR_EL1 927 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 928 // MISCREG_CSSELR_EL1 929 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 930 // MISCREG_CTR_EL0 931 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 932 // MISCREG_DCZID_EL0 933 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 934 // MISCREG_VPIDR_EL2 935 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 936 // MISCREG_VMPIDR_EL2 937 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 938 // MISCREG_SCTLR_EL1 939 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 940 // MISCREG_ACTLR_EL1 941 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 942 // MISCREG_CPACR_EL1 943 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 944 // MISCREG_SCTLR_EL2 945 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 946 // MISCREG_ACTLR_EL2 947 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 948 // MISCREG_HCR_EL2 949 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 950 // MISCREG_MDCR_EL2 951 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 952 // MISCREG_CPTR_EL2 953 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 954 // MISCREG_HSTR_EL2 955 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 956 // MISCREG_HACR_EL2 957 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 958 // MISCREG_SCTLR_EL3 959 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 960 // MISCREG_ACTLR_EL3 961 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 962 // MISCREG_SCR_EL3 963 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 964 // MISCREG_SDER32_EL3 965 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 966 // MISCREG_CPTR_EL3 967 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 968 // MISCREG_MDCR_EL3 969 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 970 // MISCREG_TTBR0_EL1 971 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 972 // MISCREG_TTBR1_EL1 973 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 974 // MISCREG_TCR_EL1 975 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 976 // MISCREG_TTBR0_EL2 977 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 978 // MISCREG_TCR_EL2 979 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 980 // MISCREG_VTTBR_EL2 981 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 982 // MISCREG_VTCR_EL2 983 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 984 // MISCREG_TTBR0_EL3 985 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 986 // MISCREG_TCR_EL3 987 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 988 // MISCREG_DACR32_EL2 989 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 990 // MISCREG_SPSR_EL1 991 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 992 // MISCREG_ELR_EL1 993 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 994 // MISCREG_SP_EL0 995 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 996 // MISCREG_SPSEL 997 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 998 // MISCREG_CURRENTEL 999 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1000 // MISCREG_NZCV 1001 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1002 // MISCREG_DAIF 1003 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1004 // MISCREG_FPCR 1005 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1006 // MISCREG_FPSR 1007 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1008 // MISCREG_DSPSR_EL0 1009 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1010 // MISCREG_DLR_EL0 1011 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1012 // MISCREG_SPSR_EL2 1013 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1014 // MISCREG_ELR_EL2 1015 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1016 // MISCREG_SP_EL1 1017 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1018 // MISCREG_SPSR_IRQ_AA64 1019 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1020 // MISCREG_SPSR_ABT_AA64 1021 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1022 // MISCREG_SPSR_UND_AA64 1023 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1024 // MISCREG_SPSR_FIQ_AA64 1025 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1026 // MISCREG_SPSR_EL3 1027 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1028 // MISCREG_ELR_EL3 1029 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1030 // MISCREG_SP_EL2 1031 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1032 // MISCREG_AFSR0_EL1 1033 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1034 // MISCREG_AFSR1_EL1 1035 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1036 // MISCREG_ESR_EL1 1037 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1038 // MISCREG_IFSR32_EL2 1039 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1040 // MISCREG_AFSR0_EL2 1041 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1042 // MISCREG_AFSR1_EL2 1043 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1044 // MISCREG_ESR_EL2 1045 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1046 // MISCREG_FPEXC32_EL2 1047 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1048 // MISCREG_AFSR0_EL3 1049 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1050 // MISCREG_AFSR1_EL3 1051 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1052 // MISCREG_ESR_EL3 1053 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1054 // MISCREG_FAR_EL1 1055 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1056 // MISCREG_FAR_EL2 1057 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1058 // MISCREG_HPFAR_EL2 1059 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1060 // MISCREG_FAR_EL3 1061 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1062 // MISCREG_IC_IALLUIS 1063 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1064 // MISCREG_PAR_EL1 1065 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1066 // MISCREG_IC_IALLU 1067 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1068 // MISCREG_DC_IVAC_Xt 1069 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1070 // MISCREG_DC_ISW_Xt 1071 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1072 // MISCREG_AT_S1E1R_Xt 1073 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1074 // MISCREG_AT_S1E1W_Xt 1075 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1076 // MISCREG_AT_S1E0R_Xt 1077 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1078 // MISCREG_AT_S1E0W_Xt 1079 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1080 // MISCREG_DC_CSW_Xt 1081 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1082 // MISCREG_DC_CISW_Xt 1083 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1084 // MISCREG_DC_ZVA_Xt 1085 bitset<NUM_MISCREG_INFOS>(string("10101010100010000101")), 1086 // MISCREG_IC_IVAU_Xt 1087 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 1088 // MISCREG_DC_CVAC_Xt 1089 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1090 // MISCREG_DC_CVAU_Xt 1091 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1092 // MISCREG_DC_CIVAC_Xt 1093 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1094 // MISCREG_AT_S1E2R_Xt 1095 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1096 // MISCREG_AT_S1E2W_Xt 1097 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1098 // MISCREG_AT_S12E1R_Xt 1099 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1100 // MISCREG_AT_S12E1W_Xt 1101 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1102 // MISCREG_AT_S12E0R_Xt 1103 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1104 // MISCREG_AT_S12E0W_Xt 1105 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1106 // MISCREG_AT_S1E3R_Xt 1107 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1108 // MISCREG_AT_S1E3W_Xt 1109 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1110 // MISCREG_TLBI_VMALLE1IS 1111 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1112 // MISCREG_TLBI_VAE1IS_Xt 1113 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1114 // MISCREG_TLBI_ASIDE1IS_Xt 1115 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1116 // MISCREG_TLBI_VAAE1IS_Xt 1117 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1118 // MISCREG_TLBI_VALE1IS_Xt 1119 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1120 // MISCREG_TLBI_VAALE1IS_Xt 1121 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1122 // MISCREG_TLBI_VMALLE1 1123 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1124 // MISCREG_TLBI_VAE1_Xt 1125 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1126 // MISCREG_TLBI_ASIDE1_Xt 1127 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1128 // MISCREG_TLBI_VAAE1_Xt 1129 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1130 // MISCREG_TLBI_VALE1_Xt 1131 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1132 // MISCREG_TLBI_VAALE1_Xt 1133 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1134 // MISCREG_TLBI_IPAS2E1IS_Xt 1135 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1136 // MISCREG_TLBI_IPAS2LE1IS_Xt 1137 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1138 // MISCREG_TLBI_ALLE2IS 1139 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1140 // MISCREG_TLBI_VAE2IS_Xt 1141 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1142 // MISCREG_TLBI_ALLE1IS 1143 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1144 // MISCREG_TLBI_VALE2IS_Xt 1145 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1146 // MISCREG_TLBI_VMALLS12E1IS 1147 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1148 // MISCREG_TLBI_IPAS2E1_Xt 1149 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1150 // MISCREG_TLBI_IPAS2LE1_Xt 1151 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1152 // MISCREG_TLBI_ALLE2 1153 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1154 // MISCREG_TLBI_VAE2_Xt 1155 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1156 // MISCREG_TLBI_ALLE1 1157 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1158 // MISCREG_TLBI_VALE2_Xt 1159 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1160 // MISCREG_TLBI_VMALLS12E1 1161 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1162 // MISCREG_TLBI_ALLE3IS 1163 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1164 // MISCREG_TLBI_VAE3IS_Xt 1165 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1166 // MISCREG_TLBI_VALE3IS_Xt 1167 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1168 // MISCREG_TLBI_ALLE3 1169 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1170 // MISCREG_TLBI_VAE3_Xt 1171 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1172 // MISCREG_TLBI_VALE3_Xt 1173 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1174 // MISCREG_PMINTENSET_EL1 1175 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1176 // MISCREG_PMINTENCLR_EL1 1177 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1178 // MISCREG_PMCR_EL0 1179 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1180 // MISCREG_PMCNTENSET_EL0 1181 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1182 // MISCREG_PMCNTENCLR_EL0 1183 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1184 // MISCREG_PMOVSCLR_EL0 1185 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1186 // MISCREG_PMSWINC_EL0 1187 bitset<NUM_MISCREG_INFOS>(string("10101010101111000001")), 1188 // MISCREG_PMSELR_EL0 1189 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1190 // MISCREG_PMCEID0_EL0 1191 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")), 1192 // MISCREG_PMCEID1_EL0 1193 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")), 1194 // MISCREG_PMCCNTR_EL0 1195 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1196 // MISCREG_PMXEVTYPER_EL0 1197 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1198 // MISCREG_PMCCFILTR_EL0 1199 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1200 // MISCREG_PMXEVCNTR_EL0 1201 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1202 // MISCREG_PMUSERENR_EL0 1203 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")), 1204 // MISCREG_PMOVSSET_EL0 1205 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1206 // MISCREG_MAIR_EL1 1207 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1208 // MISCREG_AMAIR_EL1 1209 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1210 // MISCREG_MAIR_EL2 1211 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1212 // MISCREG_AMAIR_EL2 1213 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1214 // MISCREG_MAIR_EL3 1215 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1216 // MISCREG_AMAIR_EL3 1217 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1218 // MISCREG_L2CTLR_EL1 1219 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1220 // MISCREG_L2ECTLR_EL1 1221 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1222 // MISCREG_VBAR_EL1 1223 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1224 // MISCREG_RVBAR_EL1 1225 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1226 // MISCREG_ISR_EL1 1227 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1228 // MISCREG_VBAR_EL2 1229 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1230 // MISCREG_RVBAR_EL2 1231 bitset<NUM_MISCREG_INFOS>(string("01010100000000000001")), 1232 // MISCREG_VBAR_EL3 1233 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1234 // MISCREG_RVBAR_EL3 1235 bitset<NUM_MISCREG_INFOS>(string("01010000000000000001")), 1236 // MISCREG_RMR_EL3 1237 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1238 // MISCREG_CONTEXTIDR_EL1 1239 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1240 // MISCREG_TPIDR_EL1 1241 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1242 // MISCREG_TPIDR_EL0 1243 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1244 // MISCREG_TPIDRRO_EL0 1245 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")), 1246 // MISCREG_TPIDR_EL2 1247 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1248 // MISCREG_TPIDR_EL3 1249 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1250 // MISCREG_CNTKCTL_EL1 1251 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1252 // MISCREG_CNTFRQ_EL0 1253 bitset<NUM_MISCREG_INFOS>(string("11110101010101000001")), 1254 // MISCREG_CNTPCT_EL0 1255 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 1256 // MISCREG_CNTVCT_EL0 1257 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")), 1258 // MISCREG_CNTP_TVAL_EL0 1259 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1260 // MISCREG_CNTP_CTL_EL0 1261 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1262 // MISCREG_CNTP_CVAL_EL0 1263 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1264 // MISCREG_CNTV_TVAL_EL0 1265 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1266 // MISCREG_CNTV_CTL_EL0 1267 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1268 // MISCREG_CNTV_CVAL_EL0 1269 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1270 // MISCREG_PMEVCNTR0_EL0 1271 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1272 // MISCREG_PMEVCNTR1_EL0 1273 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1274 // MISCREG_PMEVCNTR2_EL0 1275 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1276 // MISCREG_PMEVCNTR3_EL0 1277 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1278 // MISCREG_PMEVCNTR4_EL0 1279 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1280 // MISCREG_PMEVCNTR5_EL0 1281 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1282 // MISCREG_PMEVTYPER0_EL0 1283 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1284 // MISCREG_PMEVTYPER1_EL0 1285 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1286 // MISCREG_PMEVTYPER2_EL0 1287 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1288 // MISCREG_PMEVTYPER3_EL0 1289 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1290 // MISCREG_PMEVTYPER4_EL0 1291 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1292 // MISCREG_PMEVTYPER5_EL0 1293 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1294 // MISCREG_CNTVOFF_EL2 1295 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1296 // MISCREG_CNTHCTL_EL2 1297 bitset<NUM_MISCREG_INFOS>(string("01111000000000000100")), 1298 // MISCREG_CNTHP_TVAL_EL2 1299 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1300 // MISCREG_CNTHP_CTL_EL2 1301 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1302 // MISCREG_CNTHP_CVAL_EL2 1303 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1304 // MISCREG_CNTPS_TVAL_EL1 1305 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1306 // MISCREG_CNTPS_CTL_EL1 1307 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1308 // MISCREG_CNTPS_CVAL_EL1 1309 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1310 // MISCREG_IL1DATA0_EL1 1311 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1312 // MISCREG_IL1DATA1_EL1 1313 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1314 // MISCREG_IL1DATA2_EL1 1315 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1316 // MISCREG_IL1DATA3_EL1 1317 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1318 // MISCREG_DL1DATA0_EL1 1319 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1320 // MISCREG_DL1DATA1_EL1 1321 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1322 // MISCREG_DL1DATA2_EL1 1323 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1324 // MISCREG_DL1DATA3_EL1 1325 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1326 // MISCREG_DL1DATA4_EL1 1327 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1328 // MISCREG_L2ACTLR_EL1 1329 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1330 // MISCREG_CPUACTLR_EL1 1331 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1332 // MISCREG_CPUECTLR_EL1 1333 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1334 // MISCREG_CPUMERRSR_EL1 1335 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1336 // MISCREG_L2MERRSR_EL1 1337 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), 1338 // MISCREG_CBAR_EL1 1339 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1340 // MISCREG_CONTEXTIDR_EL2 1341 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1342 1343 // Dummy registers 1344 // MISCREG_NOP 1345 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1346 // MISCREG_RAZ 1347 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1348 // MISCREG_CP14_UNIMPL 1349 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")), 1350 // MISCREG_CP15_UNIMPL 1351 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")), 1352 // MISCREG_A64_UNIMPL 1353 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")), 1354 // MISCREG_UNKNOWN 1355 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")) 1356}; 1357 1358MiscRegIndex 1359decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 1360{ 1361 switch (crn) { 1362 case 0: 1363 switch (opc1) { 1364 case 0: 1365 switch (crm) { 1366 case 0: 1367 switch (opc2) { 1368 case 1: 1369 return MISCREG_CTR; 1370 case 2: 1371 return MISCREG_TCMTR; 1372 case 3: 1373 return MISCREG_TLBTR; 1374 case 5: 1375 return MISCREG_MPIDR; 1376 case 6: 1377 return MISCREG_REVIDR; 1378 default: 1379 return MISCREG_MIDR; 1380 } 1381 break; 1382 case 1: 1383 switch (opc2) { 1384 case 0: 1385 return MISCREG_ID_PFR0; 1386 case 1: 1387 return MISCREG_ID_PFR1; 1388 case 2: 1389 return MISCREG_ID_DFR0; 1390 case 3: 1391 return MISCREG_ID_AFR0; 1392 case 4: 1393 return MISCREG_ID_MMFR0; 1394 case 5: 1395 return MISCREG_ID_MMFR1; 1396 case 6: 1397 return MISCREG_ID_MMFR2; 1398 case 7: 1399 return MISCREG_ID_MMFR3; 1400 } 1401 break; 1402 case 2: 1403 switch (opc2) { 1404 case 0: 1405 return MISCREG_ID_ISAR0; 1406 case 1: 1407 return MISCREG_ID_ISAR1; 1408 case 2: 1409 return MISCREG_ID_ISAR2; 1410 case 3: 1411 return MISCREG_ID_ISAR3; 1412 case 4: 1413 return MISCREG_ID_ISAR4; 1414 case 5: 1415 return MISCREG_ID_ISAR5; 1416 case 6: 1417 case 7: 1418 return MISCREG_RAZ; // read as zero 1419 } 1420 break; 1421 default: 1422 return MISCREG_RAZ; // read as zero 1423 } 1424 break; 1425 case 1: 1426 if (crm == 0) { 1427 switch (opc2) { 1428 case 0: 1429 return MISCREG_CCSIDR; 1430 case 1: 1431 return MISCREG_CLIDR; 1432 case 7: 1433 return MISCREG_AIDR; 1434 } 1435 } 1436 break; 1437 case 2: 1438 if (crm == 0 && opc2 == 0) { 1439 return MISCREG_CSSELR; 1440 } 1441 break; 1442 case 4: 1443 if (crm == 0) { 1444 if (opc2 == 0) 1445 return MISCREG_VPIDR; 1446 else if (opc2 == 5) 1447 return MISCREG_VMPIDR; 1448 } 1449 break; 1450 } 1451 break; 1452 case 1: 1453 if (opc1 == 0) { 1454 if (crm == 0) { 1455 switch (opc2) { 1456 case 0: 1457 return MISCREG_SCTLR; 1458 case 1: 1459 return MISCREG_ACTLR; 1460 case 0x2: 1461 return MISCREG_CPACR; 1462 } 1463 } else if (crm == 1) { 1464 switch (opc2) { 1465 case 0: 1466 return MISCREG_SCR; 1467 case 1: 1468 return MISCREG_SDER; 1469 case 2: 1470 return MISCREG_NSACR; 1471 } 1472 } 1473 } else if (opc1 == 4) { 1474 if (crm == 0) { 1475 if (opc2 == 0) 1476 return MISCREG_HSCTLR; 1477 else if (opc2 == 1) 1478 return MISCREG_HACTLR; 1479 } else if (crm == 1) { 1480 switch (opc2) { 1481 case 0: 1482 return MISCREG_HCR; 1483 case 1: 1484 return MISCREG_HDCR; 1485 case 2: 1486 return MISCREG_HCPTR; 1487 case 3: 1488 return MISCREG_HSTR; 1489 case 7: 1490 return MISCREG_HACR; 1491 } 1492 } 1493 } 1494 break; 1495 case 2: 1496 if (opc1 == 0 && crm == 0) { 1497 switch (opc2) { 1498 case 0: 1499 return MISCREG_TTBR0; 1500 case 1: 1501 return MISCREG_TTBR1; 1502 case 2: 1503 return MISCREG_TTBCR; 1504 } 1505 } else if (opc1 == 4) { 1506 if (crm == 0 && opc2 == 2) 1507 return MISCREG_HTCR; 1508 else if (crm == 1 && opc2 == 2) 1509 return MISCREG_VTCR; 1510 } 1511 break; 1512 case 3: 1513 if (opc1 == 0 && crm == 0 && opc2 == 0) { 1514 return MISCREG_DACR; 1515 } 1516 break; 1517 case 5: 1518 if (opc1 == 0) { 1519 if (crm == 0) { 1520 if (opc2 == 0) { 1521 return MISCREG_DFSR; 1522 } else if (opc2 == 1) { 1523 return MISCREG_IFSR; 1524 } 1525 } else if (crm == 1) { 1526 if (opc2 == 0) { 1527 return MISCREG_ADFSR; 1528 } else if (opc2 == 1) { 1529 return MISCREG_AIFSR; 1530 } 1531 } 1532 } else if (opc1 == 4) { 1533 if (crm == 1) { 1534 if (opc2 == 0) 1535 return MISCREG_HADFSR; 1536 else if (opc2 == 1) 1537 return MISCREG_HAIFSR; 1538 } else if (crm == 2 && opc2 == 0) { 1539 return MISCREG_HSR; 1540 } 1541 } 1542 break; 1543 case 6: 1544 if (opc1 == 0 && crm == 0) { 1545 switch (opc2) { 1546 case 0: 1547 return MISCREG_DFAR; 1548 case 2: 1549 return MISCREG_IFAR; 1550 } 1551 } else if (opc1 == 4 && crm == 0) { 1552 switch (opc2) { 1553 case 0: 1554 return MISCREG_HDFAR; 1555 case 2: 1556 return MISCREG_HIFAR; 1557 case 4: 1558 return MISCREG_HPFAR; 1559 } 1560 } 1561 break; 1562 case 7: 1563 if (opc1 == 0) { 1564 switch (crm) { 1565 case 0: 1566 if (opc2 == 4) { 1567 return MISCREG_NOP; 1568 } 1569 break; 1570 case 1: 1571 switch (opc2) { 1572 case 0: 1573 return MISCREG_ICIALLUIS; 1574 case 6: 1575 return MISCREG_BPIALLIS; 1576 } 1577 break; 1578 case 4: 1579 if (opc2 == 0) { 1580 return MISCREG_PAR; 1581 } 1582 break; 1583 case 5: 1584 switch (opc2) { 1585 case 0: 1586 return MISCREG_ICIALLU; 1587 case 1: 1588 return MISCREG_ICIMVAU; 1589 case 4: 1590 return MISCREG_CP15ISB; 1591 case 6: 1592 return MISCREG_BPIALL; 1593 case 7: 1594 return MISCREG_BPIMVA; 1595 } 1596 break; 1597 case 6: 1598 if (opc2 == 1) { 1599 return MISCREG_DCIMVAC; 1600 } else if (opc2 == 2) { 1601 return MISCREG_DCISW; 1602 } 1603 break; 1604 case 8: 1605 switch (opc2) { 1606 case 0: 1607 return MISCREG_ATS1CPR; 1608 case 1: 1609 return MISCREG_ATS1CPW; 1610 case 2: 1611 return MISCREG_ATS1CUR; 1612 case 3: 1613 return MISCREG_ATS1CUW; 1614 case 4: 1615 return MISCREG_ATS12NSOPR; 1616 case 5: 1617 return MISCREG_ATS12NSOPW; 1618 case 6: 1619 return MISCREG_ATS12NSOUR; 1620 case 7: 1621 return MISCREG_ATS12NSOUW; 1622 } 1623 break; 1624 case 10: 1625 switch (opc2) { 1626 case 1: 1627 return MISCREG_DCCMVAC; 1628 case 2: 1629 return MISCREG_DCCSW; 1630 case 4: 1631 return MISCREG_CP15DSB; 1632 case 5: 1633 return MISCREG_CP15DMB; 1634 } 1635 break; 1636 case 11: 1637 if (opc2 == 1) { 1638 return MISCREG_DCCMVAU; 1639 } 1640 break; 1641 case 13: 1642 if (opc2 == 1) { 1643 return MISCREG_NOP; 1644 } 1645 break; 1646 case 14: 1647 if (opc2 == 1) { 1648 return MISCREG_DCCIMVAC; 1649 } else if (opc2 == 2) { 1650 return MISCREG_DCCISW; 1651 } 1652 break; 1653 } 1654 } else if (opc1 == 4 && crm == 8) { 1655 if (opc2 == 0) 1656 return MISCREG_ATS1HR; 1657 else if (opc2 == 1) 1658 return MISCREG_ATS1HW; 1659 } 1660 break; 1661 case 8: 1662 if (opc1 == 0) { 1663 switch (crm) { 1664 case 3: 1665 switch (opc2) { 1666 case 0: 1667 return MISCREG_TLBIALLIS; 1668 case 1: 1669 return MISCREG_TLBIMVAIS; 1670 case 2: 1671 return MISCREG_TLBIASIDIS; 1672 case 3: 1673 return MISCREG_TLBIMVAAIS; 1674 } 1675 break; 1676 case 5: 1677 switch (opc2) { 1678 case 0: 1679 return MISCREG_ITLBIALL; 1680 case 1: 1681 return MISCREG_ITLBIMVA; 1682 case 2: 1683 return MISCREG_ITLBIASID; 1684 } 1685 break; 1686 case 6: 1687 switch (opc2) { 1688 case 0: 1689 return MISCREG_DTLBIALL; 1690 case 1: 1691 return MISCREG_DTLBIMVA; 1692 case 2: 1693 return MISCREG_DTLBIASID; 1694 } 1695 break; 1696 case 7: 1697 switch (opc2) { 1698 case 0: 1699 return MISCREG_TLBIALL; 1700 case 1: 1701 return MISCREG_TLBIMVA; 1702 case 2: 1703 return MISCREG_TLBIASID; 1704 case 3: 1705 return MISCREG_TLBIMVAA; 1706 } 1707 break; 1708 } 1709 } else if (opc1 == 4) { 1710 if (crm == 3) { 1711 switch (opc2) { 1712 case 0: 1713 return MISCREG_TLBIALLHIS; 1714 case 1: 1715 return MISCREG_TLBIMVAHIS; 1716 case 4: 1717 return MISCREG_TLBIALLNSNHIS; 1718 } 1719 } else if (crm == 7) { 1720 switch (opc2) { 1721 case 0: 1722 return MISCREG_TLBIALLH; 1723 case 1: 1724 return MISCREG_TLBIMVAH; 1725 case 4: 1726 return MISCREG_TLBIALLNSNH; 1727 } 1728 } 1729 } 1730 break; 1731 case 9: 1732 if (opc1 == 0) { 1733 switch (crm) { 1734 case 12: 1735 switch (opc2) { 1736 case 0: 1737 return MISCREG_PMCR; 1738 case 1: 1739 return MISCREG_PMCNTENSET; 1740 case 2: 1741 return MISCREG_PMCNTENCLR; 1742 case 3: 1743 return MISCREG_PMOVSR; 1744 case 4: 1745 return MISCREG_PMSWINC; 1746 case 5: 1747 return MISCREG_PMSELR; 1748 case 6: 1749 return MISCREG_PMCEID0; 1750 case 7: 1751 return MISCREG_PMCEID1; 1752 } 1753 break; 1754 case 13: 1755 switch (opc2) { 1756 case 0: 1757 return MISCREG_PMCCNTR; 1758 case 1: 1759 // Selector is PMSELR.SEL 1760 return MISCREG_PMXEVTYPER_PMCCFILTR; 1761 case 2: 1762 return MISCREG_PMXEVCNTR; 1763 } 1764 break; 1765 case 14: 1766 switch (opc2) { 1767 case 0: 1768 return MISCREG_PMUSERENR; 1769 case 1: 1770 return MISCREG_PMINTENSET; 1771 case 2: 1772 return MISCREG_PMINTENCLR; 1773 case 3: 1774 return MISCREG_PMOVSSET; 1775 } 1776 break; 1777 } 1778 } else if (opc1 == 1) { 1779 switch (crm) { 1780 case 0: 1781 switch (opc2) { 1782 case 2: // L2CTLR, L2 Control Register 1783 return MISCREG_L2CTLR; 1784 case 3: 1785 return MISCREG_L2ECTLR; 1786 } 1787 break; 1788 break; 1789 } 1790 } 1791 break; 1792 case 10: 1793 if (opc1 == 0) { 1794 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 1795 if (crm == 2) { // TEX Remap Registers 1796 if (opc2 == 0) { 1797 // Selector is TTBCR.EAE 1798 return MISCREG_PRRR_MAIR0; 1799 } else if (opc2 == 1) { 1800 // Selector is TTBCR.EAE 1801 return MISCREG_NMRR_MAIR1; 1802 } 1803 } else if (crm == 3) { 1804 if (opc2 == 0) { 1805 return MISCREG_AMAIR0; 1806 } else if (opc2 == 1) { 1807 return MISCREG_AMAIR1; 1808 } 1809 } 1810 } else if (opc1 == 4) { 1811 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 1812 if (crm == 2) { 1813 if (opc2 == 0) 1814 return MISCREG_HMAIR0; 1815 else if (opc2 == 1) 1816 return MISCREG_HMAIR1; 1817 } else if (crm == 3) { 1818 if (opc2 == 0) 1819 return MISCREG_HAMAIR0; 1820 else if (opc2 == 1) 1821 return MISCREG_HAMAIR1; 1822 } 1823 } 1824 break; 1825 case 11: 1826 if (opc1 <=7) { 1827 switch (crm) { 1828 case 0: 1829 case 1: 1830 case 2: 1831 case 3: 1832 case 4: 1833 case 5: 1834 case 6: 1835 case 7: 1836 case 8: 1837 case 15: 1838 // Reserved for DMA operations for TCM access 1839 break; 1840 } 1841 } 1842 break; 1843 case 12: 1844 if (opc1 == 0) { 1845 if (crm == 0) { 1846 if (opc2 == 0) { 1847 return MISCREG_VBAR; 1848 } else if (opc2 == 1) { 1849 return MISCREG_MVBAR; 1850 } 1851 } else if (crm == 1) { 1852 if (opc2 == 0) { 1853 return MISCREG_ISR; 1854 } 1855 } 1856 } else if (opc1 == 4) { 1857 if (crm == 0 && opc2 == 0) 1858 return MISCREG_HVBAR; 1859 } 1860 break; 1861 case 13: 1862 if (opc1 == 0) { 1863 if (crm == 0) { 1864 switch (opc2) { 1865 case 0: 1866 return MISCREG_FCSEIDR; 1867 case 1: 1868 return MISCREG_CONTEXTIDR; 1869 case 2: 1870 return MISCREG_TPIDRURW; 1871 case 3: 1872 return MISCREG_TPIDRURO; 1873 case 4: 1874 return MISCREG_TPIDRPRW; 1875 } 1876 } 1877 } else if (opc1 == 4) { 1878 if (crm == 0 && opc2 == 2) 1879 return MISCREG_HTPIDR; 1880 } 1881 break; 1882 case 14: 1883 if (opc1 == 0) { 1884 switch (crm) { 1885 case 0: 1886 if (opc2 == 0) 1887 return MISCREG_CNTFRQ; 1888 break; 1889 case 1: 1890 if (opc2 == 0) 1891 return MISCREG_CNTKCTL; 1892 break; 1893 case 2: 1894 if (opc2 == 0) 1895 return MISCREG_CNTP_TVAL; 1896 else if (opc2 == 1) 1897 return MISCREG_CNTP_CTL; 1898 break; 1899 case 3: 1900 if (opc2 == 0) 1901 return MISCREG_CNTV_TVAL; 1902 else if (opc2 == 1) 1903 return MISCREG_CNTV_CTL; 1904 break; 1905 } 1906 } else if (opc1 == 4) { 1907 if (crm == 1 && opc2 == 0) { 1908 return MISCREG_CNTHCTL; 1909 } else if (crm == 2) { 1910 if (opc2 == 0) 1911 return MISCREG_CNTHP_TVAL; 1912 else if (opc2 == 1) 1913 return MISCREG_CNTHP_CTL; 1914 } 1915 } 1916 break; 1917 case 15: 1918 // Implementation defined 1919 return MISCREG_CP15_UNIMPL; 1920 } 1921 // Unrecognized register 1922 return MISCREG_CP15_UNIMPL; 1923} 1924 1925MiscRegIndex 1926decodeCP15Reg64(unsigned crm, unsigned opc1) 1927{ 1928 switch (crm) { 1929 case 2: 1930 switch (opc1) { 1931 case 0: 1932 return MISCREG_TTBR0; 1933 case 1: 1934 return MISCREG_TTBR1; 1935 case 4: 1936 return MISCREG_HTTBR; 1937 case 6: 1938 return MISCREG_VTTBR; 1939 } 1940 break; 1941 case 7: 1942 if (opc1 == 0) 1943 return MISCREG_PAR; 1944 break; 1945 case 14: 1946 switch (opc1) { 1947 case 0: 1948 return MISCREG_CNTPCT; 1949 case 1: 1950 return MISCREG_CNTVCT; 1951 case 2: 1952 return MISCREG_CNTP_CVAL; 1953 case 3: 1954 return MISCREG_CNTV_CVAL; 1955 case 4: 1956 return MISCREG_CNTVOFF; 1957 case 6: 1958 return MISCREG_CNTHP_CVAL; 1959 } 1960 break; 1961 case 15: 1962 if (opc1 == 0) 1963 return MISCREG_CPUMERRSR; 1964 else if (opc1 == 1) 1965 return MISCREG_L2MERRSR; 1966 break; 1967 } 1968 // Unrecognized register 1969 return MISCREG_CP15_UNIMPL; 1970} 1971 1972std::tuple<bool, bool> 1973canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 1974{ 1975 bool secure = !scr.ns; 1976 bool canRead = false; 1977 bool undefined = false; 1978 1979 switch (cpsr.mode) { 1980 case MODE_USER: 1981 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 1982 miscRegInfo[reg][MISCREG_USR_NS_RD]; 1983 break; 1984 case MODE_FIQ: 1985 case MODE_IRQ: 1986 case MODE_SVC: 1987 case MODE_ABORT: 1988 case MODE_UNDEFINED: 1989 case MODE_SYSTEM: 1990 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 1991 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 1992 break; 1993 case MODE_MON: 1994 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 1995 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 1996 break; 1997 case MODE_HYP: 1998 canRead = miscRegInfo[reg][MISCREG_HYP_RD]; 1999 break; 2000 default: 2001 undefined = true; 2002 } 2003 // can't do permissions checkes on the root of a banked pair of regs 2004 assert(!miscRegInfo[reg][MISCREG_BANKED]); 2005 return std::make_tuple(canRead, undefined); 2006} 2007 2008std::tuple<bool, bool> 2009canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 2010{ 2011 bool secure = !scr.ns; 2012 bool canWrite = false; 2013 bool undefined = false; 2014 2015 switch (cpsr.mode) { 2016 case MODE_USER: 2017 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 2018 miscRegInfo[reg][MISCREG_USR_NS_WR]; 2019 break; 2020 case MODE_FIQ: 2021 case MODE_IRQ: 2022 case MODE_SVC: 2023 case MODE_ABORT: 2024 case MODE_UNDEFINED: 2025 case MODE_SYSTEM: 2026 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 2027 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 2028 break; 2029 case MODE_MON: 2030 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 2031 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 2032 break; 2033 case MODE_HYP: 2034 canWrite = miscRegInfo[reg][MISCREG_HYP_WR]; 2035 break; 2036 default: 2037 undefined = true; 2038 } 2039 // can't do permissions checkes on the root of a banked pair of regs 2040 assert(!miscRegInfo[reg][MISCREG_BANKED]); 2041 return std::make_tuple(canWrite, undefined); 2042} 2043 2044int 2045flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc) 2046{ 2047 SCR scr = tc->readMiscReg(MISCREG_SCR); 2048 return flattenMiscRegNsBanked(reg, tc, scr.ns); 2049} 2050 2051int 2052flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns) 2053{ 2054 int reg_as_int = static_cast<int>(reg); 2055 if (miscRegInfo[reg][MISCREG_BANKED]) { 2056 reg_as_int += (ArmSystem::haveSecurity(tc) && 2057 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1; 2058 } 2059 return reg_as_int; 2060} 2061 2062 2063/** 2064 * If the reg is a child reg of a banked set, then the parent is the last 2065 * banked one in the list. This is messy, and the wish is to eventually have 2066 * the bitmap replaced with a better data structure. the preUnflatten function 2067 * initializes a lookup table to speed up the search for these banked 2068 * registers. 2069 */ 2070 2071int unflattenResultMiscReg[NUM_MISCREGS]; 2072 2073void 2074preUnflattenMiscReg() 2075{ 2076 int reg = -1; 2077 for (int i = 0 ; i < NUM_MISCREGS; i++){ 2078 if (miscRegInfo[i][MISCREG_BANKED]) 2079 reg = i; 2080 if (miscRegInfo[i][MISCREG_BANKED_CHILD]) 2081 unflattenResultMiscReg[i] = reg; 2082 else 2083 unflattenResultMiscReg[i] = i; 2084 // if this assert fails, no parent was found, and something is broken 2085 assert(unflattenResultMiscReg[i] > -1); 2086 } 2087} 2088 2089int 2090unflattenMiscReg(int reg) 2091{ 2092 return unflattenResultMiscReg[reg]; 2093} 2094 2095bool 2096canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 2097{ 2098 // Check for SP_EL0 access while SPSEL == 0 2099 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 2100 return false; 2101 2102 // Check for RVBAR access 2103 if (reg == MISCREG_RVBAR_EL1) { 2104 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 2105 if (highest_el == EL2 || highest_el == EL3) 2106 return false; 2107 } 2108 if (reg == MISCREG_RVBAR_EL2) { 2109 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 2110 if (highest_el == EL3) 2111 return false; 2112 } 2113 2114 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 2115 2116 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) { 2117 case EL0: 2118 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 2119 miscRegInfo[reg][MISCREG_USR_NS_RD]; 2120 case EL1: 2121 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 2122 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 2123 case EL2: 2124 return miscRegInfo[reg][MISCREG_HYP_RD]; 2125 case EL3: 2126 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 2127 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 2128 default: 2129 panic("Invalid exception level"); 2130 } 2131} 2132 2133bool 2134canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 2135{ 2136 // Check for SP_EL0 access while SPSEL == 0 2137 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 2138 return false; 2139 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode); 2140 if (reg == MISCREG_DAIF) { 2141 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 2142 if (el == EL0 && !sctlr.uma) 2143 return false; 2144 } 2145 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) { 2146 // In syscall-emulation mode, this test is skipped and DCZVA is always 2147 // allowed at EL0 2148 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 2149 if (el == EL0 && !sctlr.dze) 2150 return false; 2151 } 2152 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt || 2153 reg == MISCREG_DC_IVAC_Xt) { 2154 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 2155 if (el == EL0 && !sctlr.uci) 2156 return false; 2157 } 2158 2159 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 2160 2161 switch (el) { 2162 case EL0: 2163 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 2164 miscRegInfo[reg][MISCREG_USR_NS_WR]; 2165 case EL1: 2166 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 2167 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 2168 case EL2: 2169 return miscRegInfo[reg][MISCREG_HYP_WR]; 2170 case EL3: 2171 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 2172 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 2173 default: 2174 panic("Invalid exception level"); 2175 } 2176} 2177 2178MiscRegIndex 2179decodeAArch64SysReg(unsigned op0, unsigned op1, 2180 unsigned crn, unsigned crm, 2181 unsigned op2) 2182{ 2183 switch (op0) { 2184 case 1: 2185 switch (crn) { 2186 case 7: 2187 switch (op1) { 2188 case 0: 2189 switch (crm) { 2190 case 1: 2191 switch (op2) { 2192 case 0: 2193 return MISCREG_IC_IALLUIS; 2194 } 2195 break; 2196 case 5: 2197 switch (op2) { 2198 case 0: 2199 return MISCREG_IC_IALLU; 2200 } 2201 break; 2202 case 6: 2203 switch (op2) { 2204 case 1: 2205 return MISCREG_DC_IVAC_Xt; 2206 case 2: 2207 return MISCREG_DC_ISW_Xt; 2208 } 2209 break; 2210 case 8: 2211 switch (op2) { 2212 case 0: 2213 return MISCREG_AT_S1E1R_Xt; 2214 case 1: 2215 return MISCREG_AT_S1E1W_Xt; 2216 case 2: 2217 return MISCREG_AT_S1E0R_Xt; 2218 case 3: 2219 return MISCREG_AT_S1E0W_Xt; 2220 } 2221 break; 2222 case 10: 2223 switch (op2) { 2224 case 2: 2225 return MISCREG_DC_CSW_Xt; 2226 } 2227 break; 2228 case 14: 2229 switch (op2) { 2230 case 2: 2231 return MISCREG_DC_CISW_Xt; 2232 } 2233 break; 2234 } 2235 break; 2236 case 3: 2237 switch (crm) { 2238 case 4: 2239 switch (op2) { 2240 case 1: 2241 return MISCREG_DC_ZVA_Xt; 2242 } 2243 break; 2244 case 5: 2245 switch (op2) { 2246 case 1: 2247 return MISCREG_IC_IVAU_Xt; 2248 } 2249 break; 2250 case 10: 2251 switch (op2) { 2252 case 1: 2253 return MISCREG_DC_CVAC_Xt; 2254 } 2255 break; 2256 case 11: 2257 switch (op2) { 2258 case 1: 2259 return MISCREG_DC_CVAU_Xt; 2260 } 2261 break; 2262 case 14: 2263 switch (op2) { 2264 case 1: 2265 return MISCREG_DC_CIVAC_Xt; 2266 } 2267 break; 2268 } 2269 break; 2270 case 4: 2271 switch (crm) { 2272 case 8: 2273 switch (op2) { 2274 case 0: 2275 return MISCREG_AT_S1E2R_Xt; 2276 case 1: 2277 return MISCREG_AT_S1E2W_Xt; 2278 case 4: 2279 return MISCREG_AT_S12E1R_Xt; 2280 case 5: 2281 return MISCREG_AT_S12E1W_Xt; 2282 case 6: 2283 return MISCREG_AT_S12E0R_Xt; 2284 case 7: 2285 return MISCREG_AT_S12E0W_Xt; 2286 } 2287 break; 2288 } 2289 break; 2290 case 6: 2291 switch (crm) { 2292 case 8: 2293 switch (op2) { 2294 case 0: 2295 return MISCREG_AT_S1E3R_Xt; 2296 case 1: 2297 return MISCREG_AT_S1E3W_Xt; 2298 } 2299 break; 2300 } 2301 break; 2302 } 2303 break; 2304 case 8: 2305 switch (op1) { 2306 case 0: 2307 switch (crm) { 2308 case 3: 2309 switch (op2) { 2310 case 0: 2311 return MISCREG_TLBI_VMALLE1IS; 2312 case 1: 2313 return MISCREG_TLBI_VAE1IS_Xt; 2314 case 2: 2315 return MISCREG_TLBI_ASIDE1IS_Xt; 2316 case 3: 2317 return MISCREG_TLBI_VAAE1IS_Xt; 2318 case 5: 2319 return MISCREG_TLBI_VALE1IS_Xt; 2320 case 7: 2321 return MISCREG_TLBI_VAALE1IS_Xt; 2322 } 2323 break; 2324 case 7: 2325 switch (op2) { 2326 case 0: 2327 return MISCREG_TLBI_VMALLE1; 2328 case 1: 2329 return MISCREG_TLBI_VAE1_Xt; 2330 case 2: 2331 return MISCREG_TLBI_ASIDE1_Xt; 2332 case 3: 2333 return MISCREG_TLBI_VAAE1_Xt; 2334 case 5: 2335 return MISCREG_TLBI_VALE1_Xt; 2336 case 7: 2337 return MISCREG_TLBI_VAALE1_Xt; 2338 } 2339 break; 2340 } 2341 break; 2342 case 4: 2343 switch (crm) { 2344 case 0: 2345 switch (op2) { 2346 case 1: 2347 return MISCREG_TLBI_IPAS2E1IS_Xt; 2348 case 5: 2349 return MISCREG_TLBI_IPAS2LE1IS_Xt; 2350 } 2351 break; 2352 case 3: 2353 switch (op2) { 2354 case 0: 2355 return MISCREG_TLBI_ALLE2IS; 2356 case 1: 2357 return MISCREG_TLBI_VAE2IS_Xt; 2358 case 4: 2359 return MISCREG_TLBI_ALLE1IS; 2360 case 5: 2361 return MISCREG_TLBI_VALE2IS_Xt; 2362 case 6: 2363 return MISCREG_TLBI_VMALLS12E1IS; 2364 } 2365 break; 2366 case 4: 2367 switch (op2) { 2368 case 1: 2369 return MISCREG_TLBI_IPAS2E1_Xt; 2370 case 5: 2371 return MISCREG_TLBI_IPAS2LE1_Xt; 2372 } 2373 break; 2374 case 7: 2375 switch (op2) { 2376 case 0: 2377 return MISCREG_TLBI_ALLE2; 2378 case 1: 2379 return MISCREG_TLBI_VAE2_Xt; 2380 case 4: 2381 return MISCREG_TLBI_ALLE1; 2382 case 5: 2383 return MISCREG_TLBI_VALE2_Xt; 2384 case 6: 2385 return MISCREG_TLBI_VMALLS12E1; 2386 } 2387 break; 2388 } 2389 break; 2390 case 6: 2391 switch (crm) { 2392 case 3: 2393 switch (op2) { 2394 case 0: 2395 return MISCREG_TLBI_ALLE3IS; 2396 case 1: 2397 return MISCREG_TLBI_VAE3IS_Xt; 2398 case 5: 2399 return MISCREG_TLBI_VALE3IS_Xt; 2400 } 2401 break; 2402 case 7: 2403 switch (op2) { 2404 case 0: 2405 return MISCREG_TLBI_ALLE3; 2406 case 1: 2407 return MISCREG_TLBI_VAE3_Xt; 2408 case 5: 2409 return MISCREG_TLBI_VALE3_Xt; 2410 } 2411 break; 2412 } 2413 break; 2414 } 2415 break; 2416 } 2417 break; 2418 case 2: 2419 switch (crn) { 2420 case 0: 2421 switch (op1) { 2422 case 0: 2423 switch (crm) { 2424 case 0: 2425 switch (op2) { 2426 case 2: 2427 return MISCREG_OSDTRRX_EL1; 2428 case 4: 2429 return MISCREG_DBGBVR0_EL1; 2430 case 5: 2431 return MISCREG_DBGBCR0_EL1; 2432 case 6: 2433 return MISCREG_DBGWVR0_EL1; 2434 case 7: 2435 return MISCREG_DBGWCR0_EL1; 2436 } 2437 break; 2438 case 1: 2439 switch (op2) { 2440 case 4: 2441 return MISCREG_DBGBVR1_EL1; 2442 case 5: 2443 return MISCREG_DBGBCR1_EL1; 2444 case 6: 2445 return MISCREG_DBGWVR1_EL1; 2446 case 7: 2447 return MISCREG_DBGWCR1_EL1; 2448 } 2449 break; 2450 case 2: 2451 switch (op2) { 2452 case 0: 2453 return MISCREG_MDCCINT_EL1; 2454 case 2: 2455 return MISCREG_MDSCR_EL1; 2456 case 4: 2457 return MISCREG_DBGBVR2_EL1; 2458 case 5: 2459 return MISCREG_DBGBCR2_EL1; 2460 case 6: 2461 return MISCREG_DBGWVR2_EL1; 2462 case 7: 2463 return MISCREG_DBGWCR2_EL1; 2464 } 2465 break; 2466 case 3: 2467 switch (op2) { 2468 case 2: 2469 return MISCREG_OSDTRTX_EL1; 2470 case 4: 2471 return MISCREG_DBGBVR3_EL1; 2472 case 5: 2473 return MISCREG_DBGBCR3_EL1; 2474 case 6: 2475 return MISCREG_DBGWVR3_EL1; 2476 case 7: 2477 return MISCREG_DBGWCR3_EL1; 2478 } 2479 break; 2480 case 4: 2481 switch (op2) { 2482 case 4: 2483 return MISCREG_DBGBVR4_EL1; 2484 case 5: 2485 return MISCREG_DBGBCR4_EL1; 2486 } 2487 break; 2488 case 5: 2489 switch (op2) { 2490 case 4: 2491 return MISCREG_DBGBVR5_EL1; 2492 case 5: 2493 return MISCREG_DBGBCR5_EL1; 2494 } 2495 break; 2496 case 6: 2497 switch (op2) { 2498 case 2: 2499 return MISCREG_OSECCR_EL1; 2500 } 2501 break; 2502 } 2503 break; 2504 case 2: 2505 switch (crm) { 2506 case 0: 2507 switch (op2) { 2508 case 0: 2509 return MISCREG_TEECR32_EL1; 2510 } 2511 break; 2512 } 2513 break; 2514 case 3: 2515 switch (crm) { 2516 case 1: 2517 switch (op2) { 2518 case 0: 2519 return MISCREG_MDCCSR_EL0; 2520 } 2521 break; 2522 case 4: 2523 switch (op2) { 2524 case 0: 2525 return MISCREG_MDDTR_EL0; 2526 } 2527 break; 2528 case 5: 2529 switch (op2) { 2530 case 0: 2531 return MISCREG_MDDTRRX_EL0; 2532 } 2533 break; 2534 } 2535 break; 2536 case 4: 2537 switch (crm) { 2538 case 7: 2539 switch (op2) { 2540 case 0: 2541 return MISCREG_DBGVCR32_EL2; 2542 } 2543 break; 2544 } 2545 break; 2546 } 2547 break; 2548 case 1: 2549 switch (op1) { 2550 case 0: 2551 switch (crm) { 2552 case 0: 2553 switch (op2) { 2554 case 0: 2555 return MISCREG_MDRAR_EL1; 2556 case 4: 2557 return MISCREG_OSLAR_EL1; 2558 } 2559 break; 2560 case 1: 2561 switch (op2) { 2562 case 4: 2563 return MISCREG_OSLSR_EL1; 2564 } 2565 break; 2566 case 3: 2567 switch (op2) { 2568 case 4: 2569 return MISCREG_OSDLR_EL1; 2570 } 2571 break; 2572 case 4: 2573 switch (op2) { 2574 case 4: 2575 return MISCREG_DBGPRCR_EL1; 2576 } 2577 break; 2578 } 2579 break; 2580 case 2: 2581 switch (crm) { 2582 case 0: 2583 switch (op2) { 2584 case 0: 2585 return MISCREG_TEEHBR32_EL1; 2586 } 2587 break; 2588 } 2589 break; 2590 } 2591 break; 2592 case 7: 2593 switch (op1) { 2594 case 0: 2595 switch (crm) { 2596 case 8: 2597 switch (op2) { 2598 case 6: 2599 return MISCREG_DBGCLAIMSET_EL1; 2600 } 2601 break; 2602 case 9: 2603 switch (op2) { 2604 case 6: 2605 return MISCREG_DBGCLAIMCLR_EL1; 2606 } 2607 break; 2608 case 14: 2609 switch (op2) { 2610 case 6: 2611 return MISCREG_DBGAUTHSTATUS_EL1; 2612 } 2613 break; 2614 } 2615 break; 2616 } 2617 break; 2618 } 2619 break; 2620 case 3: 2621 switch (crn) { 2622 case 0: 2623 switch (op1) { 2624 case 0: 2625 switch (crm) { 2626 case 0: 2627 switch (op2) { 2628 case 0: 2629 return MISCREG_MIDR_EL1; 2630 case 5: 2631 return MISCREG_MPIDR_EL1; 2632 case 6: 2633 return MISCREG_REVIDR_EL1; 2634 } 2635 break; 2636 case 1: 2637 switch (op2) { 2638 case 0: 2639 return MISCREG_ID_PFR0_EL1; 2640 case 1: 2641 return MISCREG_ID_PFR1_EL1; 2642 case 2: 2643 return MISCREG_ID_DFR0_EL1; 2644 case 3: 2645 return MISCREG_ID_AFR0_EL1; 2646 case 4: 2647 return MISCREG_ID_MMFR0_EL1; 2648 case 5: 2649 return MISCREG_ID_MMFR1_EL1; 2650 case 6: 2651 return MISCREG_ID_MMFR2_EL1; 2652 case 7: 2653 return MISCREG_ID_MMFR3_EL1; 2654 } 2655 break; 2656 case 2: 2657 switch (op2) { 2658 case 0: 2659 return MISCREG_ID_ISAR0_EL1; 2660 case 1: 2661 return MISCREG_ID_ISAR1_EL1; 2662 case 2: 2663 return MISCREG_ID_ISAR2_EL1; 2664 case 3: 2665 return MISCREG_ID_ISAR3_EL1; 2666 case 4: 2667 return MISCREG_ID_ISAR4_EL1; 2668 case 5: 2669 return MISCREG_ID_ISAR5_EL1; 2670 } 2671 break; 2672 case 3: 2673 switch (op2) { 2674 case 0: 2675 return MISCREG_MVFR0_EL1; 2676 case 1: 2677 return MISCREG_MVFR1_EL1; 2678 case 2: 2679 return MISCREG_MVFR2_EL1; 2680 case 3 ... 7: 2681 return MISCREG_RAZ; 2682 } 2683 break; 2684 case 4: 2685 switch (op2) { 2686 case 0: 2687 return MISCREG_ID_AA64PFR0_EL1; 2688 case 1: 2689 return MISCREG_ID_AA64PFR1_EL1; 2690 case 2 ... 7: 2691 return MISCREG_RAZ; 2692 } 2693 break; 2694 case 5: 2695 switch (op2) { 2696 case 0: 2697 return MISCREG_ID_AA64DFR0_EL1; 2698 case 1: 2699 return MISCREG_ID_AA64DFR1_EL1; 2700 case 4: 2701 return MISCREG_ID_AA64AFR0_EL1; 2702 case 5: 2703 return MISCREG_ID_AA64AFR1_EL1; 2704 case 2: 2705 case 3: 2706 case 6: 2707 case 7: 2708 return MISCREG_RAZ; 2709 } 2710 break; 2711 case 6: 2712 switch (op2) { 2713 case 0: 2714 return MISCREG_ID_AA64ISAR0_EL1; 2715 case 1: 2716 return MISCREG_ID_AA64ISAR1_EL1; 2717 case 2 ... 7: 2718 return MISCREG_RAZ; 2719 } 2720 break; 2721 case 7: 2722 switch (op2) { 2723 case 0: 2724 return MISCREG_ID_AA64MMFR0_EL1; 2725 case 1: 2726 return MISCREG_ID_AA64MMFR1_EL1; 2727 case 2 ... 7: 2728 return MISCREG_RAZ; 2729 } 2730 break; 2731 } 2732 break; 2733 case 1: 2734 switch (crm) { 2735 case 0: 2736 switch (op2) { 2737 case 0: 2738 return MISCREG_CCSIDR_EL1; 2739 case 1: 2740 return MISCREG_CLIDR_EL1; 2741 case 7: 2742 return MISCREG_AIDR_EL1; 2743 } 2744 break; 2745 } 2746 break; 2747 case 2: 2748 switch (crm) { 2749 case 0: 2750 switch (op2) { 2751 case 0: 2752 return MISCREG_CSSELR_EL1; 2753 } 2754 break; 2755 } 2756 break; 2757 case 3: 2758 switch (crm) { 2759 case 0: 2760 switch (op2) { 2761 case 1: 2762 return MISCREG_CTR_EL0; 2763 case 7: 2764 return MISCREG_DCZID_EL0; 2765 } 2766 break; 2767 } 2768 break; 2769 case 4: 2770 switch (crm) { 2771 case 0: 2772 switch (op2) { 2773 case 0: 2774 return MISCREG_VPIDR_EL2; 2775 case 5: 2776 return MISCREG_VMPIDR_EL2; 2777 } 2778 break; 2779 } 2780 break; 2781 } 2782 break; 2783 case 1: 2784 switch (op1) { 2785 case 0: 2786 switch (crm) { 2787 case 0: 2788 switch (op2) { 2789 case 0: 2790 return MISCREG_SCTLR_EL1; 2791 case 1: 2792 return MISCREG_ACTLR_EL1; 2793 case 2: 2794 return MISCREG_CPACR_EL1; 2795 } 2796 break; 2797 } 2798 break; 2799 case 4: 2800 switch (crm) { 2801 case 0: 2802 switch (op2) { 2803 case 0: 2804 return MISCREG_SCTLR_EL2; 2805 case 1: 2806 return MISCREG_ACTLR_EL2; 2807 } 2808 break; 2809 case 1: 2810 switch (op2) { 2811 case 0: 2812 return MISCREG_HCR_EL2; 2813 case 1: 2814 return MISCREG_MDCR_EL2; 2815 case 2: 2816 return MISCREG_CPTR_EL2; 2817 case 3: 2818 return MISCREG_HSTR_EL2; 2819 case 7: 2820 return MISCREG_HACR_EL2; 2821 } 2822 break; 2823 } 2824 break; 2825 case 6: 2826 switch (crm) { 2827 case 0: 2828 switch (op2) { 2829 case 0: 2830 return MISCREG_SCTLR_EL3; 2831 case 1: 2832 return MISCREG_ACTLR_EL3; 2833 } 2834 break; 2835 case 1: 2836 switch (op2) { 2837 case 0: 2838 return MISCREG_SCR_EL3; 2839 case 1: 2840 return MISCREG_SDER32_EL3; 2841 case 2: 2842 return MISCREG_CPTR_EL3; 2843 } 2844 break; 2845 case 3: 2846 switch (op2) { 2847 case 1: 2848 return MISCREG_MDCR_EL3; 2849 } 2850 break; 2851 } 2852 break; 2853 } 2854 break; 2855 case 2: 2856 switch (op1) { 2857 case 0: 2858 switch (crm) { 2859 case 0: 2860 switch (op2) { 2861 case 0: 2862 return MISCREG_TTBR0_EL1; 2863 case 1: 2864 return MISCREG_TTBR1_EL1; 2865 case 2: 2866 return MISCREG_TCR_EL1; 2867 } 2868 break; 2869 } 2870 break; 2871 case 4: 2872 switch (crm) { 2873 case 0: 2874 switch (op2) { 2875 case 0: 2876 return MISCREG_TTBR0_EL2; 2877 case 2: 2878 return MISCREG_TCR_EL2; 2879 } 2880 break; 2881 case 1: 2882 switch (op2) { 2883 case 0: 2884 return MISCREG_VTTBR_EL2; 2885 case 2: 2886 return MISCREG_VTCR_EL2; 2887 } 2888 break; 2889 } 2890 break; 2891 case 6: 2892 switch (crm) { 2893 case 0: 2894 switch (op2) { 2895 case 0: 2896 return MISCREG_TTBR0_EL3; 2897 case 2: 2898 return MISCREG_TCR_EL3; 2899 } 2900 break; 2901 } 2902 break; 2903 } 2904 break; 2905 case 3: 2906 switch (op1) { 2907 case 4: 2908 switch (crm) { 2909 case 0: 2910 switch (op2) { 2911 case 0: 2912 return MISCREG_DACR32_EL2; 2913 } 2914 break; 2915 } 2916 break; 2917 } 2918 break; 2919 case 4: 2920 switch (op1) { 2921 case 0: 2922 switch (crm) { 2923 case 0: 2924 switch (op2) { 2925 case 0: 2926 return MISCREG_SPSR_EL1; 2927 case 1: 2928 return MISCREG_ELR_EL1; 2929 } 2930 break; 2931 case 1: 2932 switch (op2) { 2933 case 0: 2934 return MISCREG_SP_EL0; 2935 } 2936 break; 2937 case 2: 2938 switch (op2) { 2939 case 0: 2940 return MISCREG_SPSEL; 2941 case 2: 2942 return MISCREG_CURRENTEL; 2943 } 2944 break; 2945 } 2946 break; 2947 case 3: 2948 switch (crm) { 2949 case 2: 2950 switch (op2) { 2951 case 0: 2952 return MISCREG_NZCV; 2953 case 1: 2954 return MISCREG_DAIF; 2955 } 2956 break; 2957 case 4: 2958 switch (op2) { 2959 case 0: 2960 return MISCREG_FPCR; 2961 case 1: 2962 return MISCREG_FPSR; 2963 } 2964 break; 2965 case 5: 2966 switch (op2) { 2967 case 0: 2968 return MISCREG_DSPSR_EL0; 2969 case 1: 2970 return MISCREG_DLR_EL0; 2971 } 2972 break; 2973 } 2974 break; 2975 case 4: 2976 switch (crm) { 2977 case 0: 2978 switch (op2) { 2979 case 0: 2980 return MISCREG_SPSR_EL2; 2981 case 1: 2982 return MISCREG_ELR_EL2; 2983 } 2984 break; 2985 case 1: 2986 switch (op2) { 2987 case 0: 2988 return MISCREG_SP_EL1; 2989 } 2990 break; 2991 case 3: 2992 switch (op2) { 2993 case 0: 2994 return MISCREG_SPSR_IRQ_AA64; 2995 case 1: 2996 return MISCREG_SPSR_ABT_AA64; 2997 case 2: 2998 return MISCREG_SPSR_UND_AA64; 2999 case 3: 3000 return MISCREG_SPSR_FIQ_AA64; 3001 } 3002 break; 3003 } 3004 break; 3005 case 6: 3006 switch (crm) { 3007 case 0: 3008 switch (op2) { 3009 case 0: 3010 return MISCREG_SPSR_EL3; 3011 case 1: 3012 return MISCREG_ELR_EL3; 3013 } 3014 break; 3015 case 1: 3016 switch (op2) { 3017 case 0: 3018 return MISCREG_SP_EL2; 3019 } 3020 break; 3021 } 3022 break; 3023 } 3024 break; 3025 case 5: 3026 switch (op1) { 3027 case 0: 3028 switch (crm) { 3029 case 1: 3030 switch (op2) { 3031 case 0: 3032 return MISCREG_AFSR0_EL1; 3033 case 1: 3034 return MISCREG_AFSR1_EL1; 3035 } 3036 break; 3037 case 2: 3038 switch (op2) { 3039 case 0: 3040 return MISCREG_ESR_EL1; 3041 } 3042 break; 3043 } 3044 break; 3045 case 4: 3046 switch (crm) { 3047 case 0: 3048 switch (op2) { 3049 case 1: 3050 return MISCREG_IFSR32_EL2; 3051 } 3052 break; 3053 case 1: 3054 switch (op2) { 3055 case 0: 3056 return MISCREG_AFSR0_EL2; 3057 case 1: 3058 return MISCREG_AFSR1_EL2; 3059 } 3060 break; 3061 case 2: 3062 switch (op2) { 3063 case 0: 3064 return MISCREG_ESR_EL2; 3065 } 3066 break; 3067 case 3: 3068 switch (op2) { 3069 case 0: 3070 return MISCREG_FPEXC32_EL2; 3071 } 3072 break; 3073 } 3074 break; 3075 case 6: 3076 switch (crm) { 3077 case 1: 3078 switch (op2) { 3079 case 0: 3080 return MISCREG_AFSR0_EL3; 3081 case 1: 3082 return MISCREG_AFSR1_EL3; 3083 } 3084 break; 3085 case 2: 3086 switch (op2) { 3087 case 0: 3088 return MISCREG_ESR_EL3; 3089 } 3090 break; 3091 } 3092 break; 3093 } 3094 break; 3095 case 6: 3096 switch (op1) { 3097 case 0: 3098 switch (crm) { 3099 case 0: 3100 switch (op2) { 3101 case 0: 3102 return MISCREG_FAR_EL1; 3103 } 3104 break; 3105 } 3106 break; 3107 case 4: 3108 switch (crm) { 3109 case 0: 3110 switch (op2) { 3111 case 0: 3112 return MISCREG_FAR_EL2; 3113 case 4: 3114 return MISCREG_HPFAR_EL2; 3115 } 3116 break; 3117 } 3118 break; 3119 case 6: 3120 switch (crm) { 3121 case 0: 3122 switch (op2) { 3123 case 0: 3124 return MISCREG_FAR_EL3; 3125 } 3126 break; 3127 } 3128 break; 3129 } 3130 break; 3131 case 7: 3132 switch (op1) { 3133 case 0: 3134 switch (crm) { 3135 case 4: 3136 switch (op2) { 3137 case 0: 3138 return MISCREG_PAR_EL1; 3139 } 3140 break; 3141 } 3142 break; 3143 } 3144 break; 3145 case 9: 3146 switch (op1) { 3147 case 0: 3148 switch (crm) { 3149 case 14: 3150 switch (op2) { 3151 case 1: 3152 return MISCREG_PMINTENSET_EL1; 3153 case 2: 3154 return MISCREG_PMINTENCLR_EL1; 3155 } 3156 break; 3157 } 3158 break; 3159 case 3: 3160 switch (crm) { 3161 case 12: 3162 switch (op2) { 3163 case 0: 3164 return MISCREG_PMCR_EL0; 3165 case 1: 3166 return MISCREG_PMCNTENSET_EL0; 3167 case 2: 3168 return MISCREG_PMCNTENCLR_EL0; 3169 case 3: 3170 return MISCREG_PMOVSCLR_EL0; 3171 case 4: 3172 return MISCREG_PMSWINC_EL0; 3173 case 5: 3174 return MISCREG_PMSELR_EL0; 3175 case 6: 3176 return MISCREG_PMCEID0_EL0; 3177 case 7: 3178 return MISCREG_PMCEID1_EL0; 3179 } 3180 break; 3181 case 13: 3182 switch (op2) { 3183 case 0: 3184 return MISCREG_PMCCNTR_EL0; 3185 case 1: 3186 return MISCREG_PMXEVTYPER_EL0; 3187 case 2: 3188 return MISCREG_PMXEVCNTR_EL0; 3189 } 3190 break; 3191 case 14: 3192 switch (op2) { 3193 case 0: 3194 return MISCREG_PMUSERENR_EL0; 3195 case 3: 3196 return MISCREG_PMOVSSET_EL0; 3197 } 3198 break; 3199 } 3200 break; 3201 } 3202 break; 3203 case 10: 3204 switch (op1) { 3205 case 0: 3206 switch (crm) { 3207 case 2: 3208 switch (op2) { 3209 case 0: 3210 return MISCREG_MAIR_EL1; 3211 } 3212 break; 3213 case 3: 3214 switch (op2) { 3215 case 0: 3216 return MISCREG_AMAIR_EL1; 3217 } 3218 break; 3219 } 3220 break; 3221 case 4: 3222 switch (crm) { 3223 case 2: 3224 switch (op2) { 3225 case 0: 3226 return MISCREG_MAIR_EL2; 3227 } 3228 break; 3229 case 3: 3230 switch (op2) { 3231 case 0: 3232 return MISCREG_AMAIR_EL2; 3233 } 3234 break; 3235 } 3236 break; 3237 case 6: 3238 switch (crm) { 3239 case 2: 3240 switch (op2) { 3241 case 0: 3242 return MISCREG_MAIR_EL3; 3243 } 3244 break; 3245 case 3: 3246 switch (op2) { 3247 case 0: 3248 return MISCREG_AMAIR_EL3; 3249 } 3250 break; 3251 } 3252 break; 3253 } 3254 break; 3255 case 11: 3256 switch (op1) { 3257 case 1: 3258 switch (crm) { 3259 case 0: 3260 switch (op2) { 3261 case 2: 3262 return MISCREG_L2CTLR_EL1; 3263 case 3: 3264 return MISCREG_L2ECTLR_EL1; 3265 } 3266 break; 3267 } 3268 break; 3269 } 3270 break; 3271 case 12: 3272 switch (op1) { 3273 case 0: 3274 switch (crm) { 3275 case 0: 3276 switch (op2) { 3277 case 0: 3278 return MISCREG_VBAR_EL1; 3279 case 1: 3280 return MISCREG_RVBAR_EL1; 3281 } 3282 break; 3283 case 1: 3284 switch (op2) { 3285 case 0: 3286 return MISCREG_ISR_EL1; 3287 } 3288 break; 3289 } 3290 break; 3291 case 4: 3292 switch (crm) { 3293 case 0: 3294 switch (op2) { 3295 case 0: 3296 return MISCREG_VBAR_EL2; 3297 case 1: 3298 return MISCREG_RVBAR_EL2; 3299 } 3300 break; 3301 } 3302 break; 3303 case 6: 3304 switch (crm) { 3305 case 0: 3306 switch (op2) { 3307 case 0: 3308 return MISCREG_VBAR_EL3; 3309 case 1: 3310 return MISCREG_RVBAR_EL3; 3311 case 2: 3312 return MISCREG_RMR_EL3; 3313 } 3314 break; 3315 } 3316 break; 3317 } 3318 break; 3319 case 13: 3320 switch (op1) { 3321 case 0: 3322 switch (crm) { 3323 case 0: 3324 switch (op2) { 3325 case 1: 3326 return MISCREG_CONTEXTIDR_EL1; 3327 case 4: 3328 return MISCREG_TPIDR_EL1; 3329 } 3330 break; 3331 } 3332 break; 3333 case 3: 3334 switch (crm) { 3335 case 0: 3336 switch (op2) { 3337 case 2: 3338 return MISCREG_TPIDR_EL0; 3339 case 3: 3340 return MISCREG_TPIDRRO_EL0; 3341 } 3342 break; 3343 } 3344 break; 3345 case 4: 3346 switch (crm) { 3347 case 0: 3348 switch (op2) { 3349 case 1: 3350 return MISCREG_CONTEXTIDR_EL2; 3351 case 2: 3352 return MISCREG_TPIDR_EL2; 3353 } 3354 break; 3355 } 3356 break; 3357 case 6: 3358 switch (crm) { 3359 case 0: 3360 switch (op2) { 3361 case 2: 3362 return MISCREG_TPIDR_EL3; 3363 } 3364 break; 3365 } 3366 break; 3367 } 3368 break; 3369 case 14: 3370 switch (op1) { 3371 case 0: 3372 switch (crm) { 3373 case 1: 3374 switch (op2) { 3375 case 0: 3376 return MISCREG_CNTKCTL_EL1; 3377 } 3378 break; 3379 } 3380 break; 3381 case 3: 3382 switch (crm) { 3383 case 0: 3384 switch (op2) { 3385 case 0: 3386 return MISCREG_CNTFRQ_EL0; 3387 case 1: 3388 return MISCREG_CNTPCT_EL0; 3389 case 2: 3390 return MISCREG_CNTVCT_EL0; 3391 } 3392 break; 3393 case 2: 3394 switch (op2) { 3395 case 0: 3396 return MISCREG_CNTP_TVAL_EL0; 3397 case 1: 3398 return MISCREG_CNTP_CTL_EL0; 3399 case 2: 3400 return MISCREG_CNTP_CVAL_EL0; 3401 } 3402 break; 3403 case 3: 3404 switch (op2) { 3405 case 0: 3406 return MISCREG_CNTV_TVAL_EL0; 3407 case 1: 3408 return MISCREG_CNTV_CTL_EL0; 3409 case 2: 3410 return MISCREG_CNTV_CVAL_EL0; 3411 } 3412 break; 3413 case 8: 3414 switch (op2) { 3415 case 0: 3416 return MISCREG_PMEVCNTR0_EL0; 3417 case 1: 3418 return MISCREG_PMEVCNTR1_EL0; 3419 case 2: 3420 return MISCREG_PMEVCNTR2_EL0; 3421 case 3: 3422 return MISCREG_PMEVCNTR3_EL0; 3423 case 4: 3424 return MISCREG_PMEVCNTR4_EL0; 3425 case 5: 3426 return MISCREG_PMEVCNTR5_EL0; 3427 } 3428 break; 3429 case 12: 3430 switch (op2) { 3431 case 0: 3432 return MISCREG_PMEVTYPER0_EL0; 3433 case 1: 3434 return MISCREG_PMEVTYPER1_EL0; 3435 case 2: 3436 return MISCREG_PMEVTYPER2_EL0; 3437 case 3: 3438 return MISCREG_PMEVTYPER3_EL0; 3439 case 4: 3440 return MISCREG_PMEVTYPER4_EL0; 3441 case 5: 3442 return MISCREG_PMEVTYPER5_EL0; 3443 } 3444 break; 3445 case 15: 3446 switch (op2) { 3447 case 7: 3448 return MISCREG_PMCCFILTR_EL0; 3449 } 3450 } 3451 break; 3452 case 4: 3453 switch (crm) { 3454 case 0: 3455 switch (op2) { 3456 case 3: 3457 return MISCREG_CNTVOFF_EL2; 3458 } 3459 break; 3460 case 1: 3461 switch (op2) { 3462 case 0: 3463 return MISCREG_CNTHCTL_EL2; 3464 } 3465 break; 3466 case 2: 3467 switch (op2) { 3468 case 0: 3469 return MISCREG_CNTHP_TVAL_EL2; 3470 case 1: 3471 return MISCREG_CNTHP_CTL_EL2; 3472 case 2: 3473 return MISCREG_CNTHP_CVAL_EL2; 3474 } 3475 break; 3476 } 3477 break; 3478 case 7: 3479 switch (crm) { 3480 case 2: 3481 switch (op2) { 3482 case 0: 3483 return MISCREG_CNTPS_TVAL_EL1; 3484 case 1: 3485 return MISCREG_CNTPS_CTL_EL1; 3486 case 2: 3487 return MISCREG_CNTPS_CVAL_EL1; 3488 } 3489 break; 3490 } 3491 break; 3492 } 3493 break; 3494 case 15: 3495 switch (op1) { 3496 case 0: 3497 switch (crm) { 3498 case 0: 3499 switch (op2) { 3500 case 0: 3501 return MISCREG_IL1DATA0_EL1; 3502 case 1: 3503 return MISCREG_IL1DATA1_EL1; 3504 case 2: 3505 return MISCREG_IL1DATA2_EL1; 3506 case 3: 3507 return MISCREG_IL1DATA3_EL1; 3508 } 3509 break; 3510 case 1: 3511 switch (op2) { 3512 case 0: 3513 return MISCREG_DL1DATA0_EL1; 3514 case 1: 3515 return MISCREG_DL1DATA1_EL1; 3516 case 2: 3517 return MISCREG_DL1DATA2_EL1; 3518 case 3: 3519 return MISCREG_DL1DATA3_EL1; 3520 case 4: 3521 return MISCREG_DL1DATA4_EL1; 3522 } 3523 break; 3524 } 3525 break; 3526 case 1: 3527 switch (crm) { 3528 case 0: 3529 switch (op2) { 3530 case 0: 3531 return MISCREG_L2ACTLR_EL1; 3532 } 3533 break; 3534 case 2: 3535 switch (op2) { 3536 case 0: 3537 return MISCREG_CPUACTLR_EL1; 3538 case 1: 3539 return MISCREG_CPUECTLR_EL1; 3540 case 2: 3541 return MISCREG_CPUMERRSR_EL1; 3542 case 3: 3543 return MISCREG_L2MERRSR_EL1; 3544 } 3545 break; 3546 case 3: 3547 switch (op2) { 3548 case 0: 3549 return MISCREG_CBAR_EL1; 3550 3551 } 3552 break; 3553 } 3554 break; 3555 } 3556 break; 3557 } 3558 break; 3559 } 3560 3561 return MISCREG_UNKNOWN; 3562} 3563 3564} // namespace ArmISA 3565