miscregs.cc revision 11771:764eae95bbbb
1/* 2 * Copyright (c) 2010-2013, 2015-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 * Giacomo Gabrielli 40 */ 41 42#include "arch/arm/isa.hh" 43#include "arch/arm/miscregs.hh" 44#include "base/misc.hh" 45#include "cpu/thread_context.hh" 46#include "sim/full_system.hh" 47 48namespace ArmISA 49{ 50 51MiscRegIndex 52decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 53{ 54 switch(crn) { 55 case 0: 56 switch (opc1) { 57 case 0: 58 switch (opc2) { 59 case 0: 60 switch (crm) { 61 case 0: 62 return MISCREG_DBGDIDR; 63 case 1: 64 return MISCREG_DBGDSCRint; 65 } 66 break; 67 } 68 break; 69 case 7: 70 switch (opc2) { 71 case 0: 72 switch (crm) { 73 case 0: 74 return MISCREG_JIDR; 75 } 76 break; 77 } 78 break; 79 } 80 break; 81 case 1: 82 switch (opc1) { 83 case 6: 84 switch (crm) { 85 case 0: 86 switch (opc2) { 87 case 0: 88 return MISCREG_TEEHBR; 89 } 90 break; 91 } 92 break; 93 case 7: 94 switch (crm) { 95 case 0: 96 switch (opc2) { 97 case 0: 98 return MISCREG_JOSCR; 99 } 100 break; 101 } 102 break; 103 } 104 break; 105 case 2: 106 switch (opc1) { 107 case 7: 108 switch (crm) { 109 case 0: 110 switch (opc2) { 111 case 0: 112 return MISCREG_JMCR; 113 } 114 break; 115 } 116 break; 117 } 118 break; 119 } 120 // If we get here then it must be a register that we haven't implemented 121 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 122 crn, opc1, crm, opc2); 123 return MISCREG_CP14_UNIMPL; 124} 125 126using namespace std; 127 128bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = { 129 // MISCREG_CPSR 130 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 131 // MISCREG_SPSR 132 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 133 // MISCREG_SPSR_FIQ 134 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 135 // MISCREG_SPSR_IRQ 136 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 137 // MISCREG_SPSR_SVC 138 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 139 // MISCREG_SPSR_MON 140 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 141 // MISCREG_SPSR_ABT 142 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 143 // MISCREG_SPSR_HYP 144 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 145 // MISCREG_SPSR_UND 146 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 147 // MISCREG_ELR_HYP 148 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 149 // MISCREG_FPSID 150 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 151 // MISCREG_FPSCR 152 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 153 // MISCREG_MVFR1 154 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 155 // MISCREG_MVFR0 156 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 157 // MISCREG_FPEXC 158 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 159 160 // Helper registers 161 // MISCREG_CPSR_MODE 162 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 163 // MISCREG_CPSR_Q 164 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 165 // MISCREG_FPSCR_Q 166 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 167 // MISCREG_FPSCR_EXC 168 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 169 // MISCREG_LOCKADDR 170 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 171 // MISCREG_LOCKFLAG 172 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 173 // MISCREG_PRRR_MAIR0 174 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")), 175 // MISCREG_PRRR_MAIR0_NS 176 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 177 // MISCREG_PRRR_MAIR0_S 178 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 179 // MISCREG_NMRR_MAIR1 180 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")), 181 // MISCREG_NMRR_MAIR1_NS 182 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 183 // MISCREG_NMRR_MAIR1_S 184 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 185 // MISCREG_PMXEVTYPER_PMCCFILTR 186 bitset<NUM_MISCREG_INFOS>(string("00000000000000001001")), 187 // MISCREG_SCTLR_RST 188 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 189 // MISCREG_SEV_MAILBOX 190 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 191 192 // AArch32 CP14 registers 193 // MISCREG_DBGDIDR 194 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 195 // MISCREG_DBGDSCRint 196 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 197 // MISCREG_DBGDCCINT 198 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 199 // MISCREG_DBGDTRTXint 200 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 201 // MISCREG_DBGDTRRXint 202 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 203 // MISCREG_DBGWFAR 204 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 205 // MISCREG_DBGVCR 206 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 207 // MISCREG_DBGDTRRXext 208 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 209 // MISCREG_DBGDSCRext 210 bitset<NUM_MISCREG_INFOS>(string("11111111111111000100")), 211 // MISCREG_DBGDTRTXext 212 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 213 // MISCREG_DBGOSECCR 214 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 215 // MISCREG_DBGBVR0 216 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 217 // MISCREG_DBGBVR1 218 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 219 // MISCREG_DBGBVR2 220 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 221 // MISCREG_DBGBVR3 222 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 223 // MISCREG_DBGBVR4 224 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 225 // MISCREG_DBGBVR5 226 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 227 // MISCREG_DBGBCR0 228 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 229 // MISCREG_DBGBCR1 230 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 231 // MISCREG_DBGBCR2 232 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 233 // MISCREG_DBGBCR3 234 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 235 // MISCREG_DBGBCR4 236 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 237 // MISCREG_DBGBCR5 238 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 239 // MISCREG_DBGWVR0 240 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 241 // MISCREG_DBGWVR1 242 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 243 // MISCREG_DBGWVR2 244 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 245 // MISCREG_DBGWVR3 246 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 247 // MISCREG_DBGWCR0 248 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 249 // MISCREG_DBGWCR1 250 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 251 // MISCREG_DBGWCR2 252 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 253 // MISCREG_DBGWCR3 254 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 255 // MISCREG_DBGDRAR 256 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 257 // MISCREG_DBGBXVR4 258 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 259 // MISCREG_DBGBXVR5 260 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 261 // MISCREG_DBGOSLAR 262 bitset<NUM_MISCREG_INFOS>(string("10101111111111000000")), 263 // MISCREG_DBGOSLSR 264 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 265 // MISCREG_DBGOSDLR 266 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 267 // MISCREG_DBGPRCR 268 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 269 // MISCREG_DBGDSAR 270 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 271 // MISCREG_DBGCLAIMSET 272 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 273 // MISCREG_DBGCLAIMCLR 274 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 275 // MISCREG_DBGAUTHSTATUS 276 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 277 // MISCREG_DBGDEVID2 278 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 279 // MISCREG_DBGDEVID1 280 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 281 // MISCREG_DBGDEVID0 282 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 283 // MISCREG_TEECR 284 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 285 // MISCREG_JIDR 286 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 287 // MISCREG_TEEHBR 288 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 289 // MISCREG_JOSCR 290 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 291 // MISCREG_JMCR 292 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 293 294 // AArch32 CP15 registers 295 // MISCREG_MIDR 296 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 297 // MISCREG_CTR 298 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 299 // MISCREG_TCMTR 300 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 301 // MISCREG_TLBTR 302 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 303 // MISCREG_MPIDR 304 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 305 // MISCREG_REVIDR 306 bitset<NUM_MISCREG_INFOS>(string("01010101010000000100")), 307 // MISCREG_ID_PFR0 308 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 309 // MISCREG_ID_PFR1 310 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 311 // MISCREG_ID_DFR0 312 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 313 // MISCREG_ID_AFR0 314 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 315 // MISCREG_ID_MMFR0 316 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 317 // MISCREG_ID_MMFR1 318 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 319 // MISCREG_ID_MMFR2 320 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 321 // MISCREG_ID_MMFR3 322 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 323 // MISCREG_ID_ISAR0 324 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 325 // MISCREG_ID_ISAR1 326 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 327 // MISCREG_ID_ISAR2 328 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 329 // MISCREG_ID_ISAR3 330 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 331 // MISCREG_ID_ISAR4 332 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 333 // MISCREG_ID_ISAR5 334 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 335 // MISCREG_CCSIDR 336 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 337 // MISCREG_CLIDR 338 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 339 // MISCREG_AIDR 340 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 341 // MISCREG_CSSELR 342 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 343 // MISCREG_CSSELR_NS 344 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 345 // MISCREG_CSSELR_S 346 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 347 // MISCREG_VPIDR 348 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 349 // MISCREG_VMPIDR 350 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 351 // MISCREG_SCTLR 352 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 353 // MISCREG_SCTLR_NS 354 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 355 // MISCREG_SCTLR_S 356 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 357 // MISCREG_ACTLR 358 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 359 // MISCREG_ACTLR_NS 360 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 361 // MISCREG_ACTLR_S 362 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 363 // MISCREG_CPACR 364 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 365 // MISCREG_SCR 366 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")), 367 // MISCREG_SDER 368 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 369 // MISCREG_NSACR 370 bitset<NUM_MISCREG_INFOS>(string("11110111010000000001")), 371 // MISCREG_HSCTLR 372 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 373 // MISCREG_HACTLR 374 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 375 // MISCREG_HCR 376 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 377 // MISCREG_HDCR 378 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 379 // MISCREG_HCPTR 380 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 381 // MISCREG_HSTR 382 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 383 // MISCREG_HACR 384 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")), 385 // MISCREG_TTBR0 386 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 387 // MISCREG_TTBR0_NS 388 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 389 // MISCREG_TTBR0_S 390 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 391 // MISCREG_TTBR1 392 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 393 // MISCREG_TTBR1_NS 394 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 395 // MISCREG_TTBR1_S 396 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 397 // MISCREG_TTBCR 398 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 399 // MISCREG_TTBCR_NS 400 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 401 // MISCREG_TTBCR_S 402 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 403 // MISCREG_HTCR 404 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 405 // MISCREG_VTCR 406 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 407 // MISCREG_DACR 408 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 409 // MISCREG_DACR_NS 410 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 411 // MISCREG_DACR_S 412 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 413 // MISCREG_DFSR 414 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 415 // MISCREG_DFSR_NS 416 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 417 // MISCREG_DFSR_S 418 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 419 // MISCREG_IFSR 420 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 421 // MISCREG_IFSR_NS 422 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 423 // MISCREG_IFSR_S 424 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 425 // MISCREG_ADFSR 426 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")), 427 // MISCREG_ADFSR_NS 428 bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")), 429 // MISCREG_ADFSR_S 430 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")), 431 // MISCREG_AIFSR 432 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")), 433 // MISCREG_AIFSR_NS 434 bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")), 435 // MISCREG_AIFSR_S 436 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")), 437 // MISCREG_HADFSR 438 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 439 // MISCREG_HAIFSR 440 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 441 // MISCREG_HSR 442 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 443 // MISCREG_DFAR 444 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 445 // MISCREG_DFAR_NS 446 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 447 // MISCREG_DFAR_S 448 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 449 // MISCREG_IFAR 450 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 451 // MISCREG_IFAR_NS 452 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 453 // MISCREG_IFAR_S 454 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 455 // MISCREG_HDFAR 456 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 457 // MISCREG_HIFAR 458 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 459 // MISCREG_HPFAR 460 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 461 // MISCREG_ICIALLUIS 462 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 463 // MISCREG_BPIALLIS 464 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 465 // MISCREG_PAR 466 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 467 // MISCREG_PAR_NS 468 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 469 // MISCREG_PAR_S 470 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 471 // MISCREG_ICIALLU 472 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 473 // MISCREG_ICIMVAU 474 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 475 // MISCREG_CP15ISB 476 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 477 // MISCREG_BPIALL 478 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 479 // MISCREG_BPIMVA 480 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 481 // MISCREG_DCIMVAC 482 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 483 // MISCREG_DCISW 484 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 485 // MISCREG_ATS1CPR 486 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 487 // MISCREG_ATS1CPW 488 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 489 // MISCREG_ATS1CUR 490 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 491 // MISCREG_ATS1CUW 492 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 493 // MISCREG_ATS12NSOPR 494 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 495 // MISCREG_ATS12NSOPW 496 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 497 // MISCREG_ATS12NSOUR 498 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 499 // MISCREG_ATS12NSOUW 500 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 501 // MISCREG_DCCMVAC 502 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 503 // MISCREG_DCCSW 504 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 505 // MISCREG_CP15DSB 506 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 507 // MISCREG_CP15DMB 508 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 509 // MISCREG_DCCMVAU 510 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 511 // MISCREG_DCCIMVAC 512 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 513 // MISCREG_DCCISW 514 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 515 // MISCREG_ATS1HR 516 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 517 // MISCREG_ATS1HW 518 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 519 // MISCREG_TLBIALLIS 520 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 521 // MISCREG_TLBIMVAIS 522 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 523 // MISCREG_TLBIASIDIS 524 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 525 // MISCREG_TLBIMVAAIS 526 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 527 // MISCREG_TLBIMVALIS 528 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 529 // MISCREG_TLBIMVAALIS 530 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 531 // MISCREG_ITLBIALL 532 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 533 // MISCREG_ITLBIMVA 534 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 535 // MISCREG_ITLBIASID 536 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 537 // MISCREG_DTLBIALL 538 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 539 // MISCREG_DTLBIMVA 540 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 541 // MISCREG_DTLBIASID 542 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 543 // MISCREG_TLBIALL 544 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 545 // MISCREG_TLBIMVA 546 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 547 // MISCREG_TLBIASID 548 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 549 // MISCREG_TLBIMVAA 550 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 551 // MISCREG_TLBIMVAL 552 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 553 // MISCREG_TLBIMVAAL 554 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 555 // MISCREG_TLBIIPAS2IS 556 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 557 // MISCREG_TLBIIPAS2LIS 558 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 559 // MISCREG_TLBIALLHIS 560 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 561 // MISCREG_TLBIMVAHIS 562 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 563 // MISCREG_TLBIALLNSNHIS 564 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 565 // MISCREG_TLBIMVALHIS 566 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 567 // MISCREG_TLBIIPAS2 568 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 569 // MISCREG_TLBIIPAS2L 570 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 571 // MISCREG_TLBIALLH 572 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 573 // MISCREG_TLBIMVAH 574 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 575 // MISCREG_TLBIALLNSNH 576 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 577 // MISCREG_TLBIMVALH 578 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 579 // MISCREG_PMCR 580 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 581 // MISCREG_PMCNTENSET 582 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 583 // MISCREG_PMCNTENCLR 584 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 585 // MISCREG_PMOVSR 586 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 587 // MISCREG_PMSWINC 588 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 589 // MISCREG_PMSELR 590 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 591 // MISCREG_PMCEID0 592 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 593 // MISCREG_PMCEID1 594 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 595 // MISCREG_PMCCNTR 596 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 597 // MISCREG_PMXEVTYPER 598 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 599 // MISCREG_PMCCFILTR 600 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 601 // MISCREG_PMXEVCNTR 602 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 603 // MISCREG_PMUSERENR 604 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")), 605 // MISCREG_PMINTENSET 606 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 607 // MISCREG_PMINTENCLR 608 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 609 // MISCREG_PMOVSSET 610 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 611 // MISCREG_L2CTLR 612 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 613 // MISCREG_L2ECTLR 614 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 615 // MISCREG_PRRR 616 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 617 // MISCREG_PRRR_NS 618 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 619 // MISCREG_PRRR_S 620 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 621 // MISCREG_MAIR0 622 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 623 // MISCREG_MAIR0_NS 624 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 625 // MISCREG_MAIR0_S 626 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 627 // MISCREG_NMRR 628 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 629 // MISCREG_NMRR_NS 630 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 631 // MISCREG_NMRR_S 632 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 633 // MISCREG_MAIR1 634 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 635 // MISCREG_MAIR1_NS 636 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 637 // MISCREG_MAIR1_S 638 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 639 // MISCREG_AMAIR0 640 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 641 // MISCREG_AMAIR0_NS 642 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 643 // MISCREG_AMAIR0_S 644 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 645 // MISCREG_AMAIR1 646 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 647 // MISCREG_AMAIR1_NS 648 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 649 // MISCREG_AMAIR1_S 650 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 651 // MISCREG_HMAIR0 652 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 653 // MISCREG_HMAIR1 654 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 655 // MISCREG_HAMAIR0 656 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")), 657 // MISCREG_HAMAIR1 658 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")), 659 // MISCREG_VBAR 660 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 661 // MISCREG_VBAR_NS 662 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 663 // MISCREG_VBAR_S 664 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 665 // MISCREG_MVBAR 666 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")), 667 // MISCREG_RMR 668 bitset<NUM_MISCREG_INFOS>(string("11110011000000000000")), 669 // MISCREG_ISR 670 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 671 // MISCREG_HVBAR 672 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 673 // MISCREG_FCSEIDR 674 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), 675 // MISCREG_CONTEXTIDR 676 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 677 // MISCREG_CONTEXTIDR_NS 678 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 679 // MISCREG_CONTEXTIDR_S 680 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 681 // MISCREG_TPIDRURW 682 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 683 // MISCREG_TPIDRURW_NS 684 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")), 685 // MISCREG_TPIDRURW_S 686 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 687 // MISCREG_TPIDRURO 688 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 689 // MISCREG_TPIDRURO_NS 690 bitset<NUM_MISCREG_INFOS>(string("11001100110101100001")), 691 // MISCREG_TPIDRURO_S 692 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 693 // MISCREG_TPIDRPRW 694 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 695 // MISCREG_TPIDRPRW_NS 696 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")), 697 // MISCREG_TPIDRPRW_S 698 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 699 // MISCREG_HTPIDR 700 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 701 // MISCREG_CNTFRQ 702 bitset<NUM_MISCREG_INFOS>(string("11110101010101000011")), 703 // MISCREG_CNTKCTL 704 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 705 // MISCREG_CNTP_TVAL 706 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 707 // MISCREG_CNTP_TVAL_NS 708 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")), 709 // MISCREG_CNTP_TVAL_S 710 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")), 711 // MISCREG_CNTP_CTL 712 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 713 // MISCREG_CNTP_CTL_NS 714 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")), 715 // MISCREG_CNTP_CTL_S 716 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")), 717 // MISCREG_CNTV_TVAL 718 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 719 // MISCREG_CNTV_CTL 720 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 721 // MISCREG_CNTHCTL 722 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 723 // MISCREG_CNTHP_TVAL 724 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 725 // MISCREG_CNTHP_CTL 726 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 727 // MISCREG_IL1DATA0 728 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 729 // MISCREG_IL1DATA1 730 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 731 // MISCREG_IL1DATA2 732 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 733 // MISCREG_IL1DATA3 734 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 735 // MISCREG_DL1DATA0 736 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 737 // MISCREG_DL1DATA1 738 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 739 // MISCREG_DL1DATA2 740 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 741 // MISCREG_DL1DATA3 742 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 743 // MISCREG_DL1DATA4 744 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 745 // MISCREG_RAMINDEX 746 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 747 // MISCREG_L2ACTLR 748 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 749 // MISCREG_CBAR 750 bitset<NUM_MISCREG_INFOS>(string("01010101010000000000")), 751 // MISCREG_HTTBR 752 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 753 // MISCREG_VTTBR 754 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 755 // MISCREG_CNTPCT 756 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 757 // MISCREG_CNTVCT 758 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")), 759 // MISCREG_CNTP_CVAL 760 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 761 // MISCREG_CNTP_CVAL_NS 762 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")), 763 // MISCREG_CNTP_CVAL_S 764 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")), 765 // MISCREG_CNTV_CVAL 766 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 767 // MISCREG_CNTVOFF 768 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 769 // MISCREG_CNTHP_CVAL 770 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 771 // MISCREG_CPUMERRSR 772 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 773 // MISCREG_L2MERRSR 774 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), 775 776 // AArch64 registers (Op0=2) 777 // MISCREG_MDCCINT_EL1 778 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 779 // MISCREG_OSDTRRX_EL1 780 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 781 // MISCREG_MDSCR_EL1 782 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 783 // MISCREG_OSDTRTX_EL1 784 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 785 // MISCREG_OSECCR_EL1 786 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 787 // MISCREG_DBGBVR0_EL1 788 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 789 // MISCREG_DBGBVR1_EL1 790 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 791 // MISCREG_DBGBVR2_EL1 792 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 793 // MISCREG_DBGBVR3_EL1 794 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 795 // MISCREG_DBGBVR4_EL1 796 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 797 // MISCREG_DBGBVR5_EL1 798 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 799 // MISCREG_DBGBCR0_EL1 800 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 801 // MISCREG_DBGBCR1_EL1 802 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 803 // MISCREG_DBGBCR2_EL1 804 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 805 // MISCREG_DBGBCR3_EL1 806 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 807 // MISCREG_DBGBCR4_EL1 808 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 809 // MISCREG_DBGBCR5_EL1 810 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 811 // MISCREG_DBGWVR0_EL1 812 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 813 // MISCREG_DBGWVR1_EL1 814 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 815 // MISCREG_DBGWVR2_EL1 816 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 817 // MISCREG_DBGWVR3_EL1 818 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 819 // MISCREG_DBGWCR0_EL1 820 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 821 // MISCREG_DBGWCR1_EL1 822 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 823 // MISCREG_DBGWCR2_EL1 824 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 825 // MISCREG_DBGWCR3_EL1 826 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 827 // MISCREG_MDCCSR_EL0 828 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 829 // MISCREG_MDDTR_EL0 830 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 831 // MISCREG_MDDTRTX_EL0 832 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 833 // MISCREG_MDDTRRX_EL0 834 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 835 // MISCREG_DBGVCR32_EL2 836 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 837 // MISCREG_MDRAR_EL1 838 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 839 // MISCREG_OSLAR_EL1 840 bitset<NUM_MISCREG_INFOS>(string("10101111111111000001")), 841 // MISCREG_OSLSR_EL1 842 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 843 // MISCREG_OSDLR_EL1 844 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 845 // MISCREG_DBGPRCR_EL1 846 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 847 // MISCREG_DBGCLAIMSET_EL1 848 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 849 // MISCREG_DBGCLAIMCLR_EL1 850 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 851 // MISCREG_DBGAUTHSTATUS_EL1 852 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 853 // MISCREG_TEECR32_EL1 854 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")), 855 // MISCREG_TEEHBR32_EL1 856 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")), 857 858 // AArch64 registers (Op0=1,3) 859 // MISCREG_MIDR_EL1 860 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 861 // MISCREG_MPIDR_EL1 862 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 863 // MISCREG_REVIDR_EL1 864 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 865 // MISCREG_ID_PFR0_EL1 866 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 867 // MISCREG_ID_PFR1_EL1 868 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 869 // MISCREG_ID_DFR0_EL1 870 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 871 // MISCREG_ID_AFR0_EL1 872 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 873 // MISCREG_ID_MMFR0_EL1 874 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 875 // MISCREG_ID_MMFR1_EL1 876 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 877 // MISCREG_ID_MMFR2_EL1 878 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 879 // MISCREG_ID_MMFR3_EL1 880 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 881 // MISCREG_ID_ISAR0_EL1 882 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 883 // MISCREG_ID_ISAR1_EL1 884 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 885 // MISCREG_ID_ISAR2_EL1 886 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 887 // MISCREG_ID_ISAR3_EL1 888 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 889 // MISCREG_ID_ISAR4_EL1 890 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 891 // MISCREG_ID_ISAR5_EL1 892 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 893 // MISCREG_MVFR0_EL1 894 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 895 // MISCREG_MVFR1_EL1 896 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 897 // MISCREG_MVFR2_EL1 898 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 899 // MISCREG_ID_AA64PFR0_EL1 900 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 901 // MISCREG_ID_AA64PFR1_EL1 902 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 903 // MISCREG_ID_AA64DFR0_EL1 904 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 905 // MISCREG_ID_AA64DFR1_EL1 906 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 907 // MISCREG_ID_AA64AFR0_EL1 908 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 909 // MISCREG_ID_AA64AFR1_EL1 910 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 911 // MISCREG_ID_AA64ISAR0_EL1 912 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 913 // MISCREG_ID_AA64ISAR1_EL1 914 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 915 // MISCREG_ID_AA64MMFR0_EL1 916 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 917 // MISCREG_ID_AA64MMFR1_EL1 918 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 919 // MISCREG_CCSIDR_EL1 920 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 921 // MISCREG_CLIDR_EL1 922 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 923 // MISCREG_AIDR_EL1 924 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 925 // MISCREG_CSSELR_EL1 926 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 927 // MISCREG_CTR_EL0 928 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 929 // MISCREG_DCZID_EL0 930 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 931 // MISCREG_VPIDR_EL2 932 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 933 // MISCREG_VMPIDR_EL2 934 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 935 // MISCREG_SCTLR_EL1 936 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 937 // MISCREG_ACTLR_EL1 938 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 939 // MISCREG_CPACR_EL1 940 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 941 // MISCREG_SCTLR_EL2 942 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 943 // MISCREG_ACTLR_EL2 944 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 945 // MISCREG_HCR_EL2 946 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 947 // MISCREG_MDCR_EL2 948 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 949 // MISCREG_CPTR_EL2 950 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 951 // MISCREG_HSTR_EL2 952 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 953 // MISCREG_HACR_EL2 954 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 955 // MISCREG_SCTLR_EL3 956 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 957 // MISCREG_ACTLR_EL3 958 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 959 // MISCREG_SCR_EL3 960 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 961 // MISCREG_SDER32_EL3 962 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 963 // MISCREG_CPTR_EL3 964 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 965 // MISCREG_MDCR_EL3 966 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 967 // MISCREG_TTBR0_EL1 968 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 969 // MISCREG_TTBR1_EL1 970 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 971 // MISCREG_TCR_EL1 972 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 973 // MISCREG_TTBR0_EL2 974 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 975 // MISCREG_TCR_EL2 976 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 977 // MISCREG_VTTBR_EL2 978 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 979 // MISCREG_VTCR_EL2 980 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 981 // MISCREG_TTBR0_EL3 982 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 983 // MISCREG_TCR_EL3 984 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 985 // MISCREG_DACR32_EL2 986 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 987 // MISCREG_SPSR_EL1 988 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 989 // MISCREG_ELR_EL1 990 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 991 // MISCREG_SP_EL0 992 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 993 // MISCREG_SPSEL 994 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 995 // MISCREG_CURRENTEL 996 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 997 // MISCREG_NZCV 998 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 999 // MISCREG_DAIF 1000 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1001 // MISCREG_FPCR 1002 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1003 // MISCREG_FPSR 1004 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1005 // MISCREG_DSPSR_EL0 1006 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1007 // MISCREG_DLR_EL0 1008 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1009 // MISCREG_SPSR_EL2 1010 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1011 // MISCREG_ELR_EL2 1012 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1013 // MISCREG_SP_EL1 1014 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1015 // MISCREG_SPSR_IRQ_AA64 1016 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1017 // MISCREG_SPSR_ABT_AA64 1018 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1019 // MISCREG_SPSR_UND_AA64 1020 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1021 // MISCREG_SPSR_FIQ_AA64 1022 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1023 // MISCREG_SPSR_EL3 1024 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1025 // MISCREG_ELR_EL3 1026 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1027 // MISCREG_SP_EL2 1028 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1029 // MISCREG_AFSR0_EL1 1030 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1031 // MISCREG_AFSR1_EL1 1032 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1033 // MISCREG_ESR_EL1 1034 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1035 // MISCREG_IFSR32_EL2 1036 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1037 // MISCREG_AFSR0_EL2 1038 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1039 // MISCREG_AFSR1_EL2 1040 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1041 // MISCREG_ESR_EL2 1042 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1043 // MISCREG_FPEXC32_EL2 1044 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1045 // MISCREG_AFSR0_EL3 1046 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1047 // MISCREG_AFSR1_EL3 1048 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1049 // MISCREG_ESR_EL3 1050 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1051 // MISCREG_FAR_EL1 1052 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1053 // MISCREG_FAR_EL2 1054 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1055 // MISCREG_HPFAR_EL2 1056 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1057 // MISCREG_FAR_EL3 1058 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1059 // MISCREG_IC_IALLUIS 1060 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1061 // MISCREG_PAR_EL1 1062 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1063 // MISCREG_IC_IALLU 1064 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1065 // MISCREG_DC_IVAC_Xt 1066 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1067 // MISCREG_DC_ISW_Xt 1068 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1069 // MISCREG_AT_S1E1R_Xt 1070 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1071 // MISCREG_AT_S1E1W_Xt 1072 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1073 // MISCREG_AT_S1E0R_Xt 1074 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1075 // MISCREG_AT_S1E0W_Xt 1076 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1077 // MISCREG_DC_CSW_Xt 1078 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1079 // MISCREG_DC_CISW_Xt 1080 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1081 // MISCREG_DC_ZVA_Xt 1082 bitset<NUM_MISCREG_INFOS>(string("10101010100010000101")), 1083 // MISCREG_IC_IVAU_Xt 1084 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 1085 // MISCREG_DC_CVAC_Xt 1086 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1087 // MISCREG_DC_CVAU_Xt 1088 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1089 // MISCREG_DC_CIVAC_Xt 1090 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1091 // MISCREG_AT_S1E2R_Xt 1092 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1093 // MISCREG_AT_S1E2W_Xt 1094 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1095 // MISCREG_AT_S12E1R_Xt 1096 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1097 // MISCREG_AT_S12E1W_Xt 1098 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1099 // MISCREG_AT_S12E0R_Xt 1100 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1101 // MISCREG_AT_S12E0W_Xt 1102 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1103 // MISCREG_AT_S1E3R_Xt 1104 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1105 // MISCREG_AT_S1E3W_Xt 1106 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1107 // MISCREG_TLBI_VMALLE1IS 1108 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1109 // MISCREG_TLBI_VAE1IS_Xt 1110 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1111 // MISCREG_TLBI_ASIDE1IS_Xt 1112 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1113 // MISCREG_TLBI_VAAE1IS_Xt 1114 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1115 // MISCREG_TLBI_VALE1IS_Xt 1116 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1117 // MISCREG_TLBI_VAALE1IS_Xt 1118 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1119 // MISCREG_TLBI_VMALLE1 1120 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1121 // MISCREG_TLBI_VAE1_Xt 1122 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1123 // MISCREG_TLBI_ASIDE1_Xt 1124 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1125 // MISCREG_TLBI_VAAE1_Xt 1126 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1127 // MISCREG_TLBI_VALE1_Xt 1128 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1129 // MISCREG_TLBI_VAALE1_Xt 1130 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1131 // MISCREG_TLBI_IPAS2E1IS_Xt 1132 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1133 // MISCREG_TLBI_IPAS2LE1IS_Xt 1134 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1135 // MISCREG_TLBI_ALLE2IS 1136 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1137 // MISCREG_TLBI_VAE2IS_Xt 1138 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1139 // MISCREG_TLBI_ALLE1IS 1140 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1141 // MISCREG_TLBI_VALE2IS_Xt 1142 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1143 // MISCREG_TLBI_VMALLS12E1IS 1144 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1145 // MISCREG_TLBI_IPAS2E1_Xt 1146 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1147 // MISCREG_TLBI_IPAS2LE1_Xt 1148 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1149 // MISCREG_TLBI_ALLE2 1150 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1151 // MISCREG_TLBI_VAE2_Xt 1152 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1153 // MISCREG_TLBI_ALLE1 1154 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1155 // MISCREG_TLBI_VALE2_Xt 1156 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1157 // MISCREG_TLBI_VMALLS12E1 1158 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1159 // MISCREG_TLBI_ALLE3IS 1160 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1161 // MISCREG_TLBI_VAE3IS_Xt 1162 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1163 // MISCREG_TLBI_VALE3IS_Xt 1164 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1165 // MISCREG_TLBI_ALLE3 1166 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1167 // MISCREG_TLBI_VAE3_Xt 1168 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1169 // MISCREG_TLBI_VALE3_Xt 1170 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1171 // MISCREG_PMINTENSET_EL1 1172 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1173 // MISCREG_PMINTENCLR_EL1 1174 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1175 // MISCREG_PMCR_EL0 1176 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1177 // MISCREG_PMCNTENSET_EL0 1178 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1179 // MISCREG_PMCNTENCLR_EL0 1180 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1181 // MISCREG_PMOVSCLR_EL0 1182 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1183 // MISCREG_PMSWINC_EL0 1184 bitset<NUM_MISCREG_INFOS>(string("10101010101111000001")), 1185 // MISCREG_PMSELR_EL0 1186 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1187 // MISCREG_PMCEID0_EL0 1188 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")), 1189 // MISCREG_PMCEID1_EL0 1190 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")), 1191 // MISCREG_PMCCNTR_EL0 1192 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1193 // MISCREG_PMXEVTYPER_EL0 1194 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1195 // MISCREG_PMCCFILTR_EL0 1196 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1197 // MISCREG_PMXEVCNTR_EL0 1198 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1199 // MISCREG_PMUSERENR_EL0 1200 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")), 1201 // MISCREG_PMOVSSET_EL0 1202 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1203 // MISCREG_MAIR_EL1 1204 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1205 // MISCREG_AMAIR_EL1 1206 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1207 // MISCREG_MAIR_EL2 1208 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1209 // MISCREG_AMAIR_EL2 1210 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1211 // MISCREG_MAIR_EL3 1212 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1213 // MISCREG_AMAIR_EL3 1214 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1215 // MISCREG_L2CTLR_EL1 1216 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1217 // MISCREG_L2ECTLR_EL1 1218 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1219 // MISCREG_VBAR_EL1 1220 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1221 // MISCREG_RVBAR_EL1 1222 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1223 // MISCREG_ISR_EL1 1224 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1225 // MISCREG_VBAR_EL2 1226 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1227 // MISCREG_RVBAR_EL2 1228 bitset<NUM_MISCREG_INFOS>(string("01010100000000000001")), 1229 // MISCREG_VBAR_EL3 1230 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1231 // MISCREG_RVBAR_EL3 1232 bitset<NUM_MISCREG_INFOS>(string("01010000000000000001")), 1233 // MISCREG_RMR_EL3 1234 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1235 // MISCREG_CONTEXTIDR_EL1 1236 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1237 // MISCREG_TPIDR_EL1 1238 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1239 // MISCREG_TPIDR_EL0 1240 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1241 // MISCREG_TPIDRRO_EL0 1242 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")), 1243 // MISCREG_TPIDR_EL2 1244 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1245 // MISCREG_TPIDR_EL3 1246 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1247 // MISCREG_CNTKCTL_EL1 1248 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1249 // MISCREG_CNTFRQ_EL0 1250 bitset<NUM_MISCREG_INFOS>(string("11110101010101000001")), 1251 // MISCREG_CNTPCT_EL0 1252 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 1253 // MISCREG_CNTVCT_EL0 1254 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")), 1255 // MISCREG_CNTP_TVAL_EL0 1256 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1257 // MISCREG_CNTP_CTL_EL0 1258 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1259 // MISCREG_CNTP_CVAL_EL0 1260 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1261 // MISCREG_CNTV_TVAL_EL0 1262 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1263 // MISCREG_CNTV_CTL_EL0 1264 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1265 // MISCREG_CNTV_CVAL_EL0 1266 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1267 // MISCREG_PMEVCNTR0_EL0 1268 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1269 // MISCREG_PMEVCNTR1_EL0 1270 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1271 // MISCREG_PMEVCNTR2_EL0 1272 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1273 // MISCREG_PMEVCNTR3_EL0 1274 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1275 // MISCREG_PMEVCNTR4_EL0 1276 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1277 // MISCREG_PMEVCNTR5_EL0 1278 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1279 // MISCREG_PMEVTYPER0_EL0 1280 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1281 // MISCREG_PMEVTYPER1_EL0 1282 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1283 // MISCREG_PMEVTYPER2_EL0 1284 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1285 // MISCREG_PMEVTYPER3_EL0 1286 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1287 // MISCREG_PMEVTYPER4_EL0 1288 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1289 // MISCREG_PMEVTYPER5_EL0 1290 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1291 // MISCREG_CNTVOFF_EL2 1292 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1293 // MISCREG_CNTHCTL_EL2 1294 bitset<NUM_MISCREG_INFOS>(string("01111000000000000100")), 1295 // MISCREG_CNTHP_TVAL_EL2 1296 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1297 // MISCREG_CNTHP_CTL_EL2 1298 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1299 // MISCREG_CNTHP_CVAL_EL2 1300 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1301 // MISCREG_CNTPS_TVAL_EL1 1302 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1303 // MISCREG_CNTPS_CTL_EL1 1304 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1305 // MISCREG_CNTPS_CVAL_EL1 1306 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1307 // MISCREG_IL1DATA0_EL1 1308 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1309 // MISCREG_IL1DATA1_EL1 1310 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1311 // MISCREG_IL1DATA2_EL1 1312 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1313 // MISCREG_IL1DATA3_EL1 1314 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1315 // MISCREG_DL1DATA0_EL1 1316 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1317 // MISCREG_DL1DATA1_EL1 1318 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1319 // MISCREG_DL1DATA2_EL1 1320 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1321 // MISCREG_DL1DATA3_EL1 1322 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1323 // MISCREG_DL1DATA4_EL1 1324 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1325 // MISCREG_L2ACTLR_EL1 1326 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1327 // MISCREG_CPUACTLR_EL1 1328 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1329 // MISCREG_CPUECTLR_EL1 1330 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1331 // MISCREG_CPUMERRSR_EL1 1332 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1333 // MISCREG_L2MERRSR_EL1 1334 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), 1335 // MISCREG_CBAR_EL1 1336 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1337 // MISCREG_CONTEXTIDR_EL2 1338 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1339 1340 // Dummy registers 1341 // MISCREG_NOP 1342 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1343 // MISCREG_RAZ 1344 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1345 // MISCREG_CP14_UNIMPL 1346 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")), 1347 // MISCREG_CP15_UNIMPL 1348 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")), 1349 // MISCREG_A64_UNIMPL 1350 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")), 1351 // MISCREG_UNKNOWN 1352 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")) 1353}; 1354 1355MiscRegIndex 1356decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 1357{ 1358 switch (crn) { 1359 case 0: 1360 switch (opc1) { 1361 case 0: 1362 switch (crm) { 1363 case 0: 1364 switch (opc2) { 1365 case 1: 1366 return MISCREG_CTR; 1367 case 2: 1368 return MISCREG_TCMTR; 1369 case 3: 1370 return MISCREG_TLBTR; 1371 case 5: 1372 return MISCREG_MPIDR; 1373 case 6: 1374 return MISCREG_REVIDR; 1375 default: 1376 return MISCREG_MIDR; 1377 } 1378 break; 1379 case 1: 1380 switch (opc2) { 1381 case 0: 1382 return MISCREG_ID_PFR0; 1383 case 1: 1384 return MISCREG_ID_PFR1; 1385 case 2: 1386 return MISCREG_ID_DFR0; 1387 case 3: 1388 return MISCREG_ID_AFR0; 1389 case 4: 1390 return MISCREG_ID_MMFR0; 1391 case 5: 1392 return MISCREG_ID_MMFR1; 1393 case 6: 1394 return MISCREG_ID_MMFR2; 1395 case 7: 1396 return MISCREG_ID_MMFR3; 1397 } 1398 break; 1399 case 2: 1400 switch (opc2) { 1401 case 0: 1402 return MISCREG_ID_ISAR0; 1403 case 1: 1404 return MISCREG_ID_ISAR1; 1405 case 2: 1406 return MISCREG_ID_ISAR2; 1407 case 3: 1408 return MISCREG_ID_ISAR3; 1409 case 4: 1410 return MISCREG_ID_ISAR4; 1411 case 5: 1412 return MISCREG_ID_ISAR5; 1413 case 6: 1414 case 7: 1415 return MISCREG_RAZ; // read as zero 1416 } 1417 break; 1418 default: 1419 return MISCREG_RAZ; // read as zero 1420 } 1421 break; 1422 case 1: 1423 if (crm == 0) { 1424 switch (opc2) { 1425 case 0: 1426 return MISCREG_CCSIDR; 1427 case 1: 1428 return MISCREG_CLIDR; 1429 case 7: 1430 return MISCREG_AIDR; 1431 } 1432 } 1433 break; 1434 case 2: 1435 if (crm == 0 && opc2 == 0) { 1436 return MISCREG_CSSELR; 1437 } 1438 break; 1439 case 4: 1440 if (crm == 0) { 1441 if (opc2 == 0) 1442 return MISCREG_VPIDR; 1443 else if (opc2 == 5) 1444 return MISCREG_VMPIDR; 1445 } 1446 break; 1447 } 1448 break; 1449 case 1: 1450 if (opc1 == 0) { 1451 if (crm == 0) { 1452 switch (opc2) { 1453 case 0: 1454 return MISCREG_SCTLR; 1455 case 1: 1456 return MISCREG_ACTLR; 1457 case 0x2: 1458 return MISCREG_CPACR; 1459 } 1460 } else if (crm == 1) { 1461 switch (opc2) { 1462 case 0: 1463 return MISCREG_SCR; 1464 case 1: 1465 return MISCREG_SDER; 1466 case 2: 1467 return MISCREG_NSACR; 1468 } 1469 } 1470 } else if (opc1 == 4) { 1471 if (crm == 0) { 1472 if (opc2 == 0) 1473 return MISCREG_HSCTLR; 1474 else if (opc2 == 1) 1475 return MISCREG_HACTLR; 1476 } else if (crm == 1) { 1477 switch (opc2) { 1478 case 0: 1479 return MISCREG_HCR; 1480 case 1: 1481 return MISCREG_HDCR; 1482 case 2: 1483 return MISCREG_HCPTR; 1484 case 3: 1485 return MISCREG_HSTR; 1486 case 7: 1487 return MISCREG_HACR; 1488 } 1489 } 1490 } 1491 break; 1492 case 2: 1493 if (opc1 == 0 && crm == 0) { 1494 switch (opc2) { 1495 case 0: 1496 return MISCREG_TTBR0; 1497 case 1: 1498 return MISCREG_TTBR1; 1499 case 2: 1500 return MISCREG_TTBCR; 1501 } 1502 } else if (opc1 == 4) { 1503 if (crm == 0 && opc2 == 2) 1504 return MISCREG_HTCR; 1505 else if (crm == 1 && opc2 == 2) 1506 return MISCREG_VTCR; 1507 } 1508 break; 1509 case 3: 1510 if (opc1 == 0 && crm == 0 && opc2 == 0) { 1511 return MISCREG_DACR; 1512 } 1513 break; 1514 case 5: 1515 if (opc1 == 0) { 1516 if (crm == 0) { 1517 if (opc2 == 0) { 1518 return MISCREG_DFSR; 1519 } else if (opc2 == 1) { 1520 return MISCREG_IFSR; 1521 } 1522 } else if (crm == 1) { 1523 if (opc2 == 0) { 1524 return MISCREG_ADFSR; 1525 } else if (opc2 == 1) { 1526 return MISCREG_AIFSR; 1527 } 1528 } 1529 } else if (opc1 == 4) { 1530 if (crm == 1) { 1531 if (opc2 == 0) 1532 return MISCREG_HADFSR; 1533 else if (opc2 == 1) 1534 return MISCREG_HAIFSR; 1535 } else if (crm == 2 && opc2 == 0) { 1536 return MISCREG_HSR; 1537 } 1538 } 1539 break; 1540 case 6: 1541 if (opc1 == 0 && crm == 0) { 1542 switch (opc2) { 1543 case 0: 1544 return MISCREG_DFAR; 1545 case 2: 1546 return MISCREG_IFAR; 1547 } 1548 } else if (opc1 == 4 && crm == 0) { 1549 switch (opc2) { 1550 case 0: 1551 return MISCREG_HDFAR; 1552 case 2: 1553 return MISCREG_HIFAR; 1554 case 4: 1555 return MISCREG_HPFAR; 1556 } 1557 } 1558 break; 1559 case 7: 1560 if (opc1 == 0) { 1561 switch (crm) { 1562 case 0: 1563 if (opc2 == 4) { 1564 return MISCREG_NOP; 1565 } 1566 break; 1567 case 1: 1568 switch (opc2) { 1569 case 0: 1570 return MISCREG_ICIALLUIS; 1571 case 6: 1572 return MISCREG_BPIALLIS; 1573 } 1574 break; 1575 case 4: 1576 if (opc2 == 0) { 1577 return MISCREG_PAR; 1578 } 1579 break; 1580 case 5: 1581 switch (opc2) { 1582 case 0: 1583 return MISCREG_ICIALLU; 1584 case 1: 1585 return MISCREG_ICIMVAU; 1586 case 4: 1587 return MISCREG_CP15ISB; 1588 case 6: 1589 return MISCREG_BPIALL; 1590 case 7: 1591 return MISCREG_BPIMVA; 1592 } 1593 break; 1594 case 6: 1595 if (opc2 == 1) { 1596 return MISCREG_DCIMVAC; 1597 } else if (opc2 == 2) { 1598 return MISCREG_DCISW; 1599 } 1600 break; 1601 case 8: 1602 switch (opc2) { 1603 case 0: 1604 return MISCREG_ATS1CPR; 1605 case 1: 1606 return MISCREG_ATS1CPW; 1607 case 2: 1608 return MISCREG_ATS1CUR; 1609 case 3: 1610 return MISCREG_ATS1CUW; 1611 case 4: 1612 return MISCREG_ATS12NSOPR; 1613 case 5: 1614 return MISCREG_ATS12NSOPW; 1615 case 6: 1616 return MISCREG_ATS12NSOUR; 1617 case 7: 1618 return MISCREG_ATS12NSOUW; 1619 } 1620 break; 1621 case 10: 1622 switch (opc2) { 1623 case 1: 1624 return MISCREG_DCCMVAC; 1625 case 2: 1626 return MISCREG_DCCSW; 1627 case 4: 1628 return MISCREG_CP15DSB; 1629 case 5: 1630 return MISCREG_CP15DMB; 1631 } 1632 break; 1633 case 11: 1634 if (opc2 == 1) { 1635 return MISCREG_DCCMVAU; 1636 } 1637 break; 1638 case 13: 1639 if (opc2 == 1) { 1640 return MISCREG_NOP; 1641 } 1642 break; 1643 case 14: 1644 if (opc2 == 1) { 1645 return MISCREG_DCCIMVAC; 1646 } else if (opc2 == 2) { 1647 return MISCREG_DCCISW; 1648 } 1649 break; 1650 } 1651 } else if (opc1 == 4 && crm == 8) { 1652 if (opc2 == 0) 1653 return MISCREG_ATS1HR; 1654 else if (opc2 == 1) 1655 return MISCREG_ATS1HW; 1656 } 1657 break; 1658 case 8: 1659 if (opc1 == 0) { 1660 switch (crm) { 1661 case 3: 1662 switch (opc2) { 1663 case 0: 1664 return MISCREG_TLBIALLIS; 1665 case 1: 1666 return MISCREG_TLBIMVAIS; 1667 case 2: 1668 return MISCREG_TLBIASIDIS; 1669 case 3: 1670 return MISCREG_TLBIMVAAIS; 1671 } 1672 break; 1673 case 5: 1674 switch (opc2) { 1675 case 0: 1676 return MISCREG_ITLBIALL; 1677 case 1: 1678 return MISCREG_ITLBIMVA; 1679 case 2: 1680 return MISCREG_ITLBIASID; 1681 } 1682 break; 1683 case 6: 1684 switch (opc2) { 1685 case 0: 1686 return MISCREG_DTLBIALL; 1687 case 1: 1688 return MISCREG_DTLBIMVA; 1689 case 2: 1690 return MISCREG_DTLBIASID; 1691 } 1692 break; 1693 case 7: 1694 switch (opc2) { 1695 case 0: 1696 return MISCREG_TLBIALL; 1697 case 1: 1698 return MISCREG_TLBIMVA; 1699 case 2: 1700 return MISCREG_TLBIASID; 1701 case 3: 1702 return MISCREG_TLBIMVAA; 1703 } 1704 break; 1705 } 1706 } else if (opc1 == 4) { 1707 if (crm == 3) { 1708 switch (opc2) { 1709 case 0: 1710 return MISCREG_TLBIALLHIS; 1711 case 1: 1712 return MISCREG_TLBIMVAHIS; 1713 case 4: 1714 return MISCREG_TLBIALLNSNHIS; 1715 } 1716 } else if (crm == 7) { 1717 switch (opc2) { 1718 case 0: 1719 return MISCREG_TLBIALLH; 1720 case 1: 1721 return MISCREG_TLBIMVAH; 1722 case 4: 1723 return MISCREG_TLBIALLNSNH; 1724 } 1725 } 1726 } 1727 break; 1728 case 9: 1729 if (opc1 == 0) { 1730 switch (crm) { 1731 case 12: 1732 switch (opc2) { 1733 case 0: 1734 return MISCREG_PMCR; 1735 case 1: 1736 return MISCREG_PMCNTENSET; 1737 case 2: 1738 return MISCREG_PMCNTENCLR; 1739 case 3: 1740 return MISCREG_PMOVSR; 1741 case 4: 1742 return MISCREG_PMSWINC; 1743 case 5: 1744 return MISCREG_PMSELR; 1745 case 6: 1746 return MISCREG_PMCEID0; 1747 case 7: 1748 return MISCREG_PMCEID1; 1749 } 1750 break; 1751 case 13: 1752 switch (opc2) { 1753 case 0: 1754 return MISCREG_PMCCNTR; 1755 case 1: 1756 // Selector is PMSELR.SEL 1757 return MISCREG_PMXEVTYPER_PMCCFILTR; 1758 case 2: 1759 return MISCREG_PMXEVCNTR; 1760 } 1761 break; 1762 case 14: 1763 switch (opc2) { 1764 case 0: 1765 return MISCREG_PMUSERENR; 1766 case 1: 1767 return MISCREG_PMINTENSET; 1768 case 2: 1769 return MISCREG_PMINTENCLR; 1770 case 3: 1771 return MISCREG_PMOVSSET; 1772 } 1773 break; 1774 } 1775 } else if (opc1 == 1) { 1776 switch (crm) { 1777 case 0: 1778 switch (opc2) { 1779 case 2: // L2CTLR, L2 Control Register 1780 return MISCREG_L2CTLR; 1781 case 3: 1782 return MISCREG_L2ECTLR; 1783 } 1784 break; 1785 break; 1786 } 1787 } 1788 break; 1789 case 10: 1790 if (opc1 == 0) { 1791 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 1792 if (crm == 2) { // TEX Remap Registers 1793 if (opc2 == 0) { 1794 // Selector is TTBCR.EAE 1795 return MISCREG_PRRR_MAIR0; 1796 } else if (opc2 == 1) { 1797 // Selector is TTBCR.EAE 1798 return MISCREG_NMRR_MAIR1; 1799 } 1800 } else if (crm == 3) { 1801 if (opc2 == 0) { 1802 return MISCREG_AMAIR0; 1803 } else if (opc2 == 1) { 1804 return MISCREG_AMAIR1; 1805 } 1806 } 1807 } else if (opc1 == 4) { 1808 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 1809 if (crm == 2) { 1810 if (opc2 == 0) 1811 return MISCREG_HMAIR0; 1812 else if (opc2 == 1) 1813 return MISCREG_HMAIR1; 1814 } else if (crm == 3) { 1815 if (opc2 == 0) 1816 return MISCREG_HAMAIR0; 1817 else if (opc2 == 1) 1818 return MISCREG_HAMAIR1; 1819 } 1820 } 1821 break; 1822 case 11: 1823 if (opc1 <=7) { 1824 switch (crm) { 1825 case 0: 1826 case 1: 1827 case 2: 1828 case 3: 1829 case 4: 1830 case 5: 1831 case 6: 1832 case 7: 1833 case 8: 1834 case 15: 1835 // Reserved for DMA operations for TCM access 1836 break; 1837 } 1838 } 1839 break; 1840 case 12: 1841 if (opc1 == 0) { 1842 if (crm == 0) { 1843 if (opc2 == 0) { 1844 return MISCREG_VBAR; 1845 } else if (opc2 == 1) { 1846 return MISCREG_MVBAR; 1847 } 1848 } else if (crm == 1) { 1849 if (opc2 == 0) { 1850 return MISCREG_ISR; 1851 } 1852 } 1853 } else if (opc1 == 4) { 1854 if (crm == 0 && opc2 == 0) 1855 return MISCREG_HVBAR; 1856 } 1857 break; 1858 case 13: 1859 if (opc1 == 0) { 1860 if (crm == 0) { 1861 switch (opc2) { 1862 case 0: 1863 return MISCREG_FCSEIDR; 1864 case 1: 1865 return MISCREG_CONTEXTIDR; 1866 case 2: 1867 return MISCREG_TPIDRURW; 1868 case 3: 1869 return MISCREG_TPIDRURO; 1870 case 4: 1871 return MISCREG_TPIDRPRW; 1872 } 1873 } 1874 } else if (opc1 == 4) { 1875 if (crm == 0 && opc2 == 2) 1876 return MISCREG_HTPIDR; 1877 } 1878 break; 1879 case 14: 1880 if (opc1 == 0) { 1881 switch (crm) { 1882 case 0: 1883 if (opc2 == 0) 1884 return MISCREG_CNTFRQ; 1885 break; 1886 case 1: 1887 if (opc2 == 0) 1888 return MISCREG_CNTKCTL; 1889 break; 1890 case 2: 1891 if (opc2 == 0) 1892 return MISCREG_CNTP_TVAL; 1893 else if (opc2 == 1) 1894 return MISCREG_CNTP_CTL; 1895 break; 1896 case 3: 1897 if (opc2 == 0) 1898 return MISCREG_CNTV_TVAL; 1899 else if (opc2 == 1) 1900 return MISCREG_CNTV_CTL; 1901 break; 1902 } 1903 } else if (opc1 == 4) { 1904 if (crm == 1 && opc2 == 0) { 1905 return MISCREG_CNTHCTL; 1906 } else if (crm == 2) { 1907 if (opc2 == 0) 1908 return MISCREG_CNTHP_TVAL; 1909 else if (opc2 == 1) 1910 return MISCREG_CNTHP_CTL; 1911 } 1912 } 1913 break; 1914 case 15: 1915 // Implementation defined 1916 return MISCREG_CP15_UNIMPL; 1917 } 1918 // Unrecognized register 1919 return MISCREG_CP15_UNIMPL; 1920} 1921 1922MiscRegIndex 1923decodeCP15Reg64(unsigned crm, unsigned opc1) 1924{ 1925 switch (crm) { 1926 case 2: 1927 switch (opc1) { 1928 case 0: 1929 return MISCREG_TTBR0; 1930 case 1: 1931 return MISCREG_TTBR1; 1932 case 4: 1933 return MISCREG_HTTBR; 1934 case 6: 1935 return MISCREG_VTTBR; 1936 } 1937 break; 1938 case 7: 1939 if (opc1 == 0) 1940 return MISCREG_PAR; 1941 break; 1942 case 14: 1943 switch (opc1) { 1944 case 0: 1945 return MISCREG_CNTPCT; 1946 case 1: 1947 return MISCREG_CNTVCT; 1948 case 2: 1949 return MISCREG_CNTP_CVAL; 1950 case 3: 1951 return MISCREG_CNTV_CVAL; 1952 case 4: 1953 return MISCREG_CNTVOFF; 1954 case 6: 1955 return MISCREG_CNTHP_CVAL; 1956 } 1957 break; 1958 case 15: 1959 if (opc1 == 0) 1960 return MISCREG_CPUMERRSR; 1961 else if (opc1 == 1) 1962 return MISCREG_L2MERRSR; 1963 break; 1964 } 1965 // Unrecognized register 1966 return MISCREG_CP15_UNIMPL; 1967} 1968 1969bool 1970canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 1971{ 1972 bool secure = !scr.ns; 1973 bool canRead; 1974 1975 switch (cpsr.mode) { 1976 case MODE_USER: 1977 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 1978 miscRegInfo[reg][MISCREG_USR_NS_RD]; 1979 break; 1980 case MODE_FIQ: 1981 case MODE_IRQ: 1982 case MODE_SVC: 1983 case MODE_ABORT: 1984 case MODE_UNDEFINED: 1985 case MODE_SYSTEM: 1986 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 1987 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 1988 break; 1989 case MODE_MON: 1990 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 1991 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 1992 break; 1993 case MODE_HYP: 1994 canRead = miscRegInfo[reg][MISCREG_HYP_RD]; 1995 break; 1996 default: 1997 panic("Unrecognized mode setting in CPSR.\n"); 1998 } 1999 // can't do permissions checkes on the root of a banked pair of regs 2000 assert(!miscRegInfo[reg][MISCREG_BANKED]); 2001 return canRead; 2002} 2003 2004bool 2005canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 2006{ 2007 bool secure = !scr.ns; 2008 bool canWrite; 2009 2010 switch (cpsr.mode) { 2011 case MODE_USER: 2012 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 2013 miscRegInfo[reg][MISCREG_USR_NS_WR]; 2014 break; 2015 case MODE_FIQ: 2016 case MODE_IRQ: 2017 case MODE_SVC: 2018 case MODE_ABORT: 2019 case MODE_UNDEFINED: 2020 case MODE_SYSTEM: 2021 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 2022 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 2023 break; 2024 case MODE_MON: 2025 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 2026 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 2027 break; 2028 case MODE_HYP: 2029 canWrite = miscRegInfo[reg][MISCREG_HYP_WR]; 2030 break; 2031 default: 2032 panic("Unrecognized mode setting in CPSR.\n"); 2033 } 2034 // can't do permissions checkes on the root of a banked pair of regs 2035 assert(!miscRegInfo[reg][MISCREG_BANKED]); 2036 return canWrite; 2037} 2038 2039int 2040flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc) 2041{ 2042 SCR scr = tc->readMiscReg(MISCREG_SCR); 2043 return flattenMiscRegNsBanked(reg, tc, scr.ns); 2044} 2045 2046int 2047flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns) 2048{ 2049 int reg_as_int = static_cast<int>(reg); 2050 if (miscRegInfo[reg][MISCREG_BANKED]) { 2051 reg_as_int += (ArmSystem::haveSecurity(tc) && 2052 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1; 2053 } 2054 return reg_as_int; 2055} 2056 2057 2058/** 2059 * If the reg is a child reg of a banked set, then the parent is the last 2060 * banked one in the list. This is messy, and the wish is to eventually have 2061 * the bitmap replaced with a better data structure. the preUnflatten function 2062 * initializes a lookup table to speed up the search for these banked 2063 * registers. 2064 */ 2065 2066int unflattenResultMiscReg[NUM_MISCREGS]; 2067 2068void 2069preUnflattenMiscReg() 2070{ 2071 int reg = -1; 2072 for (int i = 0 ; i < NUM_MISCREGS; i++){ 2073 if (miscRegInfo[i][MISCREG_BANKED]) 2074 reg = i; 2075 if (miscRegInfo[i][MISCREG_BANKED_CHILD]) 2076 unflattenResultMiscReg[i] = reg; 2077 else 2078 unflattenResultMiscReg[i] = i; 2079 // if this assert fails, no parent was found, and something is broken 2080 assert(unflattenResultMiscReg[i] > -1); 2081 } 2082} 2083 2084int 2085unflattenMiscReg(int reg) 2086{ 2087 return unflattenResultMiscReg[reg]; 2088} 2089 2090bool 2091canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 2092{ 2093 // Check for SP_EL0 access while SPSEL == 0 2094 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 2095 return false; 2096 2097 // Check for RVBAR access 2098 if (reg == MISCREG_RVBAR_EL1) { 2099 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 2100 if (highest_el == EL2 || highest_el == EL3) 2101 return false; 2102 } 2103 if (reg == MISCREG_RVBAR_EL2) { 2104 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 2105 if (highest_el == EL3) 2106 return false; 2107 } 2108 2109 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 2110 2111 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) { 2112 case EL0: 2113 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 2114 miscRegInfo[reg][MISCREG_USR_NS_RD]; 2115 case EL1: 2116 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 2117 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 2118 case EL2: 2119 return miscRegInfo[reg][MISCREG_HYP_RD]; 2120 case EL3: 2121 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 2122 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 2123 default: 2124 panic("Invalid exception level"); 2125 } 2126} 2127 2128bool 2129canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 2130{ 2131 // Check for SP_EL0 access while SPSEL == 0 2132 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 2133 return false; 2134 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode); 2135 if (reg == MISCREG_DAIF) { 2136 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 2137 if (el == EL0 && !sctlr.uma) 2138 return false; 2139 } 2140 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) { 2141 // In syscall-emulation mode, this test is skipped and DCZVA is always 2142 // allowed at EL0 2143 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 2144 if (el == EL0 && !sctlr.dze) 2145 return false; 2146 } 2147 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) { 2148 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 2149 if (el == EL0 && !sctlr.uci) 2150 return false; 2151 } 2152 2153 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 2154 2155 switch (el) { 2156 case EL0: 2157 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 2158 miscRegInfo[reg][MISCREG_USR_NS_WR]; 2159 case EL1: 2160 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 2161 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 2162 case EL2: 2163 return miscRegInfo[reg][MISCREG_HYP_WR]; 2164 case EL3: 2165 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 2166 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 2167 default: 2168 panic("Invalid exception level"); 2169 } 2170} 2171 2172MiscRegIndex 2173decodeAArch64SysReg(unsigned op0, unsigned op1, 2174 unsigned crn, unsigned crm, 2175 unsigned op2) 2176{ 2177 switch (op0) { 2178 case 1: 2179 switch (crn) { 2180 case 7: 2181 switch (op1) { 2182 case 0: 2183 switch (crm) { 2184 case 1: 2185 switch (op2) { 2186 case 0: 2187 return MISCREG_IC_IALLUIS; 2188 } 2189 break; 2190 case 5: 2191 switch (op2) { 2192 case 0: 2193 return MISCREG_IC_IALLU; 2194 } 2195 break; 2196 case 6: 2197 switch (op2) { 2198 case 1: 2199 return MISCREG_DC_IVAC_Xt; 2200 case 2: 2201 return MISCREG_DC_ISW_Xt; 2202 } 2203 break; 2204 case 8: 2205 switch (op2) { 2206 case 0: 2207 return MISCREG_AT_S1E1R_Xt; 2208 case 1: 2209 return MISCREG_AT_S1E1W_Xt; 2210 case 2: 2211 return MISCREG_AT_S1E0R_Xt; 2212 case 3: 2213 return MISCREG_AT_S1E0W_Xt; 2214 } 2215 break; 2216 case 10: 2217 switch (op2) { 2218 case 2: 2219 return MISCREG_DC_CSW_Xt; 2220 } 2221 break; 2222 case 14: 2223 switch (op2) { 2224 case 2: 2225 return MISCREG_DC_CISW_Xt; 2226 } 2227 break; 2228 } 2229 break; 2230 case 3: 2231 switch (crm) { 2232 case 4: 2233 switch (op2) { 2234 case 1: 2235 return MISCREG_DC_ZVA_Xt; 2236 } 2237 break; 2238 case 5: 2239 switch (op2) { 2240 case 1: 2241 return MISCREG_IC_IVAU_Xt; 2242 } 2243 break; 2244 case 10: 2245 switch (op2) { 2246 case 1: 2247 return MISCREG_DC_CVAC_Xt; 2248 } 2249 break; 2250 case 11: 2251 switch (op2) { 2252 case 1: 2253 return MISCREG_DC_CVAU_Xt; 2254 } 2255 break; 2256 case 14: 2257 switch (op2) { 2258 case 1: 2259 return MISCREG_DC_CIVAC_Xt; 2260 } 2261 break; 2262 } 2263 break; 2264 case 4: 2265 switch (crm) { 2266 case 8: 2267 switch (op2) { 2268 case 0: 2269 return MISCREG_AT_S1E2R_Xt; 2270 case 1: 2271 return MISCREG_AT_S1E2W_Xt; 2272 case 4: 2273 return MISCREG_AT_S12E1R_Xt; 2274 case 5: 2275 return MISCREG_AT_S12E1W_Xt; 2276 case 6: 2277 return MISCREG_AT_S12E0R_Xt; 2278 case 7: 2279 return MISCREG_AT_S12E0W_Xt; 2280 } 2281 break; 2282 } 2283 break; 2284 case 6: 2285 switch (crm) { 2286 case 8: 2287 switch (op2) { 2288 case 0: 2289 return MISCREG_AT_S1E3R_Xt; 2290 case 1: 2291 return MISCREG_AT_S1E3W_Xt; 2292 } 2293 break; 2294 } 2295 break; 2296 } 2297 break; 2298 case 8: 2299 switch (op1) { 2300 case 0: 2301 switch (crm) { 2302 case 3: 2303 switch (op2) { 2304 case 0: 2305 return MISCREG_TLBI_VMALLE1IS; 2306 case 1: 2307 return MISCREG_TLBI_VAE1IS_Xt; 2308 case 2: 2309 return MISCREG_TLBI_ASIDE1IS_Xt; 2310 case 3: 2311 return MISCREG_TLBI_VAAE1IS_Xt; 2312 case 5: 2313 return MISCREG_TLBI_VALE1IS_Xt; 2314 case 7: 2315 return MISCREG_TLBI_VAALE1IS_Xt; 2316 } 2317 break; 2318 case 7: 2319 switch (op2) { 2320 case 0: 2321 return MISCREG_TLBI_VMALLE1; 2322 case 1: 2323 return MISCREG_TLBI_VAE1_Xt; 2324 case 2: 2325 return MISCREG_TLBI_ASIDE1_Xt; 2326 case 3: 2327 return MISCREG_TLBI_VAAE1_Xt; 2328 case 5: 2329 return MISCREG_TLBI_VALE1_Xt; 2330 case 7: 2331 return MISCREG_TLBI_VAALE1_Xt; 2332 } 2333 break; 2334 } 2335 break; 2336 case 4: 2337 switch (crm) { 2338 case 0: 2339 switch (op2) { 2340 case 1: 2341 return MISCREG_TLBI_IPAS2E1IS_Xt; 2342 case 5: 2343 return MISCREG_TLBI_IPAS2LE1IS_Xt; 2344 } 2345 break; 2346 case 3: 2347 switch (op2) { 2348 case 0: 2349 return MISCREG_TLBI_ALLE2IS; 2350 case 1: 2351 return MISCREG_TLBI_VAE2IS_Xt; 2352 case 4: 2353 return MISCREG_TLBI_ALLE1IS; 2354 case 5: 2355 return MISCREG_TLBI_VALE2IS_Xt; 2356 case 6: 2357 return MISCREG_TLBI_VMALLS12E1IS; 2358 } 2359 break; 2360 case 4: 2361 switch (op2) { 2362 case 1: 2363 return MISCREG_TLBI_IPAS2E1_Xt; 2364 case 5: 2365 return MISCREG_TLBI_IPAS2LE1_Xt; 2366 } 2367 break; 2368 case 7: 2369 switch (op2) { 2370 case 0: 2371 return MISCREG_TLBI_ALLE2; 2372 case 1: 2373 return MISCREG_TLBI_VAE2_Xt; 2374 case 4: 2375 return MISCREG_TLBI_ALLE1; 2376 case 5: 2377 return MISCREG_TLBI_VALE2_Xt; 2378 case 6: 2379 return MISCREG_TLBI_VMALLS12E1; 2380 } 2381 break; 2382 } 2383 break; 2384 case 6: 2385 switch (crm) { 2386 case 3: 2387 switch (op2) { 2388 case 0: 2389 return MISCREG_TLBI_ALLE3IS; 2390 case 1: 2391 return MISCREG_TLBI_VAE3IS_Xt; 2392 case 5: 2393 return MISCREG_TLBI_VALE3IS_Xt; 2394 } 2395 break; 2396 case 7: 2397 switch (op2) { 2398 case 0: 2399 return MISCREG_TLBI_ALLE3; 2400 case 1: 2401 return MISCREG_TLBI_VAE3_Xt; 2402 case 5: 2403 return MISCREG_TLBI_VALE3_Xt; 2404 } 2405 break; 2406 } 2407 break; 2408 } 2409 break; 2410 } 2411 break; 2412 case 2: 2413 switch (crn) { 2414 case 0: 2415 switch (op1) { 2416 case 0: 2417 switch (crm) { 2418 case 0: 2419 switch (op2) { 2420 case 2: 2421 return MISCREG_OSDTRRX_EL1; 2422 case 4: 2423 return MISCREG_DBGBVR0_EL1; 2424 case 5: 2425 return MISCREG_DBGBCR0_EL1; 2426 case 6: 2427 return MISCREG_DBGWVR0_EL1; 2428 case 7: 2429 return MISCREG_DBGWCR0_EL1; 2430 } 2431 break; 2432 case 1: 2433 switch (op2) { 2434 case 4: 2435 return MISCREG_DBGBVR1_EL1; 2436 case 5: 2437 return MISCREG_DBGBCR1_EL1; 2438 case 6: 2439 return MISCREG_DBGWVR1_EL1; 2440 case 7: 2441 return MISCREG_DBGWCR1_EL1; 2442 } 2443 break; 2444 case 2: 2445 switch (op2) { 2446 case 0: 2447 return MISCREG_MDCCINT_EL1; 2448 case 2: 2449 return MISCREG_MDSCR_EL1; 2450 case 4: 2451 return MISCREG_DBGBVR2_EL1; 2452 case 5: 2453 return MISCREG_DBGBCR2_EL1; 2454 case 6: 2455 return MISCREG_DBGWVR2_EL1; 2456 case 7: 2457 return MISCREG_DBGWCR2_EL1; 2458 } 2459 break; 2460 case 3: 2461 switch (op2) { 2462 case 2: 2463 return MISCREG_OSDTRTX_EL1; 2464 case 4: 2465 return MISCREG_DBGBVR3_EL1; 2466 case 5: 2467 return MISCREG_DBGBCR3_EL1; 2468 case 6: 2469 return MISCREG_DBGWVR3_EL1; 2470 case 7: 2471 return MISCREG_DBGWCR3_EL1; 2472 } 2473 break; 2474 case 4: 2475 switch (op2) { 2476 case 4: 2477 return MISCREG_DBGBVR4_EL1; 2478 case 5: 2479 return MISCREG_DBGBCR4_EL1; 2480 } 2481 break; 2482 case 5: 2483 switch (op2) { 2484 case 4: 2485 return MISCREG_DBGBVR5_EL1; 2486 case 5: 2487 return MISCREG_DBGBCR5_EL1; 2488 } 2489 break; 2490 case 6: 2491 switch (op2) { 2492 case 2: 2493 return MISCREG_OSECCR_EL1; 2494 } 2495 break; 2496 } 2497 break; 2498 case 2: 2499 switch (crm) { 2500 case 0: 2501 switch (op2) { 2502 case 0: 2503 return MISCREG_TEECR32_EL1; 2504 } 2505 break; 2506 } 2507 break; 2508 case 3: 2509 switch (crm) { 2510 case 1: 2511 switch (op2) { 2512 case 0: 2513 return MISCREG_MDCCSR_EL0; 2514 } 2515 break; 2516 case 4: 2517 switch (op2) { 2518 case 0: 2519 return MISCREG_MDDTR_EL0; 2520 } 2521 break; 2522 case 5: 2523 switch (op2) { 2524 case 0: 2525 return MISCREG_MDDTRRX_EL0; 2526 } 2527 break; 2528 } 2529 break; 2530 case 4: 2531 switch (crm) { 2532 case 7: 2533 switch (op2) { 2534 case 0: 2535 return MISCREG_DBGVCR32_EL2; 2536 } 2537 break; 2538 } 2539 break; 2540 } 2541 break; 2542 case 1: 2543 switch (op1) { 2544 case 0: 2545 switch (crm) { 2546 case 0: 2547 switch (op2) { 2548 case 0: 2549 return MISCREG_MDRAR_EL1; 2550 case 4: 2551 return MISCREG_OSLAR_EL1; 2552 } 2553 break; 2554 case 1: 2555 switch (op2) { 2556 case 4: 2557 return MISCREG_OSLSR_EL1; 2558 } 2559 break; 2560 case 3: 2561 switch (op2) { 2562 case 4: 2563 return MISCREG_OSDLR_EL1; 2564 } 2565 break; 2566 case 4: 2567 switch (op2) { 2568 case 4: 2569 return MISCREG_DBGPRCR_EL1; 2570 } 2571 break; 2572 } 2573 break; 2574 case 2: 2575 switch (crm) { 2576 case 0: 2577 switch (op2) { 2578 case 0: 2579 return MISCREG_TEEHBR32_EL1; 2580 } 2581 break; 2582 } 2583 break; 2584 } 2585 break; 2586 case 7: 2587 switch (op1) { 2588 case 0: 2589 switch (crm) { 2590 case 8: 2591 switch (op2) { 2592 case 6: 2593 return MISCREG_DBGCLAIMSET_EL1; 2594 } 2595 break; 2596 case 9: 2597 switch (op2) { 2598 case 6: 2599 return MISCREG_DBGCLAIMCLR_EL1; 2600 } 2601 break; 2602 case 14: 2603 switch (op2) { 2604 case 6: 2605 return MISCREG_DBGAUTHSTATUS_EL1; 2606 } 2607 break; 2608 } 2609 break; 2610 } 2611 break; 2612 } 2613 break; 2614 case 3: 2615 switch (crn) { 2616 case 0: 2617 switch (op1) { 2618 case 0: 2619 switch (crm) { 2620 case 0: 2621 switch (op2) { 2622 case 0: 2623 return MISCREG_MIDR_EL1; 2624 case 5: 2625 return MISCREG_MPIDR_EL1; 2626 case 6: 2627 return MISCREG_REVIDR_EL1; 2628 } 2629 break; 2630 case 1: 2631 switch (op2) { 2632 case 0: 2633 return MISCREG_ID_PFR0_EL1; 2634 case 1: 2635 return MISCREG_ID_PFR1_EL1; 2636 case 2: 2637 return MISCREG_ID_DFR0_EL1; 2638 case 3: 2639 return MISCREG_ID_AFR0_EL1; 2640 case 4: 2641 return MISCREG_ID_MMFR0_EL1; 2642 case 5: 2643 return MISCREG_ID_MMFR1_EL1; 2644 case 6: 2645 return MISCREG_ID_MMFR2_EL1; 2646 case 7: 2647 return MISCREG_ID_MMFR3_EL1; 2648 } 2649 break; 2650 case 2: 2651 switch (op2) { 2652 case 0: 2653 return MISCREG_ID_ISAR0_EL1; 2654 case 1: 2655 return MISCREG_ID_ISAR1_EL1; 2656 case 2: 2657 return MISCREG_ID_ISAR2_EL1; 2658 case 3: 2659 return MISCREG_ID_ISAR3_EL1; 2660 case 4: 2661 return MISCREG_ID_ISAR4_EL1; 2662 case 5: 2663 return MISCREG_ID_ISAR5_EL1; 2664 } 2665 break; 2666 case 3: 2667 switch (op2) { 2668 case 0: 2669 return MISCREG_MVFR0_EL1; 2670 case 1: 2671 return MISCREG_MVFR1_EL1; 2672 case 2: 2673 return MISCREG_MVFR2_EL1; 2674 case 3 ... 7: 2675 return MISCREG_RAZ; 2676 } 2677 break; 2678 case 4: 2679 switch (op2) { 2680 case 0: 2681 return MISCREG_ID_AA64PFR0_EL1; 2682 case 1: 2683 return MISCREG_ID_AA64PFR1_EL1; 2684 case 2 ... 7: 2685 return MISCREG_RAZ; 2686 } 2687 break; 2688 case 5: 2689 switch (op2) { 2690 case 0: 2691 return MISCREG_ID_AA64DFR0_EL1; 2692 case 1: 2693 return MISCREG_ID_AA64DFR1_EL1; 2694 case 4: 2695 return MISCREG_ID_AA64AFR0_EL1; 2696 case 5: 2697 return MISCREG_ID_AA64AFR1_EL1; 2698 case 2: 2699 case 3: 2700 case 6: 2701 case 7: 2702 return MISCREG_RAZ; 2703 } 2704 break; 2705 case 6: 2706 switch (op2) { 2707 case 0: 2708 return MISCREG_ID_AA64ISAR0_EL1; 2709 case 1: 2710 return MISCREG_ID_AA64ISAR1_EL1; 2711 case 2 ... 7: 2712 return MISCREG_RAZ; 2713 } 2714 break; 2715 case 7: 2716 switch (op2) { 2717 case 0: 2718 return MISCREG_ID_AA64MMFR0_EL1; 2719 case 1: 2720 return MISCREG_ID_AA64MMFR1_EL1; 2721 case 2 ... 7: 2722 return MISCREG_RAZ; 2723 } 2724 break; 2725 } 2726 break; 2727 case 1: 2728 switch (crm) { 2729 case 0: 2730 switch (op2) { 2731 case 0: 2732 return MISCREG_CCSIDR_EL1; 2733 case 1: 2734 return MISCREG_CLIDR_EL1; 2735 case 7: 2736 return MISCREG_AIDR_EL1; 2737 } 2738 break; 2739 } 2740 break; 2741 case 2: 2742 switch (crm) { 2743 case 0: 2744 switch (op2) { 2745 case 0: 2746 return MISCREG_CSSELR_EL1; 2747 } 2748 break; 2749 } 2750 break; 2751 case 3: 2752 switch (crm) { 2753 case 0: 2754 switch (op2) { 2755 case 1: 2756 return MISCREG_CTR_EL0; 2757 case 7: 2758 return MISCREG_DCZID_EL0; 2759 } 2760 break; 2761 } 2762 break; 2763 case 4: 2764 switch (crm) { 2765 case 0: 2766 switch (op2) { 2767 case 0: 2768 return MISCREG_VPIDR_EL2; 2769 case 5: 2770 return MISCREG_VMPIDR_EL2; 2771 } 2772 break; 2773 } 2774 break; 2775 } 2776 break; 2777 case 1: 2778 switch (op1) { 2779 case 0: 2780 switch (crm) { 2781 case 0: 2782 switch (op2) { 2783 case 0: 2784 return MISCREG_SCTLR_EL1; 2785 case 1: 2786 return MISCREG_ACTLR_EL1; 2787 case 2: 2788 return MISCREG_CPACR_EL1; 2789 } 2790 break; 2791 } 2792 break; 2793 case 4: 2794 switch (crm) { 2795 case 0: 2796 switch (op2) { 2797 case 0: 2798 return MISCREG_SCTLR_EL2; 2799 case 1: 2800 return MISCREG_ACTLR_EL2; 2801 } 2802 break; 2803 case 1: 2804 switch (op2) { 2805 case 0: 2806 return MISCREG_HCR_EL2; 2807 case 1: 2808 return MISCREG_MDCR_EL2; 2809 case 2: 2810 return MISCREG_CPTR_EL2; 2811 case 3: 2812 return MISCREG_HSTR_EL2; 2813 case 7: 2814 return MISCREG_HACR_EL2; 2815 } 2816 break; 2817 } 2818 break; 2819 case 6: 2820 switch (crm) { 2821 case 0: 2822 switch (op2) { 2823 case 0: 2824 return MISCREG_SCTLR_EL3; 2825 case 1: 2826 return MISCREG_ACTLR_EL3; 2827 } 2828 break; 2829 case 1: 2830 switch (op2) { 2831 case 0: 2832 return MISCREG_SCR_EL3; 2833 case 1: 2834 return MISCREG_SDER32_EL3; 2835 case 2: 2836 return MISCREG_CPTR_EL3; 2837 } 2838 break; 2839 case 3: 2840 switch (op2) { 2841 case 1: 2842 return MISCREG_MDCR_EL3; 2843 } 2844 break; 2845 } 2846 break; 2847 } 2848 break; 2849 case 2: 2850 switch (op1) { 2851 case 0: 2852 switch (crm) { 2853 case 0: 2854 switch (op2) { 2855 case 0: 2856 return MISCREG_TTBR0_EL1; 2857 case 1: 2858 return MISCREG_TTBR1_EL1; 2859 case 2: 2860 return MISCREG_TCR_EL1; 2861 } 2862 break; 2863 } 2864 break; 2865 case 4: 2866 switch (crm) { 2867 case 0: 2868 switch (op2) { 2869 case 0: 2870 return MISCREG_TTBR0_EL2; 2871 case 2: 2872 return MISCREG_TCR_EL2; 2873 } 2874 break; 2875 case 1: 2876 switch (op2) { 2877 case 0: 2878 return MISCREG_VTTBR_EL2; 2879 case 2: 2880 return MISCREG_VTCR_EL2; 2881 } 2882 break; 2883 } 2884 break; 2885 case 6: 2886 switch (crm) { 2887 case 0: 2888 switch (op2) { 2889 case 0: 2890 return MISCREG_TTBR0_EL3; 2891 case 2: 2892 return MISCREG_TCR_EL3; 2893 } 2894 break; 2895 } 2896 break; 2897 } 2898 break; 2899 case 3: 2900 switch (op1) { 2901 case 4: 2902 switch (crm) { 2903 case 0: 2904 switch (op2) { 2905 case 0: 2906 return MISCREG_DACR32_EL2; 2907 } 2908 break; 2909 } 2910 break; 2911 } 2912 break; 2913 case 4: 2914 switch (op1) { 2915 case 0: 2916 switch (crm) { 2917 case 0: 2918 switch (op2) { 2919 case 0: 2920 return MISCREG_SPSR_EL1; 2921 case 1: 2922 return MISCREG_ELR_EL1; 2923 } 2924 break; 2925 case 1: 2926 switch (op2) { 2927 case 0: 2928 return MISCREG_SP_EL0; 2929 } 2930 break; 2931 case 2: 2932 switch (op2) { 2933 case 0: 2934 return MISCREG_SPSEL; 2935 case 2: 2936 return MISCREG_CURRENTEL; 2937 } 2938 break; 2939 } 2940 break; 2941 case 3: 2942 switch (crm) { 2943 case 2: 2944 switch (op2) { 2945 case 0: 2946 return MISCREG_NZCV; 2947 case 1: 2948 return MISCREG_DAIF; 2949 } 2950 break; 2951 case 4: 2952 switch (op2) { 2953 case 0: 2954 return MISCREG_FPCR; 2955 case 1: 2956 return MISCREG_FPSR; 2957 } 2958 break; 2959 case 5: 2960 switch (op2) { 2961 case 0: 2962 return MISCREG_DSPSR_EL0; 2963 case 1: 2964 return MISCREG_DLR_EL0; 2965 } 2966 break; 2967 } 2968 break; 2969 case 4: 2970 switch (crm) { 2971 case 0: 2972 switch (op2) { 2973 case 0: 2974 return MISCREG_SPSR_EL2; 2975 case 1: 2976 return MISCREG_ELR_EL2; 2977 } 2978 break; 2979 case 1: 2980 switch (op2) { 2981 case 0: 2982 return MISCREG_SP_EL1; 2983 } 2984 break; 2985 case 3: 2986 switch (op2) { 2987 case 0: 2988 return MISCREG_SPSR_IRQ_AA64; 2989 case 1: 2990 return MISCREG_SPSR_ABT_AA64; 2991 case 2: 2992 return MISCREG_SPSR_UND_AA64; 2993 case 3: 2994 return MISCREG_SPSR_FIQ_AA64; 2995 } 2996 break; 2997 } 2998 break; 2999 case 6: 3000 switch (crm) { 3001 case 0: 3002 switch (op2) { 3003 case 0: 3004 return MISCREG_SPSR_EL3; 3005 case 1: 3006 return MISCREG_ELR_EL3; 3007 } 3008 break; 3009 case 1: 3010 switch (op2) { 3011 case 0: 3012 return MISCREG_SP_EL2; 3013 } 3014 break; 3015 } 3016 break; 3017 } 3018 break; 3019 case 5: 3020 switch (op1) { 3021 case 0: 3022 switch (crm) { 3023 case 1: 3024 switch (op2) { 3025 case 0: 3026 return MISCREG_AFSR0_EL1; 3027 case 1: 3028 return MISCREG_AFSR1_EL1; 3029 } 3030 break; 3031 case 2: 3032 switch (op2) { 3033 case 0: 3034 return MISCREG_ESR_EL1; 3035 } 3036 break; 3037 } 3038 break; 3039 case 4: 3040 switch (crm) { 3041 case 0: 3042 switch (op2) { 3043 case 1: 3044 return MISCREG_IFSR32_EL2; 3045 } 3046 break; 3047 case 1: 3048 switch (op2) { 3049 case 0: 3050 return MISCREG_AFSR0_EL2; 3051 case 1: 3052 return MISCREG_AFSR1_EL2; 3053 } 3054 break; 3055 case 2: 3056 switch (op2) { 3057 case 0: 3058 return MISCREG_ESR_EL2; 3059 } 3060 break; 3061 case 3: 3062 switch (op2) { 3063 case 0: 3064 return MISCREG_FPEXC32_EL2; 3065 } 3066 break; 3067 } 3068 break; 3069 case 6: 3070 switch (crm) { 3071 case 1: 3072 switch (op2) { 3073 case 0: 3074 return MISCREG_AFSR0_EL3; 3075 case 1: 3076 return MISCREG_AFSR1_EL3; 3077 } 3078 break; 3079 case 2: 3080 switch (op2) { 3081 case 0: 3082 return MISCREG_ESR_EL3; 3083 } 3084 break; 3085 } 3086 break; 3087 } 3088 break; 3089 case 6: 3090 switch (op1) { 3091 case 0: 3092 switch (crm) { 3093 case 0: 3094 switch (op2) { 3095 case 0: 3096 return MISCREG_FAR_EL1; 3097 } 3098 break; 3099 } 3100 break; 3101 case 4: 3102 switch (crm) { 3103 case 0: 3104 switch (op2) { 3105 case 0: 3106 return MISCREG_FAR_EL2; 3107 case 4: 3108 return MISCREG_HPFAR_EL2; 3109 } 3110 break; 3111 } 3112 break; 3113 case 6: 3114 switch (crm) { 3115 case 0: 3116 switch (op2) { 3117 case 0: 3118 return MISCREG_FAR_EL3; 3119 } 3120 break; 3121 } 3122 break; 3123 } 3124 break; 3125 case 7: 3126 switch (op1) { 3127 case 0: 3128 switch (crm) { 3129 case 4: 3130 switch (op2) { 3131 case 0: 3132 return MISCREG_PAR_EL1; 3133 } 3134 break; 3135 } 3136 break; 3137 } 3138 break; 3139 case 9: 3140 switch (op1) { 3141 case 0: 3142 switch (crm) { 3143 case 14: 3144 switch (op2) { 3145 case 1: 3146 return MISCREG_PMINTENSET_EL1; 3147 case 2: 3148 return MISCREG_PMINTENCLR_EL1; 3149 } 3150 break; 3151 } 3152 break; 3153 case 3: 3154 switch (crm) { 3155 case 12: 3156 switch (op2) { 3157 case 0: 3158 return MISCREG_PMCR_EL0; 3159 case 1: 3160 return MISCREG_PMCNTENSET_EL0; 3161 case 2: 3162 return MISCREG_PMCNTENCLR_EL0; 3163 case 3: 3164 return MISCREG_PMOVSCLR_EL0; 3165 case 4: 3166 return MISCREG_PMSWINC_EL0; 3167 case 5: 3168 return MISCREG_PMSELR_EL0; 3169 case 6: 3170 return MISCREG_PMCEID0_EL0; 3171 case 7: 3172 return MISCREG_PMCEID1_EL0; 3173 } 3174 break; 3175 case 13: 3176 switch (op2) { 3177 case 0: 3178 return MISCREG_PMCCNTR_EL0; 3179 case 1: 3180 return MISCREG_PMXEVTYPER_EL0; 3181 case 2: 3182 return MISCREG_PMXEVCNTR_EL0; 3183 } 3184 break; 3185 case 14: 3186 switch (op2) { 3187 case 0: 3188 return MISCREG_PMUSERENR_EL0; 3189 case 3: 3190 return MISCREG_PMOVSSET_EL0; 3191 } 3192 break; 3193 } 3194 break; 3195 } 3196 break; 3197 case 10: 3198 switch (op1) { 3199 case 0: 3200 switch (crm) { 3201 case 2: 3202 switch (op2) { 3203 case 0: 3204 return MISCREG_MAIR_EL1; 3205 } 3206 break; 3207 case 3: 3208 switch (op2) { 3209 case 0: 3210 return MISCREG_AMAIR_EL1; 3211 } 3212 break; 3213 } 3214 break; 3215 case 4: 3216 switch (crm) { 3217 case 2: 3218 switch (op2) { 3219 case 0: 3220 return MISCREG_MAIR_EL2; 3221 } 3222 break; 3223 case 3: 3224 switch (op2) { 3225 case 0: 3226 return MISCREG_AMAIR_EL2; 3227 } 3228 break; 3229 } 3230 break; 3231 case 6: 3232 switch (crm) { 3233 case 2: 3234 switch (op2) { 3235 case 0: 3236 return MISCREG_MAIR_EL3; 3237 } 3238 break; 3239 case 3: 3240 switch (op2) { 3241 case 0: 3242 return MISCREG_AMAIR_EL3; 3243 } 3244 break; 3245 } 3246 break; 3247 } 3248 break; 3249 case 11: 3250 switch (op1) { 3251 case 1: 3252 switch (crm) { 3253 case 0: 3254 switch (op2) { 3255 case 2: 3256 return MISCREG_L2CTLR_EL1; 3257 case 3: 3258 return MISCREG_L2ECTLR_EL1; 3259 } 3260 break; 3261 } 3262 break; 3263 } 3264 break; 3265 case 12: 3266 switch (op1) { 3267 case 0: 3268 switch (crm) { 3269 case 0: 3270 switch (op2) { 3271 case 0: 3272 return MISCREG_VBAR_EL1; 3273 case 1: 3274 return MISCREG_RVBAR_EL1; 3275 } 3276 break; 3277 case 1: 3278 switch (op2) { 3279 case 0: 3280 return MISCREG_ISR_EL1; 3281 } 3282 break; 3283 } 3284 break; 3285 case 4: 3286 switch (crm) { 3287 case 0: 3288 switch (op2) { 3289 case 0: 3290 return MISCREG_VBAR_EL2; 3291 case 1: 3292 return MISCREG_RVBAR_EL2; 3293 } 3294 break; 3295 } 3296 break; 3297 case 6: 3298 switch (crm) { 3299 case 0: 3300 switch (op2) { 3301 case 0: 3302 return MISCREG_VBAR_EL3; 3303 case 1: 3304 return MISCREG_RVBAR_EL3; 3305 case 2: 3306 return MISCREG_RMR_EL3; 3307 } 3308 break; 3309 } 3310 break; 3311 } 3312 break; 3313 case 13: 3314 switch (op1) { 3315 case 0: 3316 switch (crm) { 3317 case 0: 3318 switch (op2) { 3319 case 1: 3320 return MISCREG_CONTEXTIDR_EL1; 3321 case 4: 3322 return MISCREG_TPIDR_EL1; 3323 } 3324 break; 3325 } 3326 break; 3327 case 3: 3328 switch (crm) { 3329 case 0: 3330 switch (op2) { 3331 case 2: 3332 return MISCREG_TPIDR_EL0; 3333 case 3: 3334 return MISCREG_TPIDRRO_EL0; 3335 } 3336 break; 3337 } 3338 break; 3339 case 4: 3340 switch (crm) { 3341 case 0: 3342 switch (op2) { 3343 case 1: 3344 return MISCREG_CONTEXTIDR_EL2; 3345 case 2: 3346 return MISCREG_TPIDR_EL2; 3347 } 3348 break; 3349 } 3350 break; 3351 case 6: 3352 switch (crm) { 3353 case 0: 3354 switch (op2) { 3355 case 2: 3356 return MISCREG_TPIDR_EL3; 3357 } 3358 break; 3359 } 3360 break; 3361 } 3362 break; 3363 case 14: 3364 switch (op1) { 3365 case 0: 3366 switch (crm) { 3367 case 1: 3368 switch (op2) { 3369 case 0: 3370 return MISCREG_CNTKCTL_EL1; 3371 } 3372 break; 3373 } 3374 break; 3375 case 3: 3376 switch (crm) { 3377 case 0: 3378 switch (op2) { 3379 case 0: 3380 return MISCREG_CNTFRQ_EL0; 3381 case 1: 3382 return MISCREG_CNTPCT_EL0; 3383 case 2: 3384 return MISCREG_CNTVCT_EL0; 3385 } 3386 break; 3387 case 2: 3388 switch (op2) { 3389 case 0: 3390 return MISCREG_CNTP_TVAL_EL0; 3391 case 1: 3392 return MISCREG_CNTP_CTL_EL0; 3393 case 2: 3394 return MISCREG_CNTP_CVAL_EL0; 3395 } 3396 break; 3397 case 3: 3398 switch (op2) { 3399 case 0: 3400 return MISCREG_CNTV_TVAL_EL0; 3401 case 1: 3402 return MISCREG_CNTV_CTL_EL0; 3403 case 2: 3404 return MISCREG_CNTV_CVAL_EL0; 3405 } 3406 break; 3407 case 8: 3408 switch (op2) { 3409 case 0: 3410 return MISCREG_PMEVCNTR0_EL0; 3411 case 1: 3412 return MISCREG_PMEVCNTR1_EL0; 3413 case 2: 3414 return MISCREG_PMEVCNTR2_EL0; 3415 case 3: 3416 return MISCREG_PMEVCNTR3_EL0; 3417 case 4: 3418 return MISCREG_PMEVCNTR4_EL0; 3419 case 5: 3420 return MISCREG_PMEVCNTR5_EL0; 3421 } 3422 break; 3423 case 12: 3424 switch (op2) { 3425 case 0: 3426 return MISCREG_PMEVTYPER0_EL0; 3427 case 1: 3428 return MISCREG_PMEVTYPER1_EL0; 3429 case 2: 3430 return MISCREG_PMEVTYPER2_EL0; 3431 case 3: 3432 return MISCREG_PMEVTYPER3_EL0; 3433 case 4: 3434 return MISCREG_PMEVTYPER4_EL0; 3435 case 5: 3436 return MISCREG_PMEVTYPER5_EL0; 3437 } 3438 break; 3439 case 15: 3440 switch (op2) { 3441 case 7: 3442 return MISCREG_PMCCFILTR_EL0; 3443 } 3444 } 3445 break; 3446 case 4: 3447 switch (crm) { 3448 case 0: 3449 switch (op2) { 3450 case 3: 3451 return MISCREG_CNTVOFF_EL2; 3452 } 3453 break; 3454 case 1: 3455 switch (op2) { 3456 case 0: 3457 return MISCREG_CNTHCTL_EL2; 3458 } 3459 break; 3460 case 2: 3461 switch (op2) { 3462 case 0: 3463 return MISCREG_CNTHP_TVAL_EL2; 3464 case 1: 3465 return MISCREG_CNTHP_CTL_EL2; 3466 case 2: 3467 return MISCREG_CNTHP_CVAL_EL2; 3468 } 3469 break; 3470 } 3471 break; 3472 case 7: 3473 switch (crm) { 3474 case 2: 3475 switch (op2) { 3476 case 0: 3477 return MISCREG_CNTPS_TVAL_EL1; 3478 case 1: 3479 return MISCREG_CNTPS_CTL_EL1; 3480 case 2: 3481 return MISCREG_CNTPS_CVAL_EL1; 3482 } 3483 break; 3484 } 3485 break; 3486 } 3487 break; 3488 case 15: 3489 switch (op1) { 3490 case 0: 3491 switch (crm) { 3492 case 0: 3493 switch (op2) { 3494 case 0: 3495 return MISCREG_IL1DATA0_EL1; 3496 case 1: 3497 return MISCREG_IL1DATA1_EL1; 3498 case 2: 3499 return MISCREG_IL1DATA2_EL1; 3500 case 3: 3501 return MISCREG_IL1DATA3_EL1; 3502 } 3503 break; 3504 case 1: 3505 switch (op2) { 3506 case 0: 3507 return MISCREG_DL1DATA0_EL1; 3508 case 1: 3509 return MISCREG_DL1DATA1_EL1; 3510 case 2: 3511 return MISCREG_DL1DATA2_EL1; 3512 case 3: 3513 return MISCREG_DL1DATA3_EL1; 3514 case 4: 3515 return MISCREG_DL1DATA4_EL1; 3516 } 3517 break; 3518 } 3519 break; 3520 case 1: 3521 switch (crm) { 3522 case 0: 3523 switch (op2) { 3524 case 0: 3525 return MISCREG_L2ACTLR_EL1; 3526 } 3527 break; 3528 case 2: 3529 switch (op2) { 3530 case 0: 3531 return MISCREG_CPUACTLR_EL1; 3532 case 1: 3533 return MISCREG_CPUECTLR_EL1; 3534 case 2: 3535 return MISCREG_CPUMERRSR_EL1; 3536 case 3: 3537 return MISCREG_L2MERRSR_EL1; 3538 } 3539 break; 3540 case 3: 3541 switch (op2) { 3542 case 0: 3543 return MISCREG_CBAR_EL1; 3544 3545 } 3546 break; 3547 } 3548 break; 3549 } 3550 break; 3551 } 3552 break; 3553 } 3554 3555 return MISCREG_UNKNOWN; 3556} 3557 3558} // namespace ArmISA 3559