miscregs.cc revision 13116
17259Sgblack@eecs.umich.edu/* 212669Schuan.zhu@arm.com * Copyright (c) 2010-2013, 2015-2018 ARM Limited 37259Sgblack@eecs.umich.edu * All rights reserved 47259Sgblack@eecs.umich.edu * 57259Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67259Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77259Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87259Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97259Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107259Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117259Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127259Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137259Sgblack@eecs.umich.edu * 147259Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 157259Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 167259Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 177259Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 187259Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 197259Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 207259Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 217259Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 227259Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237259Sgblack@eecs.umich.edu * this software without specific prior written permission. 247259Sgblack@eecs.umich.edu * 257259Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267259Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277259Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287259Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297259Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307259Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317259Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327259Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337259Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347259Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357259Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367259Sgblack@eecs.umich.edu * 377259Sgblack@eecs.umich.edu * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 3910037SARM gem5 Developers * Giacomo Gabrielli 407259Sgblack@eecs.umich.edu */ 417259Sgblack@eecs.umich.edu 4211793Sbrandon.potter@amd.com#include "arch/arm/miscregs.hh" 4311793Sbrandon.potter@amd.com 4411939Snikos.nikoleris@arm.com#include <tuple> 4511939Snikos.nikoleris@arm.com 467405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4712334Sgabeblack@google.com#include "base/logging.hh" 4810037SARM gem5 Developers#include "cpu/thread_context.hh" 4910828SGiacomo.Gabrielli@arm.com#include "sim/full_system.hh" 507259Sgblack@eecs.umich.edu 517259Sgblack@eecs.umich.edunamespace ArmISA 527259Sgblack@eecs.umich.edu{ 537259Sgblack@eecs.umich.edu 547259Sgblack@eecs.umich.eduMiscRegIndex 558868SMatt.Horsnell@arm.comdecodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 568868SMatt.Horsnell@arm.com{ 578868SMatt.Horsnell@arm.com switch(crn) { 588868SMatt.Horsnell@arm.com case 0: 5910037SARM gem5 Developers switch (opc1) { 608868SMatt.Horsnell@arm.com case 0: 6110037SARM gem5 Developers switch (opc2) { 628868SMatt.Horsnell@arm.com case 0: 6310037SARM gem5 Developers switch (crm) { 6410037SARM gem5 Developers case 0: 6510037SARM gem5 Developers return MISCREG_DBGDIDR; 6610037SARM gem5 Developers case 1: 6710037SARM gem5 Developers return MISCREG_DBGDSCRint; 6810037SARM gem5 Developers } 6910037SARM gem5 Developers break; 708868SMatt.Horsnell@arm.com } 7110037SARM gem5 Developers break; 7210037SARM gem5 Developers case 7: 7310037SARM gem5 Developers switch (opc2) { 7410037SARM gem5 Developers case 0: 7510037SARM gem5 Developers switch (crm) { 7610037SARM gem5 Developers case 0: 7710037SARM gem5 Developers return MISCREG_JIDR; 7810037SARM gem5 Developers } 7910037SARM gem5 Developers break; 8010037SARM gem5 Developers } 8110037SARM gem5 Developers break; 829959Schander.sudanthi@arm.com } 8310037SARM gem5 Developers break; 849959Schander.sudanthi@arm.com case 1: 859959Schander.sudanthi@arm.com switch (opc1) { 869959Schander.sudanthi@arm.com case 6: 879959Schander.sudanthi@arm.com switch (crm) { 889959Schander.sudanthi@arm.com case 0: 899959Schander.sudanthi@arm.com switch (opc2) { 909959Schander.sudanthi@arm.com case 0: 919959Schander.sudanthi@arm.com return MISCREG_TEEHBR; 929959Schander.sudanthi@arm.com } 9310037SARM gem5 Developers break; 949959Schander.sudanthi@arm.com } 9510037SARM gem5 Developers break; 9610037SARM gem5 Developers case 7: 9710037SARM gem5 Developers switch (crm) { 9810037SARM gem5 Developers case 0: 9910037SARM gem5 Developers switch (opc2) { 10010037SARM gem5 Developers case 0: 10110037SARM gem5 Developers return MISCREG_JOSCR; 10210037SARM gem5 Developers } 10310037SARM gem5 Developers break; 10410037SARM gem5 Developers } 10510037SARM gem5 Developers break; 1068868SMatt.Horsnell@arm.com } 10710037SARM gem5 Developers break; 10810037SARM gem5 Developers case 2: 10910037SARM gem5 Developers switch (opc1) { 11010037SARM gem5 Developers case 7: 11110037SARM gem5 Developers switch (crm) { 11210037SARM gem5 Developers case 0: 11310037SARM gem5 Developers switch (opc2) { 11410037SARM gem5 Developers case 0: 11510037SARM gem5 Developers return MISCREG_JMCR; 11610037SARM gem5 Developers } 11710037SARM gem5 Developers break; 11810037SARM gem5 Developers } 11910037SARM gem5 Developers break; 12010037SARM gem5 Developers } 12110037SARM gem5 Developers break; 1228868SMatt.Horsnell@arm.com } 12310037SARM gem5 Developers // If we get here then it must be a register that we haven't implemented 12410037SARM gem5 Developers warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 12510037SARM gem5 Developers crn, opc1, crm, opc2); 12610037SARM gem5 Developers return MISCREG_CP14_UNIMPL; 12710037SARM gem5 Developers} 1288868SMatt.Horsnell@arm.com 12910037SARM gem5 Developersusing namespace std; 13010037SARM gem5 Developers 1318868SMatt.Horsnell@arm.comMiscRegIndex 1327259Sgblack@eecs.umich.edudecodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 1337259Sgblack@eecs.umich.edu{ 1347259Sgblack@eecs.umich.edu switch (crn) { 1357259Sgblack@eecs.umich.edu case 0: 1367259Sgblack@eecs.umich.edu switch (opc1) { 1377259Sgblack@eecs.umich.edu case 0: 1387259Sgblack@eecs.umich.edu switch (crm) { 1397259Sgblack@eecs.umich.edu case 0: 1407259Sgblack@eecs.umich.edu switch (opc2) { 1417259Sgblack@eecs.umich.edu case 1: 1427259Sgblack@eecs.umich.edu return MISCREG_CTR; 1437259Sgblack@eecs.umich.edu case 2: 1447259Sgblack@eecs.umich.edu return MISCREG_TCMTR; 1457351Sgblack@eecs.umich.edu case 3: 1467351Sgblack@eecs.umich.edu return MISCREG_TLBTR; 1477259Sgblack@eecs.umich.edu case 5: 1487259Sgblack@eecs.umich.edu return MISCREG_MPIDR; 14910037SARM gem5 Developers case 6: 15010037SARM gem5 Developers return MISCREG_REVIDR; 1517259Sgblack@eecs.umich.edu default: 1527259Sgblack@eecs.umich.edu return MISCREG_MIDR; 1537259Sgblack@eecs.umich.edu } 1547259Sgblack@eecs.umich.edu break; 1557259Sgblack@eecs.umich.edu case 1: 1567259Sgblack@eecs.umich.edu switch (opc2) { 1577259Sgblack@eecs.umich.edu case 0: 1587259Sgblack@eecs.umich.edu return MISCREG_ID_PFR0; 1597259Sgblack@eecs.umich.edu case 1: 1607259Sgblack@eecs.umich.edu return MISCREG_ID_PFR1; 1617259Sgblack@eecs.umich.edu case 2: 1627259Sgblack@eecs.umich.edu return MISCREG_ID_DFR0; 1637259Sgblack@eecs.umich.edu case 3: 1647259Sgblack@eecs.umich.edu return MISCREG_ID_AFR0; 1657259Sgblack@eecs.umich.edu case 4: 1667259Sgblack@eecs.umich.edu return MISCREG_ID_MMFR0; 1677259Sgblack@eecs.umich.edu case 5: 1687259Sgblack@eecs.umich.edu return MISCREG_ID_MMFR1; 1697259Sgblack@eecs.umich.edu case 6: 1707259Sgblack@eecs.umich.edu return MISCREG_ID_MMFR2; 1717259Sgblack@eecs.umich.edu case 7: 1727259Sgblack@eecs.umich.edu return MISCREG_ID_MMFR3; 1737259Sgblack@eecs.umich.edu } 1747259Sgblack@eecs.umich.edu break; 1757259Sgblack@eecs.umich.edu case 2: 1767259Sgblack@eecs.umich.edu switch (opc2) { 1777259Sgblack@eecs.umich.edu case 0: 1787259Sgblack@eecs.umich.edu return MISCREG_ID_ISAR0; 1797259Sgblack@eecs.umich.edu case 1: 1807259Sgblack@eecs.umich.edu return MISCREG_ID_ISAR1; 1817259Sgblack@eecs.umich.edu case 2: 1827259Sgblack@eecs.umich.edu return MISCREG_ID_ISAR2; 1837259Sgblack@eecs.umich.edu case 3: 1847259Sgblack@eecs.umich.edu return MISCREG_ID_ISAR3; 1857259Sgblack@eecs.umich.edu case 4: 1867259Sgblack@eecs.umich.edu return MISCREG_ID_ISAR4; 1877259Sgblack@eecs.umich.edu case 5: 1887259Sgblack@eecs.umich.edu return MISCREG_ID_ISAR5; 1897259Sgblack@eecs.umich.edu case 6: 1907259Sgblack@eecs.umich.edu case 7: 1917259Sgblack@eecs.umich.edu return MISCREG_RAZ; // read as zero 1927259Sgblack@eecs.umich.edu } 1937259Sgblack@eecs.umich.edu break; 1947259Sgblack@eecs.umich.edu default: 1957259Sgblack@eecs.umich.edu return MISCREG_RAZ; // read as zero 1967259Sgblack@eecs.umich.edu } 1977259Sgblack@eecs.umich.edu break; 1987259Sgblack@eecs.umich.edu case 1: 1997259Sgblack@eecs.umich.edu if (crm == 0) { 2007259Sgblack@eecs.umich.edu switch (opc2) { 2017259Sgblack@eecs.umich.edu case 0: 2027259Sgblack@eecs.umich.edu return MISCREG_CCSIDR; 2037259Sgblack@eecs.umich.edu case 1: 2047259Sgblack@eecs.umich.edu return MISCREG_CLIDR; 2057259Sgblack@eecs.umich.edu case 7: 2067259Sgblack@eecs.umich.edu return MISCREG_AIDR; 2077259Sgblack@eecs.umich.edu } 2087259Sgblack@eecs.umich.edu } 2097259Sgblack@eecs.umich.edu break; 2107259Sgblack@eecs.umich.edu case 2: 2117259Sgblack@eecs.umich.edu if (crm == 0 && opc2 == 0) { 2127259Sgblack@eecs.umich.edu return MISCREG_CSSELR; 2137259Sgblack@eecs.umich.edu } 2147259Sgblack@eecs.umich.edu break; 21510037SARM gem5 Developers case 4: 21610037SARM gem5 Developers if (crm == 0) { 21710037SARM gem5 Developers if (opc2 == 0) 21810037SARM gem5 Developers return MISCREG_VPIDR; 21910037SARM gem5 Developers else if (opc2 == 5) 22010037SARM gem5 Developers return MISCREG_VMPIDR; 22110037SARM gem5 Developers } 22210037SARM gem5 Developers break; 2237259Sgblack@eecs.umich.edu } 2247259Sgblack@eecs.umich.edu break; 2257259Sgblack@eecs.umich.edu case 1: 2267351Sgblack@eecs.umich.edu if (opc1 == 0) { 2277351Sgblack@eecs.umich.edu if (crm == 0) { 2287351Sgblack@eecs.umich.edu switch (opc2) { 2297351Sgblack@eecs.umich.edu case 0: 2307351Sgblack@eecs.umich.edu return MISCREG_SCTLR; 2317351Sgblack@eecs.umich.edu case 1: 2327351Sgblack@eecs.umich.edu return MISCREG_ACTLR; 2337351Sgblack@eecs.umich.edu case 0x2: 2347351Sgblack@eecs.umich.edu return MISCREG_CPACR; 2357351Sgblack@eecs.umich.edu } 2367351Sgblack@eecs.umich.edu } else if (crm == 1) { 2377351Sgblack@eecs.umich.edu switch (opc2) { 2387351Sgblack@eecs.umich.edu case 0: 2397351Sgblack@eecs.umich.edu return MISCREG_SCR; 2407351Sgblack@eecs.umich.edu case 1: 2417351Sgblack@eecs.umich.edu return MISCREG_SDER; 2427351Sgblack@eecs.umich.edu case 2: 2437351Sgblack@eecs.umich.edu return MISCREG_NSACR; 2447351Sgblack@eecs.umich.edu } 2457351Sgblack@eecs.umich.edu } 24610037SARM gem5 Developers } else if (opc1 == 4) { 24710037SARM gem5 Developers if (crm == 0) { 24810037SARM gem5 Developers if (opc2 == 0) 24910037SARM gem5 Developers return MISCREG_HSCTLR; 25010037SARM gem5 Developers else if (opc2 == 1) 25110037SARM gem5 Developers return MISCREG_HACTLR; 25210037SARM gem5 Developers } else if (crm == 1) { 25310037SARM gem5 Developers switch (opc2) { 25410037SARM gem5 Developers case 0: 25510037SARM gem5 Developers return MISCREG_HCR; 25610037SARM gem5 Developers case 1: 25710037SARM gem5 Developers return MISCREG_HDCR; 25810037SARM gem5 Developers case 2: 25910037SARM gem5 Developers return MISCREG_HCPTR; 26010037SARM gem5 Developers case 3: 26110037SARM gem5 Developers return MISCREG_HSTR; 26210037SARM gem5 Developers case 7: 26310037SARM gem5 Developers return MISCREG_HACR; 26410037SARM gem5 Developers } 26510037SARM gem5 Developers } 2667351Sgblack@eecs.umich.edu } 2677351Sgblack@eecs.umich.edu break; 2687351Sgblack@eecs.umich.edu case 2: 2697406SAli.Saidi@ARM.com if (opc1 == 0 && crm == 0) { 2707259Sgblack@eecs.umich.edu switch (opc2) { 2717259Sgblack@eecs.umich.edu case 0: 2727351Sgblack@eecs.umich.edu return MISCREG_TTBR0; 2737259Sgblack@eecs.umich.edu case 1: 2747351Sgblack@eecs.umich.edu return MISCREG_TTBR1; 2757351Sgblack@eecs.umich.edu case 2: 2767351Sgblack@eecs.umich.edu return MISCREG_TTBCR; 2777259Sgblack@eecs.umich.edu } 27810037SARM gem5 Developers } else if (opc1 == 4) { 27910037SARM gem5 Developers if (crm == 0 && opc2 == 2) 28010037SARM gem5 Developers return MISCREG_HTCR; 28110037SARM gem5 Developers else if (crm == 1 && opc2 == 2) 28210037SARM gem5 Developers return MISCREG_VTCR; 2837259Sgblack@eecs.umich.edu } 2847259Sgblack@eecs.umich.edu break; 2857351Sgblack@eecs.umich.edu case 3: 2867351Sgblack@eecs.umich.edu if (opc1 == 0 && crm == 0 && opc2 == 0) { 2877351Sgblack@eecs.umich.edu return MISCREG_DACR; 2887351Sgblack@eecs.umich.edu } 2897351Sgblack@eecs.umich.edu break; 2907259Sgblack@eecs.umich.edu case 5: 2917259Sgblack@eecs.umich.edu if (opc1 == 0) { 2927259Sgblack@eecs.umich.edu if (crm == 0) { 2937259Sgblack@eecs.umich.edu if (opc2 == 0) { 2947259Sgblack@eecs.umich.edu return MISCREG_DFSR; 2957259Sgblack@eecs.umich.edu } else if (opc2 == 1) { 2967259Sgblack@eecs.umich.edu return MISCREG_IFSR; 2977259Sgblack@eecs.umich.edu } 2987259Sgblack@eecs.umich.edu } else if (crm == 1) { 2997259Sgblack@eecs.umich.edu if (opc2 == 0) { 3007259Sgblack@eecs.umich.edu return MISCREG_ADFSR; 3017259Sgblack@eecs.umich.edu } else if (opc2 == 1) { 3027259Sgblack@eecs.umich.edu return MISCREG_AIFSR; 3037259Sgblack@eecs.umich.edu } 3047259Sgblack@eecs.umich.edu } 30510037SARM gem5 Developers } else if (opc1 == 4) { 30610037SARM gem5 Developers if (crm == 1) { 30710037SARM gem5 Developers if (opc2 == 0) 30810037SARM gem5 Developers return MISCREG_HADFSR; 30910037SARM gem5 Developers else if (opc2 == 1) 31010037SARM gem5 Developers return MISCREG_HAIFSR; 31110037SARM gem5 Developers } else if (crm == 2 && opc2 == 0) { 31210037SARM gem5 Developers return MISCREG_HSR; 31310037SARM gem5 Developers } 3147259Sgblack@eecs.umich.edu } 3157259Sgblack@eecs.umich.edu break; 3167259Sgblack@eecs.umich.edu case 6: 3177351Sgblack@eecs.umich.edu if (opc1 == 0 && crm == 0) { 3187351Sgblack@eecs.umich.edu switch (opc2) { 3197259Sgblack@eecs.umich.edu case 0: 3207351Sgblack@eecs.umich.edu return MISCREG_DFAR; 3217259Sgblack@eecs.umich.edu case 2: 3227351Sgblack@eecs.umich.edu return MISCREG_IFAR; 3237259Sgblack@eecs.umich.edu } 32410037SARM gem5 Developers } else if (opc1 == 4 && crm == 0) { 32510037SARM gem5 Developers switch (opc2) { 32610037SARM gem5 Developers case 0: 32710037SARM gem5 Developers return MISCREG_HDFAR; 32810037SARM gem5 Developers case 2: 32910037SARM gem5 Developers return MISCREG_HIFAR; 33010037SARM gem5 Developers case 4: 33110037SARM gem5 Developers return MISCREG_HPFAR; 33210037SARM gem5 Developers } 3337259Sgblack@eecs.umich.edu } 3347259Sgblack@eecs.umich.edu break; 3357259Sgblack@eecs.umich.edu case 7: 3367259Sgblack@eecs.umich.edu if (opc1 == 0) { 3377259Sgblack@eecs.umich.edu switch (crm) { 3387259Sgblack@eecs.umich.edu case 0: 3397259Sgblack@eecs.umich.edu if (opc2 == 4) { 3407259Sgblack@eecs.umich.edu return MISCREG_NOP; 3417259Sgblack@eecs.umich.edu } 3427259Sgblack@eecs.umich.edu break; 3437259Sgblack@eecs.umich.edu case 1: 3447259Sgblack@eecs.umich.edu switch (opc2) { 3457259Sgblack@eecs.umich.edu case 0: 3467259Sgblack@eecs.umich.edu return MISCREG_ICIALLUIS; 3477259Sgblack@eecs.umich.edu case 6: 3487259Sgblack@eecs.umich.edu return MISCREG_BPIALLIS; 3497259Sgblack@eecs.umich.edu } 3507259Sgblack@eecs.umich.edu break; 3517351Sgblack@eecs.umich.edu case 4: 3527351Sgblack@eecs.umich.edu if (opc2 == 0) { 3537351Sgblack@eecs.umich.edu return MISCREG_PAR; 3547351Sgblack@eecs.umich.edu } 3557351Sgblack@eecs.umich.edu break; 3567259Sgblack@eecs.umich.edu case 5: 3577259Sgblack@eecs.umich.edu switch (opc2) { 3587259Sgblack@eecs.umich.edu case 0: 3597259Sgblack@eecs.umich.edu return MISCREG_ICIALLU; 3607259Sgblack@eecs.umich.edu case 1: 3617259Sgblack@eecs.umich.edu return MISCREG_ICIMVAU; 3627259Sgblack@eecs.umich.edu case 4: 3637259Sgblack@eecs.umich.edu return MISCREG_CP15ISB; 3647259Sgblack@eecs.umich.edu case 6: 3657259Sgblack@eecs.umich.edu return MISCREG_BPIALL; 3667259Sgblack@eecs.umich.edu case 7: 3677259Sgblack@eecs.umich.edu return MISCREG_BPIMVA; 3687259Sgblack@eecs.umich.edu } 3697259Sgblack@eecs.umich.edu break; 3707259Sgblack@eecs.umich.edu case 6: 3717259Sgblack@eecs.umich.edu if (opc2 == 1) { 3727259Sgblack@eecs.umich.edu return MISCREG_DCIMVAC; 3737259Sgblack@eecs.umich.edu } else if (opc2 == 2) { 3747259Sgblack@eecs.umich.edu return MISCREG_DCISW; 3757259Sgblack@eecs.umich.edu } 3767259Sgblack@eecs.umich.edu break; 3777351Sgblack@eecs.umich.edu case 8: 3787351Sgblack@eecs.umich.edu switch (opc2) { 3797351Sgblack@eecs.umich.edu case 0: 38010037SARM gem5 Developers return MISCREG_ATS1CPR; 3817351Sgblack@eecs.umich.edu case 1: 38210037SARM gem5 Developers return MISCREG_ATS1CPW; 3837351Sgblack@eecs.umich.edu case 2: 38410037SARM gem5 Developers return MISCREG_ATS1CUR; 3857351Sgblack@eecs.umich.edu case 3: 38610037SARM gem5 Developers return MISCREG_ATS1CUW; 3877351Sgblack@eecs.umich.edu case 4: 38810037SARM gem5 Developers return MISCREG_ATS12NSOPR; 3897351Sgblack@eecs.umich.edu case 5: 39010037SARM gem5 Developers return MISCREG_ATS12NSOPW; 3917351Sgblack@eecs.umich.edu case 6: 39210037SARM gem5 Developers return MISCREG_ATS12NSOUR; 3937351Sgblack@eecs.umich.edu case 7: 39410037SARM gem5 Developers return MISCREG_ATS12NSOUW; 3957351Sgblack@eecs.umich.edu } 3967351Sgblack@eecs.umich.edu break; 3977259Sgblack@eecs.umich.edu case 10: 3987259Sgblack@eecs.umich.edu switch (opc2) { 3997259Sgblack@eecs.umich.edu case 1: 4007259Sgblack@eecs.umich.edu return MISCREG_DCCMVAC; 4017259Sgblack@eecs.umich.edu case 2: 40210037SARM gem5 Developers return MISCREG_DCCSW; 4037259Sgblack@eecs.umich.edu case 4: 4047259Sgblack@eecs.umich.edu return MISCREG_CP15DSB; 4057259Sgblack@eecs.umich.edu case 5: 4067259Sgblack@eecs.umich.edu return MISCREG_CP15DMB; 4077259Sgblack@eecs.umich.edu } 4087259Sgblack@eecs.umich.edu break; 4097259Sgblack@eecs.umich.edu case 11: 4107259Sgblack@eecs.umich.edu if (opc2 == 1) { 4117259Sgblack@eecs.umich.edu return MISCREG_DCCMVAU; 4127259Sgblack@eecs.umich.edu } 4137259Sgblack@eecs.umich.edu break; 4147259Sgblack@eecs.umich.edu case 13: 4157259Sgblack@eecs.umich.edu if (opc2 == 1) { 4167259Sgblack@eecs.umich.edu return MISCREG_NOP; 4177259Sgblack@eecs.umich.edu } 4187259Sgblack@eecs.umich.edu break; 4197259Sgblack@eecs.umich.edu case 14: 4207259Sgblack@eecs.umich.edu if (opc2 == 1) { 4217259Sgblack@eecs.umich.edu return MISCREG_DCCIMVAC; 4227259Sgblack@eecs.umich.edu } else if (opc2 == 2) { 4237259Sgblack@eecs.umich.edu return MISCREG_DCCISW; 4247259Sgblack@eecs.umich.edu } 4257259Sgblack@eecs.umich.edu break; 4267259Sgblack@eecs.umich.edu } 42710037SARM gem5 Developers } else if (opc1 == 4 && crm == 8) { 42810037SARM gem5 Developers if (opc2 == 0) 42910037SARM gem5 Developers return MISCREG_ATS1HR; 43010037SARM gem5 Developers else if (opc2 == 1) 43110037SARM gem5 Developers return MISCREG_ATS1HW; 4327259Sgblack@eecs.umich.edu } 4337259Sgblack@eecs.umich.edu break; 4347351Sgblack@eecs.umich.edu case 8: 4357351Sgblack@eecs.umich.edu if (opc1 == 0) { 4367351Sgblack@eecs.umich.edu switch (crm) { 4377351Sgblack@eecs.umich.edu case 3: 4387351Sgblack@eecs.umich.edu switch (opc2) { 4397351Sgblack@eecs.umich.edu case 0: 4407351Sgblack@eecs.umich.edu return MISCREG_TLBIALLIS; 4417351Sgblack@eecs.umich.edu case 1: 4427351Sgblack@eecs.umich.edu return MISCREG_TLBIMVAIS; 4437351Sgblack@eecs.umich.edu case 2: 4447351Sgblack@eecs.umich.edu return MISCREG_TLBIASIDIS; 4457351Sgblack@eecs.umich.edu case 3: 4467351Sgblack@eecs.umich.edu return MISCREG_TLBIMVAAIS; 44712576Sgiacomo.travaglini@arm.com case 5: 44812576Sgiacomo.travaglini@arm.com return MISCREG_TLBIMVALIS; 44912576Sgiacomo.travaglini@arm.com case 7: 45012576Sgiacomo.travaglini@arm.com return MISCREG_TLBIMVAALIS; 4517351Sgblack@eecs.umich.edu } 4527351Sgblack@eecs.umich.edu break; 4537351Sgblack@eecs.umich.edu case 5: 4547351Sgblack@eecs.umich.edu switch (opc2) { 4557351Sgblack@eecs.umich.edu case 0: 4567351Sgblack@eecs.umich.edu return MISCREG_ITLBIALL; 4577351Sgblack@eecs.umich.edu case 1: 4587351Sgblack@eecs.umich.edu return MISCREG_ITLBIMVA; 4597351Sgblack@eecs.umich.edu case 2: 4607351Sgblack@eecs.umich.edu return MISCREG_ITLBIASID; 4617351Sgblack@eecs.umich.edu } 4627351Sgblack@eecs.umich.edu break; 4637351Sgblack@eecs.umich.edu case 6: 4647351Sgblack@eecs.umich.edu switch (opc2) { 4657351Sgblack@eecs.umich.edu case 0: 4667351Sgblack@eecs.umich.edu return MISCREG_DTLBIALL; 4677351Sgblack@eecs.umich.edu case 1: 4687351Sgblack@eecs.umich.edu return MISCREG_DTLBIMVA; 4697351Sgblack@eecs.umich.edu case 2: 4707351Sgblack@eecs.umich.edu return MISCREG_DTLBIASID; 4717351Sgblack@eecs.umich.edu } 4727351Sgblack@eecs.umich.edu break; 4737351Sgblack@eecs.umich.edu case 7: 4747351Sgblack@eecs.umich.edu switch (opc2) { 4757351Sgblack@eecs.umich.edu case 0: 4767351Sgblack@eecs.umich.edu return MISCREG_TLBIALL; 4777351Sgblack@eecs.umich.edu case 1: 4787351Sgblack@eecs.umich.edu return MISCREG_TLBIMVA; 4797351Sgblack@eecs.umich.edu case 2: 4807351Sgblack@eecs.umich.edu return MISCREG_TLBIASID; 4817351Sgblack@eecs.umich.edu case 3: 4827351Sgblack@eecs.umich.edu return MISCREG_TLBIMVAA; 48312576Sgiacomo.travaglini@arm.com case 5: 48412576Sgiacomo.travaglini@arm.com return MISCREG_TLBIMVAL; 48512576Sgiacomo.travaglini@arm.com case 7: 48612576Sgiacomo.travaglini@arm.com return MISCREG_TLBIMVAAL; 4877351Sgblack@eecs.umich.edu } 4887351Sgblack@eecs.umich.edu break; 4897351Sgblack@eecs.umich.edu } 49010037SARM gem5 Developers } else if (opc1 == 4) { 49112577Sgiacomo.travaglini@arm.com if (crm == 0) { 49212577Sgiacomo.travaglini@arm.com switch (opc2) { 49312577Sgiacomo.travaglini@arm.com case 1: 49412577Sgiacomo.travaglini@arm.com return MISCREG_TLBIIPAS2IS; 49512577Sgiacomo.travaglini@arm.com case 5: 49612577Sgiacomo.travaglini@arm.com return MISCREG_TLBIIPAS2LIS; 49712577Sgiacomo.travaglini@arm.com } 49812577Sgiacomo.travaglini@arm.com } else if (crm == 3) { 49910037SARM gem5 Developers switch (opc2) { 50010037SARM gem5 Developers case 0: 50110037SARM gem5 Developers return MISCREG_TLBIALLHIS; 50210037SARM gem5 Developers case 1: 50310037SARM gem5 Developers return MISCREG_TLBIMVAHIS; 50410037SARM gem5 Developers case 4: 50510037SARM gem5 Developers return MISCREG_TLBIALLNSNHIS; 50612576Sgiacomo.travaglini@arm.com case 5: 50712576Sgiacomo.travaglini@arm.com return MISCREG_TLBIMVALHIS; 50810037SARM gem5 Developers } 50912577Sgiacomo.travaglini@arm.com } else if (crm == 4) { 51012577Sgiacomo.travaglini@arm.com switch (opc2) { 51112577Sgiacomo.travaglini@arm.com case 1: 51212577Sgiacomo.travaglini@arm.com return MISCREG_TLBIIPAS2; 51312577Sgiacomo.travaglini@arm.com case 5: 51412577Sgiacomo.travaglini@arm.com return MISCREG_TLBIIPAS2L; 51512577Sgiacomo.travaglini@arm.com } 51610037SARM gem5 Developers } else if (crm == 7) { 51710037SARM gem5 Developers switch (opc2) { 51810037SARM gem5 Developers case 0: 51910037SARM gem5 Developers return MISCREG_TLBIALLH; 52010037SARM gem5 Developers case 1: 52110037SARM gem5 Developers return MISCREG_TLBIMVAH; 52210037SARM gem5 Developers case 4: 52310037SARM gem5 Developers return MISCREG_TLBIALLNSNH; 52412576Sgiacomo.travaglini@arm.com case 5: 52512576Sgiacomo.travaglini@arm.com return MISCREG_TLBIMVALH; 52610037SARM gem5 Developers } 52710037SARM gem5 Developers } 5287351Sgblack@eecs.umich.edu } 5297351Sgblack@eecs.umich.edu break; 5307259Sgblack@eecs.umich.edu case 9: 53112530Sgiacomo.travaglini@arm.com // Every cop register with CRn = 9 and CRm in 53212530Sgiacomo.travaglini@arm.com // {0-2}, {5-8} is implementation defined regardless 53312530Sgiacomo.travaglini@arm.com // of opc1 and opc2. 53412530Sgiacomo.travaglini@arm.com switch (crm) { 53512530Sgiacomo.travaglini@arm.com case 0: 53612530Sgiacomo.travaglini@arm.com case 1: 53712530Sgiacomo.travaglini@arm.com case 2: 53812530Sgiacomo.travaglini@arm.com case 5: 53912530Sgiacomo.travaglini@arm.com case 6: 54012530Sgiacomo.travaglini@arm.com case 7: 54112530Sgiacomo.travaglini@arm.com case 8: 54212530Sgiacomo.travaglini@arm.com return MISCREG_IMPDEF_UNIMPL; 54312530Sgiacomo.travaglini@arm.com } 5447583SAli.Saidi@arm.com if (opc1 == 0) { 5457259Sgblack@eecs.umich.edu switch (crm) { 5467259Sgblack@eecs.umich.edu case 12: 5477583SAli.Saidi@arm.com switch (opc2) { 5487583SAli.Saidi@arm.com case 0: 5497583SAli.Saidi@arm.com return MISCREG_PMCR; 5507583SAli.Saidi@arm.com case 1: 5517583SAli.Saidi@arm.com return MISCREG_PMCNTENSET; 5527583SAli.Saidi@arm.com case 2: 5537583SAli.Saidi@arm.com return MISCREG_PMCNTENCLR; 5547583SAli.Saidi@arm.com case 3: 5557583SAli.Saidi@arm.com return MISCREG_PMOVSR; 5567583SAli.Saidi@arm.com case 4: 5577583SAli.Saidi@arm.com return MISCREG_PMSWINC; 5587583SAli.Saidi@arm.com case 5: 5597583SAli.Saidi@arm.com return MISCREG_PMSELR; 5607583SAli.Saidi@arm.com case 6: 5617583SAli.Saidi@arm.com return MISCREG_PMCEID0; 5627583SAli.Saidi@arm.com case 7: 5637583SAli.Saidi@arm.com return MISCREG_PMCEID1; 5647583SAli.Saidi@arm.com } 5658988SAli.Saidi@ARM.com break; 5667259Sgblack@eecs.umich.edu case 13: 5677583SAli.Saidi@arm.com switch (opc2) { 5687583SAli.Saidi@arm.com case 0: 5697583SAli.Saidi@arm.com return MISCREG_PMCCNTR; 5707583SAli.Saidi@arm.com case 1: 57110037SARM gem5 Developers // Selector is PMSELR.SEL 57210037SARM gem5 Developers return MISCREG_PMXEVTYPER_PMCCFILTR; 5737583SAli.Saidi@arm.com case 2: 5747583SAli.Saidi@arm.com return MISCREG_PMXEVCNTR; 5757583SAli.Saidi@arm.com } 5768988SAli.Saidi@ARM.com break; 5777259Sgblack@eecs.umich.edu case 14: 5787583SAli.Saidi@arm.com switch (opc2) { 5797583SAli.Saidi@arm.com case 0: 5807583SAli.Saidi@arm.com return MISCREG_PMUSERENR; 5817583SAli.Saidi@arm.com case 1: 5827583SAli.Saidi@arm.com return MISCREG_PMINTENSET; 5837583SAli.Saidi@arm.com case 2: 5847583SAli.Saidi@arm.com return MISCREG_PMINTENCLR; 58510037SARM gem5 Developers case 3: 58610037SARM gem5 Developers return MISCREG_PMOVSSET; 5877583SAli.Saidi@arm.com } 5888988SAli.Saidi@ARM.com break; 5897259Sgblack@eecs.umich.edu } 5908058SAli.Saidi@ARM.com } else if (opc1 == 1) { 5918549Sdaniel.johnson@arm.com switch (crm) { 5928549Sdaniel.johnson@arm.com case 0: 5938549Sdaniel.johnson@arm.com switch (opc2) { 5948549Sdaniel.johnson@arm.com case 2: // L2CTLR, L2 Control Register 5958549Sdaniel.johnson@arm.com return MISCREG_L2CTLR; 59610037SARM gem5 Developers case 3: 59710037SARM gem5 Developers return MISCREG_L2ECTLR; 5988549Sdaniel.johnson@arm.com } 5998988SAli.Saidi@ARM.com break; 60010037SARM gem5 Developers break; 6018549Sdaniel.johnson@arm.com } 6027259Sgblack@eecs.umich.edu } 6037259Sgblack@eecs.umich.edu break; 6047351Sgblack@eecs.umich.edu case 10: 6057351Sgblack@eecs.umich.edu if (opc1 == 0) { 6067351Sgblack@eecs.umich.edu // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 60712530Sgiacomo.travaglini@arm.com if (crm < 2) { 60812530Sgiacomo.travaglini@arm.com return MISCREG_IMPDEF_UNIMPL; 60912530Sgiacomo.travaglini@arm.com } else if (crm == 2) { // TEX Remap Registers 6107351Sgblack@eecs.umich.edu if (opc2 == 0) { 61110037SARM gem5 Developers // Selector is TTBCR.EAE 61210037SARM gem5 Developers return MISCREG_PRRR_MAIR0; 6137351Sgblack@eecs.umich.edu } else if (opc2 == 1) { 61410037SARM gem5 Developers // Selector is TTBCR.EAE 61510037SARM gem5 Developers return MISCREG_NMRR_MAIR1; 6167351Sgblack@eecs.umich.edu } 61710037SARM gem5 Developers } else if (crm == 3) { 61810037SARM gem5 Developers if (opc2 == 0) { 61910037SARM gem5 Developers return MISCREG_AMAIR0; 62010037SARM gem5 Developers } else if (opc2 == 1) { 62110037SARM gem5 Developers return MISCREG_AMAIR1; 62210037SARM gem5 Developers } 62310037SARM gem5 Developers } 62410037SARM gem5 Developers } else if (opc1 == 4) { 62510037SARM gem5 Developers // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 62610037SARM gem5 Developers if (crm == 2) { 62710037SARM gem5 Developers if (opc2 == 0) 62810037SARM gem5 Developers return MISCREG_HMAIR0; 62910037SARM gem5 Developers else if (opc2 == 1) 63010037SARM gem5 Developers return MISCREG_HMAIR1; 63110037SARM gem5 Developers } else if (crm == 3) { 63210037SARM gem5 Developers if (opc2 == 0) 63310037SARM gem5 Developers return MISCREG_HAMAIR0; 63410037SARM gem5 Developers else if (opc2 == 1) 63510037SARM gem5 Developers return MISCREG_HAMAIR1; 6367351Sgblack@eecs.umich.edu } 6377351Sgblack@eecs.umich.edu } 6387351Sgblack@eecs.umich.edu break; 6397259Sgblack@eecs.umich.edu case 11: 6408737Skoansin.tan@gmail.com if (opc1 <=7) { 6417259Sgblack@eecs.umich.edu switch (crm) { 6427259Sgblack@eecs.umich.edu case 0: 6437259Sgblack@eecs.umich.edu case 1: 6447259Sgblack@eecs.umich.edu case 2: 6457259Sgblack@eecs.umich.edu case 3: 6467259Sgblack@eecs.umich.edu case 4: 6477259Sgblack@eecs.umich.edu case 5: 6487259Sgblack@eecs.umich.edu case 6: 6497259Sgblack@eecs.umich.edu case 7: 6507259Sgblack@eecs.umich.edu case 8: 6517259Sgblack@eecs.umich.edu case 15: 6527259Sgblack@eecs.umich.edu // Reserved for DMA operations for TCM access 65312530Sgiacomo.travaglini@arm.com return MISCREG_IMPDEF_UNIMPL; 65412530Sgiacomo.travaglini@arm.com default: 6557259Sgblack@eecs.umich.edu break; 6567259Sgblack@eecs.umich.edu } 6577259Sgblack@eecs.umich.edu } 6587259Sgblack@eecs.umich.edu break; 6597351Sgblack@eecs.umich.edu case 12: 6607351Sgblack@eecs.umich.edu if (opc1 == 0) { 6617351Sgblack@eecs.umich.edu if (crm == 0) { 6627351Sgblack@eecs.umich.edu if (opc2 == 0) { 6637351Sgblack@eecs.umich.edu return MISCREG_VBAR; 6647351Sgblack@eecs.umich.edu } else if (opc2 == 1) { 6657351Sgblack@eecs.umich.edu return MISCREG_MVBAR; 6667351Sgblack@eecs.umich.edu } 6677351Sgblack@eecs.umich.edu } else if (crm == 1) { 6687351Sgblack@eecs.umich.edu if (opc2 == 0) { 6697351Sgblack@eecs.umich.edu return MISCREG_ISR; 6707351Sgblack@eecs.umich.edu } 6717351Sgblack@eecs.umich.edu } 67210037SARM gem5 Developers } else if (opc1 == 4) { 67310037SARM gem5 Developers if (crm == 0 && opc2 == 0) 67410037SARM gem5 Developers return MISCREG_HVBAR; 6757351Sgblack@eecs.umich.edu } 6767351Sgblack@eecs.umich.edu break; 6777259Sgblack@eecs.umich.edu case 13: 6787259Sgblack@eecs.umich.edu if (opc1 == 0) { 6797259Sgblack@eecs.umich.edu if (crm == 0) { 6807406SAli.Saidi@ARM.com switch (opc2) { 6817351Sgblack@eecs.umich.edu case 0: 68210037SARM gem5 Developers return MISCREG_FCSEIDR; 6837259Sgblack@eecs.umich.edu case 1: 6847259Sgblack@eecs.umich.edu return MISCREG_CONTEXTIDR; 6857259Sgblack@eecs.umich.edu case 2: 6867259Sgblack@eecs.umich.edu return MISCREG_TPIDRURW; 6877259Sgblack@eecs.umich.edu case 3: 6887259Sgblack@eecs.umich.edu return MISCREG_TPIDRURO; 6897259Sgblack@eecs.umich.edu case 4: 6907259Sgblack@eecs.umich.edu return MISCREG_TPIDRPRW; 6917259Sgblack@eecs.umich.edu } 6927259Sgblack@eecs.umich.edu } 69310037SARM gem5 Developers } else if (opc1 == 4) { 69410037SARM gem5 Developers if (crm == 0 && opc2 == 2) 69510037SARM gem5 Developers return MISCREG_HTPIDR; 69610037SARM gem5 Developers } 69710037SARM gem5 Developers break; 69810037SARM gem5 Developers case 14: 69910037SARM gem5 Developers if (opc1 == 0) { 70010037SARM gem5 Developers switch (crm) { 70110037SARM gem5 Developers case 0: 70210037SARM gem5 Developers if (opc2 == 0) 70310037SARM gem5 Developers return MISCREG_CNTFRQ; 70410037SARM gem5 Developers break; 70510037SARM gem5 Developers case 1: 70610037SARM gem5 Developers if (opc2 == 0) 70710037SARM gem5 Developers return MISCREG_CNTKCTL; 70810037SARM gem5 Developers break; 70910037SARM gem5 Developers case 2: 71010037SARM gem5 Developers if (opc2 == 0) 71110037SARM gem5 Developers return MISCREG_CNTP_TVAL; 71210037SARM gem5 Developers else if (opc2 == 1) 71310037SARM gem5 Developers return MISCREG_CNTP_CTL; 71410037SARM gem5 Developers break; 71510037SARM gem5 Developers case 3: 71610037SARM gem5 Developers if (opc2 == 0) 71710037SARM gem5 Developers return MISCREG_CNTV_TVAL; 71810037SARM gem5 Developers else if (opc2 == 1) 71910037SARM gem5 Developers return MISCREG_CNTV_CTL; 72010037SARM gem5 Developers break; 72110037SARM gem5 Developers } 72210037SARM gem5 Developers } else if (opc1 == 4) { 72310037SARM gem5 Developers if (crm == 1 && opc2 == 0) { 72410037SARM gem5 Developers return MISCREG_CNTHCTL; 72510037SARM gem5 Developers } else if (crm == 2) { 72610037SARM gem5 Developers if (opc2 == 0) 72710037SARM gem5 Developers return MISCREG_CNTHP_TVAL; 72810037SARM gem5 Developers else if (opc2 == 1) 72910037SARM gem5 Developers return MISCREG_CNTHP_CTL; 73010037SARM gem5 Developers } 7317259Sgblack@eecs.umich.edu } 7327259Sgblack@eecs.umich.edu break; 7337259Sgblack@eecs.umich.edu case 15: 7347259Sgblack@eecs.umich.edu // Implementation defined 73512530Sgiacomo.travaglini@arm.com return MISCREG_IMPDEF_UNIMPL; 7367259Sgblack@eecs.umich.edu } 7377259Sgblack@eecs.umich.edu // Unrecognized register 73810037SARM gem5 Developers return MISCREG_CP15_UNIMPL; 7397259Sgblack@eecs.umich.edu} 7407259Sgblack@eecs.umich.edu 74110037SARM gem5 DevelopersMiscRegIndex 74210037SARM gem5 DevelopersdecodeCP15Reg64(unsigned crm, unsigned opc1) 74310037SARM gem5 Developers{ 74410037SARM gem5 Developers switch (crm) { 74510037SARM gem5 Developers case 2: 74610037SARM gem5 Developers switch (opc1) { 74710037SARM gem5 Developers case 0: 74810037SARM gem5 Developers return MISCREG_TTBR0; 74910037SARM gem5 Developers case 1: 75010037SARM gem5 Developers return MISCREG_TTBR1; 75110037SARM gem5 Developers case 4: 75210037SARM gem5 Developers return MISCREG_HTTBR; 75310037SARM gem5 Developers case 6: 75410037SARM gem5 Developers return MISCREG_VTTBR; 75510037SARM gem5 Developers } 75610037SARM gem5 Developers break; 75710037SARM gem5 Developers case 7: 75810037SARM gem5 Developers if (opc1 == 0) 75910037SARM gem5 Developers return MISCREG_PAR; 76010037SARM gem5 Developers break; 76110037SARM gem5 Developers case 14: 76210037SARM gem5 Developers switch (opc1) { 76310037SARM gem5 Developers case 0: 76410037SARM gem5 Developers return MISCREG_CNTPCT; 76510037SARM gem5 Developers case 1: 76610037SARM gem5 Developers return MISCREG_CNTVCT; 76710037SARM gem5 Developers case 2: 76810037SARM gem5 Developers return MISCREG_CNTP_CVAL; 76910037SARM gem5 Developers case 3: 77010037SARM gem5 Developers return MISCREG_CNTV_CVAL; 77110037SARM gem5 Developers case 4: 77210037SARM gem5 Developers return MISCREG_CNTVOFF; 77310037SARM gem5 Developers case 6: 77410037SARM gem5 Developers return MISCREG_CNTHP_CVAL; 77510037SARM gem5 Developers } 77610037SARM gem5 Developers break; 77710037SARM gem5 Developers case 15: 77810037SARM gem5 Developers if (opc1 == 0) 77910037SARM gem5 Developers return MISCREG_CPUMERRSR; 78010037SARM gem5 Developers else if (opc1 == 1) 78110037SARM gem5 Developers return MISCREG_L2MERRSR; 78210037SARM gem5 Developers break; 78310037SARM gem5 Developers } 78410037SARM gem5 Developers // Unrecognized register 78510037SARM gem5 Developers return MISCREG_CP15_UNIMPL; 7868902Sandreas.hansson@arm.com} 78710037SARM gem5 Developers 78811939Snikos.nikoleris@arm.comstd::tuple<bool, bool> 78911939Snikos.nikoleris@arm.comcanReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 79010037SARM gem5 Developers{ 79110037SARM gem5 Developers bool secure = !scr.ns; 79211939Snikos.nikoleris@arm.com bool canRead = false; 79311939Snikos.nikoleris@arm.com bool undefined = false; 79410037SARM gem5 Developers 79510037SARM gem5 Developers switch (cpsr.mode) { 79610037SARM gem5 Developers case MODE_USER: 79710037SARM gem5 Developers canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 79810037SARM gem5 Developers miscRegInfo[reg][MISCREG_USR_NS_RD]; 79910037SARM gem5 Developers break; 80010037SARM gem5 Developers case MODE_FIQ: 80110037SARM gem5 Developers case MODE_IRQ: 80210037SARM gem5 Developers case MODE_SVC: 80310037SARM gem5 Developers case MODE_ABORT: 80410037SARM gem5 Developers case MODE_UNDEFINED: 80510037SARM gem5 Developers case MODE_SYSTEM: 80610037SARM gem5 Developers canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 80710037SARM gem5 Developers miscRegInfo[reg][MISCREG_PRI_NS_RD]; 80810037SARM gem5 Developers break; 80910037SARM gem5 Developers case MODE_MON: 81010037SARM gem5 Developers canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 81110037SARM gem5 Developers miscRegInfo[reg][MISCREG_MON_NS1_RD]; 81210037SARM gem5 Developers break; 81310037SARM gem5 Developers case MODE_HYP: 81410037SARM gem5 Developers canRead = miscRegInfo[reg][MISCREG_HYP_RD]; 81510037SARM gem5 Developers break; 81610037SARM gem5 Developers default: 81711939Snikos.nikoleris@arm.com undefined = true; 81810037SARM gem5 Developers } 81910037SARM gem5 Developers // can't do permissions checkes on the root of a banked pair of regs 82010037SARM gem5 Developers assert(!miscRegInfo[reg][MISCREG_BANKED]); 82111939Snikos.nikoleris@arm.com return std::make_tuple(canRead, undefined); 82210037SARM gem5 Developers} 82310037SARM gem5 Developers 82411939Snikos.nikoleris@arm.comstd::tuple<bool, bool> 82511939Snikos.nikoleris@arm.comcanWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 82610037SARM gem5 Developers{ 82710037SARM gem5 Developers bool secure = !scr.ns; 82811939Snikos.nikoleris@arm.com bool canWrite = false; 82911939Snikos.nikoleris@arm.com bool undefined = false; 83010037SARM gem5 Developers 83110037SARM gem5 Developers switch (cpsr.mode) { 83210037SARM gem5 Developers case MODE_USER: 83310037SARM gem5 Developers canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 83410037SARM gem5 Developers miscRegInfo[reg][MISCREG_USR_NS_WR]; 83510037SARM gem5 Developers break; 83610037SARM gem5 Developers case MODE_FIQ: 83710037SARM gem5 Developers case MODE_IRQ: 83810037SARM gem5 Developers case MODE_SVC: 83910037SARM gem5 Developers case MODE_ABORT: 84010037SARM gem5 Developers case MODE_UNDEFINED: 84110037SARM gem5 Developers case MODE_SYSTEM: 84210037SARM gem5 Developers canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 84310037SARM gem5 Developers miscRegInfo[reg][MISCREG_PRI_NS_WR]; 84410037SARM gem5 Developers break; 84510037SARM gem5 Developers case MODE_MON: 84610037SARM gem5 Developers canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 84710037SARM gem5 Developers miscRegInfo[reg][MISCREG_MON_NS1_WR]; 84810037SARM gem5 Developers break; 84910037SARM gem5 Developers case MODE_HYP: 85010037SARM gem5 Developers canWrite = miscRegInfo[reg][MISCREG_HYP_WR]; 85110037SARM gem5 Developers break; 85210037SARM gem5 Developers default: 85311939Snikos.nikoleris@arm.com undefined = true; 85410037SARM gem5 Developers } 85510037SARM gem5 Developers // can't do permissions checkes on the root of a banked pair of regs 85610037SARM gem5 Developers assert(!miscRegInfo[reg][MISCREG_BANKED]); 85711939Snikos.nikoleris@arm.com return std::make_tuple(canWrite, undefined); 85810037SARM gem5 Developers} 85910037SARM gem5 Developers 86010037SARM gem5 Developersint 86112499Sgiacomo.travaglini@arm.comsnsBankedIndex(MiscRegIndex reg, ThreadContext *tc) 86210037SARM gem5 Developers{ 86311771SCurtis.Dunham@arm.com SCR scr = tc->readMiscReg(MISCREG_SCR); 86412499Sgiacomo.travaglini@arm.com return snsBankedIndex(reg, tc, scr.ns); 86510037SARM gem5 Developers} 86610037SARM gem5 Developers 86710037SARM gem5 Developersint 86812499Sgiacomo.travaglini@arm.comsnsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns) 86910037SARM gem5 Developers{ 87010421Sandreas.hansson@arm.com int reg_as_int = static_cast<int>(reg); 87110037SARM gem5 Developers if (miscRegInfo[reg][MISCREG_BANKED]) { 87211771SCurtis.Dunham@arm.com reg_as_int += (ArmSystem::haveSecurity(tc) && 87311771SCurtis.Dunham@arm.com !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1; 87410037SARM gem5 Developers } 87510421Sandreas.hansson@arm.com return reg_as_int; 87610037SARM gem5 Developers} 87710037SARM gem5 Developers 87810037SARM gem5 Developers 87910037SARM gem5 Developers/** 88010037SARM gem5 Developers * If the reg is a child reg of a banked set, then the parent is the last 88110037SARM gem5 Developers * banked one in the list. This is messy, and the wish is to eventually have 88210037SARM gem5 Developers * the bitmap replaced with a better data structure. the preUnflatten function 88310037SARM gem5 Developers * initializes a lookup table to speed up the search for these banked 88410037SARM gem5 Developers * registers. 88510037SARM gem5 Developers */ 88610037SARM gem5 Developers 88710037SARM gem5 Developersint unflattenResultMiscReg[NUM_MISCREGS]; 88810037SARM gem5 Developers 88910037SARM gem5 Developersvoid 89010037SARM gem5 DeveloperspreUnflattenMiscReg() 89110037SARM gem5 Developers{ 89210037SARM gem5 Developers int reg = -1; 89310037SARM gem5 Developers for (int i = 0 ; i < NUM_MISCREGS; i++){ 89410037SARM gem5 Developers if (miscRegInfo[i][MISCREG_BANKED]) 89510037SARM gem5 Developers reg = i; 89610037SARM gem5 Developers if (miscRegInfo[i][MISCREG_BANKED_CHILD]) 89710037SARM gem5 Developers unflattenResultMiscReg[i] = reg; 89810037SARM gem5 Developers else 89910037SARM gem5 Developers unflattenResultMiscReg[i] = i; 90010037SARM gem5 Developers // if this assert fails, no parent was found, and something is broken 90110037SARM gem5 Developers assert(unflattenResultMiscReg[i] > -1); 90210037SARM gem5 Developers } 90310037SARM gem5 Developers} 90410037SARM gem5 Developers 90510037SARM gem5 Developersint 90610037SARM gem5 DevelopersunflattenMiscReg(int reg) 90710037SARM gem5 Developers{ 90810037SARM gem5 Developers return unflattenResultMiscReg[reg]; 90910037SARM gem5 Developers} 91010037SARM gem5 Developers 91110037SARM gem5 Developersbool 91210037SARM gem5 DeveloperscanReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 91310037SARM gem5 Developers{ 91410037SARM gem5 Developers // Check for SP_EL0 access while SPSEL == 0 91510037SARM gem5 Developers if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 91610037SARM gem5 Developers return false; 91710037SARM gem5 Developers 91810037SARM gem5 Developers // Check for RVBAR access 91910037SARM gem5 Developers if (reg == MISCREG_RVBAR_EL1) { 92010037SARM gem5 Developers ExceptionLevel highest_el = ArmSystem::highestEL(tc); 92110037SARM gem5 Developers if (highest_el == EL2 || highest_el == EL3) 92210037SARM gem5 Developers return false; 92310037SARM gem5 Developers } 92410037SARM gem5 Developers if (reg == MISCREG_RVBAR_EL2) { 92510037SARM gem5 Developers ExceptionLevel highest_el = ArmSystem::highestEL(tc); 92610037SARM gem5 Developers if (highest_el == EL3) 92710037SARM gem5 Developers return false; 92810037SARM gem5 Developers } 92910037SARM gem5 Developers 93010037SARM gem5 Developers bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 93110037SARM gem5 Developers 93210037SARM gem5 Developers switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) { 93310037SARM gem5 Developers case EL0: 93410037SARM gem5 Developers return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 93510037SARM gem5 Developers miscRegInfo[reg][MISCREG_USR_NS_RD]; 93610037SARM gem5 Developers case EL1: 93710037SARM gem5 Developers return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 93810037SARM gem5 Developers miscRegInfo[reg][MISCREG_PRI_NS_RD]; 93911574SCurtis.Dunham@arm.com case EL2: 94011574SCurtis.Dunham@arm.com return miscRegInfo[reg][MISCREG_HYP_RD]; 94110037SARM gem5 Developers case EL3: 94210037SARM gem5 Developers return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 94310037SARM gem5 Developers miscRegInfo[reg][MISCREG_MON_NS1_RD]; 94410037SARM gem5 Developers default: 94510037SARM gem5 Developers panic("Invalid exception level"); 94610037SARM gem5 Developers } 94710037SARM gem5 Developers} 94810037SARM gem5 Developers 94910037SARM gem5 Developersbool 95010037SARM gem5 DeveloperscanWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 95110037SARM gem5 Developers{ 95210037SARM gem5 Developers // Check for SP_EL0 access while SPSEL == 0 95310037SARM gem5 Developers if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 95410037SARM gem5 Developers return false; 95510037SARM gem5 Developers ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode); 95610037SARM gem5 Developers if (reg == MISCREG_DAIF) { 95710037SARM gem5 Developers SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 95810037SARM gem5 Developers if (el == EL0 && !sctlr.uma) 95910037SARM gem5 Developers return false; 96010037SARM gem5 Developers } 96110828SGiacomo.Gabrielli@arm.com if (FullSystem && reg == MISCREG_DC_ZVA_Xt) { 96210828SGiacomo.Gabrielli@arm.com // In syscall-emulation mode, this test is skipped and DCZVA is always 96310828SGiacomo.Gabrielli@arm.com // allowed at EL0 96410037SARM gem5 Developers SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 96510037SARM gem5 Developers if (el == EL0 && !sctlr.dze) 96610037SARM gem5 Developers return false; 96710037SARM gem5 Developers } 96812502Snikos.nikoleris@arm.com if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) { 96910037SARM gem5 Developers SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 97010037SARM gem5 Developers if (el == EL0 && !sctlr.uci) 97110037SARM gem5 Developers return false; 97210037SARM gem5 Developers } 97310037SARM gem5 Developers 97410037SARM gem5 Developers bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 97510037SARM gem5 Developers 97610037SARM gem5 Developers switch (el) { 97710037SARM gem5 Developers case EL0: 97810037SARM gem5 Developers return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 97910037SARM gem5 Developers miscRegInfo[reg][MISCREG_USR_NS_WR]; 98010037SARM gem5 Developers case EL1: 98110037SARM gem5 Developers return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 98210037SARM gem5 Developers miscRegInfo[reg][MISCREG_PRI_NS_WR]; 98311574SCurtis.Dunham@arm.com case EL2: 98411574SCurtis.Dunham@arm.com return miscRegInfo[reg][MISCREG_HYP_WR]; 98510037SARM gem5 Developers case EL3: 98610037SARM gem5 Developers return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 98710037SARM gem5 Developers miscRegInfo[reg][MISCREG_MON_NS1_WR]; 98810037SARM gem5 Developers default: 98910037SARM gem5 Developers panic("Invalid exception level"); 99010037SARM gem5 Developers } 99110037SARM gem5 Developers} 99210037SARM gem5 Developers 99310037SARM gem5 DevelopersMiscRegIndex 99410037SARM gem5 DevelopersdecodeAArch64SysReg(unsigned op0, unsigned op1, 99510037SARM gem5 Developers unsigned crn, unsigned crm, 99610037SARM gem5 Developers unsigned op2) 99710037SARM gem5 Developers{ 99810037SARM gem5 Developers switch (op0) { 99910037SARM gem5 Developers case 1: 100010037SARM gem5 Developers switch (crn) { 100110037SARM gem5 Developers case 7: 100210037SARM gem5 Developers switch (op1) { 100310037SARM gem5 Developers case 0: 100410037SARM gem5 Developers switch (crm) { 100510037SARM gem5 Developers case 1: 100610037SARM gem5 Developers switch (op2) { 100710037SARM gem5 Developers case 0: 100810037SARM gem5 Developers return MISCREG_IC_IALLUIS; 100910037SARM gem5 Developers } 101010037SARM gem5 Developers break; 101110037SARM gem5 Developers case 5: 101210037SARM gem5 Developers switch (op2) { 101310037SARM gem5 Developers case 0: 101410037SARM gem5 Developers return MISCREG_IC_IALLU; 101510037SARM gem5 Developers } 101610037SARM gem5 Developers break; 101710037SARM gem5 Developers case 6: 101810037SARM gem5 Developers switch (op2) { 101910037SARM gem5 Developers case 1: 102010037SARM gem5 Developers return MISCREG_DC_IVAC_Xt; 102110037SARM gem5 Developers case 2: 102210037SARM gem5 Developers return MISCREG_DC_ISW_Xt; 102310037SARM gem5 Developers } 102410037SARM gem5 Developers break; 102510037SARM gem5 Developers case 8: 102610037SARM gem5 Developers switch (op2) { 102710037SARM gem5 Developers case 0: 102810037SARM gem5 Developers return MISCREG_AT_S1E1R_Xt; 102910037SARM gem5 Developers case 1: 103010037SARM gem5 Developers return MISCREG_AT_S1E1W_Xt; 103110037SARM gem5 Developers case 2: 103210037SARM gem5 Developers return MISCREG_AT_S1E0R_Xt; 103310037SARM gem5 Developers case 3: 103410037SARM gem5 Developers return MISCREG_AT_S1E0W_Xt; 103510037SARM gem5 Developers } 103610037SARM gem5 Developers break; 103710037SARM gem5 Developers case 10: 103810037SARM gem5 Developers switch (op2) { 103910037SARM gem5 Developers case 2: 104010037SARM gem5 Developers return MISCREG_DC_CSW_Xt; 104110037SARM gem5 Developers } 104210037SARM gem5 Developers break; 104310037SARM gem5 Developers case 14: 104410037SARM gem5 Developers switch (op2) { 104510037SARM gem5 Developers case 2: 104610037SARM gem5 Developers return MISCREG_DC_CISW_Xt; 104710037SARM gem5 Developers } 104810037SARM gem5 Developers break; 104910037SARM gem5 Developers } 105010037SARM gem5 Developers break; 105110037SARM gem5 Developers case 3: 105210037SARM gem5 Developers switch (crm) { 105310037SARM gem5 Developers case 4: 105410037SARM gem5 Developers switch (op2) { 105510037SARM gem5 Developers case 1: 105610037SARM gem5 Developers return MISCREG_DC_ZVA_Xt; 105710037SARM gem5 Developers } 105810037SARM gem5 Developers break; 105910037SARM gem5 Developers case 5: 106010037SARM gem5 Developers switch (op2) { 106110037SARM gem5 Developers case 1: 106210037SARM gem5 Developers return MISCREG_IC_IVAU_Xt; 106310037SARM gem5 Developers } 106410037SARM gem5 Developers break; 106510037SARM gem5 Developers case 10: 106610037SARM gem5 Developers switch (op2) { 106710037SARM gem5 Developers case 1: 106810037SARM gem5 Developers return MISCREG_DC_CVAC_Xt; 106910037SARM gem5 Developers } 107010037SARM gem5 Developers break; 107110037SARM gem5 Developers case 11: 107210037SARM gem5 Developers switch (op2) { 107310037SARM gem5 Developers case 1: 107410037SARM gem5 Developers return MISCREG_DC_CVAU_Xt; 107510037SARM gem5 Developers } 107610037SARM gem5 Developers break; 107710037SARM gem5 Developers case 14: 107810037SARM gem5 Developers switch (op2) { 107910037SARM gem5 Developers case 1: 108010037SARM gem5 Developers return MISCREG_DC_CIVAC_Xt; 108110037SARM gem5 Developers } 108210037SARM gem5 Developers break; 108310037SARM gem5 Developers } 108410037SARM gem5 Developers break; 108510037SARM gem5 Developers case 4: 108610037SARM gem5 Developers switch (crm) { 108710037SARM gem5 Developers case 8: 108810037SARM gem5 Developers switch (op2) { 108910037SARM gem5 Developers case 0: 109010037SARM gem5 Developers return MISCREG_AT_S1E2R_Xt; 109110037SARM gem5 Developers case 1: 109210037SARM gem5 Developers return MISCREG_AT_S1E2W_Xt; 109310037SARM gem5 Developers case 4: 109410037SARM gem5 Developers return MISCREG_AT_S12E1R_Xt; 109510037SARM gem5 Developers case 5: 109610037SARM gem5 Developers return MISCREG_AT_S12E1W_Xt; 109710037SARM gem5 Developers case 6: 109810037SARM gem5 Developers return MISCREG_AT_S12E0R_Xt; 109910037SARM gem5 Developers case 7: 110010037SARM gem5 Developers return MISCREG_AT_S12E0W_Xt; 110110037SARM gem5 Developers } 110210037SARM gem5 Developers break; 110310037SARM gem5 Developers } 110410037SARM gem5 Developers break; 110510037SARM gem5 Developers case 6: 110610037SARM gem5 Developers switch (crm) { 110710037SARM gem5 Developers case 8: 110810037SARM gem5 Developers switch (op2) { 110910037SARM gem5 Developers case 0: 111010037SARM gem5 Developers return MISCREG_AT_S1E3R_Xt; 111110037SARM gem5 Developers case 1: 111210037SARM gem5 Developers return MISCREG_AT_S1E3W_Xt; 111310037SARM gem5 Developers } 111410037SARM gem5 Developers break; 111510037SARM gem5 Developers } 111610037SARM gem5 Developers break; 111710037SARM gem5 Developers } 111810037SARM gem5 Developers break; 111910037SARM gem5 Developers case 8: 112010037SARM gem5 Developers switch (op1) { 112110037SARM gem5 Developers case 0: 112210037SARM gem5 Developers switch (crm) { 112310037SARM gem5 Developers case 3: 112410037SARM gem5 Developers switch (op2) { 112510037SARM gem5 Developers case 0: 112610037SARM gem5 Developers return MISCREG_TLBI_VMALLE1IS; 112710037SARM gem5 Developers case 1: 112810037SARM gem5 Developers return MISCREG_TLBI_VAE1IS_Xt; 112910037SARM gem5 Developers case 2: 113010037SARM gem5 Developers return MISCREG_TLBI_ASIDE1IS_Xt; 113110037SARM gem5 Developers case 3: 113210037SARM gem5 Developers return MISCREG_TLBI_VAAE1IS_Xt; 113310037SARM gem5 Developers case 5: 113410037SARM gem5 Developers return MISCREG_TLBI_VALE1IS_Xt; 113510037SARM gem5 Developers case 7: 113610037SARM gem5 Developers return MISCREG_TLBI_VAALE1IS_Xt; 113710037SARM gem5 Developers } 113810037SARM gem5 Developers break; 113910037SARM gem5 Developers case 7: 114010037SARM gem5 Developers switch (op2) { 114110037SARM gem5 Developers case 0: 114210037SARM gem5 Developers return MISCREG_TLBI_VMALLE1; 114310037SARM gem5 Developers case 1: 114410037SARM gem5 Developers return MISCREG_TLBI_VAE1_Xt; 114510037SARM gem5 Developers case 2: 114610037SARM gem5 Developers return MISCREG_TLBI_ASIDE1_Xt; 114710037SARM gem5 Developers case 3: 114810037SARM gem5 Developers return MISCREG_TLBI_VAAE1_Xt; 114910037SARM gem5 Developers case 5: 115010037SARM gem5 Developers return MISCREG_TLBI_VALE1_Xt; 115110037SARM gem5 Developers case 7: 115210037SARM gem5 Developers return MISCREG_TLBI_VAALE1_Xt; 115310037SARM gem5 Developers } 115410037SARM gem5 Developers break; 115510037SARM gem5 Developers } 115610037SARM gem5 Developers break; 115710037SARM gem5 Developers case 4: 115810037SARM gem5 Developers switch (crm) { 115910037SARM gem5 Developers case 0: 116010037SARM gem5 Developers switch (op2) { 116110037SARM gem5 Developers case 1: 116210037SARM gem5 Developers return MISCREG_TLBI_IPAS2E1IS_Xt; 116310037SARM gem5 Developers case 5: 116410037SARM gem5 Developers return MISCREG_TLBI_IPAS2LE1IS_Xt; 116510037SARM gem5 Developers } 116610037SARM gem5 Developers break; 116710037SARM gem5 Developers case 3: 116810037SARM gem5 Developers switch (op2) { 116910037SARM gem5 Developers case 0: 117010037SARM gem5 Developers return MISCREG_TLBI_ALLE2IS; 117110037SARM gem5 Developers case 1: 117210037SARM gem5 Developers return MISCREG_TLBI_VAE2IS_Xt; 117310037SARM gem5 Developers case 4: 117410037SARM gem5 Developers return MISCREG_TLBI_ALLE1IS; 117510037SARM gem5 Developers case 5: 117610037SARM gem5 Developers return MISCREG_TLBI_VALE2IS_Xt; 117710037SARM gem5 Developers case 6: 117810037SARM gem5 Developers return MISCREG_TLBI_VMALLS12E1IS; 117910037SARM gem5 Developers } 118010037SARM gem5 Developers break; 118110037SARM gem5 Developers case 4: 118210037SARM gem5 Developers switch (op2) { 118310037SARM gem5 Developers case 1: 118410037SARM gem5 Developers return MISCREG_TLBI_IPAS2E1_Xt; 118510037SARM gem5 Developers case 5: 118610037SARM gem5 Developers return MISCREG_TLBI_IPAS2LE1_Xt; 118710037SARM gem5 Developers } 118810037SARM gem5 Developers break; 118910037SARM gem5 Developers case 7: 119010037SARM gem5 Developers switch (op2) { 119110037SARM gem5 Developers case 0: 119210037SARM gem5 Developers return MISCREG_TLBI_ALLE2; 119310037SARM gem5 Developers case 1: 119410037SARM gem5 Developers return MISCREG_TLBI_VAE2_Xt; 119510037SARM gem5 Developers case 4: 119610037SARM gem5 Developers return MISCREG_TLBI_ALLE1; 119710037SARM gem5 Developers case 5: 119810037SARM gem5 Developers return MISCREG_TLBI_VALE2_Xt; 119910037SARM gem5 Developers case 6: 120010037SARM gem5 Developers return MISCREG_TLBI_VMALLS12E1; 120110037SARM gem5 Developers } 120210037SARM gem5 Developers break; 120310037SARM gem5 Developers } 120410037SARM gem5 Developers break; 120510037SARM gem5 Developers case 6: 120610037SARM gem5 Developers switch (crm) { 120710037SARM gem5 Developers case 3: 120810037SARM gem5 Developers switch (op2) { 120910037SARM gem5 Developers case 0: 121010037SARM gem5 Developers return MISCREG_TLBI_ALLE3IS; 121110037SARM gem5 Developers case 1: 121210037SARM gem5 Developers return MISCREG_TLBI_VAE3IS_Xt; 121310037SARM gem5 Developers case 5: 121410037SARM gem5 Developers return MISCREG_TLBI_VALE3IS_Xt; 121510037SARM gem5 Developers } 121610037SARM gem5 Developers break; 121710037SARM gem5 Developers case 7: 121810037SARM gem5 Developers switch (op2) { 121910037SARM gem5 Developers case 0: 122010037SARM gem5 Developers return MISCREG_TLBI_ALLE3; 122110037SARM gem5 Developers case 1: 122210037SARM gem5 Developers return MISCREG_TLBI_VAE3_Xt; 122310037SARM gem5 Developers case 5: 122410037SARM gem5 Developers return MISCREG_TLBI_VALE3_Xt; 122510037SARM gem5 Developers } 122610037SARM gem5 Developers break; 122710037SARM gem5 Developers } 122810037SARM gem5 Developers break; 122910037SARM gem5 Developers } 123010037SARM gem5 Developers break; 123110037SARM gem5 Developers } 123210037SARM gem5 Developers break; 123310037SARM gem5 Developers case 2: 123410037SARM gem5 Developers switch (crn) { 123510037SARM gem5 Developers case 0: 123610037SARM gem5 Developers switch (op1) { 123710037SARM gem5 Developers case 0: 123810037SARM gem5 Developers switch (crm) { 123910037SARM gem5 Developers case 0: 124010037SARM gem5 Developers switch (op2) { 124110037SARM gem5 Developers case 2: 124210037SARM gem5 Developers return MISCREG_OSDTRRX_EL1; 124310037SARM gem5 Developers case 4: 124410037SARM gem5 Developers return MISCREG_DBGBVR0_EL1; 124510037SARM gem5 Developers case 5: 124610037SARM gem5 Developers return MISCREG_DBGBCR0_EL1; 124710037SARM gem5 Developers case 6: 124810037SARM gem5 Developers return MISCREG_DBGWVR0_EL1; 124910037SARM gem5 Developers case 7: 125010037SARM gem5 Developers return MISCREG_DBGWCR0_EL1; 125110037SARM gem5 Developers } 125210037SARM gem5 Developers break; 125310037SARM gem5 Developers case 1: 125410037SARM gem5 Developers switch (op2) { 125510037SARM gem5 Developers case 4: 125610037SARM gem5 Developers return MISCREG_DBGBVR1_EL1; 125710037SARM gem5 Developers case 5: 125810037SARM gem5 Developers return MISCREG_DBGBCR1_EL1; 125910037SARM gem5 Developers case 6: 126010037SARM gem5 Developers return MISCREG_DBGWVR1_EL1; 126110037SARM gem5 Developers case 7: 126210037SARM gem5 Developers return MISCREG_DBGWCR1_EL1; 126310037SARM gem5 Developers } 126410037SARM gem5 Developers break; 126510037SARM gem5 Developers case 2: 126610037SARM gem5 Developers switch (op2) { 126710037SARM gem5 Developers case 0: 126810037SARM gem5 Developers return MISCREG_MDCCINT_EL1; 126910037SARM gem5 Developers case 2: 127010037SARM gem5 Developers return MISCREG_MDSCR_EL1; 127110037SARM gem5 Developers case 4: 127210037SARM gem5 Developers return MISCREG_DBGBVR2_EL1; 127310037SARM gem5 Developers case 5: 127410037SARM gem5 Developers return MISCREG_DBGBCR2_EL1; 127510037SARM gem5 Developers case 6: 127610037SARM gem5 Developers return MISCREG_DBGWVR2_EL1; 127710037SARM gem5 Developers case 7: 127810037SARM gem5 Developers return MISCREG_DBGWCR2_EL1; 127910037SARM gem5 Developers } 128010037SARM gem5 Developers break; 128110037SARM gem5 Developers case 3: 128210037SARM gem5 Developers switch (op2) { 128310037SARM gem5 Developers case 2: 128410037SARM gem5 Developers return MISCREG_OSDTRTX_EL1; 128510037SARM gem5 Developers case 4: 128610037SARM gem5 Developers return MISCREG_DBGBVR3_EL1; 128710037SARM gem5 Developers case 5: 128810037SARM gem5 Developers return MISCREG_DBGBCR3_EL1; 128910037SARM gem5 Developers case 6: 129010037SARM gem5 Developers return MISCREG_DBGWVR3_EL1; 129110037SARM gem5 Developers case 7: 129210037SARM gem5 Developers return MISCREG_DBGWCR3_EL1; 129310037SARM gem5 Developers } 129410037SARM gem5 Developers break; 129510037SARM gem5 Developers case 4: 129610037SARM gem5 Developers switch (op2) { 129710037SARM gem5 Developers case 4: 129810037SARM gem5 Developers return MISCREG_DBGBVR4_EL1; 129910037SARM gem5 Developers case 5: 130010037SARM gem5 Developers return MISCREG_DBGBCR4_EL1; 130110037SARM gem5 Developers } 130210037SARM gem5 Developers break; 130310037SARM gem5 Developers case 5: 130410037SARM gem5 Developers switch (op2) { 130510037SARM gem5 Developers case 4: 130610037SARM gem5 Developers return MISCREG_DBGBVR5_EL1; 130710037SARM gem5 Developers case 5: 130810037SARM gem5 Developers return MISCREG_DBGBCR5_EL1; 130910037SARM gem5 Developers } 131010037SARM gem5 Developers break; 131110037SARM gem5 Developers case 6: 131210037SARM gem5 Developers switch (op2) { 131310037SARM gem5 Developers case 2: 131410037SARM gem5 Developers return MISCREG_OSECCR_EL1; 131510037SARM gem5 Developers } 131610037SARM gem5 Developers break; 131710037SARM gem5 Developers } 131810037SARM gem5 Developers break; 131910037SARM gem5 Developers case 2: 132010037SARM gem5 Developers switch (crm) { 132110037SARM gem5 Developers case 0: 132210037SARM gem5 Developers switch (op2) { 132310037SARM gem5 Developers case 0: 132410037SARM gem5 Developers return MISCREG_TEECR32_EL1; 132510037SARM gem5 Developers } 132610037SARM gem5 Developers break; 132710037SARM gem5 Developers } 132810037SARM gem5 Developers break; 132910037SARM gem5 Developers case 3: 133010037SARM gem5 Developers switch (crm) { 133110037SARM gem5 Developers case 1: 133210037SARM gem5 Developers switch (op2) { 133310037SARM gem5 Developers case 0: 133410037SARM gem5 Developers return MISCREG_MDCCSR_EL0; 133510037SARM gem5 Developers } 133610037SARM gem5 Developers break; 133710037SARM gem5 Developers case 4: 133810037SARM gem5 Developers switch (op2) { 133910037SARM gem5 Developers case 0: 134010037SARM gem5 Developers return MISCREG_MDDTR_EL0; 134110037SARM gem5 Developers } 134210037SARM gem5 Developers break; 134310037SARM gem5 Developers case 5: 134410037SARM gem5 Developers switch (op2) { 134510037SARM gem5 Developers case 0: 134610037SARM gem5 Developers return MISCREG_MDDTRRX_EL0; 134710037SARM gem5 Developers } 134810037SARM gem5 Developers break; 134910037SARM gem5 Developers } 135010037SARM gem5 Developers break; 135110037SARM gem5 Developers case 4: 135210037SARM gem5 Developers switch (crm) { 135310037SARM gem5 Developers case 7: 135410037SARM gem5 Developers switch (op2) { 135510037SARM gem5 Developers case 0: 135610037SARM gem5 Developers return MISCREG_DBGVCR32_EL2; 135710037SARM gem5 Developers } 135810037SARM gem5 Developers break; 135910037SARM gem5 Developers } 136010037SARM gem5 Developers break; 136110037SARM gem5 Developers } 136210037SARM gem5 Developers break; 136310037SARM gem5 Developers case 1: 136410037SARM gem5 Developers switch (op1) { 136510037SARM gem5 Developers case 0: 136610037SARM gem5 Developers switch (crm) { 136710037SARM gem5 Developers case 0: 136810037SARM gem5 Developers switch (op2) { 136910037SARM gem5 Developers case 0: 137010037SARM gem5 Developers return MISCREG_MDRAR_EL1; 137110037SARM gem5 Developers case 4: 137210037SARM gem5 Developers return MISCREG_OSLAR_EL1; 137310037SARM gem5 Developers } 137410037SARM gem5 Developers break; 137510037SARM gem5 Developers case 1: 137610037SARM gem5 Developers switch (op2) { 137710037SARM gem5 Developers case 4: 137810037SARM gem5 Developers return MISCREG_OSLSR_EL1; 137910037SARM gem5 Developers } 138010037SARM gem5 Developers break; 138110037SARM gem5 Developers case 3: 138210037SARM gem5 Developers switch (op2) { 138310037SARM gem5 Developers case 4: 138410037SARM gem5 Developers return MISCREG_OSDLR_EL1; 138510037SARM gem5 Developers } 138610037SARM gem5 Developers break; 138710037SARM gem5 Developers case 4: 138810037SARM gem5 Developers switch (op2) { 138910037SARM gem5 Developers case 4: 139010037SARM gem5 Developers return MISCREG_DBGPRCR_EL1; 139110037SARM gem5 Developers } 139210037SARM gem5 Developers break; 139310037SARM gem5 Developers } 139410037SARM gem5 Developers break; 139510037SARM gem5 Developers case 2: 139610037SARM gem5 Developers switch (crm) { 139710037SARM gem5 Developers case 0: 139810037SARM gem5 Developers switch (op2) { 139910037SARM gem5 Developers case 0: 140010037SARM gem5 Developers return MISCREG_TEEHBR32_EL1; 140110037SARM gem5 Developers } 140210037SARM gem5 Developers break; 140310037SARM gem5 Developers } 140410037SARM gem5 Developers break; 140510037SARM gem5 Developers } 140610037SARM gem5 Developers break; 140710037SARM gem5 Developers case 7: 140810037SARM gem5 Developers switch (op1) { 140910037SARM gem5 Developers case 0: 141010037SARM gem5 Developers switch (crm) { 141110037SARM gem5 Developers case 8: 141210037SARM gem5 Developers switch (op2) { 141310037SARM gem5 Developers case 6: 141410037SARM gem5 Developers return MISCREG_DBGCLAIMSET_EL1; 141510037SARM gem5 Developers } 141610037SARM gem5 Developers break; 141710037SARM gem5 Developers case 9: 141810037SARM gem5 Developers switch (op2) { 141910037SARM gem5 Developers case 6: 142010037SARM gem5 Developers return MISCREG_DBGCLAIMCLR_EL1; 142110037SARM gem5 Developers } 142210037SARM gem5 Developers break; 142310037SARM gem5 Developers case 14: 142410037SARM gem5 Developers switch (op2) { 142510037SARM gem5 Developers case 6: 142610037SARM gem5 Developers return MISCREG_DBGAUTHSTATUS_EL1; 142710037SARM gem5 Developers } 142810037SARM gem5 Developers break; 142910037SARM gem5 Developers } 143010037SARM gem5 Developers break; 143110037SARM gem5 Developers } 143210037SARM gem5 Developers break; 143310037SARM gem5 Developers } 143410037SARM gem5 Developers break; 143510037SARM gem5 Developers case 3: 143610037SARM gem5 Developers switch (crn) { 143710037SARM gem5 Developers case 0: 143810037SARM gem5 Developers switch (op1) { 143910037SARM gem5 Developers case 0: 144010037SARM gem5 Developers switch (crm) { 144110037SARM gem5 Developers case 0: 144210037SARM gem5 Developers switch (op2) { 144310037SARM gem5 Developers case 0: 144410037SARM gem5 Developers return MISCREG_MIDR_EL1; 144510037SARM gem5 Developers case 5: 144610037SARM gem5 Developers return MISCREG_MPIDR_EL1; 144710037SARM gem5 Developers case 6: 144810037SARM gem5 Developers return MISCREG_REVIDR_EL1; 144910037SARM gem5 Developers } 145010037SARM gem5 Developers break; 145110037SARM gem5 Developers case 1: 145210037SARM gem5 Developers switch (op2) { 145310037SARM gem5 Developers case 0: 145410037SARM gem5 Developers return MISCREG_ID_PFR0_EL1; 145510037SARM gem5 Developers case 1: 145610037SARM gem5 Developers return MISCREG_ID_PFR1_EL1; 145710037SARM gem5 Developers case 2: 145810037SARM gem5 Developers return MISCREG_ID_DFR0_EL1; 145910037SARM gem5 Developers case 3: 146010037SARM gem5 Developers return MISCREG_ID_AFR0_EL1; 146110037SARM gem5 Developers case 4: 146210037SARM gem5 Developers return MISCREG_ID_MMFR0_EL1; 146310037SARM gem5 Developers case 5: 146410037SARM gem5 Developers return MISCREG_ID_MMFR1_EL1; 146510037SARM gem5 Developers case 6: 146610037SARM gem5 Developers return MISCREG_ID_MMFR2_EL1; 146710037SARM gem5 Developers case 7: 146810037SARM gem5 Developers return MISCREG_ID_MMFR3_EL1; 146910037SARM gem5 Developers } 147010037SARM gem5 Developers break; 147110037SARM gem5 Developers case 2: 147210037SARM gem5 Developers switch (op2) { 147310037SARM gem5 Developers case 0: 147410037SARM gem5 Developers return MISCREG_ID_ISAR0_EL1; 147510037SARM gem5 Developers case 1: 147610037SARM gem5 Developers return MISCREG_ID_ISAR1_EL1; 147710037SARM gem5 Developers case 2: 147810037SARM gem5 Developers return MISCREG_ID_ISAR2_EL1; 147910037SARM gem5 Developers case 3: 148010037SARM gem5 Developers return MISCREG_ID_ISAR3_EL1; 148110037SARM gem5 Developers case 4: 148210037SARM gem5 Developers return MISCREG_ID_ISAR4_EL1; 148310037SARM gem5 Developers case 5: 148410037SARM gem5 Developers return MISCREG_ID_ISAR5_EL1; 148510037SARM gem5 Developers } 148610037SARM gem5 Developers break; 148710037SARM gem5 Developers case 3: 148810037SARM gem5 Developers switch (op2) { 148910037SARM gem5 Developers case 0: 149010037SARM gem5 Developers return MISCREG_MVFR0_EL1; 149110037SARM gem5 Developers case 1: 149210037SARM gem5 Developers return MISCREG_MVFR1_EL1; 149310037SARM gem5 Developers case 2: 149410037SARM gem5 Developers return MISCREG_MVFR2_EL1; 149510037SARM gem5 Developers case 3 ... 7: 149610037SARM gem5 Developers return MISCREG_RAZ; 149710037SARM gem5 Developers } 149810037SARM gem5 Developers break; 149910037SARM gem5 Developers case 4: 150010037SARM gem5 Developers switch (op2) { 150110037SARM gem5 Developers case 0: 150210037SARM gem5 Developers return MISCREG_ID_AA64PFR0_EL1; 150310037SARM gem5 Developers case 1: 150410037SARM gem5 Developers return MISCREG_ID_AA64PFR1_EL1; 150510037SARM gem5 Developers case 2 ... 7: 150610037SARM gem5 Developers return MISCREG_RAZ; 150710037SARM gem5 Developers } 150810037SARM gem5 Developers break; 150910037SARM gem5 Developers case 5: 151010037SARM gem5 Developers switch (op2) { 151110037SARM gem5 Developers case 0: 151210037SARM gem5 Developers return MISCREG_ID_AA64DFR0_EL1; 151310037SARM gem5 Developers case 1: 151410037SARM gem5 Developers return MISCREG_ID_AA64DFR1_EL1; 151510037SARM gem5 Developers case 4: 151610037SARM gem5 Developers return MISCREG_ID_AA64AFR0_EL1; 151710037SARM gem5 Developers case 5: 151810037SARM gem5 Developers return MISCREG_ID_AA64AFR1_EL1; 151910037SARM gem5 Developers case 2: 152010037SARM gem5 Developers case 3: 152110037SARM gem5 Developers case 6: 152210037SARM gem5 Developers case 7: 152310037SARM gem5 Developers return MISCREG_RAZ; 152410037SARM gem5 Developers } 152510037SARM gem5 Developers break; 152610037SARM gem5 Developers case 6: 152710037SARM gem5 Developers switch (op2) { 152810037SARM gem5 Developers case 0: 152910037SARM gem5 Developers return MISCREG_ID_AA64ISAR0_EL1; 153010037SARM gem5 Developers case 1: 153110037SARM gem5 Developers return MISCREG_ID_AA64ISAR1_EL1; 153210037SARM gem5 Developers case 2 ... 7: 153310037SARM gem5 Developers return MISCREG_RAZ; 153410037SARM gem5 Developers } 153510037SARM gem5 Developers break; 153610037SARM gem5 Developers case 7: 153710037SARM gem5 Developers switch (op2) { 153810037SARM gem5 Developers case 0: 153910037SARM gem5 Developers return MISCREG_ID_AA64MMFR0_EL1; 154010037SARM gem5 Developers case 1: 154110037SARM gem5 Developers return MISCREG_ID_AA64MMFR1_EL1; 154213116Sgiacomo.travaglini@arm.com case 2: 154313116Sgiacomo.travaglini@arm.com return MISCREG_ID_AA64MMFR2_EL1; 154413116Sgiacomo.travaglini@arm.com case 3 ... 7: 154510037SARM gem5 Developers return MISCREG_RAZ; 154610037SARM gem5 Developers } 154710037SARM gem5 Developers break; 154810037SARM gem5 Developers } 154910037SARM gem5 Developers break; 155010037SARM gem5 Developers case 1: 155110037SARM gem5 Developers switch (crm) { 155210037SARM gem5 Developers case 0: 155310037SARM gem5 Developers switch (op2) { 155410037SARM gem5 Developers case 0: 155510037SARM gem5 Developers return MISCREG_CCSIDR_EL1; 155610037SARM gem5 Developers case 1: 155710037SARM gem5 Developers return MISCREG_CLIDR_EL1; 155810037SARM gem5 Developers case 7: 155910037SARM gem5 Developers return MISCREG_AIDR_EL1; 156010037SARM gem5 Developers } 156110037SARM gem5 Developers break; 156210037SARM gem5 Developers } 156310037SARM gem5 Developers break; 156410037SARM gem5 Developers case 2: 156510037SARM gem5 Developers switch (crm) { 156610037SARM gem5 Developers case 0: 156710037SARM gem5 Developers switch (op2) { 156810037SARM gem5 Developers case 0: 156910037SARM gem5 Developers return MISCREG_CSSELR_EL1; 157010037SARM gem5 Developers } 157110037SARM gem5 Developers break; 157210037SARM gem5 Developers } 157310037SARM gem5 Developers break; 157410037SARM gem5 Developers case 3: 157510037SARM gem5 Developers switch (crm) { 157610037SARM gem5 Developers case 0: 157710037SARM gem5 Developers switch (op2) { 157810037SARM gem5 Developers case 1: 157910037SARM gem5 Developers return MISCREG_CTR_EL0; 158010037SARM gem5 Developers case 7: 158110037SARM gem5 Developers return MISCREG_DCZID_EL0; 158210037SARM gem5 Developers } 158310037SARM gem5 Developers break; 158410037SARM gem5 Developers } 158510037SARM gem5 Developers break; 158610037SARM gem5 Developers case 4: 158710037SARM gem5 Developers switch (crm) { 158810037SARM gem5 Developers case 0: 158910037SARM gem5 Developers switch (op2) { 159010037SARM gem5 Developers case 0: 159110037SARM gem5 Developers return MISCREG_VPIDR_EL2; 159210037SARM gem5 Developers case 5: 159310037SARM gem5 Developers return MISCREG_VMPIDR_EL2; 159410037SARM gem5 Developers } 159510037SARM gem5 Developers break; 159610037SARM gem5 Developers } 159710037SARM gem5 Developers break; 159810037SARM gem5 Developers } 159910037SARM gem5 Developers break; 160010037SARM gem5 Developers case 1: 160110037SARM gem5 Developers switch (op1) { 160210037SARM gem5 Developers case 0: 160310037SARM gem5 Developers switch (crm) { 160410037SARM gem5 Developers case 0: 160510037SARM gem5 Developers switch (op2) { 160610037SARM gem5 Developers case 0: 160710037SARM gem5 Developers return MISCREG_SCTLR_EL1; 160810037SARM gem5 Developers case 1: 160910037SARM gem5 Developers return MISCREG_ACTLR_EL1; 161010037SARM gem5 Developers case 2: 161110037SARM gem5 Developers return MISCREG_CPACR_EL1; 161210037SARM gem5 Developers } 161310037SARM gem5 Developers break; 161410037SARM gem5 Developers } 161510037SARM gem5 Developers break; 161610037SARM gem5 Developers case 4: 161710037SARM gem5 Developers switch (crm) { 161810037SARM gem5 Developers case 0: 161910037SARM gem5 Developers switch (op2) { 162010037SARM gem5 Developers case 0: 162110037SARM gem5 Developers return MISCREG_SCTLR_EL2; 162210037SARM gem5 Developers case 1: 162310037SARM gem5 Developers return MISCREG_ACTLR_EL2; 162410037SARM gem5 Developers } 162510037SARM gem5 Developers break; 162610037SARM gem5 Developers case 1: 162710037SARM gem5 Developers switch (op2) { 162810037SARM gem5 Developers case 0: 162910037SARM gem5 Developers return MISCREG_HCR_EL2; 163010037SARM gem5 Developers case 1: 163110037SARM gem5 Developers return MISCREG_MDCR_EL2; 163210037SARM gem5 Developers case 2: 163310037SARM gem5 Developers return MISCREG_CPTR_EL2; 163410037SARM gem5 Developers case 3: 163510037SARM gem5 Developers return MISCREG_HSTR_EL2; 163610037SARM gem5 Developers case 7: 163710037SARM gem5 Developers return MISCREG_HACR_EL2; 163810037SARM gem5 Developers } 163910037SARM gem5 Developers break; 164010037SARM gem5 Developers } 164110037SARM gem5 Developers break; 164210037SARM gem5 Developers case 6: 164310037SARM gem5 Developers switch (crm) { 164410037SARM gem5 Developers case 0: 164510037SARM gem5 Developers switch (op2) { 164610037SARM gem5 Developers case 0: 164710037SARM gem5 Developers return MISCREG_SCTLR_EL3; 164810037SARM gem5 Developers case 1: 164910037SARM gem5 Developers return MISCREG_ACTLR_EL3; 165010037SARM gem5 Developers } 165110037SARM gem5 Developers break; 165210037SARM gem5 Developers case 1: 165310037SARM gem5 Developers switch (op2) { 165410037SARM gem5 Developers case 0: 165510037SARM gem5 Developers return MISCREG_SCR_EL3; 165610037SARM gem5 Developers case 1: 165710037SARM gem5 Developers return MISCREG_SDER32_EL3; 165810037SARM gem5 Developers case 2: 165910037SARM gem5 Developers return MISCREG_CPTR_EL3; 166010037SARM gem5 Developers } 166110037SARM gem5 Developers break; 166210037SARM gem5 Developers case 3: 166310037SARM gem5 Developers switch (op2) { 166410037SARM gem5 Developers case 1: 166510037SARM gem5 Developers return MISCREG_MDCR_EL3; 166610037SARM gem5 Developers } 166710037SARM gem5 Developers break; 166810037SARM gem5 Developers } 166910037SARM gem5 Developers break; 167010037SARM gem5 Developers } 167110037SARM gem5 Developers break; 167210037SARM gem5 Developers case 2: 167310037SARM gem5 Developers switch (op1) { 167410037SARM gem5 Developers case 0: 167510037SARM gem5 Developers switch (crm) { 167610037SARM gem5 Developers case 0: 167710037SARM gem5 Developers switch (op2) { 167810037SARM gem5 Developers case 0: 167910037SARM gem5 Developers return MISCREG_TTBR0_EL1; 168010037SARM gem5 Developers case 1: 168110037SARM gem5 Developers return MISCREG_TTBR1_EL1; 168210037SARM gem5 Developers case 2: 168310037SARM gem5 Developers return MISCREG_TCR_EL1; 168410037SARM gem5 Developers } 168510037SARM gem5 Developers break; 168610037SARM gem5 Developers } 168710037SARM gem5 Developers break; 168810037SARM gem5 Developers case 4: 168910037SARM gem5 Developers switch (crm) { 169010037SARM gem5 Developers case 0: 169110037SARM gem5 Developers switch (op2) { 169210037SARM gem5 Developers case 0: 169310037SARM gem5 Developers return MISCREG_TTBR0_EL2; 169412675Sgiacomo.travaglini@arm.com case 1: 169512675Sgiacomo.travaglini@arm.com return MISCREG_TTBR1_EL2; 169610037SARM gem5 Developers case 2: 169710037SARM gem5 Developers return MISCREG_TCR_EL2; 169810037SARM gem5 Developers } 169910037SARM gem5 Developers break; 170010037SARM gem5 Developers case 1: 170110037SARM gem5 Developers switch (op2) { 170210037SARM gem5 Developers case 0: 170310037SARM gem5 Developers return MISCREG_VTTBR_EL2; 170410037SARM gem5 Developers case 2: 170510037SARM gem5 Developers return MISCREG_VTCR_EL2; 170610037SARM gem5 Developers } 170710037SARM gem5 Developers break; 170810037SARM gem5 Developers } 170910037SARM gem5 Developers break; 171010037SARM gem5 Developers case 6: 171110037SARM gem5 Developers switch (crm) { 171210037SARM gem5 Developers case 0: 171310037SARM gem5 Developers switch (op2) { 171410037SARM gem5 Developers case 0: 171510037SARM gem5 Developers return MISCREG_TTBR0_EL3; 171610037SARM gem5 Developers case 2: 171710037SARM gem5 Developers return MISCREG_TCR_EL3; 171810037SARM gem5 Developers } 171910037SARM gem5 Developers break; 172010037SARM gem5 Developers } 172110037SARM gem5 Developers break; 172210037SARM gem5 Developers } 172310037SARM gem5 Developers break; 172410037SARM gem5 Developers case 3: 172510037SARM gem5 Developers switch (op1) { 172610037SARM gem5 Developers case 4: 172710037SARM gem5 Developers switch (crm) { 172810037SARM gem5 Developers case 0: 172910037SARM gem5 Developers switch (op2) { 173010037SARM gem5 Developers case 0: 173110037SARM gem5 Developers return MISCREG_DACR32_EL2; 173210037SARM gem5 Developers } 173310037SARM gem5 Developers break; 173410037SARM gem5 Developers } 173510037SARM gem5 Developers break; 173610037SARM gem5 Developers } 173710037SARM gem5 Developers break; 173810037SARM gem5 Developers case 4: 173910037SARM gem5 Developers switch (op1) { 174010037SARM gem5 Developers case 0: 174110037SARM gem5 Developers switch (crm) { 174210037SARM gem5 Developers case 0: 174310037SARM gem5 Developers switch (op2) { 174410037SARM gem5 Developers case 0: 174510037SARM gem5 Developers return MISCREG_SPSR_EL1; 174610037SARM gem5 Developers case 1: 174710037SARM gem5 Developers return MISCREG_ELR_EL1; 174810037SARM gem5 Developers } 174910037SARM gem5 Developers break; 175010037SARM gem5 Developers case 1: 175110037SARM gem5 Developers switch (op2) { 175210037SARM gem5 Developers case 0: 175310037SARM gem5 Developers return MISCREG_SP_EL0; 175410037SARM gem5 Developers } 175510037SARM gem5 Developers break; 175610037SARM gem5 Developers case 2: 175710037SARM gem5 Developers switch (op2) { 175810037SARM gem5 Developers case 0: 175910037SARM gem5 Developers return MISCREG_SPSEL; 176010037SARM gem5 Developers case 2: 176110037SARM gem5 Developers return MISCREG_CURRENTEL; 176210037SARM gem5 Developers } 176310037SARM gem5 Developers break; 176410037SARM gem5 Developers } 176510037SARM gem5 Developers break; 176610037SARM gem5 Developers case 3: 176710037SARM gem5 Developers switch (crm) { 176810037SARM gem5 Developers case 2: 176910037SARM gem5 Developers switch (op2) { 177010037SARM gem5 Developers case 0: 177110037SARM gem5 Developers return MISCREG_NZCV; 177210037SARM gem5 Developers case 1: 177310037SARM gem5 Developers return MISCREG_DAIF; 177410037SARM gem5 Developers } 177510037SARM gem5 Developers break; 177610037SARM gem5 Developers case 4: 177710037SARM gem5 Developers switch (op2) { 177810037SARM gem5 Developers case 0: 177910037SARM gem5 Developers return MISCREG_FPCR; 178010037SARM gem5 Developers case 1: 178110037SARM gem5 Developers return MISCREG_FPSR; 178210037SARM gem5 Developers } 178310037SARM gem5 Developers break; 178410037SARM gem5 Developers case 5: 178510037SARM gem5 Developers switch (op2) { 178610037SARM gem5 Developers case 0: 178710037SARM gem5 Developers return MISCREG_DSPSR_EL0; 178810037SARM gem5 Developers case 1: 178910037SARM gem5 Developers return MISCREG_DLR_EL0; 179010037SARM gem5 Developers } 179110037SARM gem5 Developers break; 179210037SARM gem5 Developers } 179310037SARM gem5 Developers break; 179410037SARM gem5 Developers case 4: 179510037SARM gem5 Developers switch (crm) { 179610037SARM gem5 Developers case 0: 179710037SARM gem5 Developers switch (op2) { 179810037SARM gem5 Developers case 0: 179910037SARM gem5 Developers return MISCREG_SPSR_EL2; 180010037SARM gem5 Developers case 1: 180110037SARM gem5 Developers return MISCREG_ELR_EL2; 180210037SARM gem5 Developers } 180310037SARM gem5 Developers break; 180410037SARM gem5 Developers case 1: 180510037SARM gem5 Developers switch (op2) { 180610037SARM gem5 Developers case 0: 180710037SARM gem5 Developers return MISCREG_SP_EL1; 180810037SARM gem5 Developers } 180910037SARM gem5 Developers break; 181010037SARM gem5 Developers case 3: 181110037SARM gem5 Developers switch (op2) { 181210037SARM gem5 Developers case 0: 181310037SARM gem5 Developers return MISCREG_SPSR_IRQ_AA64; 181410037SARM gem5 Developers case 1: 181510037SARM gem5 Developers return MISCREG_SPSR_ABT_AA64; 181610037SARM gem5 Developers case 2: 181710037SARM gem5 Developers return MISCREG_SPSR_UND_AA64; 181810037SARM gem5 Developers case 3: 181910037SARM gem5 Developers return MISCREG_SPSR_FIQ_AA64; 182010037SARM gem5 Developers } 182110037SARM gem5 Developers break; 182210037SARM gem5 Developers } 182310037SARM gem5 Developers break; 182410037SARM gem5 Developers case 6: 182510037SARM gem5 Developers switch (crm) { 182610037SARM gem5 Developers case 0: 182710037SARM gem5 Developers switch (op2) { 182810037SARM gem5 Developers case 0: 182910037SARM gem5 Developers return MISCREG_SPSR_EL3; 183010037SARM gem5 Developers case 1: 183110037SARM gem5 Developers return MISCREG_ELR_EL3; 183210037SARM gem5 Developers } 183310037SARM gem5 Developers break; 183410037SARM gem5 Developers case 1: 183510037SARM gem5 Developers switch (op2) { 183610037SARM gem5 Developers case 0: 183710037SARM gem5 Developers return MISCREG_SP_EL2; 183810037SARM gem5 Developers } 183910037SARM gem5 Developers break; 184010037SARM gem5 Developers } 184110037SARM gem5 Developers break; 184210037SARM gem5 Developers } 184310037SARM gem5 Developers break; 184410037SARM gem5 Developers case 5: 184510037SARM gem5 Developers switch (op1) { 184610037SARM gem5 Developers case 0: 184710037SARM gem5 Developers switch (crm) { 184810037SARM gem5 Developers case 1: 184910037SARM gem5 Developers switch (op2) { 185010037SARM gem5 Developers case 0: 185110037SARM gem5 Developers return MISCREG_AFSR0_EL1; 185210037SARM gem5 Developers case 1: 185310037SARM gem5 Developers return MISCREG_AFSR1_EL1; 185410037SARM gem5 Developers } 185510037SARM gem5 Developers break; 185610037SARM gem5 Developers case 2: 185710037SARM gem5 Developers switch (op2) { 185810037SARM gem5 Developers case 0: 185910037SARM gem5 Developers return MISCREG_ESR_EL1; 186010037SARM gem5 Developers } 186110037SARM gem5 Developers break; 186212815Sgiacomo.travaglini@arm.com case 3: 186312815Sgiacomo.travaglini@arm.com switch (op2) { 186412815Sgiacomo.travaglini@arm.com case 0: 186512815Sgiacomo.travaglini@arm.com return MISCREG_ERRIDR_EL1; 186612815Sgiacomo.travaglini@arm.com case 1: 186712815Sgiacomo.travaglini@arm.com return MISCREG_ERRSELR_EL1; 186812815Sgiacomo.travaglini@arm.com } 186912815Sgiacomo.travaglini@arm.com break; 187012815Sgiacomo.travaglini@arm.com case 4: 187112815Sgiacomo.travaglini@arm.com switch (op2) { 187212815Sgiacomo.travaglini@arm.com case 0: 187312815Sgiacomo.travaglini@arm.com return MISCREG_ERXFR_EL1; 187412815Sgiacomo.travaglini@arm.com case 1: 187512815Sgiacomo.travaglini@arm.com return MISCREG_ERXCTLR_EL1; 187612815Sgiacomo.travaglini@arm.com case 2: 187712815Sgiacomo.travaglini@arm.com return MISCREG_ERXSTATUS_EL1; 187812815Sgiacomo.travaglini@arm.com case 3: 187912815Sgiacomo.travaglini@arm.com return MISCREG_ERXADDR_EL1; 188012815Sgiacomo.travaglini@arm.com } 188112815Sgiacomo.travaglini@arm.com break; 188212815Sgiacomo.travaglini@arm.com case 5: 188312815Sgiacomo.travaglini@arm.com switch (op2) { 188412815Sgiacomo.travaglini@arm.com case 0: 188512815Sgiacomo.travaglini@arm.com return MISCREG_ERXMISC0_EL1; 188612815Sgiacomo.travaglini@arm.com case 1: 188712815Sgiacomo.travaglini@arm.com return MISCREG_ERXMISC1_EL1; 188812815Sgiacomo.travaglini@arm.com } 188912815Sgiacomo.travaglini@arm.com break; 189010037SARM gem5 Developers } 189110037SARM gem5 Developers break; 189210037SARM gem5 Developers case 4: 189310037SARM gem5 Developers switch (crm) { 189410037SARM gem5 Developers case 0: 189510037SARM gem5 Developers switch (op2) { 189610037SARM gem5 Developers case 1: 189710037SARM gem5 Developers return MISCREG_IFSR32_EL2; 189810037SARM gem5 Developers } 189910037SARM gem5 Developers break; 190010037SARM gem5 Developers case 1: 190110037SARM gem5 Developers switch (op2) { 190210037SARM gem5 Developers case 0: 190310037SARM gem5 Developers return MISCREG_AFSR0_EL2; 190410037SARM gem5 Developers case 1: 190510037SARM gem5 Developers return MISCREG_AFSR1_EL2; 190610037SARM gem5 Developers } 190710037SARM gem5 Developers break; 190810037SARM gem5 Developers case 2: 190910037SARM gem5 Developers switch (op2) { 191010037SARM gem5 Developers case 0: 191110037SARM gem5 Developers return MISCREG_ESR_EL2; 191212815Sgiacomo.travaglini@arm.com case 3: 191312815Sgiacomo.travaglini@arm.com return MISCREG_VSESR_EL2; 191410037SARM gem5 Developers } 191510037SARM gem5 Developers break; 191610037SARM gem5 Developers case 3: 191710037SARM gem5 Developers switch (op2) { 191810037SARM gem5 Developers case 0: 191910037SARM gem5 Developers return MISCREG_FPEXC32_EL2; 192010037SARM gem5 Developers } 192110037SARM gem5 Developers break; 192210037SARM gem5 Developers } 192310037SARM gem5 Developers break; 192410037SARM gem5 Developers case 6: 192510037SARM gem5 Developers switch (crm) { 192610037SARM gem5 Developers case 1: 192710037SARM gem5 Developers switch (op2) { 192810037SARM gem5 Developers case 0: 192910037SARM gem5 Developers return MISCREG_AFSR0_EL3; 193010037SARM gem5 Developers case 1: 193110037SARM gem5 Developers return MISCREG_AFSR1_EL3; 193210037SARM gem5 Developers } 193310037SARM gem5 Developers break; 193410037SARM gem5 Developers case 2: 193510037SARM gem5 Developers switch (op2) { 193610037SARM gem5 Developers case 0: 193710037SARM gem5 Developers return MISCREG_ESR_EL3; 193810037SARM gem5 Developers } 193910037SARM gem5 Developers break; 194010037SARM gem5 Developers } 194110037SARM gem5 Developers break; 194210037SARM gem5 Developers } 194310037SARM gem5 Developers break; 194410037SARM gem5 Developers case 6: 194510037SARM gem5 Developers switch (op1) { 194610037SARM gem5 Developers case 0: 194710037SARM gem5 Developers switch (crm) { 194810037SARM gem5 Developers case 0: 194910037SARM gem5 Developers switch (op2) { 195010037SARM gem5 Developers case 0: 195110037SARM gem5 Developers return MISCREG_FAR_EL1; 195210037SARM gem5 Developers } 195310037SARM gem5 Developers break; 195410037SARM gem5 Developers } 195510037SARM gem5 Developers break; 195610037SARM gem5 Developers case 4: 195710037SARM gem5 Developers switch (crm) { 195810037SARM gem5 Developers case 0: 195910037SARM gem5 Developers switch (op2) { 196010037SARM gem5 Developers case 0: 196110037SARM gem5 Developers return MISCREG_FAR_EL2; 196210037SARM gem5 Developers case 4: 196310037SARM gem5 Developers return MISCREG_HPFAR_EL2; 196410037SARM gem5 Developers } 196510037SARM gem5 Developers break; 196610037SARM gem5 Developers } 196710037SARM gem5 Developers break; 196810037SARM gem5 Developers case 6: 196910037SARM gem5 Developers switch (crm) { 197010037SARM gem5 Developers case 0: 197110037SARM gem5 Developers switch (op2) { 197210037SARM gem5 Developers case 0: 197310037SARM gem5 Developers return MISCREG_FAR_EL3; 197410037SARM gem5 Developers } 197510037SARM gem5 Developers break; 197610037SARM gem5 Developers } 197710037SARM gem5 Developers break; 197810037SARM gem5 Developers } 197910037SARM gem5 Developers break; 198010037SARM gem5 Developers case 7: 198110037SARM gem5 Developers switch (op1) { 198210037SARM gem5 Developers case 0: 198310037SARM gem5 Developers switch (crm) { 198410037SARM gem5 Developers case 4: 198510037SARM gem5 Developers switch (op2) { 198610037SARM gem5 Developers case 0: 198710037SARM gem5 Developers return MISCREG_PAR_EL1; 198810037SARM gem5 Developers } 198910037SARM gem5 Developers break; 199010037SARM gem5 Developers } 199110037SARM gem5 Developers break; 199210037SARM gem5 Developers } 199310037SARM gem5 Developers break; 199410037SARM gem5 Developers case 9: 199510037SARM gem5 Developers switch (op1) { 199610037SARM gem5 Developers case 0: 199710037SARM gem5 Developers switch (crm) { 199810037SARM gem5 Developers case 14: 199910037SARM gem5 Developers switch (op2) { 200010037SARM gem5 Developers case 1: 200110037SARM gem5 Developers return MISCREG_PMINTENSET_EL1; 200210037SARM gem5 Developers case 2: 200310037SARM gem5 Developers return MISCREG_PMINTENCLR_EL1; 200410037SARM gem5 Developers } 200510037SARM gem5 Developers break; 200610037SARM gem5 Developers } 200710037SARM gem5 Developers break; 200810037SARM gem5 Developers case 3: 200910037SARM gem5 Developers switch (crm) { 201010037SARM gem5 Developers case 12: 201110037SARM gem5 Developers switch (op2) { 201210037SARM gem5 Developers case 0: 201310037SARM gem5 Developers return MISCREG_PMCR_EL0; 201410037SARM gem5 Developers case 1: 201510037SARM gem5 Developers return MISCREG_PMCNTENSET_EL0; 201610037SARM gem5 Developers case 2: 201710037SARM gem5 Developers return MISCREG_PMCNTENCLR_EL0; 201810037SARM gem5 Developers case 3: 201910037SARM gem5 Developers return MISCREG_PMOVSCLR_EL0; 202010037SARM gem5 Developers case 4: 202110037SARM gem5 Developers return MISCREG_PMSWINC_EL0; 202210037SARM gem5 Developers case 5: 202310037SARM gem5 Developers return MISCREG_PMSELR_EL0; 202410037SARM gem5 Developers case 6: 202510037SARM gem5 Developers return MISCREG_PMCEID0_EL0; 202610037SARM gem5 Developers case 7: 202710037SARM gem5 Developers return MISCREG_PMCEID1_EL0; 202810037SARM gem5 Developers } 202910037SARM gem5 Developers break; 203010037SARM gem5 Developers case 13: 203110037SARM gem5 Developers switch (op2) { 203210037SARM gem5 Developers case 0: 203310037SARM gem5 Developers return MISCREG_PMCCNTR_EL0; 203410037SARM gem5 Developers case 1: 203510604SAndreas.Sandberg@ARM.com return MISCREG_PMXEVTYPER_EL0; 203610037SARM gem5 Developers case 2: 203710037SARM gem5 Developers return MISCREG_PMXEVCNTR_EL0; 203810037SARM gem5 Developers } 203910037SARM gem5 Developers break; 204010037SARM gem5 Developers case 14: 204110037SARM gem5 Developers switch (op2) { 204210037SARM gem5 Developers case 0: 204310037SARM gem5 Developers return MISCREG_PMUSERENR_EL0; 204410037SARM gem5 Developers case 3: 204510037SARM gem5 Developers return MISCREG_PMOVSSET_EL0; 204610037SARM gem5 Developers } 204710037SARM gem5 Developers break; 204810037SARM gem5 Developers } 204910037SARM gem5 Developers break; 205010037SARM gem5 Developers } 205110037SARM gem5 Developers break; 205210037SARM gem5 Developers case 10: 205310037SARM gem5 Developers switch (op1) { 205410037SARM gem5 Developers case 0: 205510037SARM gem5 Developers switch (crm) { 205610037SARM gem5 Developers case 2: 205710037SARM gem5 Developers switch (op2) { 205810037SARM gem5 Developers case 0: 205910037SARM gem5 Developers return MISCREG_MAIR_EL1; 206010037SARM gem5 Developers } 206110037SARM gem5 Developers break; 206210037SARM gem5 Developers case 3: 206310037SARM gem5 Developers switch (op2) { 206410037SARM gem5 Developers case 0: 206510037SARM gem5 Developers return MISCREG_AMAIR_EL1; 206610037SARM gem5 Developers } 206710037SARM gem5 Developers break; 206810037SARM gem5 Developers } 206910037SARM gem5 Developers break; 207010037SARM gem5 Developers case 4: 207110037SARM gem5 Developers switch (crm) { 207210037SARM gem5 Developers case 2: 207310037SARM gem5 Developers switch (op2) { 207410037SARM gem5 Developers case 0: 207510037SARM gem5 Developers return MISCREG_MAIR_EL2; 207610037SARM gem5 Developers } 207710037SARM gem5 Developers break; 207810037SARM gem5 Developers case 3: 207910037SARM gem5 Developers switch (op2) { 208010037SARM gem5 Developers case 0: 208110037SARM gem5 Developers return MISCREG_AMAIR_EL2; 208210037SARM gem5 Developers } 208310037SARM gem5 Developers break; 208410037SARM gem5 Developers } 208510037SARM gem5 Developers break; 208610037SARM gem5 Developers case 6: 208710037SARM gem5 Developers switch (crm) { 208810037SARM gem5 Developers case 2: 208910037SARM gem5 Developers switch (op2) { 209010037SARM gem5 Developers case 0: 209110037SARM gem5 Developers return MISCREG_MAIR_EL3; 209210037SARM gem5 Developers } 209310037SARM gem5 Developers break; 209410037SARM gem5 Developers case 3: 209510037SARM gem5 Developers switch (op2) { 209610037SARM gem5 Developers case 0: 209710037SARM gem5 Developers return MISCREG_AMAIR_EL3; 209810037SARM gem5 Developers } 209910037SARM gem5 Developers break; 210010037SARM gem5 Developers } 210110037SARM gem5 Developers break; 210210037SARM gem5 Developers } 210310037SARM gem5 Developers break; 210410037SARM gem5 Developers case 11: 210510037SARM gem5 Developers switch (op1) { 210610037SARM gem5 Developers case 1: 210710037SARM gem5 Developers switch (crm) { 210810037SARM gem5 Developers case 0: 210910037SARM gem5 Developers switch (op2) { 211010037SARM gem5 Developers case 2: 211110037SARM gem5 Developers return MISCREG_L2CTLR_EL1; 211210037SARM gem5 Developers case 3: 211310037SARM gem5 Developers return MISCREG_L2ECTLR_EL1; 211410037SARM gem5 Developers } 211510037SARM gem5 Developers break; 211610037SARM gem5 Developers } 211712711Sgiacomo.travaglini@arm.com M5_FALLTHROUGH; 211812711Sgiacomo.travaglini@arm.com default: 211912711Sgiacomo.travaglini@arm.com // S3_<op1>_11_<Cm>_<op2> 212012711Sgiacomo.travaglini@arm.com return MISCREG_IMPDEF_UNIMPL; 212110037SARM gem5 Developers } 212212711Sgiacomo.travaglini@arm.com M5_UNREACHABLE; 212310037SARM gem5 Developers case 12: 212410037SARM gem5 Developers switch (op1) { 212510037SARM gem5 Developers case 0: 212610037SARM gem5 Developers switch (crm) { 212710037SARM gem5 Developers case 0: 212810037SARM gem5 Developers switch (op2) { 212910037SARM gem5 Developers case 0: 213010037SARM gem5 Developers return MISCREG_VBAR_EL1; 213110037SARM gem5 Developers case 1: 213210037SARM gem5 Developers return MISCREG_RVBAR_EL1; 213310037SARM gem5 Developers } 213410037SARM gem5 Developers break; 213510037SARM gem5 Developers case 1: 213610037SARM gem5 Developers switch (op2) { 213710037SARM gem5 Developers case 0: 213810037SARM gem5 Developers return MISCREG_ISR_EL1; 213912815Sgiacomo.travaglini@arm.com case 1: 214012815Sgiacomo.travaglini@arm.com return MISCREG_DISR_EL1; 214110037SARM gem5 Developers } 214210037SARM gem5 Developers break; 214310037SARM gem5 Developers } 214410037SARM gem5 Developers break; 214510037SARM gem5 Developers case 4: 214610037SARM gem5 Developers switch (crm) { 214710037SARM gem5 Developers case 0: 214810037SARM gem5 Developers switch (op2) { 214910037SARM gem5 Developers case 0: 215010037SARM gem5 Developers return MISCREG_VBAR_EL2; 215110037SARM gem5 Developers case 1: 215210037SARM gem5 Developers return MISCREG_RVBAR_EL2; 215310037SARM gem5 Developers } 215410037SARM gem5 Developers break; 215512815Sgiacomo.travaglini@arm.com case 1: 215612815Sgiacomo.travaglini@arm.com switch (op2) { 215712815Sgiacomo.travaglini@arm.com case 1: 215812815Sgiacomo.travaglini@arm.com return MISCREG_VDISR_EL2; 215912815Sgiacomo.travaglini@arm.com } 216012815Sgiacomo.travaglini@arm.com break; 216110037SARM gem5 Developers } 216210037SARM gem5 Developers break; 216310037SARM gem5 Developers case 6: 216410037SARM gem5 Developers switch (crm) { 216510037SARM gem5 Developers case 0: 216610037SARM gem5 Developers switch (op2) { 216710037SARM gem5 Developers case 0: 216810037SARM gem5 Developers return MISCREG_VBAR_EL3; 216910037SARM gem5 Developers case 1: 217010037SARM gem5 Developers return MISCREG_RVBAR_EL3; 217110037SARM gem5 Developers case 2: 217210037SARM gem5 Developers return MISCREG_RMR_EL3; 217310037SARM gem5 Developers } 217410037SARM gem5 Developers break; 217510037SARM gem5 Developers } 217610037SARM gem5 Developers break; 217710037SARM gem5 Developers } 217810037SARM gem5 Developers break; 217910037SARM gem5 Developers case 13: 218010037SARM gem5 Developers switch (op1) { 218110037SARM gem5 Developers case 0: 218210037SARM gem5 Developers switch (crm) { 218310037SARM gem5 Developers case 0: 218410037SARM gem5 Developers switch (op2) { 218510037SARM gem5 Developers case 1: 218610037SARM gem5 Developers return MISCREG_CONTEXTIDR_EL1; 218710037SARM gem5 Developers case 4: 218810037SARM gem5 Developers return MISCREG_TPIDR_EL1; 218910037SARM gem5 Developers } 219010037SARM gem5 Developers break; 219110037SARM gem5 Developers } 219210037SARM gem5 Developers break; 219310037SARM gem5 Developers case 3: 219410037SARM gem5 Developers switch (crm) { 219510037SARM gem5 Developers case 0: 219610037SARM gem5 Developers switch (op2) { 219710037SARM gem5 Developers case 2: 219810037SARM gem5 Developers return MISCREG_TPIDR_EL0; 219910037SARM gem5 Developers case 3: 220010037SARM gem5 Developers return MISCREG_TPIDRRO_EL0; 220110037SARM gem5 Developers } 220210037SARM gem5 Developers break; 220310037SARM gem5 Developers } 220410037SARM gem5 Developers break; 220510037SARM gem5 Developers case 4: 220610037SARM gem5 Developers switch (crm) { 220710037SARM gem5 Developers case 0: 220810037SARM gem5 Developers switch (op2) { 220910856SCurtis.Dunham@arm.com case 1: 221010856SCurtis.Dunham@arm.com return MISCREG_CONTEXTIDR_EL2; 221110037SARM gem5 Developers case 2: 221210037SARM gem5 Developers return MISCREG_TPIDR_EL2; 221310037SARM gem5 Developers } 221410037SARM gem5 Developers break; 221510037SARM gem5 Developers } 221610037SARM gem5 Developers break; 221710037SARM gem5 Developers case 6: 221810037SARM gem5 Developers switch (crm) { 221910037SARM gem5 Developers case 0: 222010037SARM gem5 Developers switch (op2) { 222110037SARM gem5 Developers case 2: 222210037SARM gem5 Developers return MISCREG_TPIDR_EL3; 222310037SARM gem5 Developers } 222410037SARM gem5 Developers break; 222510037SARM gem5 Developers } 222610037SARM gem5 Developers break; 222710037SARM gem5 Developers } 222810037SARM gem5 Developers break; 222910037SARM gem5 Developers case 14: 223010037SARM gem5 Developers switch (op1) { 223110037SARM gem5 Developers case 0: 223210037SARM gem5 Developers switch (crm) { 223310037SARM gem5 Developers case 1: 223410037SARM gem5 Developers switch (op2) { 223510037SARM gem5 Developers case 0: 223610037SARM gem5 Developers return MISCREG_CNTKCTL_EL1; 223710037SARM gem5 Developers } 223810037SARM gem5 Developers break; 223910037SARM gem5 Developers } 224010037SARM gem5 Developers break; 224110037SARM gem5 Developers case 3: 224210037SARM gem5 Developers switch (crm) { 224310037SARM gem5 Developers case 0: 224410037SARM gem5 Developers switch (op2) { 224510037SARM gem5 Developers case 0: 224610037SARM gem5 Developers return MISCREG_CNTFRQ_EL0; 224710037SARM gem5 Developers case 1: 224810037SARM gem5 Developers return MISCREG_CNTPCT_EL0; 224910037SARM gem5 Developers case 2: 225010037SARM gem5 Developers return MISCREG_CNTVCT_EL0; 225110037SARM gem5 Developers } 225210037SARM gem5 Developers break; 225310037SARM gem5 Developers case 2: 225410037SARM gem5 Developers switch (op2) { 225510037SARM gem5 Developers case 0: 225610037SARM gem5 Developers return MISCREG_CNTP_TVAL_EL0; 225710037SARM gem5 Developers case 1: 225810037SARM gem5 Developers return MISCREG_CNTP_CTL_EL0; 225910037SARM gem5 Developers case 2: 226010037SARM gem5 Developers return MISCREG_CNTP_CVAL_EL0; 226110037SARM gem5 Developers } 226210037SARM gem5 Developers break; 226310037SARM gem5 Developers case 3: 226410037SARM gem5 Developers switch (op2) { 226510037SARM gem5 Developers case 0: 226610037SARM gem5 Developers return MISCREG_CNTV_TVAL_EL0; 226710037SARM gem5 Developers case 1: 226810037SARM gem5 Developers return MISCREG_CNTV_CTL_EL0; 226910037SARM gem5 Developers case 2: 227010037SARM gem5 Developers return MISCREG_CNTV_CVAL_EL0; 227110037SARM gem5 Developers } 227210037SARM gem5 Developers break; 227310037SARM gem5 Developers case 8: 227410037SARM gem5 Developers switch (op2) { 227510037SARM gem5 Developers case 0: 227610037SARM gem5 Developers return MISCREG_PMEVCNTR0_EL0; 227710037SARM gem5 Developers case 1: 227810037SARM gem5 Developers return MISCREG_PMEVCNTR1_EL0; 227910037SARM gem5 Developers case 2: 228010037SARM gem5 Developers return MISCREG_PMEVCNTR2_EL0; 228110037SARM gem5 Developers case 3: 228210037SARM gem5 Developers return MISCREG_PMEVCNTR3_EL0; 228310037SARM gem5 Developers case 4: 228410037SARM gem5 Developers return MISCREG_PMEVCNTR4_EL0; 228510037SARM gem5 Developers case 5: 228610037SARM gem5 Developers return MISCREG_PMEVCNTR5_EL0; 228710037SARM gem5 Developers } 228810037SARM gem5 Developers break; 228910037SARM gem5 Developers case 12: 229010037SARM gem5 Developers switch (op2) { 229110037SARM gem5 Developers case 0: 229210037SARM gem5 Developers return MISCREG_PMEVTYPER0_EL0; 229310037SARM gem5 Developers case 1: 229410037SARM gem5 Developers return MISCREG_PMEVTYPER1_EL0; 229510037SARM gem5 Developers case 2: 229610037SARM gem5 Developers return MISCREG_PMEVTYPER2_EL0; 229710037SARM gem5 Developers case 3: 229810037SARM gem5 Developers return MISCREG_PMEVTYPER3_EL0; 229910037SARM gem5 Developers case 4: 230010037SARM gem5 Developers return MISCREG_PMEVTYPER4_EL0; 230110037SARM gem5 Developers case 5: 230210037SARM gem5 Developers return MISCREG_PMEVTYPER5_EL0; 230310037SARM gem5 Developers } 230410037SARM gem5 Developers break; 230510604SAndreas.Sandberg@ARM.com case 15: 230610604SAndreas.Sandberg@ARM.com switch (op2) { 230710604SAndreas.Sandberg@ARM.com case 7: 230810604SAndreas.Sandberg@ARM.com return MISCREG_PMCCFILTR_EL0; 230910604SAndreas.Sandberg@ARM.com } 231010037SARM gem5 Developers } 231110037SARM gem5 Developers break; 231210037SARM gem5 Developers case 4: 231310037SARM gem5 Developers switch (crm) { 231410037SARM gem5 Developers case 0: 231510037SARM gem5 Developers switch (op2) { 231610037SARM gem5 Developers case 3: 231710037SARM gem5 Developers return MISCREG_CNTVOFF_EL2; 231810037SARM gem5 Developers } 231910037SARM gem5 Developers break; 232010037SARM gem5 Developers case 1: 232110037SARM gem5 Developers switch (op2) { 232210037SARM gem5 Developers case 0: 232310037SARM gem5 Developers return MISCREG_CNTHCTL_EL2; 232410037SARM gem5 Developers } 232510037SARM gem5 Developers break; 232610037SARM gem5 Developers case 2: 232710037SARM gem5 Developers switch (op2) { 232810037SARM gem5 Developers case 0: 232910037SARM gem5 Developers return MISCREG_CNTHP_TVAL_EL2; 233010037SARM gem5 Developers case 1: 233110037SARM gem5 Developers return MISCREG_CNTHP_CTL_EL2; 233210037SARM gem5 Developers case 2: 233310037SARM gem5 Developers return MISCREG_CNTHP_CVAL_EL2; 233410037SARM gem5 Developers } 233510037SARM gem5 Developers break; 233612816Sgiacomo.travaglini@arm.com case 3: 233712816Sgiacomo.travaglini@arm.com switch (op2) { 233812816Sgiacomo.travaglini@arm.com case 0: 233912816Sgiacomo.travaglini@arm.com return MISCREG_CNTHV_TVAL_EL2; 234012816Sgiacomo.travaglini@arm.com case 1: 234112816Sgiacomo.travaglini@arm.com return MISCREG_CNTHV_CTL_EL2; 234212816Sgiacomo.travaglini@arm.com case 2: 234312816Sgiacomo.travaglini@arm.com return MISCREG_CNTHV_CVAL_EL2; 234412816Sgiacomo.travaglini@arm.com } 234512816Sgiacomo.travaglini@arm.com break; 234610037SARM gem5 Developers } 234710037SARM gem5 Developers break; 234810037SARM gem5 Developers case 7: 234910037SARM gem5 Developers switch (crm) { 235010037SARM gem5 Developers case 2: 235110037SARM gem5 Developers switch (op2) { 235210037SARM gem5 Developers case 0: 235310037SARM gem5 Developers return MISCREG_CNTPS_TVAL_EL1; 235410037SARM gem5 Developers case 1: 235510037SARM gem5 Developers return MISCREG_CNTPS_CTL_EL1; 235610037SARM gem5 Developers case 2: 235710037SARM gem5 Developers return MISCREG_CNTPS_CVAL_EL1; 235810037SARM gem5 Developers } 235910037SARM gem5 Developers break; 236010037SARM gem5 Developers } 236110037SARM gem5 Developers break; 236210037SARM gem5 Developers } 236310037SARM gem5 Developers break; 236410037SARM gem5 Developers case 15: 236510037SARM gem5 Developers switch (op1) { 236610037SARM gem5 Developers case 0: 236710037SARM gem5 Developers switch (crm) { 236810037SARM gem5 Developers case 0: 236910037SARM gem5 Developers switch (op2) { 237010037SARM gem5 Developers case 0: 237110037SARM gem5 Developers return MISCREG_IL1DATA0_EL1; 237210037SARM gem5 Developers case 1: 237310037SARM gem5 Developers return MISCREG_IL1DATA1_EL1; 237410037SARM gem5 Developers case 2: 237510037SARM gem5 Developers return MISCREG_IL1DATA2_EL1; 237610037SARM gem5 Developers case 3: 237710037SARM gem5 Developers return MISCREG_IL1DATA3_EL1; 237810037SARM gem5 Developers } 237910037SARM gem5 Developers break; 238010037SARM gem5 Developers case 1: 238110037SARM gem5 Developers switch (op2) { 238210037SARM gem5 Developers case 0: 238310037SARM gem5 Developers return MISCREG_DL1DATA0_EL1; 238410037SARM gem5 Developers case 1: 238510037SARM gem5 Developers return MISCREG_DL1DATA1_EL1; 238610037SARM gem5 Developers case 2: 238710037SARM gem5 Developers return MISCREG_DL1DATA2_EL1; 238810037SARM gem5 Developers case 3: 238910037SARM gem5 Developers return MISCREG_DL1DATA3_EL1; 239010037SARM gem5 Developers case 4: 239110037SARM gem5 Developers return MISCREG_DL1DATA4_EL1; 239210037SARM gem5 Developers } 239310037SARM gem5 Developers break; 239410037SARM gem5 Developers } 239510037SARM gem5 Developers break; 239610037SARM gem5 Developers case 1: 239710037SARM gem5 Developers switch (crm) { 239810037SARM gem5 Developers case 0: 239910037SARM gem5 Developers switch (op2) { 240010037SARM gem5 Developers case 0: 240110037SARM gem5 Developers return MISCREG_L2ACTLR_EL1; 240210037SARM gem5 Developers } 240310037SARM gem5 Developers break; 240410037SARM gem5 Developers case 2: 240510037SARM gem5 Developers switch (op2) { 240610037SARM gem5 Developers case 0: 240710037SARM gem5 Developers return MISCREG_CPUACTLR_EL1; 240810037SARM gem5 Developers case 1: 240910037SARM gem5 Developers return MISCREG_CPUECTLR_EL1; 241010037SARM gem5 Developers case 2: 241110037SARM gem5 Developers return MISCREG_CPUMERRSR_EL1; 241210037SARM gem5 Developers case 3: 241310037SARM gem5 Developers return MISCREG_L2MERRSR_EL1; 241410037SARM gem5 Developers } 241510037SARM gem5 Developers break; 241610037SARM gem5 Developers case 3: 241710037SARM gem5 Developers switch (op2) { 241810037SARM gem5 Developers case 0: 241910037SARM gem5 Developers return MISCREG_CBAR_EL1; 242010037SARM gem5 Developers 242110037SARM gem5 Developers } 242210037SARM gem5 Developers break; 242310037SARM gem5 Developers } 242410037SARM gem5 Developers break; 242510037SARM gem5 Developers } 242612711Sgiacomo.travaglini@arm.com // S3_<op1>_15_<Cm>_<op2> 242712711Sgiacomo.travaglini@arm.com return MISCREG_IMPDEF_UNIMPL; 242810037SARM gem5 Developers } 242910037SARM gem5 Developers break; 243010037SARM gem5 Developers } 243110037SARM gem5 Developers 243210037SARM gem5 Developers return MISCREG_UNKNOWN; 243310037SARM gem5 Developers} 243410037SARM gem5 Developers 243512479SCurtis.Dunham@arm.combitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below 243612479SCurtis.Dunham@arm.com 243712479SCurtis.Dunham@arm.comvoid 243812479SCurtis.Dunham@arm.comISA::initializeMiscRegMetadata() 243912479SCurtis.Dunham@arm.com{ 244012479SCurtis.Dunham@arm.com // the MiscReg metadata tables are shared across all instances of the 244112479SCurtis.Dunham@arm.com // ISA object, so there's no need to initialize them multiple times. 244212479SCurtis.Dunham@arm.com static bool completed = false; 244312479SCurtis.Dunham@arm.com if (completed) 244412479SCurtis.Dunham@arm.com return; 244512479SCurtis.Dunham@arm.com 244612661Sgiacomo.travaglini@arm.com // This boolean variable specifies if the system is running in aarch32 at 244712661Sgiacomo.travaglini@arm.com // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it 244812661Sgiacomo.travaglini@arm.com // is running in aarch64 (aarch32EL3 = false) 244912661Sgiacomo.travaglini@arm.com bool aarch32EL3 = haveSecurity && !highestELIs64; 245012661Sgiacomo.travaglini@arm.com 245112479SCurtis.Dunham@arm.com /** 245212479SCurtis.Dunham@arm.com * Some registers alias with others, and therefore need to be translated. 245312479SCurtis.Dunham@arm.com * When two mapping registers are given, they are the 32b lower and 245412479SCurtis.Dunham@arm.com * upper halves, respectively, of the 64b register being mapped. 245512479SCurtis.Dunham@arm.com * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 245612479SCurtis.Dunham@arm.com * 245712479SCurtis.Dunham@arm.com * NAM = "not architecturally mandated", 245812479SCurtis.Dunham@arm.com * from ARM DDI 0487A.i, template text 245912479SCurtis.Dunham@arm.com * "AArch64 System register ___ can be mapped to 246012479SCurtis.Dunham@arm.com * AArch32 System register ___, but this is not 246112479SCurtis.Dunham@arm.com * architecturally mandated." 246212479SCurtis.Dunham@arm.com */ 246312479SCurtis.Dunham@arm.com 246412479SCurtis.Dunham@arm.com InitReg(MISCREG_CPSR) 246512479SCurtis.Dunham@arm.com .allPrivileges(); 246612479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR) 246712479SCurtis.Dunham@arm.com .allPrivileges(); 246812479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_FIQ) 246912479SCurtis.Dunham@arm.com .allPrivileges(); 247012479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_IRQ) 247112479SCurtis.Dunham@arm.com .allPrivileges(); 247212479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_SVC) 247312479SCurtis.Dunham@arm.com .allPrivileges(); 247412479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_MON) 247512479SCurtis.Dunham@arm.com .allPrivileges(); 247612479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_ABT) 247712479SCurtis.Dunham@arm.com .allPrivileges(); 247812479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_HYP) 247912479SCurtis.Dunham@arm.com .allPrivileges(); 248012479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_UND) 248112479SCurtis.Dunham@arm.com .allPrivileges(); 248212479SCurtis.Dunham@arm.com InitReg(MISCREG_ELR_HYP) 248312479SCurtis.Dunham@arm.com .allPrivileges(); 248412479SCurtis.Dunham@arm.com InitReg(MISCREG_FPSID) 248512479SCurtis.Dunham@arm.com .allPrivileges(); 248612479SCurtis.Dunham@arm.com InitReg(MISCREG_FPSCR) 248712479SCurtis.Dunham@arm.com .allPrivileges(); 248812479SCurtis.Dunham@arm.com InitReg(MISCREG_MVFR1) 248912479SCurtis.Dunham@arm.com .allPrivileges(); 249012479SCurtis.Dunham@arm.com InitReg(MISCREG_MVFR0) 249112479SCurtis.Dunham@arm.com .allPrivileges(); 249212479SCurtis.Dunham@arm.com InitReg(MISCREG_FPEXC) 249312479SCurtis.Dunham@arm.com .allPrivileges(); 249412479SCurtis.Dunham@arm.com 249512479SCurtis.Dunham@arm.com // Helper registers 249612479SCurtis.Dunham@arm.com InitReg(MISCREG_CPSR_MODE) 249712479SCurtis.Dunham@arm.com .allPrivileges(); 249812479SCurtis.Dunham@arm.com InitReg(MISCREG_CPSR_Q) 249912479SCurtis.Dunham@arm.com .allPrivileges(); 250012479SCurtis.Dunham@arm.com InitReg(MISCREG_FPSCR_EXC) 250112479SCurtis.Dunham@arm.com .allPrivileges(); 250212479SCurtis.Dunham@arm.com InitReg(MISCREG_FPSCR_QC) 250312479SCurtis.Dunham@arm.com .allPrivileges(); 250412479SCurtis.Dunham@arm.com InitReg(MISCREG_LOCKADDR) 250512479SCurtis.Dunham@arm.com .allPrivileges(); 250612479SCurtis.Dunham@arm.com InitReg(MISCREG_LOCKFLAG) 250712479SCurtis.Dunham@arm.com .allPrivileges(); 250812479SCurtis.Dunham@arm.com InitReg(MISCREG_PRRR_MAIR0) 250912479SCurtis.Dunham@arm.com .mutex() 251012479SCurtis.Dunham@arm.com .banked(); 251112479SCurtis.Dunham@arm.com InitReg(MISCREG_PRRR_MAIR0_NS) 251212479SCurtis.Dunham@arm.com .mutex() 251312661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 251412479SCurtis.Dunham@arm.com .bankedChild(); 251512479SCurtis.Dunham@arm.com InitReg(MISCREG_PRRR_MAIR0_S) 251612479SCurtis.Dunham@arm.com .mutex() 251712479SCurtis.Dunham@arm.com .bankedChild(); 251812479SCurtis.Dunham@arm.com InitReg(MISCREG_NMRR_MAIR1) 251912479SCurtis.Dunham@arm.com .mutex() 252012479SCurtis.Dunham@arm.com .banked(); 252112479SCurtis.Dunham@arm.com InitReg(MISCREG_NMRR_MAIR1_NS) 252212479SCurtis.Dunham@arm.com .mutex() 252312661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 252412479SCurtis.Dunham@arm.com .bankedChild(); 252512479SCurtis.Dunham@arm.com InitReg(MISCREG_NMRR_MAIR1_S) 252612479SCurtis.Dunham@arm.com .mutex() 252712479SCurtis.Dunham@arm.com .bankedChild(); 252812479SCurtis.Dunham@arm.com InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) 252912479SCurtis.Dunham@arm.com .mutex(); 253012479SCurtis.Dunham@arm.com InitReg(MISCREG_SCTLR_RST) 253112479SCurtis.Dunham@arm.com .allPrivileges(); 253212479SCurtis.Dunham@arm.com InitReg(MISCREG_SEV_MAILBOX) 253312479SCurtis.Dunham@arm.com .allPrivileges(); 253412479SCurtis.Dunham@arm.com 253512479SCurtis.Dunham@arm.com // AArch32 CP14 registers 253612479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDIDR) 253712479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 253812479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDSCRint) 253912479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 254012479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDCCINT) 254112479SCurtis.Dunham@arm.com .unimplemented() 254212479SCurtis.Dunham@arm.com .allPrivileges(); 254312479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDTRTXint) 254412479SCurtis.Dunham@arm.com .unimplemented() 254512479SCurtis.Dunham@arm.com .allPrivileges(); 254612479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDTRRXint) 254712479SCurtis.Dunham@arm.com .unimplemented() 254812479SCurtis.Dunham@arm.com .allPrivileges(); 254912479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWFAR) 255012479SCurtis.Dunham@arm.com .unimplemented() 255112479SCurtis.Dunham@arm.com .allPrivileges(); 255212479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGVCR) 255312479SCurtis.Dunham@arm.com .unimplemented() 255412479SCurtis.Dunham@arm.com .allPrivileges(); 255512479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDTRRXext) 255612479SCurtis.Dunham@arm.com .unimplemented() 255712479SCurtis.Dunham@arm.com .allPrivileges(); 255812479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDSCRext) 255912479SCurtis.Dunham@arm.com .unimplemented() 256012479SCurtis.Dunham@arm.com .warnNotFail() 256112479SCurtis.Dunham@arm.com .allPrivileges(); 256212479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDTRTXext) 256312479SCurtis.Dunham@arm.com .unimplemented() 256412479SCurtis.Dunham@arm.com .allPrivileges(); 256512479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGOSECCR) 256612479SCurtis.Dunham@arm.com .unimplemented() 256712479SCurtis.Dunham@arm.com .allPrivileges(); 256812479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR0) 256912479SCurtis.Dunham@arm.com .unimplemented() 257012479SCurtis.Dunham@arm.com .allPrivileges(); 257112479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR1) 257212479SCurtis.Dunham@arm.com .unimplemented() 257312479SCurtis.Dunham@arm.com .allPrivileges(); 257412479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR2) 257512479SCurtis.Dunham@arm.com .unimplemented() 257612479SCurtis.Dunham@arm.com .allPrivileges(); 257712479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR3) 257812479SCurtis.Dunham@arm.com .unimplemented() 257912479SCurtis.Dunham@arm.com .allPrivileges(); 258012479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR4) 258112479SCurtis.Dunham@arm.com .unimplemented() 258212479SCurtis.Dunham@arm.com .allPrivileges(); 258312479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR5) 258412479SCurtis.Dunham@arm.com .unimplemented() 258512479SCurtis.Dunham@arm.com .allPrivileges(); 258612479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR0) 258712479SCurtis.Dunham@arm.com .unimplemented() 258812479SCurtis.Dunham@arm.com .allPrivileges(); 258912479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR1) 259012479SCurtis.Dunham@arm.com .unimplemented() 259112479SCurtis.Dunham@arm.com .allPrivileges(); 259212479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR2) 259312479SCurtis.Dunham@arm.com .unimplemented() 259412479SCurtis.Dunham@arm.com .allPrivileges(); 259512479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR3) 259612479SCurtis.Dunham@arm.com .unimplemented() 259712479SCurtis.Dunham@arm.com .allPrivileges(); 259812479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR4) 259912479SCurtis.Dunham@arm.com .unimplemented() 260012479SCurtis.Dunham@arm.com .allPrivileges(); 260112479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR5) 260212479SCurtis.Dunham@arm.com .unimplemented() 260312479SCurtis.Dunham@arm.com .allPrivileges(); 260412479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR0) 260512479SCurtis.Dunham@arm.com .unimplemented() 260612479SCurtis.Dunham@arm.com .allPrivileges(); 260712479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR1) 260812479SCurtis.Dunham@arm.com .unimplemented() 260912479SCurtis.Dunham@arm.com .allPrivileges(); 261012479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR2) 261112479SCurtis.Dunham@arm.com .unimplemented() 261212479SCurtis.Dunham@arm.com .allPrivileges(); 261312479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR3) 261412479SCurtis.Dunham@arm.com .unimplemented() 261512479SCurtis.Dunham@arm.com .allPrivileges(); 261612479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR0) 261712479SCurtis.Dunham@arm.com .unimplemented() 261812479SCurtis.Dunham@arm.com .allPrivileges(); 261912479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR1) 262012479SCurtis.Dunham@arm.com .unimplemented() 262112479SCurtis.Dunham@arm.com .allPrivileges(); 262212479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR2) 262312479SCurtis.Dunham@arm.com .unimplemented() 262412479SCurtis.Dunham@arm.com .allPrivileges(); 262512479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR3) 262612479SCurtis.Dunham@arm.com .unimplemented() 262712479SCurtis.Dunham@arm.com .allPrivileges(); 262812479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDRAR) 262912479SCurtis.Dunham@arm.com .unimplemented() 263012479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 263112479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBXVR4) 263212479SCurtis.Dunham@arm.com .unimplemented() 263312479SCurtis.Dunham@arm.com .allPrivileges(); 263412479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBXVR5) 263512479SCurtis.Dunham@arm.com .unimplemented() 263612479SCurtis.Dunham@arm.com .allPrivileges(); 263712479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGOSLAR) 263812479SCurtis.Dunham@arm.com .unimplemented() 263912479SCurtis.Dunham@arm.com .allPrivileges().monSecureRead(0).monNonSecureRead(0); 264012479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGOSLSR) 264112479SCurtis.Dunham@arm.com .unimplemented() 264212479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 264312479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGOSDLR) 264412479SCurtis.Dunham@arm.com .unimplemented() 264512479SCurtis.Dunham@arm.com .allPrivileges(); 264612479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGPRCR) 264712479SCurtis.Dunham@arm.com .unimplemented() 264812479SCurtis.Dunham@arm.com .allPrivileges(); 264912479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDSAR) 265012479SCurtis.Dunham@arm.com .unimplemented() 265112479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 265212479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGCLAIMSET) 265312479SCurtis.Dunham@arm.com .unimplemented() 265412479SCurtis.Dunham@arm.com .allPrivileges(); 265512479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGCLAIMCLR) 265612479SCurtis.Dunham@arm.com .unimplemented() 265712479SCurtis.Dunham@arm.com .allPrivileges(); 265812479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGAUTHSTATUS) 265912479SCurtis.Dunham@arm.com .unimplemented() 266012479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 266112479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDEVID2) 266212479SCurtis.Dunham@arm.com .unimplemented() 266312479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 266412479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDEVID1) 266512479SCurtis.Dunham@arm.com .unimplemented() 266612479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 266712479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGDEVID0) 266812479SCurtis.Dunham@arm.com .unimplemented() 266912479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 267012479SCurtis.Dunham@arm.com InitReg(MISCREG_TEECR) 267112479SCurtis.Dunham@arm.com .unimplemented() 267212479SCurtis.Dunham@arm.com .allPrivileges(); 267312479SCurtis.Dunham@arm.com InitReg(MISCREG_JIDR) 267412479SCurtis.Dunham@arm.com .allPrivileges(); 267512479SCurtis.Dunham@arm.com InitReg(MISCREG_TEEHBR) 267612479SCurtis.Dunham@arm.com .allPrivileges(); 267712479SCurtis.Dunham@arm.com InitReg(MISCREG_JOSCR) 267812479SCurtis.Dunham@arm.com .allPrivileges(); 267912479SCurtis.Dunham@arm.com InitReg(MISCREG_JMCR) 268012479SCurtis.Dunham@arm.com .allPrivileges(); 268112479SCurtis.Dunham@arm.com 268212479SCurtis.Dunham@arm.com // AArch32 CP15 registers 268312479SCurtis.Dunham@arm.com InitReg(MISCREG_MIDR) 268412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 268512479SCurtis.Dunham@arm.com InitReg(MISCREG_CTR) 268612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 268712479SCurtis.Dunham@arm.com InitReg(MISCREG_TCMTR) 268812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 268912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBTR) 269012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 269112479SCurtis.Dunham@arm.com InitReg(MISCREG_MPIDR) 269212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 269312479SCurtis.Dunham@arm.com InitReg(MISCREG_REVIDR) 269412479SCurtis.Dunham@arm.com .unimplemented() 269512479SCurtis.Dunham@arm.com .warnNotFail() 269612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 269712479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_PFR0) 269812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 269912479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_PFR1) 270012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 270112479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_DFR0) 270212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 270312479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AFR0) 270412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 270512479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_MMFR0) 270612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 270712479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_MMFR1) 270812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 270912479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_MMFR2) 271012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 271112479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_MMFR3) 271212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 271312479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR0) 271412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 271512479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR1) 271612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 271712479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR2) 271812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 271912479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR3) 272012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 272112479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR4) 272212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 272312479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR5) 272412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 272512479SCurtis.Dunham@arm.com InitReg(MISCREG_CCSIDR) 272612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 272712479SCurtis.Dunham@arm.com InitReg(MISCREG_CLIDR) 272812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 272912479SCurtis.Dunham@arm.com InitReg(MISCREG_AIDR) 273012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 273112479SCurtis.Dunham@arm.com InitReg(MISCREG_CSSELR) 273212479SCurtis.Dunham@arm.com .banked(); 273312479SCurtis.Dunham@arm.com InitReg(MISCREG_CSSELR_NS) 273412479SCurtis.Dunham@arm.com .bankedChild() 273512661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 273612479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 273712479SCurtis.Dunham@arm.com InitReg(MISCREG_CSSELR_S) 273812479SCurtis.Dunham@arm.com .bankedChild() 273912479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 274012479SCurtis.Dunham@arm.com InitReg(MISCREG_VPIDR) 274112479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 274212479SCurtis.Dunham@arm.com InitReg(MISCREG_VMPIDR) 274312479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 274412479SCurtis.Dunham@arm.com InitReg(MISCREG_SCTLR) 274512479SCurtis.Dunham@arm.com .banked(); 274612479SCurtis.Dunham@arm.com InitReg(MISCREG_SCTLR_NS) 274712479SCurtis.Dunham@arm.com .bankedChild() 274812661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 274912479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 275012479SCurtis.Dunham@arm.com InitReg(MISCREG_SCTLR_S) 275112479SCurtis.Dunham@arm.com .bankedChild() 275212479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 275312479SCurtis.Dunham@arm.com InitReg(MISCREG_ACTLR) 275412479SCurtis.Dunham@arm.com .banked(); 275512479SCurtis.Dunham@arm.com InitReg(MISCREG_ACTLR_NS) 275612479SCurtis.Dunham@arm.com .bankedChild() 275712661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 275812479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 275912479SCurtis.Dunham@arm.com InitReg(MISCREG_ACTLR_S) 276012479SCurtis.Dunham@arm.com .bankedChild() 276112479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 276212479SCurtis.Dunham@arm.com InitReg(MISCREG_CPACR) 276312479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 276412479SCurtis.Dunham@arm.com InitReg(MISCREG_SCR) 276512479SCurtis.Dunham@arm.com .mon().secure().exceptUserMode() 276612479SCurtis.Dunham@arm.com .res0(0xff40) // [31:16], [6] 276712479SCurtis.Dunham@arm.com .res1(0x0030); // [5:4] 276812479SCurtis.Dunham@arm.com InitReg(MISCREG_SDER) 276912479SCurtis.Dunham@arm.com .mon(); 277012479SCurtis.Dunham@arm.com InitReg(MISCREG_NSACR) 277112479SCurtis.Dunham@arm.com .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode(); 277212479SCurtis.Dunham@arm.com InitReg(MISCREG_HSCTLR) 277312479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 277412479SCurtis.Dunham@arm.com InitReg(MISCREG_HACTLR) 277512479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 277612479SCurtis.Dunham@arm.com InitReg(MISCREG_HCR) 277712479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 277812479SCurtis.Dunham@arm.com InitReg(MISCREG_HDCR) 277912479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 278012479SCurtis.Dunham@arm.com InitReg(MISCREG_HCPTR) 278112479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 278212479SCurtis.Dunham@arm.com InitReg(MISCREG_HSTR) 278312479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 278412479SCurtis.Dunham@arm.com InitReg(MISCREG_HACR) 278512479SCurtis.Dunham@arm.com .unimplemented() 278612479SCurtis.Dunham@arm.com .warnNotFail() 278712479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 278812479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR0) 278912479SCurtis.Dunham@arm.com .banked(); 279012479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR0_NS) 279112479SCurtis.Dunham@arm.com .bankedChild() 279212661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 279312479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 279412479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR0_S) 279512479SCurtis.Dunham@arm.com .bankedChild() 279612479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 279712479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR1) 279812479SCurtis.Dunham@arm.com .banked(); 279912479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR1_NS) 280012479SCurtis.Dunham@arm.com .bankedChild() 280112661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 280212479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 280312479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR1_S) 280412479SCurtis.Dunham@arm.com .bankedChild() 280512479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 280612479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBCR) 280712479SCurtis.Dunham@arm.com .banked(); 280812479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBCR_NS) 280912479SCurtis.Dunham@arm.com .bankedChild() 281012661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 281112479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 281212479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBCR_S) 281312479SCurtis.Dunham@arm.com .bankedChild() 281412479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 281512479SCurtis.Dunham@arm.com InitReg(MISCREG_HTCR) 281612479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 281712479SCurtis.Dunham@arm.com InitReg(MISCREG_VTCR) 281812479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 281912479SCurtis.Dunham@arm.com InitReg(MISCREG_DACR) 282012479SCurtis.Dunham@arm.com .banked(); 282112479SCurtis.Dunham@arm.com InitReg(MISCREG_DACR_NS) 282212479SCurtis.Dunham@arm.com .bankedChild() 282312661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 282412479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 282512479SCurtis.Dunham@arm.com InitReg(MISCREG_DACR_S) 282612479SCurtis.Dunham@arm.com .bankedChild() 282712479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 282812479SCurtis.Dunham@arm.com InitReg(MISCREG_DFSR) 282912479SCurtis.Dunham@arm.com .banked(); 283012479SCurtis.Dunham@arm.com InitReg(MISCREG_DFSR_NS) 283112479SCurtis.Dunham@arm.com .bankedChild() 283212661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 283312479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 283412479SCurtis.Dunham@arm.com InitReg(MISCREG_DFSR_S) 283512479SCurtis.Dunham@arm.com .bankedChild() 283612479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 283712479SCurtis.Dunham@arm.com InitReg(MISCREG_IFSR) 283812479SCurtis.Dunham@arm.com .banked(); 283912479SCurtis.Dunham@arm.com InitReg(MISCREG_IFSR_NS) 284012479SCurtis.Dunham@arm.com .bankedChild() 284112661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 284212479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 284312479SCurtis.Dunham@arm.com InitReg(MISCREG_IFSR_S) 284412479SCurtis.Dunham@arm.com .bankedChild() 284512479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 284612479SCurtis.Dunham@arm.com InitReg(MISCREG_ADFSR) 284712479SCurtis.Dunham@arm.com .unimplemented() 284812479SCurtis.Dunham@arm.com .warnNotFail() 284912479SCurtis.Dunham@arm.com .banked(); 285012479SCurtis.Dunham@arm.com InitReg(MISCREG_ADFSR_NS) 285112479SCurtis.Dunham@arm.com .unimplemented() 285212479SCurtis.Dunham@arm.com .warnNotFail() 285312479SCurtis.Dunham@arm.com .bankedChild() 285412661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 285512479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 285612479SCurtis.Dunham@arm.com InitReg(MISCREG_ADFSR_S) 285712479SCurtis.Dunham@arm.com .unimplemented() 285812479SCurtis.Dunham@arm.com .warnNotFail() 285912479SCurtis.Dunham@arm.com .bankedChild() 286012479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 286112479SCurtis.Dunham@arm.com InitReg(MISCREG_AIFSR) 286212479SCurtis.Dunham@arm.com .unimplemented() 286312479SCurtis.Dunham@arm.com .warnNotFail() 286412479SCurtis.Dunham@arm.com .banked(); 286512479SCurtis.Dunham@arm.com InitReg(MISCREG_AIFSR_NS) 286612479SCurtis.Dunham@arm.com .unimplemented() 286712479SCurtis.Dunham@arm.com .warnNotFail() 286812479SCurtis.Dunham@arm.com .bankedChild() 286912661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 287012479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 287112479SCurtis.Dunham@arm.com InitReg(MISCREG_AIFSR_S) 287212479SCurtis.Dunham@arm.com .unimplemented() 287312479SCurtis.Dunham@arm.com .warnNotFail() 287412479SCurtis.Dunham@arm.com .bankedChild() 287512479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 287612479SCurtis.Dunham@arm.com InitReg(MISCREG_HADFSR) 287712479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 287812479SCurtis.Dunham@arm.com InitReg(MISCREG_HAIFSR) 287912479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 288012479SCurtis.Dunham@arm.com InitReg(MISCREG_HSR) 288112479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 288212479SCurtis.Dunham@arm.com InitReg(MISCREG_DFAR) 288312479SCurtis.Dunham@arm.com .banked(); 288412479SCurtis.Dunham@arm.com InitReg(MISCREG_DFAR_NS) 288512479SCurtis.Dunham@arm.com .bankedChild() 288612661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 288712479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 288812479SCurtis.Dunham@arm.com InitReg(MISCREG_DFAR_S) 288912479SCurtis.Dunham@arm.com .bankedChild() 289012479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 289112479SCurtis.Dunham@arm.com InitReg(MISCREG_IFAR) 289212479SCurtis.Dunham@arm.com .banked(); 289312479SCurtis.Dunham@arm.com InitReg(MISCREG_IFAR_NS) 289412479SCurtis.Dunham@arm.com .bankedChild() 289512661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 289612479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 289712479SCurtis.Dunham@arm.com InitReg(MISCREG_IFAR_S) 289812479SCurtis.Dunham@arm.com .bankedChild() 289912479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 290012479SCurtis.Dunham@arm.com InitReg(MISCREG_HDFAR) 290112479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 290212479SCurtis.Dunham@arm.com InitReg(MISCREG_HIFAR) 290312479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 290412479SCurtis.Dunham@arm.com InitReg(MISCREG_HPFAR) 290512479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 290612479SCurtis.Dunham@arm.com InitReg(MISCREG_ICIALLUIS) 290712479SCurtis.Dunham@arm.com .unimplemented() 290812479SCurtis.Dunham@arm.com .warnNotFail() 290912479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 291012479SCurtis.Dunham@arm.com InitReg(MISCREG_BPIALLIS) 291112479SCurtis.Dunham@arm.com .unimplemented() 291212479SCurtis.Dunham@arm.com .warnNotFail() 291312479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 291412479SCurtis.Dunham@arm.com InitReg(MISCREG_PAR) 291512479SCurtis.Dunham@arm.com .banked(); 291612479SCurtis.Dunham@arm.com InitReg(MISCREG_PAR_NS) 291712479SCurtis.Dunham@arm.com .bankedChild() 291812661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 291912479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 292012479SCurtis.Dunham@arm.com InitReg(MISCREG_PAR_S) 292112479SCurtis.Dunham@arm.com .bankedChild() 292212479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 292312479SCurtis.Dunham@arm.com InitReg(MISCREG_ICIALLU) 292412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 292512479SCurtis.Dunham@arm.com InitReg(MISCREG_ICIMVAU) 292612479SCurtis.Dunham@arm.com .unimplemented() 292712479SCurtis.Dunham@arm.com .warnNotFail() 292812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 292912479SCurtis.Dunham@arm.com InitReg(MISCREG_CP15ISB) 293012479SCurtis.Dunham@arm.com .writes(1); 293112479SCurtis.Dunham@arm.com InitReg(MISCREG_BPIALL) 293212479SCurtis.Dunham@arm.com .unimplemented() 293312479SCurtis.Dunham@arm.com .warnNotFail() 293412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 293512479SCurtis.Dunham@arm.com InitReg(MISCREG_BPIMVA) 293612479SCurtis.Dunham@arm.com .unimplemented() 293712479SCurtis.Dunham@arm.com .warnNotFail() 293812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 293912479SCurtis.Dunham@arm.com InitReg(MISCREG_DCIMVAC) 294012479SCurtis.Dunham@arm.com .unimplemented() 294112479SCurtis.Dunham@arm.com .warnNotFail() 294212479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 294312479SCurtis.Dunham@arm.com InitReg(MISCREG_DCISW) 294412479SCurtis.Dunham@arm.com .unimplemented() 294512479SCurtis.Dunham@arm.com .warnNotFail() 294612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 294712479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS1CPR) 294812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 294912479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS1CPW) 295012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 295112479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS1CUR) 295212479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 295312479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS1CUW) 295412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 295512479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS12NSOPR) 295612479SCurtis.Dunham@arm.com .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 295712479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS12NSOPW) 295812479SCurtis.Dunham@arm.com .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 295912479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS12NSOUR) 296012479SCurtis.Dunham@arm.com .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 296112479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS12NSOUW) 296212479SCurtis.Dunham@arm.com .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 296312479SCurtis.Dunham@arm.com InitReg(MISCREG_DCCMVAC) 296412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 296512479SCurtis.Dunham@arm.com InitReg(MISCREG_DCCSW) 296612479SCurtis.Dunham@arm.com .unimplemented() 296712479SCurtis.Dunham@arm.com .warnNotFail() 296812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 296912479SCurtis.Dunham@arm.com InitReg(MISCREG_CP15DSB) 297012479SCurtis.Dunham@arm.com .writes(1); 297112479SCurtis.Dunham@arm.com InitReg(MISCREG_CP15DMB) 297212479SCurtis.Dunham@arm.com .writes(1); 297312479SCurtis.Dunham@arm.com InitReg(MISCREG_DCCMVAU) 297412479SCurtis.Dunham@arm.com .unimplemented() 297512479SCurtis.Dunham@arm.com .warnNotFail() 297612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 297712479SCurtis.Dunham@arm.com InitReg(MISCREG_DCCIMVAC) 297812479SCurtis.Dunham@arm.com .unimplemented() 297912479SCurtis.Dunham@arm.com .warnNotFail() 298012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 298112479SCurtis.Dunham@arm.com InitReg(MISCREG_DCCISW) 298212479SCurtis.Dunham@arm.com .unimplemented() 298312479SCurtis.Dunham@arm.com .warnNotFail() 298412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 298512479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS1HR) 298612479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 298712479SCurtis.Dunham@arm.com InitReg(MISCREG_ATS1HW) 298812479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 298912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIALLIS) 299012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 299112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVAIS) 299212479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 299312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIASIDIS) 299412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 299512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVAAIS) 299612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 299712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVALIS) 299812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 299912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVAALIS) 300012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 300112479SCurtis.Dunham@arm.com InitReg(MISCREG_ITLBIALL) 300212479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 300312479SCurtis.Dunham@arm.com InitReg(MISCREG_ITLBIMVA) 300412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 300512479SCurtis.Dunham@arm.com InitReg(MISCREG_ITLBIASID) 300612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 300712479SCurtis.Dunham@arm.com InitReg(MISCREG_DTLBIALL) 300812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 300912479SCurtis.Dunham@arm.com InitReg(MISCREG_DTLBIMVA) 301012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 301112479SCurtis.Dunham@arm.com InitReg(MISCREG_DTLBIASID) 301212479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 301312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIALL) 301412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 301512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVA) 301612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 301712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIASID) 301812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 301912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVAA) 302012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 302112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVAL) 302212479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 302312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVAAL) 302412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 302512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIIPAS2IS) 302612479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 302712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIIPAS2LIS) 302812479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 302912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIALLHIS) 303012479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 303112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVAHIS) 303212479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 303312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIALLNSNHIS) 303412479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 303512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVALHIS) 303612479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 303712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIIPAS2) 303812479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 303912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIIPAS2L) 304012479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 304112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIALLH) 304212479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 304312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVAH) 304412479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 304512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIALLNSNH) 304612479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 304712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBIMVALH) 304812479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 304912479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCR) 305012479SCurtis.Dunham@arm.com .allPrivileges(); 305112479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCNTENSET) 305212479SCurtis.Dunham@arm.com .allPrivileges(); 305312479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCNTENCLR) 305412479SCurtis.Dunham@arm.com .allPrivileges(); 305512479SCurtis.Dunham@arm.com InitReg(MISCREG_PMOVSR) 305612479SCurtis.Dunham@arm.com .allPrivileges(); 305712479SCurtis.Dunham@arm.com InitReg(MISCREG_PMSWINC) 305812479SCurtis.Dunham@arm.com .allPrivileges(); 305912479SCurtis.Dunham@arm.com InitReg(MISCREG_PMSELR) 306012479SCurtis.Dunham@arm.com .allPrivileges(); 306112479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCEID0) 306212479SCurtis.Dunham@arm.com .allPrivileges(); 306312479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCEID1) 306412479SCurtis.Dunham@arm.com .allPrivileges(); 306512479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCCNTR) 306612479SCurtis.Dunham@arm.com .allPrivileges(); 306712479SCurtis.Dunham@arm.com InitReg(MISCREG_PMXEVTYPER) 306812479SCurtis.Dunham@arm.com .allPrivileges(); 306912479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCCFILTR) 307012479SCurtis.Dunham@arm.com .allPrivileges(); 307112479SCurtis.Dunham@arm.com InitReg(MISCREG_PMXEVCNTR) 307212479SCurtis.Dunham@arm.com .allPrivileges(); 307312479SCurtis.Dunham@arm.com InitReg(MISCREG_PMUSERENR) 307412479SCurtis.Dunham@arm.com .allPrivileges().userNonSecureWrite(0).userSecureWrite(0); 307512479SCurtis.Dunham@arm.com InitReg(MISCREG_PMINTENSET) 307612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 307712479SCurtis.Dunham@arm.com InitReg(MISCREG_PMINTENCLR) 307812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 307912479SCurtis.Dunham@arm.com InitReg(MISCREG_PMOVSSET) 308012479SCurtis.Dunham@arm.com .unimplemented() 308112479SCurtis.Dunham@arm.com .allPrivileges(); 308212479SCurtis.Dunham@arm.com InitReg(MISCREG_L2CTLR) 308312479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 308412479SCurtis.Dunham@arm.com InitReg(MISCREG_L2ECTLR) 308512479SCurtis.Dunham@arm.com .unimplemented() 308612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 308712479SCurtis.Dunham@arm.com InitReg(MISCREG_PRRR) 308812479SCurtis.Dunham@arm.com .banked(); 308912479SCurtis.Dunham@arm.com InitReg(MISCREG_PRRR_NS) 309012479SCurtis.Dunham@arm.com .bankedChild() 309112661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 309212479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 309312479SCurtis.Dunham@arm.com InitReg(MISCREG_PRRR_S) 309412479SCurtis.Dunham@arm.com .bankedChild() 309512479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 309612479SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR0) 309712479SCurtis.Dunham@arm.com .banked(); 309812479SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR0_NS) 309912479SCurtis.Dunham@arm.com .bankedChild() 310012661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 310112479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 310212479SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR0_S) 310312479SCurtis.Dunham@arm.com .bankedChild() 310412479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 310512479SCurtis.Dunham@arm.com InitReg(MISCREG_NMRR) 310612479SCurtis.Dunham@arm.com .banked(); 310712479SCurtis.Dunham@arm.com InitReg(MISCREG_NMRR_NS) 310812479SCurtis.Dunham@arm.com .bankedChild() 310912661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 311012479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 311112479SCurtis.Dunham@arm.com InitReg(MISCREG_NMRR_S) 311212479SCurtis.Dunham@arm.com .bankedChild() 311312479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 311412479SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR1) 311512479SCurtis.Dunham@arm.com .banked(); 311612479SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR1_NS) 311712479SCurtis.Dunham@arm.com .bankedChild() 311812661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 311912479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 312012479SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR1_S) 312112479SCurtis.Dunham@arm.com .bankedChild() 312212479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 312312479SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR0) 312412479SCurtis.Dunham@arm.com .banked(); 312512479SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR0_NS) 312612479SCurtis.Dunham@arm.com .bankedChild() 312712661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 312812479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 312912479SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR0_S) 313012479SCurtis.Dunham@arm.com .bankedChild() 313112479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 313212479SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR1) 313312479SCurtis.Dunham@arm.com .banked(); 313412479SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR1_NS) 313512479SCurtis.Dunham@arm.com .bankedChild() 313612661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 313712479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 313812479SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR1_S) 313912479SCurtis.Dunham@arm.com .bankedChild() 314012479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 314112479SCurtis.Dunham@arm.com InitReg(MISCREG_HMAIR0) 314212479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 314312479SCurtis.Dunham@arm.com InitReg(MISCREG_HMAIR1) 314412479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 314512479SCurtis.Dunham@arm.com InitReg(MISCREG_HAMAIR0) 314612479SCurtis.Dunham@arm.com .unimplemented() 314712479SCurtis.Dunham@arm.com .warnNotFail() 314812479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 314912479SCurtis.Dunham@arm.com InitReg(MISCREG_HAMAIR1) 315012479SCurtis.Dunham@arm.com .unimplemented() 315112479SCurtis.Dunham@arm.com .warnNotFail() 315212479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 315312479SCurtis.Dunham@arm.com InitReg(MISCREG_VBAR) 315412479SCurtis.Dunham@arm.com .banked(); 315512479SCurtis.Dunham@arm.com InitReg(MISCREG_VBAR_NS) 315612479SCurtis.Dunham@arm.com .bankedChild() 315712661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 315812479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 315912479SCurtis.Dunham@arm.com InitReg(MISCREG_VBAR_S) 316012479SCurtis.Dunham@arm.com .bankedChild() 316112479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 316212479SCurtis.Dunham@arm.com InitReg(MISCREG_MVBAR) 316312479SCurtis.Dunham@arm.com .mon().secure().exceptUserMode(); 316412479SCurtis.Dunham@arm.com InitReg(MISCREG_RMR) 316512479SCurtis.Dunham@arm.com .unimplemented() 316612479SCurtis.Dunham@arm.com .mon().secure().exceptUserMode(); 316712479SCurtis.Dunham@arm.com InitReg(MISCREG_ISR) 316812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 316912479SCurtis.Dunham@arm.com InitReg(MISCREG_HVBAR) 317012479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 317112479SCurtis.Dunham@arm.com InitReg(MISCREG_FCSEIDR) 317212479SCurtis.Dunham@arm.com .unimplemented() 317312479SCurtis.Dunham@arm.com .warnNotFail() 317412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 317512479SCurtis.Dunham@arm.com InitReg(MISCREG_CONTEXTIDR) 317612479SCurtis.Dunham@arm.com .banked(); 317712479SCurtis.Dunham@arm.com InitReg(MISCREG_CONTEXTIDR_NS) 317812479SCurtis.Dunham@arm.com .bankedChild() 317912661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 318012479SCurtis.Dunham@arm.com .nonSecure().exceptUserMode(); 318112479SCurtis.Dunham@arm.com InitReg(MISCREG_CONTEXTIDR_S) 318212479SCurtis.Dunham@arm.com .bankedChild() 318312479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 318412479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRURW) 318512479SCurtis.Dunham@arm.com .banked(); 318612479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRURW_NS) 318712479SCurtis.Dunham@arm.com .bankedChild() 318812661Sgiacomo.travaglini@arm.com .allPrivileges() 318912661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 319012661Sgiacomo.travaglini@arm.com .monSecure(0); 319112479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRURW_S) 319212479SCurtis.Dunham@arm.com .bankedChild() 319312479SCurtis.Dunham@arm.com .secure(); 319412479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRURO) 319512479SCurtis.Dunham@arm.com .banked(); 319612479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRURO_NS) 319712479SCurtis.Dunham@arm.com .bankedChild() 319812661Sgiacomo.travaglini@arm.com .allPrivileges() 319912661Sgiacomo.travaglini@arm.com .userNonSecureWrite(0).userSecureRead(1) 320012661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 320112661Sgiacomo.travaglini@arm.com .monSecure(0); 320212479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRURO_S) 320312479SCurtis.Dunham@arm.com .bankedChild() 320412479SCurtis.Dunham@arm.com .secure().userSecureWrite(0); 320512479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRPRW) 320612479SCurtis.Dunham@arm.com .banked(); 320712479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRPRW_NS) 320812479SCurtis.Dunham@arm.com .bankedChild() 320912661Sgiacomo.travaglini@arm.com .nonSecure().exceptUserMode() 321012661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3); 321112479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRPRW_S) 321212479SCurtis.Dunham@arm.com .bankedChild() 321312479SCurtis.Dunham@arm.com .secure().exceptUserMode(); 321412479SCurtis.Dunham@arm.com InitReg(MISCREG_HTPIDR) 321512479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 321612479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTFRQ) 321712479SCurtis.Dunham@arm.com .unverifiable() 321812479SCurtis.Dunham@arm.com .reads(1).mon(); 321912479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTKCTL) 322012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 322112479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_TVAL) 322212479SCurtis.Dunham@arm.com .banked(); 322312479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_TVAL_NS) 322412479SCurtis.Dunham@arm.com .bankedChild() 322512661Sgiacomo.travaglini@arm.com .allPrivileges() 322612661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 322712661Sgiacomo.travaglini@arm.com .monSecure(0); 322812479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_TVAL_S) 322912479SCurtis.Dunham@arm.com .bankedChild() 323012479SCurtis.Dunham@arm.com .secure().user(1); 323112479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CTL) 323212479SCurtis.Dunham@arm.com .banked(); 323312479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CTL_NS) 323412479SCurtis.Dunham@arm.com .bankedChild() 323512661Sgiacomo.travaglini@arm.com .allPrivileges() 323612661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 323712661Sgiacomo.travaglini@arm.com .monSecure(0); 323812479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CTL_S) 323912479SCurtis.Dunham@arm.com .bankedChild() 324012479SCurtis.Dunham@arm.com .secure().user(1); 324112479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTV_TVAL) 324212479SCurtis.Dunham@arm.com .allPrivileges(); 324312479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTV_CTL) 324412479SCurtis.Dunham@arm.com .allPrivileges(); 324512479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHCTL) 324612479SCurtis.Dunham@arm.com .hypWrite().monNonSecureRead(); 324712479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHP_TVAL) 324812479SCurtis.Dunham@arm.com .hypWrite().monNonSecureRead(); 324912479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHP_CTL) 325012479SCurtis.Dunham@arm.com .hypWrite().monNonSecureRead(); 325112479SCurtis.Dunham@arm.com InitReg(MISCREG_IL1DATA0) 325212479SCurtis.Dunham@arm.com .unimplemented() 325312479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 325412479SCurtis.Dunham@arm.com InitReg(MISCREG_IL1DATA1) 325512479SCurtis.Dunham@arm.com .unimplemented() 325612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 325712479SCurtis.Dunham@arm.com InitReg(MISCREG_IL1DATA2) 325812479SCurtis.Dunham@arm.com .unimplemented() 325912479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 326012479SCurtis.Dunham@arm.com InitReg(MISCREG_IL1DATA3) 326112479SCurtis.Dunham@arm.com .unimplemented() 326212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 326312479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA0) 326412479SCurtis.Dunham@arm.com .unimplemented() 326512479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 326612479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA1) 326712479SCurtis.Dunham@arm.com .unimplemented() 326812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 326912479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA2) 327012479SCurtis.Dunham@arm.com .unimplemented() 327112479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 327212479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA3) 327312479SCurtis.Dunham@arm.com .unimplemented() 327412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 327512479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA4) 327612479SCurtis.Dunham@arm.com .unimplemented() 327712479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 327812479SCurtis.Dunham@arm.com InitReg(MISCREG_RAMINDEX) 327912479SCurtis.Dunham@arm.com .unimplemented() 328012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 328112479SCurtis.Dunham@arm.com InitReg(MISCREG_L2ACTLR) 328212479SCurtis.Dunham@arm.com .unimplemented() 328312479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 328412479SCurtis.Dunham@arm.com InitReg(MISCREG_CBAR) 328512479SCurtis.Dunham@arm.com .unimplemented() 328612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 328712479SCurtis.Dunham@arm.com InitReg(MISCREG_HTTBR) 328812479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 328912479SCurtis.Dunham@arm.com InitReg(MISCREG_VTTBR) 329012479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 329112479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTPCT) 329212479SCurtis.Dunham@arm.com .reads(1); 329312479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTVCT) 329412479SCurtis.Dunham@arm.com .unverifiable() 329512479SCurtis.Dunham@arm.com .reads(1); 329612479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CVAL) 329712479SCurtis.Dunham@arm.com .banked(); 329812479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CVAL_NS) 329912479SCurtis.Dunham@arm.com .bankedChild() 330012661Sgiacomo.travaglini@arm.com .allPrivileges() 330112661Sgiacomo.travaglini@arm.com .privSecure(!aarch32EL3) 330212661Sgiacomo.travaglini@arm.com .monSecure(0); 330312479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CVAL_S) 330412479SCurtis.Dunham@arm.com .bankedChild() 330512479SCurtis.Dunham@arm.com .secure().user(1); 330612479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTV_CVAL) 330712479SCurtis.Dunham@arm.com .allPrivileges(); 330812479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTVOFF) 330912479SCurtis.Dunham@arm.com .hyp().monNonSecure(); 331012479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHP_CVAL) 331112479SCurtis.Dunham@arm.com .hypWrite().monNonSecureRead(); 331212479SCurtis.Dunham@arm.com InitReg(MISCREG_CPUMERRSR) 331312479SCurtis.Dunham@arm.com .unimplemented() 331412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 331512479SCurtis.Dunham@arm.com InitReg(MISCREG_L2MERRSR) 331612479SCurtis.Dunham@arm.com .unimplemented() 331712479SCurtis.Dunham@arm.com .warnNotFail() 331812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 331912479SCurtis.Dunham@arm.com 332012479SCurtis.Dunham@arm.com // AArch64 registers (Op0=2); 332112479SCurtis.Dunham@arm.com InitReg(MISCREG_MDCCINT_EL1) 332212479SCurtis.Dunham@arm.com .allPrivileges(); 332312479SCurtis.Dunham@arm.com InitReg(MISCREG_OSDTRRX_EL1) 332412479SCurtis.Dunham@arm.com .allPrivileges() 332512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGDTRRXext); 332612479SCurtis.Dunham@arm.com InitReg(MISCREG_MDSCR_EL1) 332712479SCurtis.Dunham@arm.com .allPrivileges() 332812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGDSCRext); 332912479SCurtis.Dunham@arm.com InitReg(MISCREG_OSDTRTX_EL1) 333012479SCurtis.Dunham@arm.com .allPrivileges() 333112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGDTRTXext); 333212479SCurtis.Dunham@arm.com InitReg(MISCREG_OSECCR_EL1) 333312479SCurtis.Dunham@arm.com .allPrivileges() 333412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGOSECCR); 333512479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR0_EL1) 333612479SCurtis.Dunham@arm.com .allPrivileges() 333712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */); 333812479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR1_EL1) 333912479SCurtis.Dunham@arm.com .allPrivileges() 334012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */); 334112479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR2_EL1) 334212479SCurtis.Dunham@arm.com .allPrivileges() 334312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */); 334412479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR3_EL1) 334512479SCurtis.Dunham@arm.com .allPrivileges() 334612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */); 334712479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR4_EL1) 334812479SCurtis.Dunham@arm.com .allPrivileges() 334912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */); 335012479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR5_EL1) 335112479SCurtis.Dunham@arm.com .allPrivileges() 335212479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */); 335312479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR0_EL1) 335412479SCurtis.Dunham@arm.com .allPrivileges() 335512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBCR0); 335612479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR1_EL1) 335712479SCurtis.Dunham@arm.com .allPrivileges() 335812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBCR1); 335912479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR2_EL1) 336012479SCurtis.Dunham@arm.com .allPrivileges() 336112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBCR2); 336212479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR3_EL1) 336312479SCurtis.Dunham@arm.com .allPrivileges() 336412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBCR3); 336512479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR4_EL1) 336612479SCurtis.Dunham@arm.com .allPrivileges() 336712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBCR4); 336812479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR5_EL1) 336912479SCurtis.Dunham@arm.com .allPrivileges() 337012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGBCR5); 337112479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR0_EL1) 337212479SCurtis.Dunham@arm.com .allPrivileges() 337312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGWVR0); 337412479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR1_EL1) 337512479SCurtis.Dunham@arm.com .allPrivileges() 337612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGWVR1); 337712479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR2_EL1) 337812479SCurtis.Dunham@arm.com .allPrivileges() 337912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGWVR2); 338012479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR3_EL1) 338112479SCurtis.Dunham@arm.com .allPrivileges() 338212479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGWVR3); 338312479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR0_EL1) 338412479SCurtis.Dunham@arm.com .allPrivileges() 338512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGWCR0); 338612479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR1_EL1) 338712479SCurtis.Dunham@arm.com .allPrivileges() 338812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGWCR1); 338912479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR2_EL1) 339012479SCurtis.Dunham@arm.com .allPrivileges() 339112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGWCR2); 339212479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR3_EL1) 339312479SCurtis.Dunham@arm.com .allPrivileges() 339412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGWCR3); 339512479SCurtis.Dunham@arm.com InitReg(MISCREG_MDCCSR_EL0) 339612479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 339712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGDSCRint); 339812479SCurtis.Dunham@arm.com InitReg(MISCREG_MDDTR_EL0) 339912479SCurtis.Dunham@arm.com .allPrivileges(); 340012479SCurtis.Dunham@arm.com InitReg(MISCREG_MDDTRTX_EL0) 340112479SCurtis.Dunham@arm.com .allPrivileges(); 340212479SCurtis.Dunham@arm.com InitReg(MISCREG_MDDTRRX_EL0) 340312479SCurtis.Dunham@arm.com .allPrivileges(); 340412479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGVCR32_EL2) 340512479SCurtis.Dunham@arm.com .allPrivileges() 340612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGVCR); 340712479SCurtis.Dunham@arm.com InitReg(MISCREG_MDRAR_EL1) 340812479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 340912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGDRAR); 341012479SCurtis.Dunham@arm.com InitReg(MISCREG_OSLAR_EL1) 341112479SCurtis.Dunham@arm.com .allPrivileges().monSecureRead(0).monNonSecureRead(0) 341212479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGOSLAR); 341312479SCurtis.Dunham@arm.com InitReg(MISCREG_OSLSR_EL1) 341412479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 341512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGOSLSR); 341612479SCurtis.Dunham@arm.com InitReg(MISCREG_OSDLR_EL1) 341712479SCurtis.Dunham@arm.com .allPrivileges() 341812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGOSDLR); 341912479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGPRCR_EL1) 342012479SCurtis.Dunham@arm.com .allPrivileges() 342112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGPRCR); 342212479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGCLAIMSET_EL1) 342312479SCurtis.Dunham@arm.com .allPrivileges() 342412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGCLAIMSET); 342512479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGCLAIMCLR_EL1) 342612479SCurtis.Dunham@arm.com .allPrivileges() 342712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGCLAIMCLR); 342812479SCurtis.Dunham@arm.com InitReg(MISCREG_DBGAUTHSTATUS_EL1) 342912479SCurtis.Dunham@arm.com .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 343012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DBGAUTHSTATUS); 343112479SCurtis.Dunham@arm.com InitReg(MISCREG_TEECR32_EL1); 343212479SCurtis.Dunham@arm.com InitReg(MISCREG_TEEHBR32_EL1); 343312479SCurtis.Dunham@arm.com 343412479SCurtis.Dunham@arm.com // AArch64 registers (Op0=1,3); 343512479SCurtis.Dunham@arm.com InitReg(MISCREG_MIDR_EL1) 343612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 343712479SCurtis.Dunham@arm.com InitReg(MISCREG_MPIDR_EL1) 343812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 343912479SCurtis.Dunham@arm.com InitReg(MISCREG_REVIDR_EL1) 344012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 344112479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_PFR0_EL1) 344212690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 344312690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_PFR0); 344412479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_PFR1_EL1) 344512690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 344612690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_PFR1); 344712479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_DFR0_EL1) 344812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0) 344912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_ID_DFR0); 345012479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AFR0_EL1) 345112690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 345212690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_AFR0); 345312479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_MMFR0_EL1) 345412690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 345512690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_MMFR0); 345612479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_MMFR1_EL1) 345712690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 345812690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_MMFR1); 345912479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_MMFR2_EL1) 346012690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 346112690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_MMFR2); 346212479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_MMFR3_EL1) 346312690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 346412690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_MMFR3); 346512479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR0_EL1) 346612690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 346712690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_ISAR0); 346812479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR1_EL1) 346912690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 347012690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_ISAR1); 347112479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR2_EL1) 347212690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 347312690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_ISAR2); 347412479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR3_EL1) 347512690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 347612690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_ISAR3); 347712479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR4_EL1) 347812690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 347912690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_ISAR4); 348012479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_ISAR5_EL1) 348112690Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0) 348212690Sgiacomo.travaglini@arm.com .mapsTo(MISCREG_ID_ISAR5); 348312479SCurtis.Dunham@arm.com InitReg(MISCREG_MVFR0_EL1) 348412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 348512479SCurtis.Dunham@arm.com InitReg(MISCREG_MVFR1_EL1) 348612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 348712479SCurtis.Dunham@arm.com InitReg(MISCREG_MVFR2_EL1) 348812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 348912479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64PFR0_EL1) 349012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 349112479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64PFR1_EL1) 349212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 349312479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64DFR0_EL1) 349412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 349512479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64DFR1_EL1) 349612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 349712479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64AFR0_EL1) 349812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 349912479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64AFR1_EL1) 350012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 350112479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64ISAR0_EL1) 350212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 350312479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64ISAR1_EL1) 350412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 350512479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64MMFR0_EL1) 350612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 350712479SCurtis.Dunham@arm.com InitReg(MISCREG_ID_AA64MMFR1_EL1) 350812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 350913116Sgiacomo.travaglini@arm.com InitReg(MISCREG_ID_AA64MMFR2_EL1) 351013116Sgiacomo.travaglini@arm.com .allPrivileges().exceptUserMode().writes(0); 351112479SCurtis.Dunham@arm.com InitReg(MISCREG_CCSIDR_EL1) 351212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 351312479SCurtis.Dunham@arm.com InitReg(MISCREG_CLIDR_EL1) 351412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 351512479SCurtis.Dunham@arm.com InitReg(MISCREG_AIDR_EL1) 351612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 351712479SCurtis.Dunham@arm.com InitReg(MISCREG_CSSELR_EL1) 351812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 351912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CSSELR_NS); 352012479SCurtis.Dunham@arm.com InitReg(MISCREG_CTR_EL0) 352112479SCurtis.Dunham@arm.com .reads(1); 352212479SCurtis.Dunham@arm.com InitReg(MISCREG_DCZID_EL0) 352312479SCurtis.Dunham@arm.com .reads(1); 352412479SCurtis.Dunham@arm.com InitReg(MISCREG_VPIDR_EL2) 352512479SCurtis.Dunham@arm.com .hyp().mon() 352612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_VPIDR); 352712479SCurtis.Dunham@arm.com InitReg(MISCREG_VMPIDR_EL2) 352812479SCurtis.Dunham@arm.com .hyp().mon() 352912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_VMPIDR); 353012479SCurtis.Dunham@arm.com InitReg(MISCREG_SCTLR_EL1) 353112479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 353212479SCurtis.Dunham@arm.com .mapsTo(MISCREG_SCTLR_NS); 353312479SCurtis.Dunham@arm.com InitReg(MISCREG_ACTLR_EL1) 353412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 353512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_ACTLR_NS); 353612479SCurtis.Dunham@arm.com InitReg(MISCREG_CPACR_EL1) 353712479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 353812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CPACR); 353912479SCurtis.Dunham@arm.com InitReg(MISCREG_SCTLR_EL2) 354012479SCurtis.Dunham@arm.com .hyp().mon() 354112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HSCTLR); 354212479SCurtis.Dunham@arm.com InitReg(MISCREG_ACTLR_EL2) 354312479SCurtis.Dunham@arm.com .hyp().mon() 354412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HACTLR); 354512479SCurtis.Dunham@arm.com InitReg(MISCREG_HCR_EL2) 354612479SCurtis.Dunham@arm.com .hyp().mon() 354712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/); 354812479SCurtis.Dunham@arm.com InitReg(MISCREG_MDCR_EL2) 354912479SCurtis.Dunham@arm.com .hyp().mon() 355012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HDCR); 355112479SCurtis.Dunham@arm.com InitReg(MISCREG_CPTR_EL2) 355212479SCurtis.Dunham@arm.com .hyp().mon() 355312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HCPTR); 355412479SCurtis.Dunham@arm.com InitReg(MISCREG_HSTR_EL2) 355512479SCurtis.Dunham@arm.com .hyp().mon() 355612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HSTR); 355712479SCurtis.Dunham@arm.com InitReg(MISCREG_HACR_EL2) 355812479SCurtis.Dunham@arm.com .hyp().mon() 355912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HACR); 356012479SCurtis.Dunham@arm.com InitReg(MISCREG_SCTLR_EL3) 356112479SCurtis.Dunham@arm.com .mon(); 356212479SCurtis.Dunham@arm.com InitReg(MISCREG_ACTLR_EL3) 356312479SCurtis.Dunham@arm.com .mon(); 356412479SCurtis.Dunham@arm.com InitReg(MISCREG_SCR_EL3) 356512479SCurtis.Dunham@arm.com .mon() 356612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_SCR); // NAM D7-2005 356712479SCurtis.Dunham@arm.com InitReg(MISCREG_SDER32_EL3) 356812479SCurtis.Dunham@arm.com .mon() 356912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_SDER); 357012479SCurtis.Dunham@arm.com InitReg(MISCREG_CPTR_EL3) 357112479SCurtis.Dunham@arm.com .mon(); 357212479SCurtis.Dunham@arm.com InitReg(MISCREG_MDCR_EL3) 357312479SCurtis.Dunham@arm.com .mon(); 357412479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR0_EL1) 357512479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 357612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_TTBR0_NS); 357712479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR1_EL1) 357812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 357912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_TTBR1_NS); 358012479SCurtis.Dunham@arm.com InitReg(MISCREG_TCR_EL1) 358112479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 358212479SCurtis.Dunham@arm.com .mapsTo(MISCREG_TTBCR_NS); 358312479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR0_EL2) 358412479SCurtis.Dunham@arm.com .hyp().mon() 358512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HTTBR); 358612675Sgiacomo.travaglini@arm.com InitReg(MISCREG_TTBR1_EL2) 358712709Sgiacomo.travaglini@arm.com .hyp().mon(); 358812479SCurtis.Dunham@arm.com InitReg(MISCREG_TCR_EL2) 358912479SCurtis.Dunham@arm.com .hyp().mon() 359012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HTCR); 359112479SCurtis.Dunham@arm.com InitReg(MISCREG_VTTBR_EL2) 359212479SCurtis.Dunham@arm.com .hyp().mon() 359312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_VTTBR); 359412479SCurtis.Dunham@arm.com InitReg(MISCREG_VTCR_EL2) 359512479SCurtis.Dunham@arm.com .hyp().mon() 359612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_VTCR); 359712479SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR0_EL3) 359812479SCurtis.Dunham@arm.com .mon(); 359912479SCurtis.Dunham@arm.com InitReg(MISCREG_TCR_EL3) 360012479SCurtis.Dunham@arm.com .mon(); 360112479SCurtis.Dunham@arm.com InitReg(MISCREG_DACR32_EL2) 360212479SCurtis.Dunham@arm.com .hyp().mon() 360312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DACR_NS); 360412479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_EL1) 360512479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 360612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1 360712479SCurtis.Dunham@arm.com InitReg(MISCREG_ELR_EL1) 360812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 360912479SCurtis.Dunham@arm.com InitReg(MISCREG_SP_EL0) 361012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 361112479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSEL) 361212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 361312479SCurtis.Dunham@arm.com InitReg(MISCREG_CURRENTEL) 361412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 361512479SCurtis.Dunham@arm.com InitReg(MISCREG_NZCV) 361612479SCurtis.Dunham@arm.com .allPrivileges(); 361712479SCurtis.Dunham@arm.com InitReg(MISCREG_DAIF) 361812479SCurtis.Dunham@arm.com .allPrivileges(); 361912479SCurtis.Dunham@arm.com InitReg(MISCREG_FPCR) 362012479SCurtis.Dunham@arm.com .allPrivileges(); 362112479SCurtis.Dunham@arm.com InitReg(MISCREG_FPSR) 362212479SCurtis.Dunham@arm.com .allPrivileges(); 362312479SCurtis.Dunham@arm.com InitReg(MISCREG_DSPSR_EL0) 362412479SCurtis.Dunham@arm.com .allPrivileges(); 362512479SCurtis.Dunham@arm.com InitReg(MISCREG_DLR_EL0) 362612479SCurtis.Dunham@arm.com .allPrivileges(); 362712479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_EL2) 362812479SCurtis.Dunham@arm.com .hyp().mon() 362912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2 363012479SCurtis.Dunham@arm.com InitReg(MISCREG_ELR_EL2) 363112479SCurtis.Dunham@arm.com .hyp().mon(); 363212479SCurtis.Dunham@arm.com InitReg(MISCREG_SP_EL1) 363312479SCurtis.Dunham@arm.com .hyp().mon(); 363412479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_IRQ_AA64) 363512479SCurtis.Dunham@arm.com .hyp().mon(); 363612479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_ABT_AA64) 363712479SCurtis.Dunham@arm.com .hyp().mon(); 363812479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_UND_AA64) 363912479SCurtis.Dunham@arm.com .hyp().mon(); 364012479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_FIQ_AA64) 364112479SCurtis.Dunham@arm.com .hyp().mon(); 364212479SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_EL3) 364312479SCurtis.Dunham@arm.com .mon() 364412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3 364512479SCurtis.Dunham@arm.com InitReg(MISCREG_ELR_EL3) 364612479SCurtis.Dunham@arm.com .mon(); 364712479SCurtis.Dunham@arm.com InitReg(MISCREG_SP_EL2) 364812479SCurtis.Dunham@arm.com .mon(); 364912479SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR0_EL1) 365012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 365112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_ADFSR_NS); 365212479SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR1_EL1) 365312479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 365412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_AIFSR_NS); 365512479SCurtis.Dunham@arm.com InitReg(MISCREG_ESR_EL1) 365612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 365712479SCurtis.Dunham@arm.com InitReg(MISCREG_IFSR32_EL2) 365812479SCurtis.Dunham@arm.com .hyp().mon() 365912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_IFSR_NS); 366012479SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR0_EL2) 366112479SCurtis.Dunham@arm.com .hyp().mon() 366212479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HADFSR); 366312479SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR1_EL2) 366412479SCurtis.Dunham@arm.com .hyp().mon() 366512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HAIFSR); 366612479SCurtis.Dunham@arm.com InitReg(MISCREG_ESR_EL2) 366712479SCurtis.Dunham@arm.com .hyp().mon() 366812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HSR); 366912479SCurtis.Dunham@arm.com InitReg(MISCREG_FPEXC32_EL2) 367012669Schuan.zhu@arm.com .hyp().mon().mapsTo(MISCREG_FPEXC); 367112479SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR0_EL3) 367212479SCurtis.Dunham@arm.com .mon(); 367312479SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR1_EL3) 367412479SCurtis.Dunham@arm.com .mon(); 367512479SCurtis.Dunham@arm.com InitReg(MISCREG_ESR_EL3) 367612479SCurtis.Dunham@arm.com .mon(); 367712479SCurtis.Dunham@arm.com InitReg(MISCREG_FAR_EL1) 367812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 367912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS); 368012479SCurtis.Dunham@arm.com InitReg(MISCREG_FAR_EL2) 368112479SCurtis.Dunham@arm.com .hyp().mon() 368212479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR); 368312479SCurtis.Dunham@arm.com InitReg(MISCREG_HPFAR_EL2) 368412479SCurtis.Dunham@arm.com .hyp().mon() 368512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HPFAR); 368612479SCurtis.Dunham@arm.com InitReg(MISCREG_FAR_EL3) 368712479SCurtis.Dunham@arm.com .mon(); 368812479SCurtis.Dunham@arm.com InitReg(MISCREG_IC_IALLUIS) 368912479SCurtis.Dunham@arm.com .warnNotFail() 369012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 369112479SCurtis.Dunham@arm.com InitReg(MISCREG_PAR_EL1) 369212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 369312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PAR_NS); 369412479SCurtis.Dunham@arm.com InitReg(MISCREG_IC_IALLU) 369512479SCurtis.Dunham@arm.com .warnNotFail() 369612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 369712479SCurtis.Dunham@arm.com InitReg(MISCREG_DC_IVAC_Xt) 369812479SCurtis.Dunham@arm.com .warnNotFail() 369912502Snikos.nikoleris@arm.com .writes(1).exceptUserMode(); 370012479SCurtis.Dunham@arm.com InitReg(MISCREG_DC_ISW_Xt) 370112479SCurtis.Dunham@arm.com .warnNotFail() 370212479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 370312479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S1E1R_Xt) 370412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 370512479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S1E1W_Xt) 370612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 370712479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S1E0R_Xt) 370812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 370912479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S1E0W_Xt) 371012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 371112479SCurtis.Dunham@arm.com InitReg(MISCREG_DC_CSW_Xt) 371212479SCurtis.Dunham@arm.com .warnNotFail() 371312479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 371412479SCurtis.Dunham@arm.com InitReg(MISCREG_DC_CISW_Xt) 371512479SCurtis.Dunham@arm.com .warnNotFail() 371612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 371712479SCurtis.Dunham@arm.com InitReg(MISCREG_DC_ZVA_Xt) 371812479SCurtis.Dunham@arm.com .warnNotFail() 371912479SCurtis.Dunham@arm.com .writes(1).userSecureWrite(0); 372012479SCurtis.Dunham@arm.com InitReg(MISCREG_IC_IVAU_Xt) 372112479SCurtis.Dunham@arm.com .writes(1); 372212479SCurtis.Dunham@arm.com InitReg(MISCREG_DC_CVAC_Xt) 372312479SCurtis.Dunham@arm.com .warnNotFail() 372412479SCurtis.Dunham@arm.com .writes(1); 372512479SCurtis.Dunham@arm.com InitReg(MISCREG_DC_CVAU_Xt) 372612479SCurtis.Dunham@arm.com .warnNotFail() 372712479SCurtis.Dunham@arm.com .writes(1); 372812479SCurtis.Dunham@arm.com InitReg(MISCREG_DC_CIVAC_Xt) 372912479SCurtis.Dunham@arm.com .warnNotFail() 373012479SCurtis.Dunham@arm.com .writes(1); 373112479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S1E2R_Xt) 373212479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 373312479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S1E2W_Xt) 373412479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 373512479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S12E1R_Xt) 373612479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 373712479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S12E1W_Xt) 373812479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 373912479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S12E0R_Xt) 374012479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 374112479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S12E0W_Xt) 374212479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 374312479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S1E3R_Xt) 374412479SCurtis.Dunham@arm.com .monSecureWrite().monNonSecureWrite(); 374512479SCurtis.Dunham@arm.com InitReg(MISCREG_AT_S1E3W_Xt) 374612479SCurtis.Dunham@arm.com .monSecureWrite().monNonSecureWrite(); 374712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VMALLE1IS) 374812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 374912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAE1IS_Xt) 375012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 375112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_ASIDE1IS_Xt) 375212479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 375312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAAE1IS_Xt) 375412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 375512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VALE1IS_Xt) 375612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 375712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAALE1IS_Xt) 375812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 375912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VMALLE1) 376012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 376112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAE1_Xt) 376212479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 376312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_ASIDE1_Xt) 376412479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 376512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAAE1_Xt) 376612479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 376712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VALE1_Xt) 376812479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 376912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAALE1_Xt) 377012479SCurtis.Dunham@arm.com .writes(1).exceptUserMode(); 377112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_IPAS2E1IS_Xt) 377212479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 377312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt) 377412479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 377512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_ALLE2IS) 377612479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 377712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAE2IS_Xt) 377812479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 377912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_ALLE1IS) 378012479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 378112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VALE2IS_Xt) 378212479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 378312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VMALLS12E1IS) 378412479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 378512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_IPAS2E1_Xt) 378612479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 378712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_IPAS2LE1_Xt) 378812479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 378912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_ALLE2) 379012479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 379112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAE2_Xt) 379212479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 379312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_ALLE1) 379412479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 379512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VALE2_Xt) 379612479SCurtis.Dunham@arm.com .monNonSecureWrite().hypWrite(); 379712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VMALLS12E1) 379812479SCurtis.Dunham@arm.com .hypWrite().monSecureWrite().monNonSecureWrite(); 379912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_ALLE3IS) 380012479SCurtis.Dunham@arm.com .monSecureWrite().monNonSecureWrite(); 380112479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAE3IS_Xt) 380212479SCurtis.Dunham@arm.com .monSecureWrite().monNonSecureWrite(); 380312479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VALE3IS_Xt) 380412479SCurtis.Dunham@arm.com .monSecureWrite().monNonSecureWrite(); 380512479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_ALLE3) 380612479SCurtis.Dunham@arm.com .monSecureWrite().monNonSecureWrite(); 380712479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VAE3_Xt) 380812479SCurtis.Dunham@arm.com .monSecureWrite().monNonSecureWrite(); 380912479SCurtis.Dunham@arm.com InitReg(MISCREG_TLBI_VALE3_Xt) 381012479SCurtis.Dunham@arm.com .monSecureWrite().monNonSecureWrite(); 381112479SCurtis.Dunham@arm.com InitReg(MISCREG_PMINTENSET_EL1) 381212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 381312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMINTENSET); 381412479SCurtis.Dunham@arm.com InitReg(MISCREG_PMINTENCLR_EL1) 381512479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 381612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMINTENCLR); 381712479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCR_EL0) 381812479SCurtis.Dunham@arm.com .allPrivileges() 381912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMCR); 382012479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCNTENSET_EL0) 382112479SCurtis.Dunham@arm.com .allPrivileges() 382212479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMCNTENSET); 382312479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCNTENCLR_EL0) 382412479SCurtis.Dunham@arm.com .allPrivileges() 382512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMCNTENCLR); 382612479SCurtis.Dunham@arm.com InitReg(MISCREG_PMOVSCLR_EL0) 382712479SCurtis.Dunham@arm.com .allPrivileges(); 382812479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMOVSCLR); 382912479SCurtis.Dunham@arm.com InitReg(MISCREG_PMSWINC_EL0) 383012479SCurtis.Dunham@arm.com .writes(1).user() 383112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMSWINC); 383212479SCurtis.Dunham@arm.com InitReg(MISCREG_PMSELR_EL0) 383312479SCurtis.Dunham@arm.com .allPrivileges() 383412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMSELR); 383512479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCEID0_EL0) 383612479SCurtis.Dunham@arm.com .reads(1).user() 383712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMCEID0); 383812479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCEID1_EL0) 383912479SCurtis.Dunham@arm.com .reads(1).user() 384012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMCEID1); 384112479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCCNTR_EL0) 384212479SCurtis.Dunham@arm.com .allPrivileges() 384312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMCCNTR); 384412479SCurtis.Dunham@arm.com InitReg(MISCREG_PMXEVTYPER_EL0) 384512479SCurtis.Dunham@arm.com .allPrivileges() 384612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMXEVTYPER); 384712479SCurtis.Dunham@arm.com InitReg(MISCREG_PMCCFILTR_EL0) 384812479SCurtis.Dunham@arm.com .allPrivileges(); 384912479SCurtis.Dunham@arm.com InitReg(MISCREG_PMXEVCNTR_EL0) 385012479SCurtis.Dunham@arm.com .allPrivileges() 385112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMXEVCNTR); 385212479SCurtis.Dunham@arm.com InitReg(MISCREG_PMUSERENR_EL0) 385312479SCurtis.Dunham@arm.com .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 385412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMUSERENR); 385512479SCurtis.Dunham@arm.com InitReg(MISCREG_PMOVSSET_EL0) 385612479SCurtis.Dunham@arm.com .allPrivileges() 385712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PMOVSSET); 385812479SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR_EL1) 385912479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 386012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS); 386112479SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR_EL1) 386212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 386312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS); 386412479SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR_EL2) 386512479SCurtis.Dunham@arm.com .hyp().mon() 386612479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1); 386712479SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR_EL2) 386812479SCurtis.Dunham@arm.com .hyp().mon() 386912479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1); 387012479SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR_EL3) 387112479SCurtis.Dunham@arm.com .mon(); 387212479SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR_EL3) 387312479SCurtis.Dunham@arm.com .mon(); 387412479SCurtis.Dunham@arm.com InitReg(MISCREG_L2CTLR_EL1) 387512479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 387612479SCurtis.Dunham@arm.com InitReg(MISCREG_L2ECTLR_EL1) 387712479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 387812479SCurtis.Dunham@arm.com InitReg(MISCREG_VBAR_EL1) 387912479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 388012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_VBAR_NS); 388112479SCurtis.Dunham@arm.com InitReg(MISCREG_RVBAR_EL1) 388212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 388312479SCurtis.Dunham@arm.com InitReg(MISCREG_ISR_EL1) 388412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 388512479SCurtis.Dunham@arm.com InitReg(MISCREG_VBAR_EL2) 388612479SCurtis.Dunham@arm.com .hyp().mon() 388712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HVBAR); 388812479SCurtis.Dunham@arm.com InitReg(MISCREG_RVBAR_EL2) 388912479SCurtis.Dunham@arm.com .mon().hyp().writes(0); 389012479SCurtis.Dunham@arm.com InitReg(MISCREG_VBAR_EL3) 389112479SCurtis.Dunham@arm.com .mon(); 389212479SCurtis.Dunham@arm.com InitReg(MISCREG_RVBAR_EL3) 389312479SCurtis.Dunham@arm.com .mon().writes(0); 389412479SCurtis.Dunham@arm.com InitReg(MISCREG_RMR_EL3) 389512479SCurtis.Dunham@arm.com .mon(); 389612479SCurtis.Dunham@arm.com InitReg(MISCREG_CONTEXTIDR_EL1) 389712479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 389812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CONTEXTIDR_NS); 389912479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDR_EL1) 390012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 390112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_TPIDRPRW_NS); 390212479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDR_EL0) 390312479SCurtis.Dunham@arm.com .allPrivileges() 390412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_TPIDRURW_NS); 390512479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRRO_EL0) 390612479SCurtis.Dunham@arm.com .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 390712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_TPIDRURO_NS); 390812479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDR_EL2) 390912479SCurtis.Dunham@arm.com .hyp().mon() 391012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_HTPIDR); 391112479SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDR_EL3) 391212479SCurtis.Dunham@arm.com .mon(); 391312479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTKCTL_EL1) 391412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode() 391512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTKCTL); 391612479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTFRQ_EL0) 391712479SCurtis.Dunham@arm.com .reads(1).mon() 391812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTFRQ); 391912479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTPCT_EL0) 392012479SCurtis.Dunham@arm.com .reads(1) 392112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTPCT); /* 64b */ 392212479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTVCT_EL0) 392312479SCurtis.Dunham@arm.com .unverifiable() 392412479SCurtis.Dunham@arm.com .reads(1) 392512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTVCT); /* 64b */ 392612479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_TVAL_EL0) 392712479SCurtis.Dunham@arm.com .allPrivileges() 392812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTP_TVAL_NS); 392912479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CTL_EL0) 393012479SCurtis.Dunham@arm.com .allPrivileges() 393112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTP_CTL_NS); 393212479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CVAL_EL0) 393312479SCurtis.Dunham@arm.com .allPrivileges() 393412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */ 393512479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTV_TVAL_EL0) 393612479SCurtis.Dunham@arm.com .allPrivileges() 393712479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTV_TVAL); 393812479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTV_CTL_EL0) 393912479SCurtis.Dunham@arm.com .allPrivileges() 394012479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTV_CTL); 394112479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTV_CVAL_EL0) 394212479SCurtis.Dunham@arm.com .allPrivileges() 394312479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTV_CVAL); /* 64b */ 394412479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR0_EL0) 394512479SCurtis.Dunham@arm.com .allPrivileges(); 394612479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVCNTR0); 394712479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR1_EL0) 394812479SCurtis.Dunham@arm.com .allPrivileges(); 394912479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVCNTR1); 395012479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR2_EL0) 395112479SCurtis.Dunham@arm.com .allPrivileges(); 395212479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVCNTR2); 395312479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR3_EL0) 395412479SCurtis.Dunham@arm.com .allPrivileges(); 395512479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVCNTR3); 395612479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR4_EL0) 395712479SCurtis.Dunham@arm.com .allPrivileges(); 395812479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVCNTR4); 395912479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR5_EL0) 396012479SCurtis.Dunham@arm.com .allPrivileges(); 396112479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVCNTR5); 396212479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER0_EL0) 396312479SCurtis.Dunham@arm.com .allPrivileges(); 396412479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVTYPER0); 396512479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER1_EL0) 396612479SCurtis.Dunham@arm.com .allPrivileges(); 396712479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVTYPER1); 396812479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER2_EL0) 396912479SCurtis.Dunham@arm.com .allPrivileges(); 397012479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVTYPER2); 397112479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER3_EL0) 397212479SCurtis.Dunham@arm.com .allPrivileges(); 397312479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVTYPER3); 397412479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER4_EL0) 397512479SCurtis.Dunham@arm.com .allPrivileges(); 397612479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVTYPER4); 397712479SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER5_EL0) 397812479SCurtis.Dunham@arm.com .allPrivileges(); 397912479SCurtis.Dunham@arm.com// .mapsTo(MISCREG_PMEVTYPER5); 398012479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTVOFF_EL2) 398112479SCurtis.Dunham@arm.com .hyp().mon() 398212479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTVOFF); /* 64b */ 398312479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHCTL_EL2) 398412733Sandreas.sandberg@arm.com .mon().hyp() 398512479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTHCTL); 398612479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHP_TVAL_EL2) 398712733Sandreas.sandberg@arm.com .mon().hyp() 398812479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTHP_TVAL); 398912479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHP_CTL_EL2) 399012733Sandreas.sandberg@arm.com .mon().hyp() 399112479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTHP_CTL); 399212479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHP_CVAL_EL2) 399312733Sandreas.sandberg@arm.com .mon().hyp() 399412479SCurtis.Dunham@arm.com .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */ 399512479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTPS_TVAL_EL1) 399612733Sandreas.sandberg@arm.com .mon().privSecure(); 399712479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTPS_CTL_EL1) 399812733Sandreas.sandberg@arm.com .mon().privSecure(); 399912479SCurtis.Dunham@arm.com InitReg(MISCREG_CNTPS_CVAL_EL1) 400012733Sandreas.sandberg@arm.com .mon().privSecure(); 400112479SCurtis.Dunham@arm.com InitReg(MISCREG_IL1DATA0_EL1) 400212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 400312479SCurtis.Dunham@arm.com InitReg(MISCREG_IL1DATA1_EL1) 400412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 400512479SCurtis.Dunham@arm.com InitReg(MISCREG_IL1DATA2_EL1) 400612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 400712479SCurtis.Dunham@arm.com InitReg(MISCREG_IL1DATA3_EL1) 400812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 400912479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA0_EL1) 401012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 401112479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA1_EL1) 401212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 401312479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA2_EL1) 401412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 401512479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA3_EL1) 401612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 401712479SCurtis.Dunham@arm.com InitReg(MISCREG_DL1DATA4_EL1) 401812479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 401912479SCurtis.Dunham@arm.com InitReg(MISCREG_L2ACTLR_EL1) 402012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 402112479SCurtis.Dunham@arm.com InitReg(MISCREG_CPUACTLR_EL1) 402212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 402312479SCurtis.Dunham@arm.com InitReg(MISCREG_CPUECTLR_EL1) 402412479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 402512479SCurtis.Dunham@arm.com InitReg(MISCREG_CPUMERRSR_EL1) 402612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 402712479SCurtis.Dunham@arm.com InitReg(MISCREG_L2MERRSR_EL1) 402812479SCurtis.Dunham@arm.com .unimplemented() 402912479SCurtis.Dunham@arm.com .warnNotFail() 403012479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode(); 403112479SCurtis.Dunham@arm.com InitReg(MISCREG_CBAR_EL1) 403212479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 403312479SCurtis.Dunham@arm.com InitReg(MISCREG_CONTEXTIDR_EL2) 403412479SCurtis.Dunham@arm.com .mon().hyp(); 403512816Sgiacomo.travaglini@arm.com InitReg(MISCREG_CNTHV_CTL_EL2) 403612816Sgiacomo.travaglini@arm.com .mon().hyp(); 403712816Sgiacomo.travaglini@arm.com InitReg(MISCREG_CNTHV_CVAL_EL2) 403812816Sgiacomo.travaglini@arm.com .mon().hyp(); 403912816Sgiacomo.travaglini@arm.com InitReg(MISCREG_CNTHV_TVAL_EL2) 404012816Sgiacomo.travaglini@arm.com .mon().hyp(); 404112479SCurtis.Dunham@arm.com 404212479SCurtis.Dunham@arm.com // Dummy registers 404312479SCurtis.Dunham@arm.com InitReg(MISCREG_NOP) 404412479SCurtis.Dunham@arm.com .allPrivileges(); 404512479SCurtis.Dunham@arm.com InitReg(MISCREG_RAZ) 404612479SCurtis.Dunham@arm.com .allPrivileges().exceptUserMode().writes(0); 404712479SCurtis.Dunham@arm.com InitReg(MISCREG_CP14_UNIMPL) 404812479SCurtis.Dunham@arm.com .unimplemented() 404912479SCurtis.Dunham@arm.com .warnNotFail(); 405012479SCurtis.Dunham@arm.com InitReg(MISCREG_CP15_UNIMPL) 405112479SCurtis.Dunham@arm.com .unimplemented() 405212479SCurtis.Dunham@arm.com .warnNotFail(); 405312479SCurtis.Dunham@arm.com InitReg(MISCREG_UNKNOWN); 405412714Sgiacomo.travaglini@arm.com InitReg(MISCREG_IMPDEF_UNIMPL) 405512714Sgiacomo.travaglini@arm.com .unimplemented() 405612714Sgiacomo.travaglini@arm.com .warnNotFail(impdefAsNop); 405712479SCurtis.Dunham@arm.com 405812815Sgiacomo.travaglini@arm.com // RAS extension (unimplemented) 405912815Sgiacomo.travaglini@arm.com InitReg(MISCREG_ERRIDR_EL1) 406012815Sgiacomo.travaglini@arm.com .unimplemented() 406112815Sgiacomo.travaglini@arm.com .warnNotFail(); 406212815Sgiacomo.travaglini@arm.com InitReg(MISCREG_ERRSELR_EL1) 406312815Sgiacomo.travaglini@arm.com .unimplemented() 406412815Sgiacomo.travaglini@arm.com .warnNotFail(); 406512815Sgiacomo.travaglini@arm.com InitReg(MISCREG_ERXFR_EL1) 406612815Sgiacomo.travaglini@arm.com .unimplemented() 406712815Sgiacomo.travaglini@arm.com .warnNotFail(); 406812815Sgiacomo.travaglini@arm.com InitReg(MISCREG_ERXCTLR_EL1) 406912815Sgiacomo.travaglini@arm.com .unimplemented() 407012815Sgiacomo.travaglini@arm.com .warnNotFail(); 407112815Sgiacomo.travaglini@arm.com InitReg(MISCREG_ERXSTATUS_EL1) 407212815Sgiacomo.travaglini@arm.com .unimplemented() 407312815Sgiacomo.travaglini@arm.com .warnNotFail(); 407412815Sgiacomo.travaglini@arm.com InitReg(MISCREG_ERXADDR_EL1) 407512815Sgiacomo.travaglini@arm.com .unimplemented() 407612815Sgiacomo.travaglini@arm.com .warnNotFail(); 407712815Sgiacomo.travaglini@arm.com InitReg(MISCREG_ERXMISC0_EL1) 407812815Sgiacomo.travaglini@arm.com .unimplemented() 407912815Sgiacomo.travaglini@arm.com .warnNotFail(); 408012815Sgiacomo.travaglini@arm.com InitReg(MISCREG_ERXMISC1_EL1) 408112815Sgiacomo.travaglini@arm.com .unimplemented() 408212815Sgiacomo.travaglini@arm.com .warnNotFail(); 408312815Sgiacomo.travaglini@arm.com InitReg(MISCREG_DISR_EL1) 408412815Sgiacomo.travaglini@arm.com .unimplemented() 408512815Sgiacomo.travaglini@arm.com .warnNotFail(); 408612815Sgiacomo.travaglini@arm.com InitReg(MISCREG_VSESR_EL2) 408712815Sgiacomo.travaglini@arm.com .unimplemented() 408812815Sgiacomo.travaglini@arm.com .warnNotFail(); 408912815Sgiacomo.travaglini@arm.com InitReg(MISCREG_VDISR_EL2) 409012815Sgiacomo.travaglini@arm.com .unimplemented() 409112815Sgiacomo.travaglini@arm.com .warnNotFail(); 409212815Sgiacomo.travaglini@arm.com 409312479SCurtis.Dunham@arm.com // Register mappings for some unimplemented registers: 409412479SCurtis.Dunham@arm.com // ESR_EL1 -> DFSR 409512479SCurtis.Dunham@arm.com // RMR_EL1 -> RMR 409612479SCurtis.Dunham@arm.com // RMR_EL2 -> HRMR 409712479SCurtis.Dunham@arm.com // DBGDTR_EL0 -> DBGDTR{R or T}Xint 409812479SCurtis.Dunham@arm.com // DBGDTRRX_EL0 -> DBGDTRRXint 409912479SCurtis.Dunham@arm.com // DBGDTRTX_EL0 -> DBGDTRRXint 410012479SCurtis.Dunham@arm.com // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5) 410112479SCurtis.Dunham@arm.com 410212479SCurtis.Dunham@arm.com completed = true; 410312479SCurtis.Dunham@arm.com} 410412479SCurtis.Dunham@arm.com 410510037SARM gem5 Developers} // namespace ArmISA 4106