gic.hh revision 11842:5a766820e739
1/* 2 * Copyright (c) 2015-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Sandberg 38 * Curtis Dunham 39 */ 40 41#ifndef __ARCH_ARM_KVM_GIC_HH__ 42#define __ARCH_ARM_KVM_GIC_HH__ 43 44#include "arch/arm/system.hh" 45#include "cpu/kvm/device.hh" 46#include "cpu/kvm/vm.hh" 47#include "dev/arm/gic_pl390.hh" 48#include "dev/platform.hh" 49 50/** 51 * KVM in-kernel GIC abstraction 52 * 53 * This class defines a high-level interface to the KVM in-kernel GIC 54 * model. It exposes an API that is similar to that of 55 * software-emulated GIC models in gem5. 56 */ 57class KvmKernelGicV2 58{ 59 public: 60 /** 61 * Instantiate a KVM in-kernel GIC model. 62 * 63 * This constructor instantiates an in-kernel GIC model and wires 64 * it up to the virtual memory system. 65 * 66 * @param vm KVM VM representing this system 67 * @param cpu_addr GIC CPU interface base address 68 * @param dist_addr GIC distributor base address 69 * @param it_lines Number of interrupt lines to support 70 */ 71 KvmKernelGicV2(KvmVM &vm, Addr cpu_addr, Addr dist_addr, 72 unsigned it_lines); 73 virtual ~KvmKernelGicV2(); 74 75 KvmKernelGicV2(const KvmKernelGicV2 &other) = delete; 76 KvmKernelGicV2(const KvmKernelGicV2 &&other) = delete; 77 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &&rhs) = delete; 78 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &rhs) = delete; 79 80 public: 81 /** 82 * @{ 83 * @name In-kernel GIC API 84 */ 85 86 /** 87 * Raise a shared peripheral interrupt 88 * 89 * @param spi SPI number 90 */ 91 void setSPI(unsigned spi); 92 /** 93 * Clear a shared peripheral interrupt 94 * 95 * @param spi SPI number 96 */ 97 void clearSPI(unsigned spi); 98 99 /** 100 * Raise a private peripheral interrupt 101 * 102 * @param vcpu KVM virtual CPU number 103 * @parma ppi PPI interrupt number 104 */ 105 void setPPI(unsigned vcpu, unsigned ppi); 106 107 /** 108 * Clear a private peripheral interrupt 109 * 110 * @param vcpu KVM virtual CPU number 111 * @parma ppi PPI interrupt number 112 */ 113 void clearPPI(unsigned vcpu, unsigned ppi); 114 115 /** Address range for the CPU interfaces */ 116 const AddrRange cpuRange; 117 /** Address range for the distributor interface */ 118 const AddrRange distRange; 119 120 /* @} */ 121 122 protected: 123 /** 124 * Update the kernel's VGIC interrupt state 125 * 126 * @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI) 127 * @param vcpu CPU id within KVM (ignored for SPIs) 128 * @param irq Interrupt number 129 * @param high True to signal an interrupt, false to clear it. 130 */ 131 void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high); 132 133 /** KVM VM in the parent system */ 134 KvmVM &vm; 135 136 /** Kernel interface to the GIC */ 137 KvmDevice kdev; 138}; 139 140 141struct MuxingKvmGicParams; 142 143class MuxingKvmGic : public Pl390 144{ 145 public: // SimObject / Serializable / Drainable 146 MuxingKvmGic(const MuxingKvmGicParams *p); 147 ~MuxingKvmGic(); 148 149 void startup() override; 150 void drainResume() override; 151 152 void serialize(CheckpointOut &cp) const override; 153 void unserialize(CheckpointIn &cp) override; 154 155 public: // PioDevice 156 Tick read(PacketPtr pkt) override; 157 Tick write(PacketPtr pkt) override; 158 159 public: // Pl390 160 void sendInt(uint32_t num) override; 161 void clearInt(uint32_t num) override; 162 163 void sendPPInt(uint32_t num, uint32_t cpu) override; 164 void clearPPInt(uint32_t num, uint32_t cpu) override; 165 166 protected: 167 /** Verify gem5 configuration will support KVM emulation */ 168 bool validKvmEnvironment() const; 169 170 /** System this interrupt controller belongs to */ 171 System &system; 172 173 /** Kernel GIC device */ 174 KvmKernelGicV2 *kernelGic; 175 176 private: 177 bool usingKvm; 178 179 /** Multiplexing implementation: state transfer functions */ 180 void fromPl390ToKvm(); 181 void fromKvmToPl390(); 182}; 183 184#endif // __ARCH_ARM_KVM_GIC_HH__ 185