gic.cc revision 10859:0ba6f47025d1
13806SN/A/* 23806SN/A * Copyright (c) 2015 ARM Limited 33806SN/A * All rights reserved 43806SN/A * 53806SN/A * The license below extends only to copyright in the software and shall 63806SN/A * not be construed as granting a license to any other intellectual 73806SN/A * property including but not limited to intellectual property relating 83806SN/A * to a hardware implementation of the functionality of the software 93806SN/A * licensed hereunder. You may use the software subject to the license 103806SN/A * terms below provided that you ensure that this notice is replicated 113806SN/A * unmodified and in its entirety in all distributions of the software, 123806SN/A * modified or unmodified, in source code or in binary form. 133806SN/A * 143806SN/A * Redistribution and use in source and binary forms, with or without 153806SN/A * modification, are permitted provided that the following conditions are 163806SN/A * met: redistributions of source code must retain the above copyright 173806SN/A * notice, this list of conditions and the following disclaimer; 183806SN/A * redistributions in binary form must reproduce the above copyright 193806SN/A * notice, this list of conditions and the following disclaimer in the 203806SN/A * documentation and/or other materials provided with the distribution; 213806SN/A * neither the name of the copyright holders nor the names of its 223806SN/A * contributors may be used to endorse or promote products derived from 233806SN/A * this software without specific prior written permission. 243806SN/A * 253806SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 263806SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 273806SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 283806SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 293806SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 303806SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 318105Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 328105Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 333806SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 343806SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 353806SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 363806SN/A * 373806SN/A * Authors: Andreas Sandberg 383806SN/A */ 393806SN/A 409897Sandreas@sandberg.pp.se#include "arch/arm/kvm/gic.hh" 418229Snate@binkert.org 423806SN/A#include <linux/kvm.h> 433806SN/A 443806SN/A#include "debug/Interrupt.hh" 453806SN/A#include "params/KvmGic.hh" 463806SN/A 477741SN/AKvmGic::KvmGic(const KvmGicParams *p) 489180Sandreas.hansson@arm.com : BaseGic(p), 493806SN/A system(*p->system), 503806SN/A vm(*p->kvmVM), 519897Sandreas@sandberg.pp.se kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2)), 529897Sandreas@sandberg.pp.se distRange(RangeSize(p->dist_addr, KVM_VGIC_V2_DIST_SIZE)), 539897Sandreas@sandberg.pp.se cpuRange(RangeSize(p->cpu_addr, KVM_VGIC_V2_CPU_SIZE)), 549897Sandreas@sandberg.pp.se addrRanges{distRange, cpuRange} 553806SN/A{ 563806SN/A kdev.setAttr<uint64_t>( 579180Sandreas.hansson@arm.com KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, 583806SN/A p->dist_addr); 593806SN/A kdev.setAttr<uint64_t>( 609897Sandreas@sandberg.pp.se KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, 619897Sandreas@sandberg.pp.se p->cpu_addr); 629897Sandreas@sandberg.pp.se} 639897Sandreas@sandberg.pp.se 643806SN/AKvmGic::~KvmGic() 653806SN/A{ 663806SN/A} 673806SN/A 683806SN/Avoid 693806SN/AKvmGic::serialize(std::ostream &os) 70{ 71 panic("Checkpointing unsupported\n"); 72} 73 74void 75KvmGic::unserialize(Checkpoint *cp, const std::string &sec) 76{ 77 panic("Checkpointing unsupported\n"); 78} 79 80Tick 81KvmGic::read(PacketPtr pkt) 82{ 83 panic("KvmGic: PIO from gem5 is currently unsupported\n"); 84} 85 86Tick 87KvmGic::write(PacketPtr pkt) 88{ 89 panic("KvmGic: PIO from gem5 is currently unsupported\n"); 90} 91 92void 93KvmGic::sendInt(uint32_t num) 94{ 95 DPRINTF(Interrupt, "Set SPI %d\n", num); 96 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, num, true); 97} 98 99void 100KvmGic::clearInt(uint32_t num) 101{ 102 DPRINTF(Interrupt, "Clear SPI %d\n", num); 103 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, num, false); 104} 105 106void 107KvmGic::sendPPInt(uint32_t num, uint32_t cpu) 108{ 109 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num); 110 setIntState(KVM_ARM_IRQ_TYPE_PPI, cpu, num, true); 111} 112 113void 114KvmGic::clearPPInt(uint32_t num, uint32_t cpu) 115{ 116 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num); 117 setIntState(KVM_ARM_IRQ_TYPE_PPI, cpu, num, false); 118} 119 120void 121KvmGic::verifyMemoryMode() const 122{ 123 if (!(system.isAtomicMode() && system.bypassCaches())) { 124 fatal("The in-kernel KVM GIC can only be used with KVM CPUs, but the " 125 "current memory mode does not support KVM.\n"); 126 } 127} 128 129void 130KvmGic::setIntState(uint8_t type, uint8_t vcpu, uint16_t irq, bool high) 131{ 132 assert(type < KVM_ARM_IRQ_TYPE_MASK); 133 assert(vcpu < KVM_ARM_IRQ_VCPU_MASK); 134 assert(irq < KVM_ARM_IRQ_NUM_MASK); 135 const uint32_t line( 136 (type << KVM_ARM_IRQ_TYPE_SHIFT) | 137 (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) | 138 (irq << KVM_ARM_IRQ_NUM_SHIFT)); 139 140 vm.setIRQLine(line, high); 141} 142 143 144KvmGic * 145KvmGicParams::create() 146{ 147 return new KvmGic(this); 148} 149