armv8_cpu.hh revision 11934:72977e8e15b8
1/* 2 * Copyright (c) 2015, 2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Sandberg 38 */ 39 40#ifndef __ARCH_ARM_KVM_ARMV8_CPU_HH__ 41#define __ARCH_ARM_KVM_ARMV8_CPU_HH__ 42 43#include <vector> 44 45#include "arch/arm/intregs.hh" 46#include "arch/arm/kvm/base_cpu.hh" 47#include "arch/arm/miscregs.hh" 48 49struct ArmV8KvmCPUParams; 50 51/** 52 * This is an implementation of a KVM-based ARMv8-compatible CPU. 53 * 54 * Known limitations: 55 * <ul> 56 * 57 * <li>The system-register-based generic timer can only be simulated 58 * by the host kernel. Workaround: Use a memory mapped timer 59 * instead to simulate the timer in gem5. 60 * 61 * <li>Simulating devices (e.g., the generic timer) in the host 62 * kernel requires that the host kernel also simulates the 63 * GIC. 64 * 65 * <li>ID registers in the host and in gem5 must match for switching 66 * between simulated CPUs and KVM. This is particularly 67 * important for ID registers describing memory system 68 * capabilities (e.g., ASID size, physical address size). 69 * 70 * <li>Switching between a virtualized CPU and a simulated CPU is 71 * currently not supported if in-kernel device emulation is 72 * used. This could be worked around by adding support for 73 * switching to the gem5 (e.g., the KvmGic) side of the device 74 * models. A simpler workaround is to avoid in-kernel device 75 * models altogether. 76 * 77 * </ul> 78 * 79 */ 80class ArmV8KvmCPU : public BaseArmKvmCPU 81{ 82 public: 83 ArmV8KvmCPU(ArmV8KvmCPUParams *params); 84 virtual ~ArmV8KvmCPU(); 85 86 void startup() override; 87 88 void dump() const override; 89 90 protected: 91 void updateKvmState() override; 92 void updateThreadContext() override; 93 94 protected: 95 /** Mapping between integer registers in gem5 and KVM */ 96 struct IntRegInfo { 97 IntRegInfo(uint64_t _kvm, IntRegIndex _idx, const char *_name) 98 : kvm(_kvm), idx(_idx), name(_name) {} 99 100 /** Register index in KVM */ 101 uint64_t kvm; 102 /** Register index in gem5 */ 103 IntRegIndex idx; 104 /** Name to use in debug dumps */ 105 const char *name; 106 }; 107 108 /** Mapping between misc registers in gem5 and registers in KVM */ 109 struct MiscRegInfo { 110 MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name) 111 : kvm(_kvm), idx(_idx), name(_name) {} 112 113 /** Register index in KVM */ 114 uint64_t kvm; 115 /** Register index in gem5 */ 116 MiscRegIndex idx; 117 /** Name to use in debug dumps */ 118 const char *name; 119 }; 120 121 /** 122 * Get a map between system registers in kvm and gem5 registers 123 * 124 * This method returns a mapping between system registers in kvm 125 * and misc regs in gem5. The actual mapping is only created the 126 * first time the method is called and stored in a cache 127 * (ArmV8KvmCPU::sysRegMap). 128 * 129 * @return Vector of kvm<->misc reg mappings. 130 */ 131 const std::vector<ArmV8KvmCPU::MiscRegInfo> &getSysRegMap() const; 132 133 /** Mapping between gem5 integer registers and integer registers in kvm */ 134 static const std::vector<ArmV8KvmCPU::IntRegInfo> intRegMap; 135 /** Mapping between gem5 misc registers registers and registers in kvm */ 136 static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegMap; 137 /** Mapping between gem5 ID misc registers registers and registers in kvm */ 138 static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegIdMap; 139 140 /** Cached mapping between system registers in kvm and misc regs in gem5 */ 141 mutable std::vector<ArmV8KvmCPU::MiscRegInfo> sysRegMap; 142}; 143 144#endif // __ARCH_ARM_KVM_ARMV8_CPU_HH__ 145