armv8_cpu.hh revision 10860
15081Sgblack@eecs.umich.edu/* 25081Sgblack@eecs.umich.edu * Copyright (c) 2015 ARM Limited 35081Sgblack@eecs.umich.edu * All rights reserved 45081Sgblack@eecs.umich.edu * 55081Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 65081Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 75081Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 85081Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 95081Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 105081Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 115081Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 125081Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 135081Sgblack@eecs.umich.edu * 145081Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 155081Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 165081Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 175081Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 185081Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 195081Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 205081Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 215081Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 225081Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 235081Sgblack@eecs.umich.edu * this software without specific prior written permission. 245081Sgblack@eecs.umich.edu * 255081Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265081Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275081Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285081Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295081Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305081Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315081Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325081Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335081Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345081Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355081Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365081Sgblack@eecs.umich.edu * 375081Sgblack@eecs.umich.edu * Authors: Andreas Sandberg 385081Sgblack@eecs.umich.edu */ 395081Sgblack@eecs.umich.edu 405081Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_KVM_ARMV8_CPU_HH__ 415081Sgblack@eecs.umich.edu#define __ARCH_ARM_KVM_ARMV8_CPU_HH__ 425081Sgblack@eecs.umich.edu 435081Sgblack@eecs.umich.edu#include <vector> 445081Sgblack@eecs.umich.edu 455081Sgblack@eecs.umich.edu#include "arch/arm/intregs.hh" 465081Sgblack@eecs.umich.edu#include "arch/arm/kvm/base_cpu.hh" 475081Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 485081Sgblack@eecs.umich.edu 495081Sgblack@eecs.umich.edustruct ArmV8KvmCPUParams; 505081Sgblack@eecs.umich.edu 515081Sgblack@eecs.umich.edu/** 525081Sgblack@eecs.umich.edu * This is an implementation of a KVM-based ARMv8-compatible CPU. 535081Sgblack@eecs.umich.edu * 545081Sgblack@eecs.umich.edu * Known limitations: 555081Sgblack@eecs.umich.edu * <ul> 565920Sgblack@eecs.umich.edu * 575920Sgblack@eecs.umich.edu * <li>The system-register-based generic timer can only be simulated 585920Sgblack@eecs.umich.edu * by the host kernel. Workaround: Use a memory mapped timer 595920Sgblack@eecs.umich.edu * instead to simulate the timer in gem5. 605920Sgblack@eecs.umich.edu * 615920Sgblack@eecs.umich.edu * <li>Simulating devices (e.g., the generic timer) in the host 625920Sgblack@eecs.umich.edu * kernel requires that the host kernel also simulates the 635920Sgblack@eecs.umich.edu * GIC. 645920Sgblack@eecs.umich.edu * 655920Sgblack@eecs.umich.edu * <li>ID registers in the host and in gem5 must match for switching 665920Sgblack@eecs.umich.edu * between simulated CPUs and KVM. This is particularly 675920Sgblack@eecs.umich.edu * important for ID registers describing memory system 685920Sgblack@eecs.umich.edu * capabilities (e.g., ASID size, physical address size). 695920Sgblack@eecs.umich.edu * 705920Sgblack@eecs.umich.edu * <li>Switching between a virtualized CPU and a simulated CPU is 715920Sgblack@eecs.umich.edu * currently not supported if in-kernel device emulation is 725920Sgblack@eecs.umich.edu * used. This could be worked around by adding support for 735920Sgblack@eecs.umich.edu * switching to the gem5 (e.g., the KvmGic) side of the device 745920Sgblack@eecs.umich.edu * models. A simpler workaround is to avoid in-kernel device 755920Sgblack@eecs.umich.edu * models altogether. 765920Sgblack@eecs.umich.edu * 775920Sgblack@eecs.umich.edu * </ul> 785920Sgblack@eecs.umich.edu * 795920Sgblack@eecs.umich.edu */ 805920Sgblack@eecs.umich.educlass ArmV8KvmCPU : public BaseArmKvmCPU 815081Sgblack@eecs.umich.edu{ 825081Sgblack@eecs.umich.edu public: 835543Ssaidi@eecs.umich.edu ArmV8KvmCPU(ArmV8KvmCPUParams *params); 845081Sgblack@eecs.umich.edu virtual ~ArmV8KvmCPU(); 855543Ssaidi@eecs.umich.edu 865081Sgblack@eecs.umich.edu void dump() M5_ATTR_OVERRIDE; 875543Ssaidi@eecs.umich.edu 885081Sgblack@eecs.umich.edu protected: 895543Ssaidi@eecs.umich.edu void updateKvmState() M5_ATTR_OVERRIDE; 905081Sgblack@eecs.umich.edu void updateThreadContext() M5_ATTR_OVERRIDE; 915543Ssaidi@eecs.umich.edu 925081Sgblack@eecs.umich.edu protected: 935543Ssaidi@eecs.umich.edu /** Mapping between integer registers in gem5 and KVM */ 945081Sgblack@eecs.umich.edu struct IntRegInfo { 95 IntRegInfo(uint64_t _kvm, IntRegIndex _idx, const char *_name) 96 : kvm(_kvm), idx(_idx), name(_name) {} 97 98 /** Register index in KVM */ 99 uint64_t kvm; 100 /** Register index in gem5 */ 101 IntRegIndex idx; 102 /** Name to use in debug dumps */ 103 const char *name; 104 }; 105 106 /** Mapping between misc registers in gem5 and registers in KVM */ 107 struct MiscRegInfo { 108 MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name) 109 : kvm(_kvm), idx(_idx), name(_name) {} 110 111 /** Register index in KVM */ 112 uint64_t kvm; 113 /** Register index in gem5 */ 114 MiscRegIndex idx; 115 /** Name to use in debug dumps */ 116 const char *name; 117 }; 118 119 /** 120 * Get a map between system registers in kvm and gem5 registers 121 * 122 * This method returns a mapping between system registers in kvm 123 * and misc regs in gem5. The actual mapping is only created the 124 * first time the method is called and stored in a cache 125 * (ArmV8KvmCPU::sysRegMap). 126 * 127 * @return Vector of kvm<->misc reg mappings. 128 */ 129 const std::vector<ArmV8KvmCPU::MiscRegInfo> &getSysRegMap() const; 130 131 /** Mapping between gem5 integer registers and integer registers in kvm */ 132 static const std::vector<ArmV8KvmCPU::IntRegInfo> intRegMap; 133 /** Mapping between gem5 misc registers registers and registers in kvm */ 134 static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegMap; 135 136 /** Cached mapping between system registers in kvm and misc regs in gem5 */ 137 mutable std::vector<ArmV8KvmCPU::MiscRegInfo> sysRegMap; 138}; 139 140#endif // __ARCH_ARM_KVM_ARMV8_CPU_HH__ 141