isa_traits.hh revision 6323:fd0f91f067d2 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Stephen Hines
31 */
32
33#ifndef __ARCH_ARM_ISA_TRAITS_HH__
34#define __ARCH_ARM_ISA_TRAITS_HH__
35
36#include "arch/arm/max_inst_regs.hh"
37#include "arch/arm/types.hh"
38#include "base/types.hh"
39
40namespace LittleEndianGuest {};
41
42#define TARGET_ARM
43
44class StaticInstPtr;
45
46namespace ArmISA
47{
48    using namespace LittleEndianGuest;
49    using ArmISAInst::MaxInstSrcRegs;
50    using ArmISAInst::MaxInstDestRegs;
51
52    StaticInstPtr decodeInst(ExtMachInst);
53
54    // ARM DOES NOT have a delay slot
55    #define ISA_HAS_DELAY_SLOT 0
56
57    const Addr PageShift = 12;
58    const Addr PageBytes = ULL(1) << PageShift;
59    const Addr Page_Mask = ~(PageBytes - 1);
60    const Addr PageOffset = PageBytes - 1;
61
62
63    ////////////////////////////////////////////////////////////////////////
64    //
65    //  Translation stuff
66    //
67
68    const Addr PteShift = 3;
69    const Addr NPtePageShift = PageShift - PteShift;
70    const Addr NPtePage = ULL(1) << NPtePageShift;
71    const Addr PteMask = NPtePage - 1;
72
73    //// All 'Mapped' segments go through the TLB
74    //// All other segments are translated by dropping the MSB, to give
75    //// the corresponding physical address
76    // User Segment - Mapped
77    const Addr USegBase = ULL(0x0);
78    const Addr USegEnd = ULL(0x7FFFFFFF);
79
80    // Kernel Segment 0 - Unmapped
81    const Addr KSeg0End = ULL(0x9FFFFFFF);
82    const Addr KSeg0Base =  ULL(0x80000000);
83    const Addr KSeg0Mask = ULL(0x1FFFFFFF);
84
85    // For loading... XXX This maybe could be USegEnd?? --ali
86    const Addr LoadAddrMask = ULL(0xffffffffff);
87
88    const unsigned VABits = 32;
89    const unsigned PABits = 32; // Is this correct?
90    const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
91    const Addr VAddrUnImplMask = ~VAddrImplMask;
92    inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
93    inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
94    inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
95
96    const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
97
98    // return a no-op instruction... used for instruction fetch faults
99    const ExtMachInst NoopMachInst = 0x00000000;
100
101    // Constants Related to the number of registers
102    const int NumIntArchRegs = 16;
103    const int NumIntSpecialRegs = 19;
104    const int NumFloatArchRegs = 16;
105    const int NumFloatSpecialRegs = 5;
106    const int NumInternalProcRegs = 0;
107
108    const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
109    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
110
111    // semantically meaningful register indices
112    const int ReturnValueReg = 0;
113    const int ReturnValueReg1 = 1;
114    const int ReturnValueReg2 = 2;
115    const int ArgumentReg0 = 0;
116    const int ArgumentReg1 = 1;
117    const int ArgumentReg2 = 2;
118    const int ArgumentReg3 = 3;
119    const int FramePointerReg = 11;
120    const int StackPointerReg = 13;
121    const int ReturnAddressReg = 14;
122    const int PCReg = 15;
123
124    const int ZeroReg = NumIntArchRegs;
125    const int AddrReg = ZeroReg + 1; // Used to generate address for uops
126
127    const int SyscallNumReg = ReturnValueReg;
128    const int SyscallPseudoReturnReg = ReturnValueReg;
129    const int SyscallSuccessReg = ReturnValueReg;
130
131    const int LogVMPageSize = 12;	// 4K bytes
132    const int VMPageSize = (1 << LogVMPageSize);
133
134    const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
135
136    const int MachineBytes = 4;
137    const int WordBytes = 4;
138    const int HalfwordBytes = 2;
139    const int ByteBytes = 1;
140
141    // These help enumerate all the registers for dependence tracking.
142    const int FP_Base_DepTag = NumIntRegs;
143    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
144};
145
146using namespace ArmISA;
147
148#endif // __ARCH_ARM_ISA_TRAITS_HH__
149