isa_traits.hh revision 10318:98771a936b61
17405SAli.Saidi@ARM.com/* 212667Schuan.zhu@arm.com * Copyright (c) 2010, 2012 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 157405SAli.Saidi@ARM.com * Copyright (c) 2007-2008 The Florida State University 167405SAli.Saidi@ARM.com * All rights reserved. 177405SAli.Saidi@ARM.com * 187405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 197405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 207405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 217405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 227405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 237405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 247405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 257405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 267405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 277405SAli.Saidi@ARM.com * this software without specific prior written permission. 287405SAli.Saidi@ARM.com * 297405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407405SAli.Saidi@ARM.com * 417405SAli.Saidi@ARM.com * Authors: Gabe Black 4210461SAndreas.Sandberg@ARM.com * Stephen Hines 439050Schander.sudanthi@arm.com */ 4412406Sgabeblack@google.com 4512605Sgiacomo.travaglini@arm.com#ifndef __ARCH_ARM_ISA_TRAITS_HH__ 4611793Sbrandon.potter@amd.com#define __ARCH_ARM_ISA_TRAITS_HH__ 478887Sgeoffrey.blake@arm.com 488232Snate@binkert.org#include "arch/arm/types.hh" 498232Snate@binkert.org#include "base/types.hh" 5010844Sandreas.sandberg@arm.com#include "cpu/static_inst_fwd.hh" 5113531Sjairo.balart@metempsy.com 5213531Sjairo.balart@metempsy.comnamespace LittleEndianGuest {} 539384SAndreas.Sandberg@arm.com 547678Sgblack@eecs.umich.edunamespace ArmISA 558059SAli.Saidi@ARM.com{ 568284SAli.Saidi@ARM.com using namespace LittleEndianGuest; 577405SAli.Saidi@ARM.com 587405SAli.Saidi@ARM.com StaticInstPtr decodeInst(ExtMachInst); 597405SAli.Saidi@ARM.com 607405SAli.Saidi@ARM.com // ARM DOES NOT have a delay slot 619384SAndreas.Sandberg@arm.com #define ISA_HAS_DELAY_SLOT 0 6210461SAndreas.Sandberg@ARM.com 6310461SAndreas.Sandberg@ARM.com const Addr PageShift = 12; 6411165SRekai.GonzalezAlberquilla@arm.com const Addr PageBytes = ULL(1) << PageShift; 6512109SRekai.GonzalezAlberquilla@arm.com const Addr Page_Mask = ~(PageBytes - 1); 6612714Sgiacomo.travaglini@arm.com const Addr PageOffset = PageBytes - 1; 6712714Sgiacomo.travaglini@arm.com 689384SAndreas.Sandberg@arm.com 6911770SCurtis.Dunham@arm.com //////////////////////////////////////////////////////////////////////// 7010037SARM gem5 Developers // 7110461SAndreas.Sandberg@ARM.com // Translation stuff 7210461SAndreas.Sandberg@ARM.com // 7310461SAndreas.Sandberg@ARM.com 7410461SAndreas.Sandberg@ARM.com const Addr PteShift = 3; 7510461SAndreas.Sandberg@ARM.com const Addr NPtePageShift = PageShift - PteShift; 7610461SAndreas.Sandberg@ARM.com const Addr NPtePage = ULL(1) << NPtePageShift; 7710609Sandreas.sandberg@arm.com const Addr PteMask = NPtePage - 1; 7810609Sandreas.sandberg@arm.com 7910609Sandreas.sandberg@arm.com //// All 'Mapped' segments go through the TLB 8010037SARM gem5 Developers //// All other segments are translated by dropping the MSB, to give 8110037SARM gem5 Developers //// the corresponding physical address 8210037SARM gem5 Developers // User Segment - Mapped 8310037SARM gem5 Developers const Addr USegBase = ULL(0x0); 8411771SCurtis.Dunham@arm.com const Addr USegEnd = ULL(0x7FFFFFFF); 8510037SARM gem5 Developers 8610037SARM gem5 Developers const unsigned VABits = 32; 8713173Sgiacomo.travaglini@arm.com const unsigned PABits = 32; // Is this correct? 8810037SARM gem5 Developers const Addr VAddrImplMask = (ULL(1) << VABits) - 1; 8910037SARM gem5 Developers const Addr VAddrUnImplMask = ~VAddrImplMask; 9013114Sgiacomo.travaglini@arm.com inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 9110037SARM gem5 Developers inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } 9211771SCurtis.Dunham@arm.com inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } 9310037SARM gem5 Developers 9413499Sgiacomo.travaglini@arm.com const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 9510037SARM gem5 Developers 9613114Sgiacomo.travaglini@arm.com // Max. physical address range in bits supported by the architecture 9710037SARM gem5 Developers const unsigned MaxPhysAddrRange = 48; 9810037SARM gem5 Developers 9913531Sjairo.balart@metempsy.com // return a no-op instruction... used for instruction fetch faults 10013531Sjairo.balart@metempsy.com const ExtMachInst NoopMachInst = 0x01E320F000ULL; 10113531Sjairo.balart@metempsy.com 10213531Sjairo.balart@metempsy.com const int MachineBytes = 4; 10313531Sjairo.balart@metempsy.com 10413531Sjairo.balart@metempsy.com const uint32_t HighVecs = 0xFFFF0000; 10513531Sjairo.balart@metempsy.com 10612477SCurtis.Dunham@arm.com // Memory accesses cannot be unaligned 10710037SARM gem5 Developers const bool HasUnalignedMemAcc = true; 10810037SARM gem5 Developers 1099384SAndreas.Sandberg@arm.com const bool CurThreadInfoImplemented = false; 1109384SAndreas.Sandberg@arm.com const int CurThreadInfoReg = -1; 1119384SAndreas.Sandberg@arm.com 11212479SCurtis.Dunham@arm.com enum InterruptTypes 11312479SCurtis.Dunham@arm.com { 1149384SAndreas.Sandberg@arm.com INT_RST, 1159384SAndreas.Sandberg@arm.com INT_ABT, 1169384SAndreas.Sandberg@arm.com INT_IRQ, 1179384SAndreas.Sandberg@arm.com INT_FIQ, 1189384SAndreas.Sandberg@arm.com INT_SEV, // Special interrupt for recieving SEV's 1199384SAndreas.Sandberg@arm.com INT_VIRT_IRQ, 1207427Sgblack@eecs.umich.edu INT_VIRT_FIQ, 1217427Sgblack@eecs.umich.edu NumInterruptTypes 1227427Sgblack@eecs.umich.edu }; 1239385SAndreas.Sandberg@arm.com} // namespace ArmISA 1249385SAndreas.Sandberg@arm.com 1257427Sgblack@eecs.umich.eduusing namespace ArmISA; 1267427Sgblack@eecs.umich.edu 12710037SARM gem5 Developers#endif // __ARCH_ARM_ISA_TRAITS_HH__ 12813114Sgiacomo.travaglini@arm.com