isa_device.hh revision 12972 
1/*
2 * Copyright (c) 2014, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#ifndef __ARCH_ARM_ISA_DEVICE_HH__
41#define __ARCH_ARM_ISA_DEVICE_HH__
42
43#include "arch/arm/registers.hh"
44#include "base/compiler.hh"
45
46class ThreadContext;
47
48namespace ArmISA
49{
50
51class ISA;
52
53/**
54 * Base class for devices that use the MiscReg interfaces.
55 *
56 * This class provides a well-defined interface that the ArmISA class
57 * can use when forwarding MiscReg accesses to a device model (e.g., a
58 * PMU or GIC).
59 */
60class BaseISADevice
61{
62  public:
63    BaseISADevice();
64    virtual ~BaseISADevice() {}
65
66    virtual void setISA(ISA *isa);
67    virtual void setThreadContext(ThreadContext *tc) {}
68
69    /**
70     * Write to a system register belonging to this device.
71     *
72     * @param misc_reg Register number (see miscregs.hh)
73     * @param val Value to store
74     */
75    virtual void setMiscReg(int misc_reg, MiscReg val) = 0;
76
77    /**
78     * Read a system register belonging to this device.
79     *
80     * @param misc_reg Register number (see miscregs.hh)
81     * @return Register value.
82     */
83    virtual MiscReg readMiscReg(int misc_reg) = 0;
84
85  protected:
86    ISA *isa;
87};
88
89/**
90 * Dummy device that prints a warning when it is accessed.
91 *
92 * This device can be used as a placeholder when a real device model
93 * is not present. For example, the ISA code uses it to avoid having
94 * to check for a PMU in the register access code.
95 */
96class DummyISADevice : public BaseISADevice
97{
98  public:
99    DummyISADevice()
100        : BaseISADevice() {}
101    ~DummyISADevice() {}
102
103    void setMiscReg(int misc_reg, MiscReg val) override;
104    MiscReg readMiscReg(int misc_reg) override;
105};
106
107}
108
109#endif // __ARCH_ARM_ISA_DEVICE_HH__
110