vfp.isa revision 8303:5a95f1d2494e 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41    vfpEnabledCheckCode = '''
42        if (!vfpEnabled(Cpacr, Cpsr, Fpexc))
43            return disabledFault();
44    '''
45
46    vmsrEnabledCheckCode = '''
47        if (!vfpEnabled(Cpacr, Cpsr))
48            if (dest != (int)MISCREG_FPEXC && dest != (int)MISCREG_FPSID)
49                return disabledFault();
50        if (!inPrivilegedMode(Cpsr))
51            if (dest != (int)MISCREG_FPSCR)
52                return disabledFault();
53
54    '''
55
56    vmrsEnabledCheckCode = '''
57        if (!vfpEnabled(Cpacr, Cpsr))
58            if (op1 != (int)MISCREG_FPEXC && op1 != (int)MISCREG_FPSID &&
59                op1 != (int)MISCREG_MVFR0 && op1 != (int)MISCREG_MVFR1)
60                return disabledFault();
61        if (!inPrivilegedMode(Cpsr))
62            if (op1 != (int)MISCREG_FPSCR)
63                return disabledFault();
64    '''
65    vmrsApsrEnabledCheckCode = '''
66        if (!vfpEnabled(Cpacr, Cpsr))
67                return disabledFault();
68    '''
69}};
70
71def template FpRegRegOpDeclare {{
72class %(class_name)s : public %(base_class)s
73{
74  public:
75    // Constructor
76    %(class_name)s(ExtMachInst machInst,
77                   IntRegIndex _dest, IntRegIndex _op1,
78                   VfpMicroMode mode = VfpNotAMicroop);
79    %(BasicExecDeclare)s
80};
81}};
82
83def template FpRegRegOpConstructor {{
84    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
85                                          IntRegIndex _dest, IntRegIndex _op1,
86                                          VfpMicroMode mode)
87        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
88                _dest, _op1, mode)
89    {
90        %(constructor)s;
91        if (!(condCode == COND_AL || condCode == COND_UC)) {
92            for (int x = 0; x < _numDestRegs; x++) {
93                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
94            }
95        }
96    }
97}};
98
99def template FpRegImmOpDeclare {{
100class %(class_name)s : public %(base_class)s
101{
102  public:
103    // Constructor
104    %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
105            uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
106    %(BasicExecDeclare)s
107};
108}};
109
110def template FpRegImmOpConstructor {{
111    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
112            IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
113        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
114                _dest, _imm, mode)
115    {
116        %(constructor)s;
117        if (!(condCode == COND_AL || condCode == COND_UC)) {
118            for (int x = 0; x < _numDestRegs; x++) {
119                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
120            }
121        }
122    }
123}};
124
125def template FpRegRegImmOpDeclare {{
126class %(class_name)s : public %(base_class)s
127{
128  public:
129    // Constructor
130    %(class_name)s(ExtMachInst machInst,
131                   IntRegIndex _dest, IntRegIndex _op1,
132                   uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
133    %(BasicExecDeclare)s
134};
135}};
136
137def template FpRegRegImmOpConstructor {{
138    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
139                                          IntRegIndex _dest,
140                                          IntRegIndex _op1,
141                                          uint64_t _imm,
142                                          VfpMicroMode mode)
143        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
144                         _dest, _op1, _imm, mode)
145    {
146        %(constructor)s;
147        if (!(condCode == COND_AL || condCode == COND_UC)) {
148            for (int x = 0; x < _numDestRegs; x++) {
149                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
150            }
151        }
152    }
153}};
154
155def template FpRegRegRegOpDeclare {{
156class %(class_name)s : public %(base_class)s
157{
158  public:
159    // Constructor
160    %(class_name)s(ExtMachInst machInst,
161                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
162                   VfpMicroMode mode = VfpNotAMicroop);
163    %(BasicExecDeclare)s
164};
165}};
166
167def template FpRegRegRegOpConstructor {{
168    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
169                                          IntRegIndex _dest,
170                                          IntRegIndex _op1,
171                                          IntRegIndex _op2,
172                                          VfpMicroMode mode)
173        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
174                         _dest, _op1, _op2, mode)
175    {
176        %(constructor)s;
177        if (!(condCode == COND_AL || condCode == COND_UC)) {
178            for (int x = 0; x < _numDestRegs; x++) {
179                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
180            }
181        }
182    }
183}};
184