vfp.isa revision 7644:62873d5c2bfc 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41    vfpEnabledCheckCode = '''
42        if (!vfpEnabled(Cpacr, Cpsr, Fpexc))
43            return disabledFault();
44    '''
45
46    vmsrEnabledCheckCode = '''
47        if (!vfpEnabled(Cpacr, Cpsr))
48            if (dest != (int)MISCREG_FPEXC && dest != (int)MISCREG_FPSID)
49                return disabledFault();
50        if (!inPrivilegedMode(Cpsr))
51            if (dest != (int)MISCREG_FPSCR)
52                return disabledFault();
53
54    '''
55
56    vmrsEnabledCheckCode = '''
57        if (!vfpEnabled(Cpacr, Cpsr))
58            if (op1 != (int)MISCREG_FPEXC && op1 != (int)MISCREG_FPSID &&
59                op1 != (int)MISCREG_MVFR0 && op1 != (int)MISCREG_MVFR1)
60                return disabledFault();
61        if (!inPrivilegedMode(Cpsr))
62            if (op1 != (int)MISCREG_FPSCR)
63                return disabledFault();
64    '''
65}};
66
67def template FpRegRegOpDeclare {{
68class %(class_name)s : public %(base_class)s
69{
70  public:
71    // Constructor
72    %(class_name)s(ExtMachInst machInst,
73                   IntRegIndex _dest, IntRegIndex _op1,
74                   VfpMicroMode mode = VfpNotAMicroop);
75    %(BasicExecDeclare)s
76};
77}};
78
79def template FpRegRegOpConstructor {{
80    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
81                                          IntRegIndex _dest, IntRegIndex _op1,
82                                          VfpMicroMode mode)
83        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
84                _dest, _op1, mode)
85    {
86        %(constructor)s;
87    }
88}};
89
90def template FpRegImmOpDeclare {{
91class %(class_name)s : public %(base_class)s
92{
93  public:
94    // Constructor
95    %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
96            uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
97    %(BasicExecDeclare)s
98};
99}};
100
101def template FpRegImmOpConstructor {{
102    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
103            IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
104        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
105                _dest, _imm, mode)
106    {
107        %(constructor)s;
108    }
109}};
110
111def template FpRegRegImmOpDeclare {{
112class %(class_name)s : public %(base_class)s
113{
114  public:
115    // Constructor
116    %(class_name)s(ExtMachInst machInst,
117                   IntRegIndex _dest, IntRegIndex _op1,
118                   uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
119    %(BasicExecDeclare)s
120};
121}};
122
123def template FpRegRegImmOpConstructor {{
124    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
125                                          IntRegIndex _dest,
126                                          IntRegIndex _op1,
127                                          uint64_t _imm,
128                                          VfpMicroMode mode)
129        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
130                         _dest, _op1, _imm, mode)
131    {
132        %(constructor)s;
133    }
134}};
135
136def template FpRegRegRegOpDeclare {{
137class %(class_name)s : public %(base_class)s
138{
139  public:
140    // Constructor
141    %(class_name)s(ExtMachInst machInst,
142                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
143                   VfpMicroMode mode = VfpNotAMicroop);
144    %(BasicExecDeclare)s
145};
146}};
147
148def template FpRegRegRegOpConstructor {{
149    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
150                                          IntRegIndex _dest,
151                                          IntRegIndex _op1,
152                                          IntRegIndex _op2,
153                                          VfpMicroMode mode)
154        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
155                         _dest, _op1, _op2, mode)
156    {
157        %(constructor)s;
158    }
159}};
160