xref: /gem5/src/arch/arm/isa/templates/vfp.isa

// -*- mode:c++ -*-

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// Authors: Gabe Black

let {{
    vfpEnabledCheckCode = '''
    {
        Fault fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                                Cpsr, Cpacr, Nsacr, Fpexc,
                                                true, false);
        if (fault != NoFault)
            return fault;
    }
    '''

    vfp64EnabledCheckCode = '''
    {
        Fault fault = checkFPAdvSIMDEnabled64(xc->tcBase(), Cpsr, Cpacr64);
        if (fault != NoFault)
             return fault;
    }
    '''

    vmsrEnabledCheckCode = '''
    {
        Fault fault = NoFault;
        if (dest == (int)MISCREG_FPSCR) {
            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                              Cpsr, Cpacr, Nsacr, Fpexc,
                                              true, false);
        } else if (!inPrivilegedMode(Cpsr)) {
            fault = disabledFault();
        } else {
            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                              Cpsr, Cpacr, Nsacr, Fpexc,
                                              false, false);
        }

        if (fault != NoFault)
            return fault;
    }
    '''

    vmrsEnabledCheckCode = '''
    {
        Fault fault = NoFault;
        if (op1 == (int)MISCREG_FPSCR) {
            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                              Cpsr, Cpacr, Nsacr, Fpexc,
                                              true, false);
        } else if (!inPrivilegedMode(Cpsr)) {
            fault = disabledFault();
        } else {
            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                              Cpsr, Cpacr, Nsacr, Fpexc,
                                              false, false);
        }

        if (fault != NoFault)
            return fault;
    }
    '''
}};

def template FpRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1,
                   VfpMicroMode mode = VfpNotAMicroop);
    %(BasicExecDeclare)s
};
}};

def template FpRegRegOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest, IntRegIndex _op1,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                _dest, _op1, mode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};

def template FpRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
            uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
    %(BasicExecDeclare)s
};
}};

def template FpRegImmOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
            IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                _dest, _imm, mode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};

def template FpRegRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1,
                   uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
    %(BasicExecDeclare)s
};
}};

def template FpRegRegImmOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          uint64_t _imm,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _imm, mode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};

def template FpRegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                   VfpMicroMode mode = VfpNotAMicroop);
    %(BasicExecDeclare)s
};
}};

def template FpRegRegRegOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          IntRegIndex _op2,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, mode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};

def template FpRegRegRegCondOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                  ConditionCode _cond,
                   VfpMicroMode mode = VfpNotAMicroop);
    %(BasicExecDeclare)s
};
}};

def template FpRegRegRegCondOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          IntRegIndex _op2,
                                          ConditionCode _cond,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, _cond, mode)
    {
        %(constructor)s;
    }
}};