vfp.isa revision 11671
17375Sgblack@eecs.umich.edu// -*- mode:c++ -*-
27375Sgblack@eecs.umich.edu
311513Sandreas.sandberg@arm.com// Copyright (c) 2010-2013, 2016 ARM Limited
47375Sgblack@eecs.umich.edu// All rights reserved
57375Sgblack@eecs.umich.edu//
67375Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
77375Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
87375Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
97375Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
107375Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
117375Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
127375Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
137375Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
147375Sgblack@eecs.umich.edu//
157375Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without
167375Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are
177375Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright
187375Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer;
197375Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright
207375Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the
217375Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution;
227375Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its
237375Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from
247375Sgblack@eecs.umich.edu// this software without specific prior written permission.
257375Sgblack@eecs.umich.edu//
267375Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
277375Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
287375Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
297375Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
307375Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
317375Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
327375Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
337375Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
347375Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
357375Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
367375Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
377375Sgblack@eecs.umich.edu//
387375Sgblack@eecs.umich.edu// Authors: Gabe Black
397375Sgblack@eecs.umich.edu
407640Sgblack@eecs.umich.edulet {{
417640Sgblack@eecs.umich.edu    vfpEnabledCheckCode = '''
4211513Sandreas.sandberg@arm.com    {
4311513Sandreas.sandberg@arm.com        Fault fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
4411513Sandreas.sandberg@arm.com                                                Cpsr, Cpacr, Nsacr, Fpexc,
4511513Sandreas.sandberg@arm.com                                                true, false);
4611513Sandreas.sandberg@arm.com        if (fault != NoFault)
4711513Sandreas.sandberg@arm.com            return fault;
4811513Sandreas.sandberg@arm.com    }
4910037SARM gem5 Developers    '''
5010037SARM gem5 Developers
5110037SARM gem5 Developers    vfp64EnabledCheckCode = '''
5211513Sandreas.sandberg@arm.com    {
5311513Sandreas.sandberg@arm.com        Fault fault = checkFPAdvSIMDEnabled64(xc->tcBase(), Cpsr, Cpacr64);
5411513Sandreas.sandberg@arm.com        if (fault != NoFault)
5511513Sandreas.sandberg@arm.com             return fault;
5611513Sandreas.sandberg@arm.com    }
577640Sgblack@eecs.umich.edu    '''
587640Sgblack@eecs.umich.edu
597644Sali.saidi@arm.com    vmsrEnabledCheckCode = '''
6011513Sandreas.sandberg@arm.com    {
6111513Sandreas.sandberg@arm.com        Fault fault = NoFault;
6211513Sandreas.sandberg@arm.com        if (dest == (int)MISCREG_FPSCR) {
6311513Sandreas.sandberg@arm.com            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
6411513Sandreas.sandberg@arm.com                                              Cpsr, Cpacr, Nsacr, Fpexc,
6511513Sandreas.sandberg@arm.com                                              true, false);
6611513Sandreas.sandberg@arm.com        } else if (!inPrivilegedMode(Cpsr)) {
6711513Sandreas.sandberg@arm.com            fault = disabledFault();
6811513Sandreas.sandberg@arm.com        } else {
6911513Sandreas.sandberg@arm.com            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
7011513Sandreas.sandberg@arm.com                                              Cpsr, Cpacr, Nsacr, Fpexc,
7111513Sandreas.sandberg@arm.com                                              false, false);
7210037SARM gem5 Developers        }
7311513Sandreas.sandberg@arm.com
7411513Sandreas.sandberg@arm.com        if (fault != NoFault)
7511513Sandreas.sandberg@arm.com            return fault;
7611513Sandreas.sandberg@arm.com    }
777644Sali.saidi@arm.com    '''
787644Sali.saidi@arm.com
797644Sali.saidi@arm.com    vmrsEnabledCheckCode = '''
8011513Sandreas.sandberg@arm.com    {
8111513Sandreas.sandberg@arm.com        Fault fault = NoFault;
8211513Sandreas.sandberg@arm.com        if (op1 == (int)MISCREG_FPSCR) {
8311513Sandreas.sandberg@arm.com            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
8411513Sandreas.sandberg@arm.com                                              Cpsr, Cpacr, Nsacr, Fpexc,
8511513Sandreas.sandberg@arm.com                                              true, false);
8611513Sandreas.sandberg@arm.com        } else if (!inPrivilegedMode(Cpsr)) {
8711513Sandreas.sandberg@arm.com            fault = disabledFault();
8811513Sandreas.sandberg@arm.com        } else {
8911513Sandreas.sandberg@arm.com            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
9011513Sandreas.sandberg@arm.com                                              Cpsr, Cpacr, Nsacr, Fpexc,
9111513Sandreas.sandberg@arm.com                                              false, false);
9210037SARM gem5 Developers        }
9311513Sandreas.sandberg@arm.com
9411513Sandreas.sandberg@arm.com        if (fault != NoFault)
9511513Sandreas.sandberg@arm.com            return fault;
9611513Sandreas.sandberg@arm.com    }
978303SAli.Saidi@ARM.com    '''
987640Sgblack@eecs.umich.edu}};
997640Sgblack@eecs.umich.edu
1007396Sgblack@eecs.umich.edudef template FpRegRegOpDeclare {{
1017375Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s
1027375Sgblack@eecs.umich.edu{
1037396Sgblack@eecs.umich.edu  public:
1047396Sgblack@eecs.umich.edu    // Constructor
1057396Sgblack@eecs.umich.edu    %(class_name)s(ExtMachInst machInst,
1067396Sgblack@eecs.umich.edu                   IntRegIndex _dest, IntRegIndex _op1,
1077396Sgblack@eecs.umich.edu                   VfpMicroMode mode = VfpNotAMicroop);
1087396Sgblack@eecs.umich.edu    %(BasicExecDeclare)s
1097375Sgblack@eecs.umich.edu};
1107375Sgblack@eecs.umich.edu}};
1117375Sgblack@eecs.umich.edu
1127396Sgblack@eecs.umich.edudef template FpRegRegOpConstructor {{
11310184SCurtis.Dunham@arm.com    %(class_name)s::%(class_name)s(ExtMachInst machInst,
1147375Sgblack@eecs.umich.edu                                          IntRegIndex _dest, IntRegIndex _op1,
1157375Sgblack@eecs.umich.edu                                          VfpMicroMode mode)
1167375Sgblack@eecs.umich.edu        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1177375Sgblack@eecs.umich.edu                _dest, _op1, mode)
1187375Sgblack@eecs.umich.edu    {
1197375Sgblack@eecs.umich.edu        %(constructor)s;
1207848SAli.Saidi@ARM.com        if (!(condCode == COND_AL || condCode == COND_UC)) {
1217848SAli.Saidi@ARM.com            for (int x = 0; x < _numDestRegs; x++) {
1227848SAli.Saidi@ARM.com                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1237848SAli.Saidi@ARM.com            }
1247848SAli.Saidi@ARM.com        }
1257375Sgblack@eecs.umich.edu    }
1267375Sgblack@eecs.umich.edu}};
1277375Sgblack@eecs.umich.edu
1287396Sgblack@eecs.umich.edudef template FpRegImmOpDeclare {{
1297375Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s
1307375Sgblack@eecs.umich.edu{
1317396Sgblack@eecs.umich.edu  public:
1327396Sgblack@eecs.umich.edu    // Constructor
1337396Sgblack@eecs.umich.edu    %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
1347396Sgblack@eecs.umich.edu            uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
1357396Sgblack@eecs.umich.edu    %(BasicExecDeclare)s
1367375Sgblack@eecs.umich.edu};
1377375Sgblack@eecs.umich.edu}};
1387375Sgblack@eecs.umich.edu
1397396Sgblack@eecs.umich.edudef template FpRegImmOpConstructor {{
14010184SCurtis.Dunham@arm.com    %(class_name)s::%(class_name)s(ExtMachInst machInst,
1417375Sgblack@eecs.umich.edu            IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
1427375Sgblack@eecs.umich.edu        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1437375Sgblack@eecs.umich.edu                _dest, _imm, mode)
1447375Sgblack@eecs.umich.edu    {
1457375Sgblack@eecs.umich.edu        %(constructor)s;
1467848SAli.Saidi@ARM.com        if (!(condCode == COND_AL || condCode == COND_UC)) {
1477848SAli.Saidi@ARM.com            for (int x = 0; x < _numDestRegs; x++) {
1487848SAli.Saidi@ARM.com                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1497848SAli.Saidi@ARM.com            }
1507848SAli.Saidi@ARM.com        }
1517375Sgblack@eecs.umich.edu    }
1527375Sgblack@eecs.umich.edu}};
1537375Sgblack@eecs.umich.edu
1547396Sgblack@eecs.umich.edudef template FpRegRegImmOpDeclare {{
1557375Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s
1567375Sgblack@eecs.umich.edu{
1577396Sgblack@eecs.umich.edu  public:
1587396Sgblack@eecs.umich.edu    // Constructor
1597396Sgblack@eecs.umich.edu    %(class_name)s(ExtMachInst machInst,
1607396Sgblack@eecs.umich.edu                   IntRegIndex _dest, IntRegIndex _op1,
1617396Sgblack@eecs.umich.edu                   uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
1627396Sgblack@eecs.umich.edu    %(BasicExecDeclare)s
1637375Sgblack@eecs.umich.edu};
1647375Sgblack@eecs.umich.edu}};
1657375Sgblack@eecs.umich.edu
1667396Sgblack@eecs.umich.edudef template FpRegRegImmOpConstructor {{
16710184SCurtis.Dunham@arm.com    %(class_name)s::%(class_name)s(ExtMachInst machInst,
1687375Sgblack@eecs.umich.edu                                          IntRegIndex _dest,
1697375Sgblack@eecs.umich.edu                                          IntRegIndex _op1,
1707375Sgblack@eecs.umich.edu                                          uint64_t _imm,
1717375Sgblack@eecs.umich.edu                                          VfpMicroMode mode)
1727375Sgblack@eecs.umich.edu        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1737375Sgblack@eecs.umich.edu                         _dest, _op1, _imm, mode)
1747375Sgblack@eecs.umich.edu    {
1757375Sgblack@eecs.umich.edu        %(constructor)s;
1767848SAli.Saidi@ARM.com        if (!(condCode == COND_AL || condCode == COND_UC)) {
1777848SAli.Saidi@ARM.com            for (int x = 0; x < _numDestRegs; x++) {
1787848SAli.Saidi@ARM.com                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1797848SAli.Saidi@ARM.com            }
1807848SAli.Saidi@ARM.com        }
1817375Sgblack@eecs.umich.edu    }
1827375Sgblack@eecs.umich.edu}};
1837375Sgblack@eecs.umich.edu
1847396Sgblack@eecs.umich.edudef template FpRegRegRegOpDeclare {{
1857375Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s
1867375Sgblack@eecs.umich.edu{
1877396Sgblack@eecs.umich.edu  public:
1887396Sgblack@eecs.umich.edu    // Constructor
1897396Sgblack@eecs.umich.edu    %(class_name)s(ExtMachInst machInst,
1907396Sgblack@eecs.umich.edu                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
1917396Sgblack@eecs.umich.edu                   VfpMicroMode mode = VfpNotAMicroop);
1927396Sgblack@eecs.umich.edu    %(BasicExecDeclare)s
1937375Sgblack@eecs.umich.edu};
1947375Sgblack@eecs.umich.edu}};
1957375Sgblack@eecs.umich.edu
1967396Sgblack@eecs.umich.edudef template FpRegRegRegOpConstructor {{
19710184SCurtis.Dunham@arm.com    %(class_name)s::%(class_name)s(ExtMachInst machInst,
1987375Sgblack@eecs.umich.edu                                          IntRegIndex _dest,
1997375Sgblack@eecs.umich.edu                                          IntRegIndex _op1,
2007375Sgblack@eecs.umich.edu                                          IntRegIndex _op2,
2017375Sgblack@eecs.umich.edu                                          VfpMicroMode mode)
2027375Sgblack@eecs.umich.edu        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
2037375Sgblack@eecs.umich.edu                         _dest, _op1, _op2, mode)
2047375Sgblack@eecs.umich.edu    {
2057375Sgblack@eecs.umich.edu        %(constructor)s;
2067848SAli.Saidi@ARM.com        if (!(condCode == COND_AL || condCode == COND_UC)) {
2077848SAli.Saidi@ARM.com            for (int x = 0; x < _numDestRegs; x++) {
2087848SAli.Saidi@ARM.com                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
2097848SAli.Saidi@ARM.com            }
2107848SAli.Saidi@ARM.com        }
2117375Sgblack@eecs.umich.edu    }
2127375Sgblack@eecs.umich.edu}};
21311671Smitch.hayenga@arm.com
21411671Smitch.hayenga@arm.comdef template FpRegRegRegCondOpDeclare {{
21511671Smitch.hayenga@arm.comclass %(class_name)s : public %(base_class)s
21611671Smitch.hayenga@arm.com{
21711671Smitch.hayenga@arm.com  public:
21811671Smitch.hayenga@arm.com    // Constructor
21911671Smitch.hayenga@arm.com    %(class_name)s(ExtMachInst machInst,
22011671Smitch.hayenga@arm.com                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
22111671Smitch.hayenga@arm.com                  ConditionCode _cond,
22211671Smitch.hayenga@arm.com                   VfpMicroMode mode = VfpNotAMicroop);
22311671Smitch.hayenga@arm.com    %(BasicExecDeclare)s
22411671Smitch.hayenga@arm.com};
22511671Smitch.hayenga@arm.com}};
22611671Smitch.hayenga@arm.com
22711671Smitch.hayenga@arm.comdef template FpRegRegRegCondOpConstructor {{
22811671Smitch.hayenga@arm.com    %(class_name)s::%(class_name)s(ExtMachInst machInst,
22911671Smitch.hayenga@arm.com                                          IntRegIndex _dest,
23011671Smitch.hayenga@arm.com                                          IntRegIndex _op1,
23111671Smitch.hayenga@arm.com                                          IntRegIndex _op2,
23211671Smitch.hayenga@arm.com                                          ConditionCode _cond,
23311671Smitch.hayenga@arm.com                                          VfpMicroMode mode)
23411671Smitch.hayenga@arm.com        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
23511671Smitch.hayenga@arm.com                         _dest, _op1, _op2, _cond, mode)
23611671Smitch.hayenga@arm.com    {
23711671Smitch.hayenga@arm.com        %(constructor)s;
23811671Smitch.hayenga@arm.com    }
23911671Smitch.hayenga@arm.com}};
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